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42 lines
894 B
C
42 lines
894 B
C
/*
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* Copyright (C) 2022 Gunar Schorcht
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_esp32
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* @ingroup config
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* @brief Compile-time configuration macros for ESP32-S3 SoCs
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* @{
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*
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* @file
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* @brief ESP32-S3 specific compile-time configuration
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*
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* @author Gunar Schorcht <gunar@schorcht.net>
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*/
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#ifndef CPU_CONF_ESP32S3_H
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#define CPU_CONF_ESP32S3_H
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#ifndef ESP_ISR_STACKSIZE
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/** Stack size used in interrupt context */
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#define ESP_ISR_STACKSIZE (THREAD_STACKSIZE_DEFAULT)
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#endif /* ESP_ISR_STACKSIZE */
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/** Number of DRAM sections that can be used as heap. */
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#define NUM_HEAPS (1)
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifdef __cplusplus
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}
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#endif
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#endif /* CPU_CONF_ESP32S3_H */
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/** @} */
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