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74 lines
1.6 KiB
C
74 lines
1.6 KiB
C
/*
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* Copyright (C) 2016 Loci Controls Inc.
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_cortexm_common
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* @{
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*
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* @file mpu.c
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* @brief Cortex-M Memory Protection Unit (MPU) Driver
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*
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* @author Ian Martin <ian@locicontrols.com>
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*
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* @}
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*/
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#include "cpu.h"
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#include "mpu.h"
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int mpu_disable(void) {
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#if __MPU_PRESENT
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MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
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return 0;
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#else
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return -1;
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#endif
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}
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int mpu_enable(void) {
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#if __MPU_PRESENT
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MPU->CTRL |= MPU_CTRL_PRIVDEFENA_Msk | MPU_CTRL_ENABLE_Msk;
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#ifdef SCB_SHCSR_MEMFAULTENA_Msk
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/* Enable the memory fault exception if SCB SHCSR (System Handler Control
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* and State Register) has a separate bit for mem faults. That is the case
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* on ARMv7-M. ARMv6-M does not support separate exception enable for mem
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* faults and all fault conditions cause a HardFault. */
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SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
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#endif
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return 0;
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#else
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return -1;
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#endif
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}
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bool mpu_enabled(void) {
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#if __MPU_PRESENT
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return (MPU->CTRL & MPU_CTRL_ENABLE_Msk) != 0;
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#else
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return false;
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#endif
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}
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int mpu_configure(uint_fast8_t region, uintptr_t base, uint_fast32_t attr) {
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/* Todo enable MPU support for Cortex-M23/M33 */
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#if __MPU_PRESENT && !defined(__ARM_ARCH_8M_MAIN__) && !defined(__ARM_ARCH_8M_BASE__)
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MPU->RNR = region;
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MPU->RBAR = base & MPU_RBAR_ADDR_Msk;
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MPU->RASR = attr | MPU_RASR_ENABLE_Msk;
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return 0;
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#else
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(void)region;
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(void)base;
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(void)attr;
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return -1;
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#endif
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}
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