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e3d5a70e0c
These are leftovers from before the Cortex-M common ISR vectors were split into vectors_cortexm.c
143 lines
5.0 KiB
C
143 lines
5.0 KiB
C
/*
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* Copyright (C) 2014-2015 Freie Universität Berlin
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_cc2538
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* @{
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*
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* @file
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* @brief Interrupt vector definitions
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*
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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* @author Ian Martin <ian@locicontrols.com>
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*/
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#include <stdint.h>
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#include "cpu.h"
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#include "board.h"
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#include "vectors_cortexm.h"
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/* define a local dummy handler as it needs to be in the same compilation unit
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* as the alias definition */
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void dummy_handler(void) {
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dummy_handler_default();
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}
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/* CC2538 specific interrupt vectors */
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WEAK_DEFAULT void isr_gpioa(void);
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WEAK_DEFAULT void isr_gpiob(void);
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WEAK_DEFAULT void isr_gpioc(void);
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WEAK_DEFAULT void isr_gpiod(void);
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WEAK_DEFAULT void isr_uart0(void);
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WEAK_DEFAULT void isr_uart1(void);
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WEAK_DEFAULT void isr_ssi0(void);
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WEAK_DEFAULT void isr_i2c(void);
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WEAK_DEFAULT void isr_adc(void);
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WEAK_DEFAULT void isr_watchdog(void);
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WEAK_DEFAULT void isr_timer0_chan0(void);
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WEAK_DEFAULT void isr_timer0_chan1(void);
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WEAK_DEFAULT void isr_timer1_chan0(void);
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WEAK_DEFAULT void isr_timer1_chan1(void);
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WEAK_DEFAULT void isr_timer2_chan0(void);
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WEAK_DEFAULT void isr_timer2_chan1(void);
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WEAK_DEFAULT void isr_comp(void);
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WEAK_DEFAULT void isr_rfcorerxtx(void);
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WEAK_DEFAULT void isr_rfcoreerr(void);
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WEAK_DEFAULT void isr_icepick(void);
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WEAK_DEFAULT void isr_flash(void);
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WEAK_DEFAULT void isr_aes(void);
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WEAK_DEFAULT void isr_pka(void);
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WEAK_DEFAULT void isr_sleepmode(void);
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WEAK_DEFAULT void isr_mactimer(void);
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WEAK_DEFAULT void isr_ssi1(void);
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WEAK_DEFAULT void isr_timer3_chan0(void);
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WEAK_DEFAULT void isr_timer3_chan1(void);
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WEAK_DEFAULT void isr_usb(void);
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WEAK_DEFAULT void isr_dma(void);
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WEAK_DEFAULT void isr_dmaerr(void);
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/* CPU specific interrupt vector table */
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ISR_VECTOR(1) const isr_t vector_cpu[CPU_IRQ_NUMOF] = {
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isr_gpioa, /* 16 GPIO Port A */
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isr_gpiob, /* 17 GPIO Port B */
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isr_gpioc, /* 18 GPIO Port C */
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isr_gpiod, /* 19 GPIO Port D */
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(0UL), /* 20 none */
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isr_uart0, /* 21 UART0 Rx and Tx */
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isr_uart1, /* 22 UART1 Rx and Tx */
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isr_ssi0, /* 23 SSI0 Rx and Tx */
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isr_i2c, /* 24 I2C Master and Slave */
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(0UL), /* 25 Reserved */
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(0UL), /* 26 Reserved */
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(0UL), /* 27 Reserved */
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(0UL), /* 28 Reserved */
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(0UL), /* 29 Reserved */
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isr_adc, /* 30 ADC Sequence 0 */
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(0UL), /* 31 Reserved */
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(0UL), /* 32 Reserved */
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(0UL), /* 33 Reserved */
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isr_watchdog, /* 34 Watchdog timer, timer 0 */
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isr_timer0_chan0, /* 35 Timer 0 subtimer A */
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isr_timer0_chan1, /* 36 Timer 0 subtimer B */
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isr_timer1_chan0, /* 37 Timer 1 subtimer A */
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isr_timer1_chan1, /* 38 Timer 1 subtimer B */
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isr_timer2_chan0, /* 39 Timer 2 subtimer A */
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isr_timer2_chan1, /* 40 Timer 2 subtimer B */
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isr_comp, /* 41 Analog Comparator 0 */
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isr_rfcorerxtx, /* 42 RFCore Rx/Tx */
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isr_rfcoreerr, /* 43 RFCore Error */
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isr_icepick, /* 44 IcePick */
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isr_flash, /* 45 FLASH Control */
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isr_aes, /* 46 AES */
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isr_pka, /* 47 PKA */
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isr_sleepmode, /* 48 Sleep Timer */
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isr_mactimer, /* 49 MacTimer */
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isr_ssi1, /* 50 SSI1 Rx and Tx */
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isr_timer3_chan0, /* 51 Timer 3 subtimer A */
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isr_timer3_chan1, /* 52 Timer 3 subtimer B */
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(0UL), /* 53 Reserved */
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(0UL), /* 54 Reserved */
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(0UL), /* 55 Reserved */
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(0UL), /* 56 Reserved */
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(0UL), /* 57 Reserved */
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(0UL), /* 58 Reserved */
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(0UL), /* 59 Reserved */
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isr_usb, /* 60 USB 2538 */
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(0UL), /* 61 Reserved */
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isr_dma, /* 62 uDMA */
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isr_dmaerr, /* 63 uDMA Error */
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};
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#if UPDATE_CCA
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extern cortexm_base_t cortex_vector_base;
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/**
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* @brief Flash Customer Configuration Area (CCA)
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*
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* Defines bootloader backdoor configuration, boot image validity and base address, and flash page lock bits.
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*/
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__attribute__((section(".flashcca"), used))
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const uint32_t cca[] = {
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/* Bootloader Backdoor Configuration: */
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0xe0ffffff | (CCA_BACKDOOR_ENABLE << 28) | (CCA_BACKDOOR_ACTIVE_LEVEL << 27) | (CCA_BACKDOOR_PORT_A_PIN << 24),
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0x00000000, /**< Image Valid */
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(uint32_t)&cortex_vector_base, /**< Application Entry Point */
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/* Unlock all pages and debug: */
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0xffffffff,
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0xffffffff,
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0xffffffff,
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0xffffffff,
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0xffffffff,
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0xffffffff,
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0xffffffff,
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0xffffffff,
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};
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#endif
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/** @} */
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