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93aa10cc5c
The avr8_state variable uses bit operation to set/clear the state. This rework avr8_state to use increment/decrement instead. It introduce the use of General Purpose IO Register 1 (GPIOR1) when available. This is a preparation for future scheduling and irq optimizations. Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
114 lines
3.5 KiB
C
114 lines
3.5 KiB
C
/*
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* Copyright (C) 2023 Gerson Fernando Budke
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_avr8_common
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* @{
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*
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* @file
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* @brief States internal interface
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*
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* @author Gerson Fernando Budke <nandojve@gmail.com>
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*
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*/
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#ifndef STATES_INTERNAL_H
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#define STATES_INTERNAL_H
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#include <avr/io.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @name Internal flag which defines if uart state is stored on SRAM
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* @{
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*/
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#ifdef GPIOR0
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#define AVR8_STATE_UART_USE_SRAM 0 /**< UART state using GPIOR registers. */
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#else
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#define AVR8_STATE_UART_USE_SRAM 1 /**< UART state using SRAM. */
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#endif
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/** @} */
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/**
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* @name UART TX pending state
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* @{
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*
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* @note The content must be changed using the pair
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* @ref avr8_uart_tx_set_pending and @ref avr8_uart_tx_clear_pending
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* methods and the state is stored on @ref avr8_state_uart.
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*
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* Contents:
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* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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* 7 6 5 4 3 2 1 0
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* +---+---+---+---+---+---+---+---+
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* |TX7|TX6|TX5|TX4|TX3|TX2|TX1|TX0|
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* +---+---+---+---+---+---+---+---+
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* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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*
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* | Label | Description |
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* |:-------|:--------------------------------------------------------------|
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* | TX7 | This bit is set when on UART7 TX is pending |
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* | TX6 | This bit is set when on UART6 TX is pending |
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* | TX5 | This bit is set when on UART5 TX is pending |
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* | TX4 | This bit is set when on UART4 TX is pending |
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* | TX3 | This bit is set when on UART3 TX is pending |
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* | TX2 | This bit is set when on UART2 TX is pending |
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* | TX1 | This bit is set when on UART1 TX is pending |
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* | TX0 | This bit is set when on UART0 TX is pending |
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*/
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#if (AVR8_STATE_UART_USE_SRAM)
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extern uint8_t avr8_state_uart_sram; /**< UART state variable. */
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#define avr8_state_uart avr8_state_uart_sram /**< Definition for SRAM. */
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#else
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#define avr8_state_uart GPIOR0 /**< Definition for GPIOR0. */
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#endif
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/** @} */
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/**
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* @name Internal flag which defines if IRQ state is stored on SRAM
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* @{
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*/
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#ifdef GPIOR1
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#define AVR8_STATE_IRQ_USE_SRAM 0 /**< IRQ state using GPIOR registers. */
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#else
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#define AVR8_STATE_IRQ_USE_SRAM 1 /**< IRQ state using GPIOR registers. */
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#endif
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/** @} */
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/**
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* @name Global variable containing the current state of the MCU
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* @{
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*
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* @note This variable is updated from IRQ context; access to it should
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* be wrapped into @ref irq_disable and @ref irq_restore should be
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* used.
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*
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* Contents:
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*
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* | Label | Description |
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* |:-------|:--------------------------------------------------------------|
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* | IRQ | This variable is incremented when in IRQ context |
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*/
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#if (AVR8_STATE_IRQ_USE_SRAM)
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extern uint8_t avr8_state_irq_count_sram; /**< IRQ state variable. */
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#define avr8_state_irq_count avr8_state_irq_count_sram /**< Definition for SRAM. */
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#else
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#define avr8_state_irq_count GPIOR1 /**< Definition for GPIOR1. */
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#endif
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#endif /* STATES_INTERNAL_H */
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/** @} */
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