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The current ISR implementation for AVR8 requires use of avr8_[enter/exit]_isr pair which add some boilerplate on code. This add AVR8_ISR which clean-up the code and make it simpler and hides any schedule detail from the user perspective. This is a preparation for future scheduling and irq optimizations. Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
162 lines
4.1 KiB
C
162 lines
4.1 KiB
C
/*
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* Copyright (C) 2014 Freie Universität Berlin, Hinnerk van Bruinehsen
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* 2018 RWTH Aachen, Josua Arndt <jarndt@ias.rwth-aachen.de>
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* 2020 Otto-von-Guericke-Universität Magdeburg
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* 2021-2023 Gerson Fernando Budke
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_avr8_common
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* @{
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*
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* @file
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* @brief Implementation of the kernels irq interface
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*
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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* @author Hinnerk van Bruinehsen <h.v.bruinehsen@fu-berlin.de>
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* @author Josua Arndt <jarndt@ias.rwth-aachen.de>
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* @author Marian Buschsieweke <marian.buschsieweke@ovgu.de>
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* @author Gerson Fernando Budke <nandojve@gmail.com>
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*
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*/
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#ifndef IRQ_ARCH_H
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#define IRQ_ARCH_H
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#include <stdbool.h>
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#include <stdint.h>
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#include <stdio.h>
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#include <stdint.h>
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#include "cpu.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief Disable all maskable interrupts
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*/
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__attribute__((always_inline)) static inline unsigned int irq_disable(void)
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{
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uint8_t mask;
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__asm__ volatile(
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"in %[dest], __SREG__" "\n\t"
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"cli" "\n\t"
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: [dest] "=r"(mask)
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: /* no inputs */
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: "memory"
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);
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return mask;
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}
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/**
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* @brief Enable all maskable interrupts
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*/
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__attribute__((always_inline)) static inline unsigned int irq_enable(void)
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{
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uint8_t mask;
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__asm__ volatile(
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"in %[dest], __SREG__" "\n\t"
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"sei" "\n\t"
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: [dest] "=r"(mask)
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: /* no inputs */
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: "memory"
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);
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return mask;
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}
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/**
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* @brief Restore the state of the IRQ flags
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*/
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__attribute__((always_inline)) static inline void irq_restore(unsigned int _state)
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{
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uint8_t state = (uint8_t)_state;
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/*
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* Implementation in pseudo-code:
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*
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* disable_irqs();
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* if (state & BIT7) {
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* enable_irqs();
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* }
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*
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* This takes 3 CPU Cycles if BIT7 is set (IRQs are enabled), otherwise 2.
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*/
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__asm__ volatile(
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"cli" "\n\t"
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"sbrc %[state], 7" "\n\t"
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"sei" "\n\t"
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: /* no outputs */
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: [state] "r"(state)
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: "memory"
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);
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}
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/**
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* @brief See if the current context is inside an ISR
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*/
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__attribute__((always_inline)) static inline bool irq_is_in(void)
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{
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bool is_in = avr8_state_irq_count > 0;
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__asm__ volatile ("" : : : "memory");
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return is_in;
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}
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/**
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* @brief Test if interrupts are currently enabled
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*/
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__attribute__((always_inline)) static inline bool irq_is_enabled(void)
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{
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uint8_t mask;
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__asm__ volatile(
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"in %[dest], __SREG__" "\n\t"
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: [dest] "=r"(mask)
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: /* no inputs */
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: "memory"
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);
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return mask & (1 << 7);
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}
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/**
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* @brief Define an AVR-8 ISR
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*
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* This macro hides all RIOT-OS port internal details from user implementation.
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* The user should use this macro passing at least two parameters. The first is
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* the interrupt vector and the second one is the function to be called. Zero or
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* more optional parameters can be passed the function one by one using the
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* variable length argument list.
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*
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* It is recommended that user define a `static inline void` function to
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* the implement the interrupt. The function can accept argument list based on
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* implementation details.
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*
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* Example:
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*
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* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~{.c}
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* static inline void _my_isr_handler(int index)
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* {
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* do_something(index);
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* }
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* AVR8_ISR(PERIPHERAL_INSTANCE_0_ISR, _my_isr_handler, 0);
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* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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*/
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#define AVR8_ISR(vector, function, ...) \
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ISR(vector, ISR_BLOCK) \
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{ \
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avr8_enter_isr(); \
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function(__VA_ARGS__); \
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avr8_exit_isr(); \
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}
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#ifdef __cplusplus
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}
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#endif
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/** @} */
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#endif /* IRQ_ARCH_H */
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