mirror of
https://github.com/RIOT-OS/RIOT.git
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549e2b4de1
Fix the required PM state on i2c and spi peripherals. Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
289 lines
7.2 KiB
C
289 lines
7.2 KiB
C
/*
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* Copyright (C) 2021-2023 Gerson Fernando Budke <nandojve@gmail.com>
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_atxmega
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* @ingroup cpu_atxmega_periph
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* @{
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*
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* @file
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* @brief Low-level I2C driver implementation
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*
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* @author Gerson Fernando Budke <nandojve@gmail.com>
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*
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* @}
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*/
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#include <assert.h>
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#include <errno.h>
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#include "cpu.h"
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#include "cpu_pm.h"
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#include "irq.h"
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#include "periph/i2c.h"
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#include "periph/gpio.h"
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#include "periph/pm.h"
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#define ENABLE_DEBUG 0
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#include "debug.h"
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/**
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* @brief Device Context allocation
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*/
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static struct {
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mutex_t locks;
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mutex_t xfer;
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uint8_t *buffer;
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size_t pos;
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size_t len;
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uint8_t flags;
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int8_t status;
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} i2c_ctx[I2C_NUMOF];
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/**
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* @brief Get the pointer to the base register of the given I2C device
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*
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* @param[in] dev I2C device identifier
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*
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* @return base register address
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*/
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static inline TWI_t* dev(i2c_t dev)
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{
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return ((TWI_t*) (i2c_config[dev].dev));
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}
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static inline uint8_t _i2c_calc_baud(i2c_t i2c)
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{
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uint16_t ftwi = (((CLOCK_CORECLOCK / (2*i2c_config[i2c].speed))-5)+1);
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if (ftwi > 255) {
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DEBUG("[i2c] init: dev speed is lower than minimal speed supported.\n");
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return 0;
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}
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if (ftwi < 1) {
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DEBUG("[i2c] init: dev speed is high than maximum speed supported.\n");
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return 0;
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}
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return ftwi & 0xff;
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}
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void i2c_init(i2c_t i2c)
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{
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uint8_t baudrate;
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assert((unsigned)i2c < I2C_NUMOF);
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baudrate = _i2c_calc_baud(i2c);
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if (baudrate == 0) {
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DEBUG("[i2c] init: baudrate is invalid.\n");
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return;
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}
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mutex_init(&i2c_ctx[i2c].locks);
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mutex_init(&i2c_ctx[i2c].xfer);
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mutex_lock(&i2c_ctx[i2c].xfer);
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i2c_init_pins(i2c);
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pm_periph_enable(i2c_config[i2c].pwr);
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dev(i2c)->MASTER.BAUD = baudrate;
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pm_periph_disable(i2c_config[i2c].pwr);
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}
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void i2c_init_pins(i2c_t i2c)
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{
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assert((unsigned)i2c < I2C_NUMOF);
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gpio_init(i2c_config[i2c].sda_pin, GPIO_OPC_WRD_AND_PULL);
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gpio_init(i2c_config[i2c].scl_pin, GPIO_OPC_WRD_AND_PULL);
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}
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void i2c_acquire(i2c_t i2c)
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{
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assert((unsigned)i2c < I2C_NUMOF);
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DEBUG("acquire\n");
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pm_block(4); /* Require clkPer */
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mutex_lock(&i2c_ctx[i2c].locks);
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pm_periph_enable(i2c_config[i2c].pwr);
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dev(i2c)->MASTER.CTRLA = (i2c_config[i2c].int_lvl << TWI_MASTER_INTLVL_gp)
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| TWI_MASTER_RIEN_bm
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| TWI_MASTER_WIEN_bm
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| TWI_MASTER_ENABLE_bm;
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dev(i2c)->MASTER.STATUS = TWI_MASTER_BUSSTATE_IDLE_gc;
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}
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void i2c_release(i2c_t i2c)
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{
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assert((unsigned)i2c < I2C_NUMOF);
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dev(i2c)->MASTER.CTRLA = 0;
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pm_periph_disable(i2c_config[i2c].pwr);
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mutex_unlock(&i2c_ctx[i2c].locks);
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pm_unblock(4);
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DEBUG("release\n");
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}
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static int _i2c_transaction(i2c_t i2c, uint16_t addr, const void *data,
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size_t len, uint8_t flags, bool is_read)
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{
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assert((unsigned)i2c < I2C_NUMOF);
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if (flags & I2C_ADDR10) {
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DEBUG("[i2c] xfer: no 10 bit address support.\n");
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return -EOPNOTSUPP;
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}
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if (data == NULL || len == 0) {
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DEBUG("[i2c] xfer: invalid parameter.\n");
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return -EINVAL;
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}
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i2c_ctx[i2c].buffer = (uint8_t *) data;
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i2c_ctx[i2c].pos = 0;
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i2c_ctx[i2c].len = len;
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i2c_ctx[i2c].flags = flags;
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dev(i2c)->MASTER.ADDR = (addr << 1) | (is_read ? 0x01 : 0x00);
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mutex_lock(&i2c_ctx[i2c].xfer);
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DEBUG("[i2c] xfer: status = %d\n", i2c_ctx[i2c].status);
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return i2c_ctx[i2c].status;
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}
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int i2c_write_bytes(i2c_t i2c, uint16_t addr, const void *data, size_t len,
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uint8_t flags)
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{
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return _i2c_transaction(i2c, addr, data, len, flags, false);
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}
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int i2c_read_bytes(i2c_t i2c, uint16_t addr, void *data, size_t len,
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uint8_t flags)
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{
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return _i2c_transaction(i2c, addr, data, len, flags, true);
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}
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/**
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* @internal
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*
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* @brief TWI master write interrupt handler.
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*
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* Handles TWI transactions (master write) and responses to (N)ACK.
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*/
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static inline void _i2c_write_handler(int i2c)
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{
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if (i2c_ctx[i2c].pos < i2c_ctx[i2c].len) {
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const uint8_t* const data = i2c_ctx[i2c].buffer;
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dev(i2c)->MASTER.DATA = data[i2c_ctx[i2c].pos++];
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}
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else {
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/* Send STOP condition to complete the transaction. */
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if (!(i2c_ctx[i2c].flags & I2C_NOSTOP)) {
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dev(i2c)->MASTER.CTRLC = TWI_MASTER_CMD_STOP_gc;
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}
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i2c_ctx[i2c].status = 0;
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mutex_unlock(&i2c_ctx[i2c].xfer);
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}
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}
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/**
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* @internal
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*
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* @brief TWI master read interrupt handler.
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*
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* This is the master read interrupt handler that takes care of reading bytes
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* from the TWI slave device.
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*/
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static inline void _i2c_read_handler(int i2c)
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{
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if (i2c_ctx[i2c].pos < i2c_ctx[i2c].len) {
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uint8_t* const data = i2c_ctx[i2c].buffer;
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data[i2c_ctx[i2c].pos++] = dev(i2c)->MASTER.DATA;
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/* If there is more to read, issue ACK and start a byte read.
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* Otherwise, issue NACK and STOP to complete the transaction.
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*/
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if (i2c_ctx[i2c].pos < i2c_ctx[i2c].len) {
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dev(i2c)->MASTER.CTRLC = TWI_MASTER_CMD_RECVTRANS_gc;
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}
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else {
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uint8_t control_c = TWI_MASTER_ACKACT_bm;
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if (!(i2c_ctx[i2c].flags & I2C_NOSTOP)) {
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control_c |= TWI_MASTER_CMD_STOP_gc;
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}
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dev(i2c)->MASTER.CTRLC = control_c;
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i2c_ctx[i2c].status = 0;
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mutex_unlock(&i2c_ctx[i2c].xfer);
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}
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} else {
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/* Issue STOP and buffer overflow condition. */
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dev(i2c)->MASTER.CTRLC = TWI_MASTER_CMD_STOP_gc;
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i2c_ctx[i2c].status = -ENOMEM;
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mutex_unlock(&i2c_ctx[i2c].xfer);
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}
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}
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/**
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* @internal
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*
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* @brief Common TWI master interrupt service routine.
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*
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* Check current status and calls the appropriate handler.
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*/
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static inline void isr_handler(int i2c)
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{
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assert((unsigned)i2c < I2C_NUMOF);
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int8_t const m_status = dev(i2c)->MASTER.STATUS;
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if (m_status & TWI_MASTER_ARBLOST_bm) {
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dev(i2c)->MASTER.STATUS = m_status | TWI_MASTER_ARBLOST_bm;
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dev(i2c)->MASTER.CTRLC = TWI_MASTER_CMD_STOP_gc;
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i2c_ctx[i2c].status = -EBUSY;
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mutex_unlock(&i2c_ctx[i2c].xfer);
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}
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else if ((m_status & TWI_MASTER_BUSERR_bm)
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|| (m_status & TWI_MASTER_RXACK_bm)) {
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dev(i2c)->MASTER.CTRLC = TWI_MASTER_CMD_STOP_gc;
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i2c_ctx[i2c].status = ((m_status & TWI_MASTER_BUSERR_bm) > 0)
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? -EIO
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: -ENXIO;
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mutex_unlock(&i2c_ctx[i2c].xfer);
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}
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else if (m_status & TWI_MASTER_WIF_bm) {
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_i2c_write_handler(i2c);
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}
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else if (m_status & TWI_MASTER_RIF_bm) {
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_i2c_read_handler(i2c);
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}
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else {
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i2c_ctx[i2c].status = -EPROTO;
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mutex_unlock(&i2c_ctx[i2c].xfer);
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}
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}
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#ifdef I2C_0_ISR
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AVR8_ISR(I2C_0_ISR, isr_handler, 0);
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#endif /* I2C_0_ISR */
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#ifdef I2C_1_ISR
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AVR8_ISR(I2C_1_ISR, isr_handler, 1);
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#endif /* I2C_1_ISR */
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#ifdef I2C_2_ISR
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AVR8_ISR(I2C_2_ISR, isr_handler, 2);
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#endif /* I2C_2_ISR */
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#ifdef I2C_3_ISR
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AVR8_ISR(I2C_3_ISR, isr_handler, 3);
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#endif /* I2C_3_ISR */
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