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307e8c7a17
Introduce XMEGA EBI driver. This enable EBI for use with all memory supported by the device and peripherals. It include support to SRAM, SDRAM, LCDs or any other external bus access. Note: This feature only works for A1/A1U series, which are, the series with EBI hardware. Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
376 lines
11 KiB
C
376 lines
11 KiB
C
/*
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* Copyright (C) 2021 Gerson Fernando Budke <nandojve@gmail.com>
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_atxmega
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* @ingroup cpu_atxmega_periph
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* @{
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*
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* @file
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* @brief Low-level EBI (External BUS Interface) driver implementation
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*
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* @author Gerson Fernando Budke <nandojve@gmail.com>
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* https://www.avrfreaks.net/forum/xmega-ebi-and-sram
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* https://www.avrfreaks.net/forum/xmega-au-four-port-ebi
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* https://community.atmel.com/forum/location-variable-specified-address
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* @}
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*/
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#include <avr/io.h>
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#include "assert.h"
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#include "periph_conf.h"
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#include "cpu_pm.h"
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#include "cpu_ebi.h"
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#define ENABLE_DEBUG 0
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#include "debug.h"
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void ebi_init(void) __attribute__((naked, section(".init1"), used));
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/**
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* @brief Set up the I/O ports for use by the EBI.
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*
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* @note In SDRAM mode the \a sram_ale and \a lpc_ale parameters are ignored
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* by the hardware.
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*/
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void ebi_init(void)
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{
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EBI_CS_t *cs;
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uint8_t mode;
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uint8_t sd_ctrl = 0;
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uint8_t i;
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uint8_t expand_sram = 0;
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/*
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* This is a mandatory configuration. Whowever, to complete disable module
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* just configure it as:
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*
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* static const ebi_conf_t ebi_config = { 0 };
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*
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* or, for a temporary disable, set addr_bits to 0 at periph_conf.h:
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*
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* .addr_bits = 0,
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*/
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if (ebi_config.addr_bits == 0) {
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return;
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}
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/*
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* Set address and control lines as outputs, and active-low control lines
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* initially high.
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*/
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if (ebi_config.flags & EBI_PORT_SDRAM) {
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/* With SDRAM, the configuration is fairly fixed. */
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PORTH.OUT = 0x0f;
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PORTH.DIR = 0xff;
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PORTJ.DIR = 0xf0;
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PORTK.DIR = 0xff;
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} else {
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uint8_t ale_mask = ebi_config.sram_ale | ebi_config.lpc_ale;
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uint8_t port_mask;
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/*
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* Set PORTH initial state, set WE and CAS/RE high by default.
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* Set chip selects high by default if enabled.
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*/
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port_mask = 0x03;
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if (ebi_config.flags & EBI_PORT_CS0) {
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port_mask |= 0x10;
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}
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if (ebi_config.flags & EBI_PORT_CS1) {
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port_mask |= 0x20;
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}
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if (ebi_config.flags & EBI_PORT_CS2) {
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port_mask |= 0x40;
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}
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if (ebi_config.flags & EBI_PORT_CS3) {
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port_mask |= 0x80;
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}
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PORTH.OUT = port_mask;
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/*
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* Set PORTH direction, enable WE, CAS/RE and RAS/ALE1 to
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* output by default. Set chip select direction if enabled.
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*/
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port_mask = 0x07;
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/* If two latches are in use, enable the ALE2 pin as well. */
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if (ale_mask & 0x02) {
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port_mask |= 0x08;
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}
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if (ebi_config.flags & EBI_PORT_CS0 || ebi_config.addr_bits > 16) {
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port_mask |= 0x10;
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}
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if (ebi_config.flags & EBI_PORT_CS1 || ebi_config.addr_bits > 17) {
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port_mask |= 0x20;
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}
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if (ebi_config.flags & EBI_PORT_CS2 || ebi_config.addr_bits > 18) {
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port_mask |= 0x40;
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}
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if (ebi_config.flags & EBI_PORT_CS3 || ebi_config.addr_bits > 19) {
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port_mask |= 0x80;
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}
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PORTH.DIR = port_mask;
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/*
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* PORTJ is always used for data, direction and value is controlled by
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* the EBI module.
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*/
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/* PORTK is only used in 3-port mode */
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if (ebi_config.flags & EBI_PORT_3PORT) {
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port_mask = 0x00;
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if (ebi_config.flags & EBI_PORT_SRAM) {
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/*
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* Bits 0..7 go here, so if we have 8 lines or more, enable all
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* lines. Otherwise, enable as many as we need.
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*/
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if (ebi_config.addr_bits < 8) {
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port_mask = (1 << ebi_config.addr_bits) - 1;
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}
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else {
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port_mask = 0xff;
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}
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}
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else {
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/*
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* Bits 8..15 go here, so if we have less than 16 address lines,
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* disable the ones that we don't need. If we have 8 lines or
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* less, disable all address lines on this port.
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*/
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if (ebi_config.addr_bits <= 8) {
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port_mask = 0x00;
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}
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else if (ebi_config.addr_bits < 16) {
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port_mask = (1 << (ebi_config.addr_bits - 8)) - 1;
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}
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else {
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port_mask = 0xff;
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}
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}
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PORTK.DIR = port_mask;
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}
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}
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if (ebi_config.flags & EBI_PORT_3PORT) {
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mode = EBI_IFMODE_3PORT_gc;
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}
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else {
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mode = EBI_IFMODE_2PORT_gc;
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}
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if (ebi_config.sram_ale == 1) {
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mode |= EBI_SRMODE_ALE1_gc;
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}
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else if (ebi_config.sram_ale == 2) {
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mode |= EBI_SRMODE_ALE12_gc;
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}
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else {
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mode |= EBI_SRMODE_NOALE_gc;
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}
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if (ebi_config.lpc_ale > 0) {
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mode |= (ebi_config.lpc_ale << EBI_LPCMODE_gp);
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}
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if (ebi_config.sdram.cas_latency == EBI_SDRAM_CAS_LAT_3CLK) {
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sd_ctrl |= EBI_SDCAS_bm;
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}
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if (ebi_config.sdram.row_bits == EBI_SDRAM_ROW_BITS_12) {
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sd_ctrl |= EBI_SDROW_bm;
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}
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/* Enable EBI periph clock */
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PR.PRGEN &= ~PR_EBI_bm;
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/* 8-bit SDRAM requires 4-port EBI, which we don't have. */
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EBI.CTRL = EBI_SDDATAW_4BIT_gc
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| mode;
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EBI.SDRAMCTRLA = sd_ctrl
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| ebi_config.sdram.column_bits;
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EBI.SDRAMCTRLB = ebi_config.sdram.ld_mode_dly
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| ebi_config.sdram.row_cycle_dly
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| ebi_config.sdram.row_prechage_dly;
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EBI.SDRAMCTRLC = ebi_config.sdram.write_recovery_dly
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| ebi_config.sdram.exit_self_rfsh_dly
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| ebi_config.sdram.row_to_column_dly;
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EBI.REFRESH = ebi_config.sdram.refresh_period & 0x0FFF;
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EBI.INITDLY = ebi_config.sdram.init_dly & 0x3FFF;
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/* IRQ are disabled here */
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cs = (EBI_CS_t *)&EBI.CS0;
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for (i = 0; i < PERIPH_EBI_MAX_CS; i++) {
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if (ebi_config.cs[i].mode != EBI_CS_MODE_DISABLED_gc &&
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ebi_config.cs[i].mode != EBI_CS_MODE_SDRAM_gc) {
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/* Configure */
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cs[i].CTRLA = ebi_config.cs[i].space;
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cs[i].CTRLB = ebi_config.cs[i].wait;
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cs[i].BASEADDR = ((ebi_config.cs[i].address >> 8) & 0xfff0);
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/* Enable */
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cs[i].CTRLA = ebi_config.cs[i].space | ebi_config.cs[i].mode;
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if (ebi_config.cs[i].address == 0) {
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expand_sram = 1;
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}
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}
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}
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/**
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* Only CS[3] can be configured as SDRAM.
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* CS structure is little bit different too.
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*/
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if (ebi_config.cs[3].mode == EBI_CS_MODE_SDRAM_gc) {
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cs[3].CTRLA = ebi_config.cs[3].space;
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cs[3].CTRLB = ebi_config.sdram.mode
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| (ebi_config.sdram.refresh ? EBI_CS_SDSREN_bm : 0);
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cs[3].BASEADDR = ((ebi_config.cs[3].address >> 8) & 0xfff0);
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cs[3].CTRLA = ebi_config.cs[3].space | ebi_config.cs[3].mode;
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if (ebi_config.cs[3].address == 0) {
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expand_sram = 1;
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}
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while (!(cs[3].CTRLB & EBI_CS_SDINITDONE_bm)) {};
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}
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if (expand_sram > 0) {
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/**
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* @brief Set new Stack Pointer
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*/
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__asm__ volatile (
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"out __SP_L__, %A[stack] \n\t"
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"out __SP_H__, %B[stack] \n\t"
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: /* no output */
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: [stack] "r"(RAM_LEN)
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: "memory"
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);
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};
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}
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uint16_t hugemem_read16(const hugemem_ptr_t from)
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{
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uint16_t value;
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__asm__ volatile (
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"movw r30, %A[from] \n\t"
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"out %[rampz], %C[from] \n\t"
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"ld %A[dest], Z+ \n\t"
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"ld %B[dest], Z \n\t"
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"out %[rampz], __zero_reg__ \n\t"
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: [dest] "=r"(value)
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: [from] "r"(from),
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[rampz] "i"(&RAMPZ)
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: "r30", "r31"
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);
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return value;
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}
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void hugemem_write16(hugemem_ptr_t to, uint16_t val)
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{
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__asm__ volatile (
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"movw r30, %A[to] \n\t"
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"out %[rampz], %C[to] \n\t"
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"st Z+, %A[val] \n\t"
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"st Z, %B[val] \n\t"
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"out %[rampz], __zero_reg__ \n\t"
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: /* no output */
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: [to] "r"(to),
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[val] "r"(val),
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[rampz] "i"(&RAMPZ)
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: "r30", "r31"
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);
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}
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uint32_t hugemem_read32(const hugemem_ptr_t from)
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{
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uint32_t value;
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__asm__ volatile (
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"movw r30, %A[from] \n\t"
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"out %[rampz], %C[from] \n\t"
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"ld %A[dest], Z+ \n\t"
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"ld %B[dest], Z+ \n\t"
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"ld %C[dest], Z+ \n\t"
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"ld %D[dest], Z \n\t"
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"out %[rampz], __zero_reg__ \n\t"
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: [dest] "=r"(value)
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: [from] "r"(from),
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[rampz] "i"(&RAMPZ)
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: "r30", "r31"
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);
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return value;
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}
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void hugemem_write32(hugemem_ptr_t to, uint32_t val)
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{
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__asm__ volatile (
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"movw r30, %A[to] \n\t"
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"out %[rampz], %C[to] \n\t"
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"st Z+, %A[val] \n\t"
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"st Z+, %B[val] \n\t"
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"st Z+, %C[val] \n\t"
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"st Z, %D[val] \n\t"
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"out %[rampz], __zero_reg__ \n\t"
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: /* no output */
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: [to] "r"(to),
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[val] "r"(val),
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[rampz] "i"(&RAMPZ)
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: "r30", "r31"
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);
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}
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void hugemem_read_block(void *to, const hugemem_ptr_t from, size_t size)
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{
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if (size > 0) {
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__asm__ volatile (
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"movw r30, %A[from] \n\t"
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"out %[rampz], %C[from] \n\t"
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"get_%=: \n\t"
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"ld __tmp_reg__, Z+ \n\t"
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"st X+, __tmp_reg__ \n\t"
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"sbiw %A[size], 1 \n\t"
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"brne get_%= \n\t"
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"out %[rampz], __zero_reg__ \n\t"
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: [to] "+x"(to),
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[size] "+w"(size)
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: [from] "r"(from),
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[rampz] "i"(&RAMPZ)
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: "r30", "r31"
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);
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}
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}
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void hugemem_write_block(hugemem_ptr_t to, const void *from, size_t size)
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{
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if (size > 0) {
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__asm__ volatile (
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"movw r30, %A[from] \n\t"
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"out %[rampz], %C[from] \n\t"
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"put_%=: \n\t"
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"ld __tmp_reg__, X+ \n\t"
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"st Z+, __tmp_reg__ \n\t"
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"sbiw %A[size], 1 \n\t"
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"brne put_%= \n\t"
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"out %[rampz], __zero_reg__ \n\t"
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: [from] "+x"(from),
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[size] "+w"(size)
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: [to] "r"(to),
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[rampz] "i"(&RAMPZ)
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: "r30", "r31"
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);
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}
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}
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