mirror of
https://github.com/RIOT-OS/RIOT.git
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477 lines
16 KiB
C
477 lines
16 KiB
C
/*
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* Copyright (C) 2021 Inria
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup boards_stm32f746g-disco
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* @{
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*
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* @file
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* @brief Configuration of CPU peripherals for STM32F746G-DISCO board
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*
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* @author Alexandre Abadie <alexandre.abadie@inria.fr>
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*/
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#ifndef PERIPH_CONF_H
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#define PERIPH_CONF_H
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/* This board provides an LSE */
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#ifndef CONFIG_BOARD_HAS_LSE
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#define CONFIG_BOARD_HAS_LSE 1
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#endif
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/* This board provides an HSE */
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#ifndef CONFIG_BOARD_HAS_HSE
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#define CONFIG_BOARD_HAS_HSE 1
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#endif
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/* The HSE provides a 25MHz clock */
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#ifndef CONFIG_CLOCK_HSE
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#define CONFIG_CLOCK_HSE MHZ(25)
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#endif
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#include <stdint.h>
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#include "periph_cpu.h"
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#include "clk_conf.h"
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#include "cfg_rtt_default.h"
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#include "cfg_timer_tim2.h"
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#if defined(MODULE_PERIPH_USBDEV_HS_ULPI)
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#include "usbdev_synopsys_dwc2.h"
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#else
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#include "cfg_usb_otg_fs.h"
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#endif
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#include "mii.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @name DMA streams configuration
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* @{
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*/
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static const dma_conf_t dma_config[] = {
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{ .stream = 15 }, /* DMA2 Stream 7 - USART1_TX */
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{ .stream = 14 }, /* DMA2 Stream 6 - USART6_TX */
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{ .stream = 6 }, /* DMA1 Stream 6 - USART2_TX */
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{ .stream = 3 }, /* DMA1 Stream 3 - SPI2_RX */
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{ .stream = 4 }, /* DMA1 Stream 4 - SPI2_TX */
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{ .stream = 11 }, /* DMA2 Stream 3 - SPI4_RX Ch5 / SDMMC1 Ch 4 */
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{ .stream = 12 }, /* DMA2 Stream 4 - SPI4_TX */
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{ .stream = 8 }, /* DMA2 Stream 0 - ETH_TX */
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};
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#define DMA_0_ISR isr_dma2_stream7
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#define DMA_1_ISR isr_dma2_stream6
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#define DMA_2_ISR isr_dma1_stream6
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#define DMA_3_ISR isr_dma2_stream2
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#define DMA_4_ISR isr_dma2_stream5
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#define DMA_5_ISR isr_dma2_stream3
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#define DMA_6_ISR isr_dma2_stream4
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#define DMA_7_ISR isr_dma2_stream0
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#define DMA_NUMOF ARRAY_SIZE(dma_config)
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/** @} */
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/**
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* @name UART configuration
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* @{
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*/
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static const uart_conf_t uart_config[] = {
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{
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.dev = USART1,
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.rcc_mask = RCC_APB2ENR_USART1EN,
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.rx_pin = GPIO_PIN(PORT_B, 7),
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.tx_pin = GPIO_PIN(PORT_A, 9),
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.rx_af = GPIO_AF7,
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.tx_af = GPIO_AF7,
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.bus = APB2,
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.irqn = USART1_IRQn,
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#ifdef MODULE_PERIPH_DMA
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.dma = 0,
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.dma_chan = 4
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#endif
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},
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{ /* Arduino connectors */
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.dev = USART6,
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.rcc_mask = RCC_APB2ENR_USART6EN,
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.rx_pin = GPIO_PIN(PORT_C, 6),
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.tx_pin = GPIO_PIN(PORT_C, 7),
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.rx_af = GPIO_AF7,
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.tx_af = GPIO_AF7,
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.bus = APB2,
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.irqn = USART6_IRQn,
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#ifdef MODULE_PERIPH_DMA
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.dma = 1,
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.dma_chan = 5
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#endif
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},
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};
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#define UART_0_ISR (isr_usart1)
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#define UART_0_DMA_ISR (isr_dma2_stream7)
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#define UART_6_ISR (isr_usart6)
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#define UART_6_DMA_ISR (isr_dma2_stream6)
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#define UART_NUMOF ARRAY_SIZE(uart_config)
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/** @} */
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/**
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* @name SPI configuration
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* @{
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*/
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static const spi_conf_t spi_config[] = {
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{
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.dev = SPI2,
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.mosi_pin = GPIO_PIN(PORT_B, 15),
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.miso_pin = GPIO_PIN(PORT_B, 14),
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.sclk_pin = GPIO_PIN(PORT_I, 1),
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.cs_pin = SPI_CS_UNDEF,
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.mosi_af = GPIO_AF5,
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.miso_af = GPIO_AF5,
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.sclk_af = GPIO_AF5,
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.cs_af = GPIO_AF5,
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.rccmask = RCC_APB1ENR_SPI2EN,
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.apbbus = APB1,
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#ifdef MODULE_PERIPH_DMA
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.tx_dma = 4,
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.tx_dma_chan = 0,
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.rx_dma = 3,
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.rx_dma_chan = 0,
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#endif
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},
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};
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#define SPI_NUMOF ARRAY_SIZE(spi_config)
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/** @} */
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/**
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* @name I2C configuration
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* @{
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*/
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static const i2c_conf_t i2c_config[] = {
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{
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.dev = I2C1,
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.speed = I2C_SPEED_NORMAL,
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.scl_pin = GPIO_PIN(PORT_B, 8),
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.sda_pin = GPIO_PIN(PORT_B, 9),
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.scl_af = GPIO_AF4,
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.sda_af = GPIO_AF4,
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.bus = APB1,
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.rcc_mask = RCC_APB1ENR_I2C1EN,
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.rcc_sw_mask = RCC_DCKCFGR2_I2C1SEL_1,
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.irqn = I2C1_ER_IRQn,
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},
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{
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.dev = I2C3,
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.speed = I2C_SPEED_NORMAL,
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.scl_pin = GPIO_PIN(PORT_H, 7),
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.sda_pin = GPIO_PIN(PORT_H, 8),
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.scl_af = GPIO_AF4,
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.sda_af = GPIO_AF4,
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.bus = APB1,
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.rcc_mask = RCC_APB1ENR_I2C3EN,
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.rcc_sw_mask = RCC_DCKCFGR2_I2C3SEL_1,
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.irqn = I2C3_ER_IRQn,
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},
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};
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#define I2C_0_ISR isr_i2c1_er
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#define I2C_1_ISR isr_i2c3_er
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#define I2C_NUMOF ARRAY_SIZE(i2c_config)
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/** @} */
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/**
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* @name ETH configuration
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* @{
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*/
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static const eth_conf_t eth_config = {
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.mode = RMII,
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.speed = MII_BMCR_SPEED_100 | MII_BMCR_FULL_DPLX,
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.dma = 7,
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.dma_chan = 8,
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.phy_addr = 0x00,
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.pins = {
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GPIO_PIN(PORT_G, 13), /* TXD0 */
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GPIO_PIN(PORT_G, 14), /* TXD1 */
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GPIO_PIN(PORT_G, 11), /* TX_EN */
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GPIO_PIN(PORT_C, 4), /* RXD0 */
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GPIO_PIN(PORT_C, 5), /* RXD1 */
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GPIO_PIN(PORT_A, 7), /* CRS_DV */
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GPIO_PIN(PORT_C, 1), /* MDC */
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GPIO_PIN(PORT_A, 2), /* MDIO */
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GPIO_PIN(PORT_A, 1), /* REF_CLK */
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}
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};
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#define ETH_DMA_ISR isr_dma2_stream0
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/** @} */
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/**
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* @name LTDC configuration
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* @{
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*/
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/** LTDC static configuration struct */
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static const ltdc_conf_t ltdc_config = {
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.bus = APB2,
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.rcc_mask = RCC_APB2ENR_LTDCEN,
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.clk_pin = { .pin = GPIO_PIN(PORT_I, 14), .af = GPIO_AF14, },
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.de_pin = { .pin = GPIO_PIN(PORT_K, 7), .af = GPIO_AF14, },
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.hsync_pin = { .pin = GPIO_PIN(PORT_I, 10), .af = GPIO_AF14, },
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.vsync_pin = { .pin = GPIO_PIN(PORT_I, 9), .af = GPIO_AF14, },
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.r_pin = {
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{ .pin = GPIO_PIN(PORT_I, 15), .af = GPIO_AF14, },
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{ .pin = GPIO_PIN(PORT_J, 0), .af = GPIO_AF14, },
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{ .pin = GPIO_PIN(PORT_J, 1), .af = GPIO_AF14, },
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{ .pin = GPIO_PIN(PORT_J, 2), .af = GPIO_AF14, },
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{ .pin = GPIO_PIN(PORT_J, 3), .af = GPIO_AF14, },
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{ .pin = GPIO_PIN(PORT_J, 4), .af = GPIO_AF14, },
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{ .pin = GPIO_PIN(PORT_J, 5), .af = GPIO_AF14, },
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{ .pin = GPIO_PIN(PORT_J, 6), .af = GPIO_AF14, },
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},
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.g_pin = {
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{ .pin = GPIO_PIN(PORT_J, 7), .af = GPIO_AF14, },
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{ .pin = GPIO_PIN(PORT_J, 8), .af = GPIO_AF14, },
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{ .pin = GPIO_PIN(PORT_J, 9), .af = GPIO_AF14, },
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{ .pin = GPIO_PIN(PORT_J, 10), .af = GPIO_AF14, },
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{ .pin = GPIO_PIN(PORT_J, 11), .af = GPIO_AF14, },
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{ .pin = GPIO_PIN(PORT_K, 0), .af = GPIO_AF14, },
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{ .pin = GPIO_PIN(PORT_K, 1), .af = GPIO_AF14, },
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{ .pin = GPIO_PIN(PORT_K, 2), .af = GPIO_AF14, },
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},
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.b_pin = {
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{ .pin = GPIO_PIN(PORT_E, 4), .af = GPIO_AF14, },
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{ .pin = GPIO_PIN(PORT_J, 13), .af = GPIO_AF14, },
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{ .pin = GPIO_PIN(PORT_J, 14), .af = GPIO_AF14, },
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{ .pin = GPIO_PIN(PORT_J, 15), .af = GPIO_AF14, },
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{ .pin = GPIO_PIN(PORT_G, 12), .af = GPIO_AF9, },
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{ .pin = GPIO_PIN(PORT_K, 4), .af = GPIO_AF14, },
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{ .pin = GPIO_PIN(PORT_K, 5), .af = GPIO_AF14, },
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{ .pin = GPIO_PIN(PORT_K, 6), .af = GPIO_AF14, },
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},
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/* values below come from STM32CubeF7 code and differ from the typical
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* values mentioned in the RK043FN48H datasheet. Both sets of values work
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* with the display.
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* See the discussion in
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* https://community.st.com/s/question/0D50X0000BOvdWP/how-to-set-displays-parameters-
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*/
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.hsync = 41,
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.vsync = 10,
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.hbp = 13,
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.hfp = 32,
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.vbp = 2,
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.vfp = 2,
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};
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/** @} */
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#if defined(MODULE_PERIPH_USBDEV_HS_ULPI) || DOXYGEN
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/**
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* @name USB OTG FS configuration using ULPI HS PHY
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*
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* The USB OTG HS peripheral uses a ULPI HS PHY. The configuration of the
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* ULPI HS PHY interface is board-specific.
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*
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* @{
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*/
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/**
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* @brief Enable the high speed USB OTG peripheral
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*/
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#define DWC2_USB_OTG_HS_ENABLED
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/**
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* @brief Common USB OTG HS configuration with ULPI HS PHY
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*/
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static const dwc2_usb_otg_fshs_config_t dwc2_usb_otg_fshs_config[] = {
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{
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.periph = USB_OTG_HS_PERIPH_BASE,
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.type = DWC2_USB_OTG_HS,
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.phy = DWC2_USB_OTG_PHY_ULPI,
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.rcc_mask = RCC_AHB1ENR_OTGHSEN,
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.irqn = OTG_HS_IRQn,
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.ahb = AHB1,
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.ulpi_af = GPIO_AF10,
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.ulpi_clk = GPIO_PIN(PORT_A, 5),
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.ulpi_d0 = GPIO_PIN(PORT_A, 3),
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.ulpi_d1 = GPIO_PIN(PORT_B, 0),
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.ulpi_d2 = GPIO_PIN(PORT_B, 1),
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.ulpi_d3 = GPIO_PIN(PORT_B, 10),
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.ulpi_d4 = GPIO_PIN(PORT_B, 11),
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.ulpi_d5 = GPIO_PIN(PORT_B, 12),
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.ulpi_d6 = GPIO_PIN(PORT_B, 13),
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.ulpi_d7 = GPIO_PIN(PORT_B, 5),
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.ulpi_dir = GPIO_PIN(PORT_C, 2),
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.ulpi_stp = GPIO_PIN(PORT_C, 0),
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.ulpi_nxt = GPIO_PIN(PORT_H, 4),
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}
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};
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/**
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* @brief Number of available USB OTG peripherals
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*/
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#define USBDEV_NUMOF ARRAY_SIZE(dwc2_usb_otg_fshs_config)
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/** @} */
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#endif /* defined(MODULE_PERIPH_USBDEV_HS_ULPI) || DOXYGEN */
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/**
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* @name FMC configuration
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* @{
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*/
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/**
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* @brief FMC controller configuration
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*/
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static const fmc_conf_t fmc_config = {
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.bus = AHB3,
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.rcc_mask = RCC_AHB3ENR_FMCEN,
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#if MODULE_PERIPH_FMC_SDRAM
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.ba0_pin = { .pin = GPIO_PIN(PORT_G, 4), .af = GPIO_AF12, }, /* FMC_BA0 signal */
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.ba1_pin = { .pin = GPIO_PIN(PORT_G, 5), .af = GPIO_AF12, }, /* FMC_BA1 signal */
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.sdclk_pin = { .pin = GPIO_PIN(PORT_G, 8), .af = GPIO_AF12, }, /* FMC_SDCLK signal */
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.sdnwe_pin = { .pin = GPIO_PIN(PORT_H, 5), .af = GPIO_AF12, }, /* FMC_SDNWE signal */
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.sdnras_pin = { .pin = GPIO_PIN(PORT_F, 11), .af = GPIO_AF12, }, /* FMC_SDNRAS signal */
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.sdncas_pin = { .pin = GPIO_PIN(PORT_G, 15), .af = GPIO_AF12, }, /* FMC_SDNCAS signal */
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.sdcke0_pin = { .pin = GPIO_PIN(PORT_C, 3), .af = GPIO_AF12, }, /* FMC_SDCKE0 signal */
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.sdne0_pin = { .pin = GPIO_PIN(PORT_H, 3), .af = GPIO_AF12, }, /* FMC_SDNE0 signal */
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.addr = {
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{ .pin = GPIO_PIN(PORT_F, 0), .af = GPIO_AF12, }, /* FMC_A0 signal */
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{ .pin = GPIO_PIN(PORT_F, 1), .af = GPIO_AF12, }, /* FMC_A1 signal */
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{ .pin = GPIO_PIN(PORT_F, 2), .af = GPIO_AF12, }, /* FMC_A2 signal */
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{ .pin = GPIO_PIN(PORT_F, 3), .af = GPIO_AF12, }, /* FMC_A3 signal */
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{ .pin = GPIO_PIN(PORT_F, 4), .af = GPIO_AF12, }, /* FMC_A4 signal */
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{ .pin = GPIO_PIN(PORT_F, 5), .af = GPIO_AF12, }, /* FMC_A5 signal */
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{ .pin = GPIO_PIN(PORT_F, 12), .af = GPIO_AF12, }, /* FMC_A6 signal */
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{ .pin = GPIO_PIN(PORT_F, 13), .af = GPIO_AF12, }, /* FMC_A7 signal */
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{ .pin = GPIO_PIN(PORT_F, 14), .af = GPIO_AF12, }, /* FMC_A8 signal */
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{ .pin = GPIO_PIN(PORT_F, 15), .af = GPIO_AF12, }, /* FMC_A9 signal */
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{ .pin = GPIO_PIN(PORT_G, 0), .af = GPIO_AF12, }, /* FMC_A10 signal */
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{ .pin = GPIO_PIN(PORT_G, 1), .af = GPIO_AF12, }, /* FMC_A11 signal */
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},
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#endif
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.data = {
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{ .pin = GPIO_PIN(PORT_D, 14), .af = GPIO_AF12, }, /* FMC_D0 signal */
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{ .pin = GPIO_PIN(PORT_D, 15), .af = GPIO_AF12, }, /* FMC_D1 signal */
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{ .pin = GPIO_PIN(PORT_D, 0), .af = GPIO_AF12, }, /* FMC_D2 signal */
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{ .pin = GPIO_PIN(PORT_D, 1), .af = GPIO_AF12, }, /* FMC_D3 signal */
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{ .pin = GPIO_PIN(PORT_E, 7), .af = GPIO_AF12, }, /* FMC_D4 signal */
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{ .pin = GPIO_PIN(PORT_E, 8), .af = GPIO_AF12, }, /* FMC_D5 signal */
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{ .pin = GPIO_PIN(PORT_E, 9), .af = GPIO_AF12, }, /* FMC_D6 signal */
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{ .pin = GPIO_PIN(PORT_E, 10), .af = GPIO_AF12, }, /* FMC_D7 signal */
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#if MODULE_PERIPH_FMC_16BIT
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{ .pin = GPIO_PIN(PORT_E, 11), .af = GPIO_AF12, }, /* FMC_D8 signal */
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{ .pin = GPIO_PIN(PORT_E, 12), .af = GPIO_AF12, }, /* FMC_D9 signal */
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{ .pin = GPIO_PIN(PORT_E, 13), .af = GPIO_AF12, }, /* FMC_D10 signal */
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{ .pin = GPIO_PIN(PORT_E, 14), .af = GPIO_AF12, }, /* FMC_D11 signal */
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{ .pin = GPIO_PIN(PORT_E, 15), .af = GPIO_AF12, }, /* FMC_D12 signal */
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{ .pin = GPIO_PIN(PORT_D, 8), .af = GPIO_AF12, }, /* FMC_D13 signal */
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{ .pin = GPIO_PIN(PORT_D, 9), .af = GPIO_AF12, }, /* FMC_D14 signal */
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{ .pin = GPIO_PIN(PORT_D, 10), .af = GPIO_AF12, }, /* FMC_D15 signal */
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#endif
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},
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.nbl0_pin = { .pin = GPIO_PIN(PORT_E, 0), .af = GPIO_AF12, }, /* FMC_NBL0 signal (LB) */
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.nbl1_pin = { .pin = GPIO_PIN(PORT_E, 1), .af = GPIO_AF12, }, /* FMC_NBL1 signal (UB) */
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};
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/**
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* @brief FMC Bank configuration
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*
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* The board has a SDRAM IS42S32400F-6BL with 128 MBit on-board.
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* It is organized in 4 banks of 1M x 32 bits each and connected to bank 5
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* at address 0xc0000000.
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*
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* @note Since only D0 to D15 are connected and D16 to D31 are unused, 4 banks
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* with only 1M x 16 bits and thus half the capacity (8 MByte) can be
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* used.
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*/
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static const fmc_bank_conf_t fmc_bank_config[] = {
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/* bank 5 is used for SDRAM */
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{
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.bank = FMC_BANK_5,
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.mem_type = FMC_SDRAM,
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.data_width = FMC_BUS_WIDTH_16BIT,
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.address = 0xc0000000, /* Bank 5 is mapped to 0xc0000000 */
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.size = MiB(8), /* Size in MByte, 4M x 16 Bit */
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.sdram = {
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.clk_period = 2, /* SDCLK = 2 x HCLK */
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.row_bits = 12, /* A11..A0 used for row address */
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.col_bits = 8, /* A7..A0 used for column address */
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.cas_latency = 2, /* CAS latency is 2 clock cycles */
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.read_delay = 0, /* No read delay after CAS */
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.burst_read = true, /* Burst read mode enabled */
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|
.burst_write = false, /* Burst write mode disabled */
|
|
.burst_len = FMC_BURST_LENGTH_1, /* Burst length is 1 */
|
|
.burst_interleaved = false, /* Burst mode interleaved */
|
|
.write_protect = false, /* No write protection */
|
|
.four_banks = true, /* SDRAM has four internal banks */
|
|
.timing = { /* SDRAM Timing parameters */
|
|
.row_to_col_delay = 2, /* Row to column delay (2 clock cycles) */
|
|
.row_precharge = 2, /* Row precharge delay (2 clock cycles) */
|
|
.recovery_delay = 2, /* Recovery delay is (2 clock cycles) */
|
|
.row_cylce = 7, /* Row cycle delay is (7 clock cycles) */
|
|
.self_refresh = 4, /* Self refresh time is (4 clock cycles) */
|
|
.exit_self_refresh = 7, /* Exit self-refresh delay (7 clock cycles) */
|
|
.load_mode_register = 2, /* Load Mode Register to Activate delay */
|
|
.refresh_period = 16, /* Refresh period in ms */
|
|
},
|
|
},
|
|
},
|
|
};
|
|
|
|
/**
|
|
* @brief Number of configured FMC banks
|
|
*/
|
|
#define FMC_BANK_NUMOF ARRAY_SIZE(fmc_bank_config)
|
|
/** @} */
|
|
|
|
/**
|
|
* @name SDIO/SDMMC configuration
|
|
* @{
|
|
*/
|
|
|
|
/**
|
|
* @brief SDIO/SDMMC static configuration struct
|
|
*/
|
|
static const sdmmc_conf_t sdmmc_config[] = {
|
|
{
|
|
.dev = SDMMC1,
|
|
.bus = APB2,
|
|
.rcc_mask = RCC_APB2ENR_SDMMC1EN,
|
|
.cd = GPIO_PIN(PORT_C, 13),
|
|
.cd_active = 0, /* CD pin is LOW active */
|
|
.cd_mode = GPIO_IN_PU, /* Pull-up R12 not soldered by default */
|
|
.clk = { GPIO_PIN(PORT_C, 12), GPIO_AF12 },
|
|
.cmd = { GPIO_PIN(PORT_D, 2), GPIO_AF12 },
|
|
.dat0 = { GPIO_PIN(PORT_C, 8), GPIO_AF12 },
|
|
.dat1 = { GPIO_PIN(PORT_C, 9), GPIO_AF12 },
|
|
.dat2 = { GPIO_PIN(PORT_C, 10), GPIO_AF12 },
|
|
.dat3 = { GPIO_PIN(PORT_C, 11), GPIO_AF12 },
|
|
#ifdef MODULE_PERIPH_DMA
|
|
.dma = 5,
|
|
.dma_chan = 4,
|
|
#endif
|
|
.irqn = SDMMC1_IRQn
|
|
},
|
|
};
|
|
|
|
/**
|
|
* @brief Number of configured SDIO/SDMMC peripherals
|
|
*/
|
|
#define SDMMC_CONFIG_NUMOF 1
|
|
|
|
/** @} */
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#endif /* PERIPH_CONF_H */
|
|
/** @} */
|