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https://github.com/RIOT-OS/RIOT.git
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265 lines
7.0 KiB
C
265 lines
7.0 KiB
C
/*
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* Copyright (C) 2020 ML!PA Consulting GmbH
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup boards_samd10-xmini
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* @{
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*
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* @file
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* @brief Configuration of CPU peripherals for the Atmel SAM D10 Xplained
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* Mini board
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*
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* @author Benjamin Valentin <benjamin.valentin@ml-pa.com>
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*/
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#ifndef PERIPH_CONF_H
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#define PERIPH_CONF_H
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#include <stdint.h>
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#include "cpu.h"
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#include "periph_cpu.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @name External oscillator and clock configuration
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*
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* There are three choices for selection of CORECLOCK:
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*
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* - usage of the 48 MHz DFLL fed by external oscillator running at 32 kHz
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* - usage of the PLL fed by the internal 8MHz oscillator divided by 8
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* - usage of the internal 8MHz oscillator directly, divided by N if needed
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*
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*
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* The PLL option allows for the usage of a wider frequency range and a more
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* stable clock with less jitter. This is why this option is default.
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*
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* The target frequency is computed from the PLL multiplier and the PLL divisor.
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* Use the following formula to compute your values:
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*
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* CORECLOCK = ((PLL_MUL + 1) * 1MHz) / PLL_DIV
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*
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* NOTE: The PLL circuit does not run with less than 32MHz while the maximum PLL
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* frequency is 96MHz. So PLL_MULL must be between 31 and 95!
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*
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*
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* The internal Oscillator used directly can lead to a slightly better power
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* efficiency to the cost of a less stable clock. Use this option when you know
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* what you are doing! The actual core frequency is adjusted as follows:
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*
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* CORECLOCK = 8MHz / DIV
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*
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* NOTE: A core clock frequency below 1MHz is not recommended
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*
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* @{
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*/
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#define CLOCK_USE_PLL (1)
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#define CLOCK_USE_XOSC32_DFLL (0)
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/*
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* 0: use XOSC32K (always 32.768kHz) to clock GCLK2
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* 1: use OSCULP32K factory calibrated (~32.768kHz) to clock GCLK2
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*
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* OSCULP32K is factory calibrated to be around 32.768kHz but this values can
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* be of by a couple off % points, so prefer XOSC32K as default configuration.
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*/
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#define GEN2_ULP32K (1)
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#if CLOCK_USE_PLL
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/* edit these values to adjust the PLL output frequency */
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#define CLOCK_PLL_MUL (47U) /* must be >= 31 & <= 95 */
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#define CLOCK_PLL_DIV (1U) /* adjust to your needs */
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/* generate the actual used core clock frequency */
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#define CLOCK_CORECLOCK (((CLOCK_PLL_MUL + 1) * 1000000U) / CLOCK_PLL_DIV)
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#elif CLOCK_USE_XOSC32_DFLL
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/* Settings for 32 kHz external oscillator and 48 MHz DFLL */
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#define CLOCK_CORECLOCK (48000000U)
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#define CLOCK_XOSC32K (32768UL)
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#define CLOCK_8MHZ (1)
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#else
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/* edit this value to your needs */
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#define CLOCK_DIV (1U)
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/* generate the actual core clock frequency */
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#define CLOCK_CORECLOCK (8000000 / CLOCK_DIV)
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#endif
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/** @} */
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/**
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* @name Timer peripheral configuration
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* @{
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*/
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static const tc32_conf_t timer_config[] = {
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{ /* Timer 0 - System Clock */
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.dev = TC1,
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.irq = TC1_IRQn,
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.pm_mask = PM_APBCMASK_TC1 | PM_APBCMASK_TC2,
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.gclk_ctrl = GCLK_CLKCTRL_ID_TC1_TC2,
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#if CLOCK_USE_PLL || CLOCK_USE_XOSC32_DFLL
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.gclk_src = SAM0_GCLK_1MHZ,
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#else
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.gclk_src = SAM0_GCLK_MAIN,
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#endif
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.flags = TC_CTRLA_MODE_COUNT32,
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},
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};
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#define TIMER_0_MAX_VALUE 0xffffffff
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/* interrupt function name mapping */
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#define TIMER_0_ISR isr_tc1
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#define TIMER_NUMOF ARRAY_SIZE(timer_config)
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/** @} */
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/**
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* @name UART configuration
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* @{
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*/
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static const uart_conf_t uart_config[] = {
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{ /* Virtual COM Port */
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.dev = &SERCOM0->USART,
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.rx_pin = GPIO_PIN(PA, 11),
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.tx_pin = GPIO_PIN(PA, 10),
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#ifdef MODULE_PERIPH_UART_HW_FC
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.rts_pin = GPIO_UNDEF,
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.cts_pin = GPIO_UNDEF,
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#endif
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.mux = GPIO_MUX_C,
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.rx_pad = UART_PAD_RX_3,
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.tx_pad = UART_PAD_TX_2,
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.flags = UART_FLAG_NONE,
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.gclk_src = SAM0_GCLK_MAIN,
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},
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};
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/* interrupt function name mapping */
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#define UART_0_ISR isr_sercom0
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#define UART_NUMOF ARRAY_SIZE(uart_config)
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/** @} */
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/**
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* @name PWM configuration
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* @{
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*/
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#define PWM_0_EN 1
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#if PWM_0_EN
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/* PWM0 channels */
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static const pwm_conf_chan_t pwm_chan0_config[] = {
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/* GPIO pin, MUX value, TCC channel */
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{ GPIO_PIN(PA, 17), GPIO_MUX_F, 7 },
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{ GPIO_PIN(PA, 22), GPIO_MUX_F, 4 },
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{ GPIO_PIN(PA, 23), GPIO_MUX_F, 5 },
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{ GPIO_PIN(PA, 24), GPIO_MUX_E, 2 },
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};
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#endif
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/* PWM device configuration */
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static const pwm_conf_t pwm_config[] = {
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#if PWM_0_EN
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{TCC_CONFIG(TCC0), pwm_chan0_config, ARRAY_SIZE(pwm_chan0_config), SAM0_GCLK_MAIN},
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#endif
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};
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/* number of devices that are actually defined */
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#define PWM_NUMOF ARRAY_SIZE(pwm_config)
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/** @} */
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/**
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* @name SPI configuration
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* @{
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*/
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static const spi_conf_t spi_config[] = {
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{ /* SPI header */
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.dev = &SERCOM1->SPI,
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.miso_pin = GPIO_PIN(PA, 24),
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.mosi_pin = GPIO_PIN(PA, 22),
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.clk_pin = GPIO_PIN(PA, 9),
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.miso_mux = GPIO_MUX_C,
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.mosi_mux = GPIO_MUX_C,
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.clk_mux = GPIO_MUX_C,
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.miso_pad = SPI_PAD_MISO_2,
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.mosi_pad = SPI_PAD_MOSI_0_SCK_3,
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.gclk_src = SAM0_GCLK_MAIN,
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},
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};
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#define SPI_NUMOF ARRAY_SIZE(spi_config)
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/** @} */
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/**
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* @name I2C configuration
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* @{
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*/
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static const i2c_conf_t i2c_config[] = {
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{
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.dev = &(SERCOM2->I2CM),
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.speed = I2C_SPEED_NORMAL,
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.scl_pin = GPIO_PIN(PA, 15),
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.sda_pin = GPIO_PIN(PA, 14),
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.mux = GPIO_MUX_D,
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.gclk_src = SAM0_GCLK_MAIN,
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.flags = I2C_FLAG_NONE
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}
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};
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#define I2C_NUMOF ARRAY_SIZE(i2c_config)
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/** @} */
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/**
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* @name RTT configuration
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* @{
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*/
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#ifndef RTT_FREQUENCY
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#define RTT_FREQUENCY (32768U) /* in Hz. For changes see `rtt.c` */
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#endif
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/** @} */
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/**
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* @name ADC Configuration
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* @{
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*/
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/* ADC Default values */
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#define ADC_PRESCALER ADC_CTRLB_PRESCALER_DIV512
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#define ADC_NEG_INPUT ADC_INPUTCTRL_MUXNEG_GND
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#define ADC_GAIN_FACTOR_DEFAULT ADC_INPUTCTRL_GAIN_1X
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#define ADC_REF_DEFAULT ADC_REFCTRL_REFSEL_INT1V
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static const adc_conf_chan_t adc_channels[] = {
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/* port, pin, muxpos */
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{ .inputctrl = ADC_INPUTCTRL_MUXPOS_PA02 },
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{ .inputctrl = ADC_INPUTCTRL_MUXPOS_PA03 },
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{ .inputctrl = ADC_INPUTCTRL_MUXPOS_PA04 },
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{ .inputctrl = ADC_INPUTCTRL_MUXPOS_PA05 },
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{ .inputctrl = ADC_INPUTCTRL_MUXPOS_PA06 },
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{ .inputctrl = ADC_INPUTCTRL_MUXPOS_PA07 },
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};
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#define ADC_NUMOF ARRAY_SIZE(adc_channels)
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/** @} */
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/**
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* @name DAC configuration
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* @{
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*/
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#define DAC_CLOCK SAM0_GCLK_1MHZ
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/* use Vcc as reference voltage */
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#define DAC_VREF DAC_CTRLB_REFSEL_AVCC
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#endif /* PERIPH_CONF_H */
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/** @} */
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