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https://github.com/RIOT-OS/RIOT.git
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504db007db
Reorder ADC lines to put the external connections first in the list. Remove VREFH, VREFL signals. Add single ended reading of ADC0_DP
77 lines
1.4 KiB
C
77 lines
1.4 KiB
C
/*
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* Copyright (C) 2017 Eistec AB
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup boards_frdm-kw41z
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* @{
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*
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* @file
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* @brief Board specific configuration of direct mapped ADC
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*
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* @author Joakim Nohlgård <joakim.nohlgard@eistec.se>
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*/
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#ifndef ADC_PARAMS_H
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#define ADC_PARAMS_H
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#include "board.h"
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#include "saul/periph.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief ADC configuration
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*/
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static const saul_adc_params_t saul_adc_params[] =
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{
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{
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.name = "ADC0_DP-DM",
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.line = ADC_LINE(0),
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.res = ADC_RES_16BIT,
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},
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{
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.name = "ADC0_DP",
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.line = ADC_LINE(1),
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.res = ADC_RES_16BIT,
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},
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{
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.name = "PTB2",
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.line = ADC_LINE(2),
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.res = ADC_RES_16BIT,
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},
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{
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.name = "PTB3",
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.line = ADC_LINE(3),
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.res = ADC_RES_16BIT,
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},
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{
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.name = "coretemp",
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.line = ADC_LINE(4),
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.res = ADC_RES_16BIT,
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},
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{
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.name = "corebandgap",
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.line = ADC_LINE(5),
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.res = ADC_RES_16BIT,
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},
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{
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.name = "dcdcvbat",
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.line = ADC_LINE(6),
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.res = ADC_RES_16BIT,
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},
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};
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#ifdef __cplusplus
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}
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#endif
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#endif /* ADC_PARAMS_H */
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/** @} */
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