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6c91865916
Following best practice, this patch adds the module's header as its first include. Resulting compiler errors are also fixed by adding the header's missing include of cpu_conf.h.
273 lines
8.3 KiB
C
273 lines
8.3 KiB
C
/*
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* Copyright (C) 2016 Freie Universität Berlin
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* 2017 OTA keys S.A.
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_stm32
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* @{
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*
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* @file
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* @brief Common CPU definitions for the STM32 family
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*
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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* @author Vincent Dupont <vincent@otakeys.com>
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*/
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#ifndef PERIPH_CPU_COMMON_H
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#define PERIPH_CPU_COMMON_H
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#include <stdint.h>
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#include "cpu_conf.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifdef Doxygen
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/**
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* @brief Starting address of the ROM bootloader
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* see application note AN2606
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*/
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#define STM32_BOOTLOADER_ADDR
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#endif
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/**
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* @brief Length of the CPU_ID in octets
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*
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* This is the same for all members of the stm32 family
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*/
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#define CPUID_LEN (12U)
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/**
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* @brief Starting address of the CPU ID
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*/
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#ifndef CPUID_ADDR
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#define CPUID_ADDR (UID_BASE)
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#endif
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/**
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* @brief CPU specific LSI clock speed
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*/
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#if defined(CPU_FAM_STM32F0) || defined (CPU_FAM_STM32F1) || \
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defined(CPU_FAM_STM32F3)
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#define CLOCK_LSI (40000U)
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#elif defined(CPU_FAM_STM32L0) || defined(CPU_FAM_STM32L1)
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#define CLOCK_LSI (37000U)
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#elif defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4) || \
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defined(CPU_FAM_STM32F7) || defined(CPU_FAM_STM32L4) || \
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defined(CPU_FAM_STM32WB) || defined(CPU_FAM_STM32G4) || \
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defined(CPU_FAM_STM32G0) || defined(CPU_FAM_STM32L5) || \
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defined(CPU_FAM_STM32U5) || defined(CPU_FAM_STM32MP1) || \
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defined(CPU_FAM_STM32WL) || defined(CPU_FAM_STM32C0)
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#define CLOCK_LSI (32000U)
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#else
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#error "error: LSI clock speed not defined for your target CPU"
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#endif
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/* if CPU has APB1 bus */
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#if defined(CPU_FAM_STM32G4) || \
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defined(CPU_FAM_STM32L4) || \
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defined(CPU_FAM_STM32L5) || \
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defined(CPU_FAM_STM32U5) || \
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defined(CPU_FAM_STM32WB) || \
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defined(CPU_FAM_STM32WL)
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#define APB1_PERIPH_EN RCC->APB1ENR1
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#define APB12_PERIPH_EN RCC->APB1ENR2
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#elif defined(CPU_FAM_STM32C0) || \
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defined(CPU_FAM_STM32G0)
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#define APB1_PERIPH_EN RCC->APBENR1
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#define APB12_PERIPH_EN RCC->APBENR2
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#elif defined(CPU_FAM_STM32MP1)
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#define APB1_PERIPH_EN RCC->MC_APB1ENSETR
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#define APB1_PERIPH_DIS RCC->MC_APB1ENCLRR
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#elif defined(APB1PERIPH_BASE) || \
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defined(CPU_FAM_STM32F0) || \
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defined(CPU_FAM_STM32L0)
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#define APB1_PERIPH_EN RCC->APB1ENR
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#endif
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/* if CPU has APB2 bus */
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#if defined(CPU_FAM_STM32MP1)
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#define APB2_PERIPH_EN RCC->MC_APB2ENSETR
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#define APB2_PERIPH_DIS RCC->MC_APB2ENCLRR
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#elif defined(APB2PERIPH_BASE) || \
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defined(CPU_FAM_STM32F0) || \
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defined(CPU_FAM_STM32L0)
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#define APB2_PERIPH_EN RCC->APB2ENR
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#endif
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/* if CPU has APB3 bus */
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#if defined(CPU_FAM_STM32WB)
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/* CPU has APB3, but no periph enable registers for the bus. */
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#undef APB3_PERIPH_EN /* not defined */
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#elif defined(APB3PERIPH_BASE) || \
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defined(APB3PERIPH_BASE_S)
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#define APB3_PERIPH_EN RCC->APB3ENR
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#endif
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/* if CPU has AHB/AHB1 bus */
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#if defined(AHBPERIPH_BASE) || \
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defined(CPU_FAM_STM32F3)
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#define AHB_PERIPH_EN RCC->AHBENR
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#elif defined(CPU_FAM_STM32MP1)
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/* CPU has AHB1, but no periph enable registers for the bus. */
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#undef AHB1_PERIPH_EN /* not defined */
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#undef AHB1_PERIPH_DIS /* not defined */
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#elif defined(AHB1PERIPH_BASE)
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#define AHB1_PERIPH_EN RCC->AHB1ENR
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#endif
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/* if CPU has AHB2 bus */
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#if defined(CPU_FAM_STM32F0) || \
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defined(CPU_FAM_STM32F3)
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/* CPU has AHB2, but no periph enable registers for the bus. */
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#undef AHB2_PERIPH_EN /* not defined */
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#elif defined(CPU_FAM_STM32U5)
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#define AHB2_PERIPH_EN RCC->AHB2ENR1
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#define AHB22_PERIPH_EN RCC->AHB2ENR2
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#elif defined(CPU_FAM_STM32F4) && defined(RCC_AHB2_SUPPORT)
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#define AHB2_PERIPH_EN RCC->AHB2ENR
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#elif defined(CPU_FAM_STM32MP1)
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#define AHB2_PERIPH_EN RCC->MC_AHB2ENSETR
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#define AHB2_PERIPH_DIS RCC->MC_AHB2ENCLRR
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#elif defined(AHB2PERIPH_BASE)
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#define AHB2_PERIPH_EN RCC->AHB2ENR
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#endif
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/* if CPU has AHB3 bus */
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#if defined(CPU_FAM_STM32F3)
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/* CPU has AHB3, but no periph enable registers for the bus. */
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#undef AHB3_PERIPH_EN /* not defined */
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#elif defined(CPU_FAM_STM32F4) && defined(RCC_AHB3_SUPPORT)
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#define AHB3_PERIPH_EN RCC->AHB3ENR
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#elif defined(CPU_FAM_STM32MP1)
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#define AHB3_PERIPH_EN RCC->MC_AHB3ENSETR
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#define AHB3_PERIPH_DIS RCC->MC_AHB3ENCLRR
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#elif defined(AHB3PERIPH_BASE) || \
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defined(AHB3PERIPH_BASE_S) || \
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defined(CPU_FAM_STM32F2) || \
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defined(CPU_FAM_STM32F7) || \
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defined(CPU_FAM_STM32G4) || \
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defined(CPU_FAM_STM32L4)
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#define AHB3_PERIPH_EN RCC->AHB3ENR
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#endif
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/* if CPU has AHB4 bus */
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#if defined(CPU_FAM_STM32MP1)
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#define AHB4_PERIPH_EN RCC->MC_AHB4ENSETR
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#define AHB4_PERIPH_DIS RCC->MC_AHB4ENCLRR
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#elif defined(AHB4PERIPH_BASE)
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/* AHB3ENR is not a typo here. It controls both AHB3 and AHB4. */
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#define AHB4_PERIPH_EN RCC->AHB3ENR
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#endif
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/* if CPU has IOP bus */
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#if defined(IOPPERIPH_BASE) || \
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defined(RCC_IOPENR_GPIOAEN) || \
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defined(RCC_IOPENR_IOPAEN)
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#define IOP_PERIPH_EN RCC->IOPENR
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#endif
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/**
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* @brief Available peripheral buses
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*/
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typedef enum {
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#if defined(APB1_PERIPH_EN)
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APB1, /**< APB1 bus */
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#endif
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#if defined(APB12_PERIPH_EN)
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APB12, /**< AHB1 bus, second register */
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#endif
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#if defined(APB2_PERIPH_EN)
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APB2, /**< APB2 bus */
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#endif
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#if defined(APB3_PERIPH_EN)
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APB3, /**< APB3 bus */
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#endif
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#if defined(AHB_PERIPH_EN)
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AHB, /**< AHB bus */
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#endif
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#if defined(AHB1_PERIPH_EN)
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AHB1, /**< AHB1 bus */
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#endif
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#if defined(AHB2_PERIPH_EN)
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AHB2, /**< AHB2 bus */
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#endif
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#if defined(AHB22_PERIPH_EN)
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AHB22, /**< AHB2 bus, second register */
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#endif
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#if defined(AHB3_PERIPH_EN)
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AHB3, /**< AHB3 bus */
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#endif
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#if defined(AHB4_PERIPH_EN)
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AHB4, /**< AHB4 bus */
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#endif
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#if defined(IOP_PERIPH_EN)
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IOP, /**< IOP bus */
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#endif
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BUS_NUMOF /**< number of buses */
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} bus_t;
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/**
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* @brief Get the actual bus clock frequency for the APB buses
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*
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* @param[in] bus target APBx bus
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*
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* @return bus clock frequency in Hz
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*/
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uint32_t periph_apb_clk(bus_t bus);
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/**
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* @brief Get the actual timer clock frequency
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*
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* @param[in] bus corresponding APBx bus
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*
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* @return timer clock frequency in Hz
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*/
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uint32_t periph_timer_clk(bus_t bus);
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/**
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* @brief Enable the given peripheral clock
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*
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* @param[in] bus bus the peripheral is connected to
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* @param[in] mask bit in the RCC enable register
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*/
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void periph_clk_en(bus_t bus, uint32_t mask);
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/**
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* @brief Disable the given peripheral clock
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*
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* @param[in] bus bus the peripheral is connected to
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* @param[in] mask bit in the RCC enable register
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*/
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void periph_clk_dis(bus_t bus, uint32_t mask);
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/**
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* @brief Enable the given peripheral clock in low power mode
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*
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* @param[in] bus bus the peripheral is connected to
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* @param[in] mask bit in the RCC enable register
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*/
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void periph_lpclk_en(bus_t bus, uint32_t mask);
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/**
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* @brief Disable the given peripheral clock in low power mode
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*
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* @param[in] bus bus the peripheral is connected to
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* @param[in] mask bit in the RCC enable register
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*/
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void periph_lpclk_dis(bus_t bus, uint32_t mask);
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#ifdef __cplusplus
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}
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#endif
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#endif /* PERIPH_CPU_COMMON_H */
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/** @} */
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