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https://github.com/RIOT-OS/RIOT.git
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258 lines
15 KiB
C
258 lines
15 KiB
C
/*
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* Copyright (C) 2020
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_stm32
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* @{
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*
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* @file
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* @brief Interrupt vector definitions for STM32G4
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*
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* @author Alexandre Abadie <alexandre.abadie@inria.fr>
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*
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* @}
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*/
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#include "vectors_cortexm.h"
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/* define a local dummy handler as it needs to be in the same compilation unit
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* as the alias definition */
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void dummy_handler(void) {
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dummy_handler_default();
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}
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/* STM32L4 specific interrupt vectors */
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WEAK_DEFAULT void isr_adc1(void);
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WEAK_DEFAULT void isr_adc1_2(void);
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WEAK_DEFAULT void isr_adc3(void);
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WEAK_DEFAULT void isr_adc4(void);
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WEAK_DEFAULT void isr_adc5(void);
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WEAK_DEFAULT void isr_can1_rx0(void);
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WEAK_DEFAULT void isr_can1_rx1(void);
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WEAK_DEFAULT void isr_can1_sce(void);
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WEAK_DEFAULT void isr_can1_tx(void);
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WEAK_DEFAULT void isr_can2_rx0(void);
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WEAK_DEFAULT void isr_can2_rx1(void);
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WEAK_DEFAULT void isr_can2_sce(void);
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WEAK_DEFAULT void isr_can2_tx(void);
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WEAK_DEFAULT void isr_comp1_2_3(void);
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WEAK_DEFAULT void isr_comp4_5_6(void);
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WEAK_DEFAULT void isr_comp7(void);
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WEAK_DEFAULT void isr_cordic(void);
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WEAK_DEFAULT void isr_crs(void);
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WEAK_DEFAULT void isr_dcmi(void);
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WEAK_DEFAULT void isr_dfsdm1_flt0(void);
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WEAK_DEFAULT void isr_dfsdm1_flt1(void);
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WEAK_DEFAULT void isr_dfsdm1_flt2(void);
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WEAK_DEFAULT void isr_dfsdm1_flt3(void);
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WEAK_DEFAULT void isr_dmamux(void);
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WEAK_DEFAULT void isr_dma1_channel1(void);
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WEAK_DEFAULT void isr_dma1_channel2(void);
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WEAK_DEFAULT void isr_dma1_channel3(void);
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WEAK_DEFAULT void isr_dma1_channel4(void);
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WEAK_DEFAULT void isr_dma1_channel5(void);
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WEAK_DEFAULT void isr_dma1_channel6(void);
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WEAK_DEFAULT void isr_dma1_channel7(void);
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WEAK_DEFAULT void isr_dma1_channel8(void);
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WEAK_DEFAULT void isr_dma2_channel1(void);
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WEAK_DEFAULT void isr_dma2_channel2(void);
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WEAK_DEFAULT void isr_dma2_channel3(void);
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WEAK_DEFAULT void isr_dma2_channel4(void);
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WEAK_DEFAULT void isr_dma2_channel5(void);
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WEAK_DEFAULT void isr_dma2_channel6(void);
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WEAK_DEFAULT void isr_dma2_channel7(void);
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WEAK_DEFAULT void isr_dma2_channel8(void);
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WEAK_DEFAULT void isr_dma2d(void);
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WEAK_DEFAULT void isr_dmamux1_ovr(void);
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WEAK_DEFAULT void isr_exti(void);
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WEAK_DEFAULT void isr_fdcan1_it0(void);
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WEAK_DEFAULT void isr_fdcan1_it1(void);
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WEAK_DEFAULT void isr_fdcan2_it0(void);
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WEAK_DEFAULT void isr_fdcan2_it1(void);
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WEAK_DEFAULT void isr_fdcan3_it0(void);
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WEAK_DEFAULT void isr_fdcan3_it1(void);
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WEAK_DEFAULT void isr_flash(void);
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WEAK_DEFAULT void isr_fmc(void);
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WEAK_DEFAULT void isr_fmac(void);
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WEAK_DEFAULT void isr_fpu(void);
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WEAK_DEFAULT void isr_hrtim1_flt(void);
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WEAK_DEFAULT void isr_hrtim1_master(void);
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WEAK_DEFAULT void isr_hrtim1_tima(void);
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WEAK_DEFAULT void isr_hrtim1_timb(void);
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WEAK_DEFAULT void isr_hrtim1_timc(void);
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WEAK_DEFAULT void isr_hrtim1_timd(void);
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WEAK_DEFAULT void isr_hrtim1_time(void);
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WEAK_DEFAULT void isr_hrtim1_timf(void);
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WEAK_DEFAULT void isr_i2c1_er(void);
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WEAK_DEFAULT void isr_i2c1_ev(void);
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WEAK_DEFAULT void isr_i2c2_er(void);
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WEAK_DEFAULT void isr_i2c2_ev(void);
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WEAK_DEFAULT void isr_i2c3_er(void);
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WEAK_DEFAULT void isr_i2c3_ev(void);
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WEAK_DEFAULT void isr_i2c4_ev(void);
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WEAK_DEFAULT void isr_i2c4_er(void);
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WEAK_DEFAULT void isr_lcd(void);
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WEAK_DEFAULT void isr_lptim1(void);
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WEAK_DEFAULT void isr_lptim2(void);
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WEAK_DEFAULT void isr_lpuart1(void);
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WEAK_DEFAULT void isr_octospi1(void);
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WEAK_DEFAULT void isr_octospi2(void);
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WEAK_DEFAULT void isr_otg_fs(void);
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WEAK_DEFAULT void isr_pvd_pvm(void);
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WEAK_DEFAULT void isr_quadspi(void);
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WEAK_DEFAULT void isr_rcc(void);
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WEAK_DEFAULT void isr_rng(void);
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WEAK_DEFAULT void isr_rtc_alarm(void);
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WEAK_DEFAULT void isr_rtc_tamp_lsecss(void);
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WEAK_DEFAULT void isr_rtc_wkup(void);
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WEAK_DEFAULT void isr_sai1(void);
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WEAK_DEFAULT void isr_sai2(void);
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WEAK_DEFAULT void isr_sdmmc1(void);
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WEAK_DEFAULT void isr_spi1(void);
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WEAK_DEFAULT void isr_spi2(void);
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WEAK_DEFAULT void isr_spi3(void);
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WEAK_DEFAULT void isr_spi4(void);
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WEAK_DEFAULT void isr_swpmi1(void);
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WEAK_DEFAULT void isr_tim1_brk_tim15(void);
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WEAK_DEFAULT void isr_tim1_cc(void);
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WEAK_DEFAULT void isr_tim1_trg_com(void);
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WEAK_DEFAULT void isr_tim1_trg_com_tim17(void);
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WEAK_DEFAULT void isr_tim1_up_tim16(void);
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WEAK_DEFAULT void isr_tim2(void);
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WEAK_DEFAULT void isr_tim3(void);
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WEAK_DEFAULT void isr_tim4(void);
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WEAK_DEFAULT void isr_tim5(void);
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WEAK_DEFAULT void isr_tim6_dac(void);
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WEAK_DEFAULT void isr_tim7_dac(void);
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WEAK_DEFAULT void isr_tim8_brk(void);
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WEAK_DEFAULT void isr_tim8_cc(void);
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WEAK_DEFAULT void isr_tim8_trg_com(void);
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WEAK_DEFAULT void isr_tim8_up(void);
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WEAK_DEFAULT void isr_tim20_brk(void);
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WEAK_DEFAULT void isr_tim20_up(void);
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WEAK_DEFAULT void isr_tim20_trg_com(void);
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WEAK_DEFAULT void isr_tim20_cc(void);
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WEAK_DEFAULT void isr_tsc(void);
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WEAK_DEFAULT void isr_uart4(void);
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WEAK_DEFAULT void isr_uart5(void);
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WEAK_DEFAULT void isr_ucpd1(void);
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WEAK_DEFAULT void isr_usart1(void);
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WEAK_DEFAULT void isr_usart2(void);
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WEAK_DEFAULT void isr_usart3(void);
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WEAK_DEFAULT void isr_usb(void);
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WEAK_DEFAULT void isr_usb_hp(void);
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WEAK_DEFAULT void isr_usb_lp(void);
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WEAK_DEFAULT void isr_usbwakeup(void);
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WEAK_DEFAULT void isr_wwdg(void);
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/* CPU specific interrupt vector table */
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ISR_VECTOR(1) const isr_t vector_cpu[CPU_IRQ_NUMOF] = {
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/* shared vectors for all family members */
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[WWDG_IRQn ] = isr_wwdg, /* [ 0] Window WatchDog Interrupt */
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[PVD_PVM_IRQn ] = isr_pvd_pvm, /* [ 1] PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection Interrupts */
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[RTC_TAMP_LSECSS_IRQn ] = isr_rtc_tamp_lsecss, /* [ 2] RTC Tamper and TimeStamp and RCC LSE CSS interrupts through the EXTI */
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[RTC_WKUP_IRQn ] = isr_rtc_wkup, /* [ 3] RTC Wakeup interrupt through the EXTI line */
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[FLASH_IRQn ] = isr_flash, /* [ 4] FLASH global Interrupt */
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[RCC_IRQn ] = isr_rcc, /* [ 5] RCC global Interrupt */
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[EXTI0_IRQn ] = isr_exti, /* [ 6] EXTI Line0 Interrupt */
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[EXTI1_IRQn ] = isr_exti, /* [ 7] EXTI Line1 Interrupt */
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[EXTI2_IRQn ] = isr_exti, /* [ 8] EXTI Line2 Interrupt */
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[EXTI3_IRQn ] = isr_exti, /* [ 9] EXTI Line3 Interrupt */
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[EXTI4_IRQn ] = isr_exti, /* [10] EXTI Line4 Interrupt */
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[DMA1_Channel1_IRQn ] = isr_dma1_channel1, /* [11] DMA1 Channel 1 global Interrupt */
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[DMA1_Channel2_IRQn ] = isr_dma1_channel2, /* [12] DMA1 Channel 2 global Interrupt */
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[DMA1_Channel3_IRQn ] = isr_dma1_channel3, /* [13] DMA1 Channel 3 global Interrupt */
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[DMA1_Channel4_IRQn ] = isr_dma1_channel4, /* [14] DMA1 Channel 4 global Interrupt */
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[DMA1_Channel5_IRQn ] = isr_dma1_channel5, /* [15] DMA1 Channel 5 global Interrupt */
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[DMA1_Channel6_IRQn ] = isr_dma1_channel6, /* [16] DMA1 Channel 6 global Interrupt */
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[DMA1_Channel7_IRQn ] = isr_dma1_channel7, /* [17] DMA1 Channel 7 global Interrupt */
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[ADC1_2_IRQn ] = isr_adc1_2, /* [18] ADC1, ADC2 SAR global Interrupts */
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[USB_HP_IRQn ] = isr_usb_hp, /* [19] USB HP Interrupt */
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[USB_LP_IRQn ] = isr_usb_lp, /* [20] USB LP Interrupt */
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[FDCAN1_IT0_IRQn ] = isr_fdcan1_it0, /* [21] FDCAN1 IT0 Interrupt */
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[FDCAN1_IT1_IRQn ] = isr_fdcan1_it1, /* [22] FDCAN1 IT1 Interrupt */
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[EXTI9_5_IRQn ] = isr_exti, /* [23] External Line[9:5] Interrupts */
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[TIM1_BRK_TIM15_IRQn ] = isr_tim1_brk_tim15, /* [24] TIM1 Break interrupt and TIM15 global interrupt */
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[TIM1_UP_TIM16_IRQn ] = isr_tim1_up_tim16, /* [25] TIM1 Update Interrupt and TIM16 global interrupt */
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[TIM1_TRG_COM_TIM17_IRQn ] = isr_tim1_trg_com_tim17, /* [26] TIM1 TIM1 Trigger, Commutation, Direction change, Index and TIM17 global interrupt */
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[TIM1_CC_IRQn ] = isr_tim1_cc, /* [27] TIM1 Capture Compare Interrupt */
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[TIM2_IRQn ] = isr_tim2, /* [28] TIM2 global Interrupt */
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[TIM3_IRQn ] = isr_tim3, /* [29] TIM3 global Interrupt */
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[TIM4_IRQn ] = isr_tim4, /* [30] TIM4 global Interrupt */
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[I2C1_EV_IRQn ] = isr_i2c1_ev, /* [31] I2C1 Event Interrupt */
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[I2C1_ER_IRQn ] = isr_i2c1_er, /* [32] I2C1 Error Interrupt */
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[I2C2_EV_IRQn ] = isr_i2c2_ev, /* [33] I2C2 Event Interrupt */
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[I2C2_ER_IRQn ] = isr_i2c2_er, /* [34] I2C2 Error Interrupt */
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[SPI1_IRQn ] = isr_spi1, /* [35] SPI1 global Interrupt */
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[SPI2_IRQn ] = isr_spi2, /* [36] SPI2 global Interrupt */
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[USART1_IRQn ] = isr_usart1, /* [37] USART1 global Interrupt */
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[USART2_IRQn ] = isr_usart2, /* [38] USART2 global Interrupt */
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[USART3_IRQn ] = isr_usart3, /* [39] USART3 global Interrupt */
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[EXTI15_10_IRQn ] = isr_exti, /* [40] External Line[15:10] Interrupts */
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[RTC_Alarm_IRQn ] = isr_rtc_alarm, /* [41] RTC Alarm (A and B) through EXTI Line Interrupt */
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[USBWakeUp_IRQn ] = isr_usbwakeup, /* [42] USB Wakeup through EXTI line Interrupt */
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[TIM8_BRK_IRQn ] = isr_tim8_brk, /* [43] TIM8 Break Interrupt */
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[TIM8_UP_IRQn ] = isr_tim8_up, /* [44] TIM8 Update Interrupt */
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[TIM8_TRG_COM_IRQn ] = isr_tim8_trg_com, /* [45] TIM8 Trigger and Commutation Interrupt */
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[TIM8_CC_IRQn ] = isr_tim8_cc, /* [46] TIM8 Capture Compare Interrupt */
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[ADC3_IRQn ] = isr_adc3, /* [47] ADC3 global Interrupt */
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[FMC_IRQn ] = isr_fmc, /* [48] FMC global Interrupt */
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[LPTIM1_IRQn ] = isr_lptim1, /* [49] LP TIM1 Interrupt */
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[TIM5_IRQn ] = isr_tim5, /* [50] TIM5 global Interrupt */
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[SPI3_IRQn ] = isr_spi3, /* [51] SPI3 global Interrupt */
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[UART4_IRQn ] = isr_uart4, /* [52] UART4 global Interrupt */
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[UART5_IRQn ] = isr_uart5, /* [53] UART5 global Interrupt */
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[TIM6_DAC_IRQn ] = isr_tim6_dac, /* [54] TIM6 global and DAC1&3 underrun error interrupts */
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[TIM7_DAC_IRQn ] = isr_tim7_dac, /* [55] TIM7 global and DAC2&4 underrun error interrupts */
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[DMA2_Channel1_IRQn ] = isr_dma2_channel1, /* [56] DMA2 Channel 1 global Interrupt */
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[DMA2_Channel2_IRQn ] = isr_dma2_channel2, /* [57] DMA2 Channel 2 global Interrupt */
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[DMA2_Channel3_IRQn ] = isr_dma2_channel3, /* [58] DMA2 Channel 3 global Interrupt */
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[DMA2_Channel4_IRQn ] = isr_dma2_channel4, /* [59] DMA2 Channel 4 global Interrupt */
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[DMA2_Channel5_IRQn ] = isr_dma2_channel5, /* [60] DMA2 Channel 5 global Interrupt */
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[ADC4_IRQn ] = isr_adc4, /* [61] ADC4 global Interrupt */
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[ADC5_IRQn ] = isr_adc5, /* [62] ADC5 global Interrupt */
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[UCPD1_IRQn ] = isr_ucpd1, /* [63] UCPD global Interrupt */
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[COMP1_2_3_IRQn ] = isr_comp1_2_3, /* [64] COMP1, COMP2 and COMP3 Interrupt */
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[COMP4_5_6_IRQn ] = isr_comp4_5_6, /* [65] COMP4, COMP5 and Interrupt */
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[COMP7_IRQn ] = isr_comp7, /* [66] COMP7 Interrupt */
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[HRTIM1_Master_IRQn ] = isr_hrtim1_master, /* [67] HRTIM Master Timer global Interrupt */
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[HRTIM1_TIMA_IRQn ] = isr_hrtim1_tima, /* [68] HRTIM Timer A global Interrupt */
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[HRTIM1_TIMB_IRQn ] = isr_hrtim1_timb, /* [69] HRTIM Timer B global Interrupt */
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[HRTIM1_TIMC_IRQn ] = isr_hrtim1_timc, /* [70] HRTIM Timer C global Interrupt */
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[HRTIM1_TIMD_IRQn ] = isr_hrtim1_timd, /* [71] HRTIM Timer D global Interrupt */
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[HRTIM1_TIME_IRQn ] = isr_hrtim1_time, /* [72] HRTIM Timer E global Interrupt */
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[HRTIM1_FLT_IRQn ] = isr_hrtim1_flt, /* [73] HRTIM Fault global Interrupt */
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[HRTIM1_TIMF_IRQn ] = isr_hrtim1_timf, /* [74] HRTIM Timer F global Interrupt */
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[CRS_IRQn ] = isr_crs, /* [75] CRS global Interrupt */
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[SAI1_IRQn ] = isr_sai1, /* [76] Serial Audio Interface global Interrupt */
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[TIM20_BRK_IRQn ] = isr_tim20_brk, /* [77] TIM20 Break, Transition error and Index error Interrupt */
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[TIM20_UP_IRQn ] = isr_tim20_up, /* [78] TIM20 Update Interrupt */
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[TIM20_TRG_COM_IRQn ] = isr_tim20_trg_com, /* [79] TIM20 Trigger, Commutation, Direction change and Index Interrupt */
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[TIM20_CC_IRQn ] = isr_tim20_cc, /* [80] TIM20 Capture Compare Interrupt */
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[FPU_IRQn ] = isr_fpu, /* [81] FPU global Interrupt */
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[I2C4_EV_IRQn ] = isr_i2c4_ev, /* [82] I2C4 Event Interrupt */
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[I2C4_ER_IRQn ] = isr_i2c4_er, /* [83] I2C4 Error Interrupt */
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[SPI4_IRQn ] = isr_spi4, /* [84] SPI4 Event Interrupt */
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[FDCAN2_IT0_IRQn ] = isr_fdcan2_it0, /* [86] FDCAN2 interrupt line 0 Interrupt */
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[FDCAN2_IT1_IRQn ] = isr_fdcan2_it1, /* [87] FDCAN2 interrupt line 1 Interrupt */
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[FDCAN3_IT0_IRQn ] = isr_fdcan3_it0, /* [88] FDCAN3 interrupt line 0 Interrupt */
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[FDCAN3_IT1_IRQn ] = isr_fdcan3_it1, /* [89] FDCAN3 interrupt line 1 Interrupt */
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[RNG_IRQn ] = isr_rng, /* [90] RNG global Interrupt */
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[LPUART1_IRQn ] = isr_lpuart1, /* [91] LP UART 1 Interrupt */
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[I2C3_EV_IRQn ] = isr_i2c3_ev, /* [92] I2C3 Event Interrupt */
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[I2C3_ER_IRQn ] = isr_i2c3_er, /* [93] I2C3 Error Interrupt */
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[DMAMUX_OVR_IRQn ] = isr_dmamux, /* [94] DMAMUX overrun global Interrupt */
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[QUADSPI_IRQn ] = isr_quadspi, /* [95] QUADSPI Interrupt */
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[DMA1_Channel8_IRQn ] = isr_dma1_channel8, /* [96] DMA1 Channel 8 Interrupt */
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[DMA2_Channel6_IRQn ] = isr_dma2_channel6, /* [97] DMA2 Channel 6 Interrupt */
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[DMA2_Channel7_IRQn ] = isr_dma2_channel7, /* [98] DMA2 Channel 7 Interrupt */
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[DMA2_Channel8_IRQn ] = isr_dma2_channel8, /* [99] DMA2 Channel 8 Interrupt */
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[CORDIC_IRQn ] = isr_cordic, /* [100] CORDIC global Interrupt */
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[FMAC_IRQn ] = isr_fmac, /* [101] FMAC global Interrupt */
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};
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