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RIOT/cpu/rpx0xx/include/vendor/RP2040.h
Marian Buschsieweke bf96c28889
cpu/rpx0xx: Update vendor header files 
Generated new vendor header files from upstream SVD files using:

    ./SVDConv "$PICO_SDK_DIR"/src/rp2040/hardware_regs/rp2040.svd \
        --generate=header --fields=macro --fields=enum

Note: The missing `--fields=struct` flag resulted in the header no
      longer containing bit-fields to represent different fields
      within registers. While this would generally ease writing code,
      the RP2040 has the unpleasant feature of corrupting the
      remaining bits of the register when a write access that is not
      word-sized occurs in the memory mapped I/O area. This could
      happen e.g. when a bit field is byte-sized and byte-aligned.
2023-03-22 19:34:29 +01:00

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/*
* Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*
* @file /home/maribu/Downloads/tmp/CMSIS/Utilities/Linux64//RP2040.h
* @brief CMSIS HeaderFile
* @version 0.1
* @date 22. March 2023
* @note Generated by SVDConv V3.3.42 on Wednesday, 22.03.2023 20:19:18
* from File '/home/maribu/Repos/software/pico-sdk/src/rp2040/hardware_regs/rp2040.svd',
*/
/** @addtogroup Raspberry Pi
* @{
*/
/** @addtogroup RP2040
* @{
*/
#ifndef RP2040_H
#define RP2040_H
#ifdef __cplusplus
extern "C" {
#endif
/** @addtogroup Configuration_of_CMSIS
* @{
*/
/* =========================================================================================================================== */
/* ================ Interrupt Number Definition ================ */
/* =========================================================================================================================== */
typedef enum {
/* ======================================= ARM Cortex-M0+ Specific Interrupt Numbers ======================================= */
Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */
NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */
HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */
SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */
PendSV_IRQn = -2, /*!< -2 Pendable request for system service */
SysTick_IRQn = -1, /*!< -1 System Tick Timer */
/* =========================================== RP2040 Specific Interrupt Numbers =========================================== */
TIMER_IRQ_0_IRQn = 0, /*!< 0 TIMER_IRQ_0 */
TIMER_IRQ_1_IRQn = 1, /*!< 1 TIMER_IRQ_1 */
TIMER_IRQ_2_IRQn = 2, /*!< 2 TIMER_IRQ_2 */
TIMER_IRQ_3_IRQn = 3, /*!< 3 TIMER_IRQ_3 */
PWM_IRQ_WRAP_IRQn = 4, /*!< 4 PWM_IRQ_WRAP */
USBCTRL_IRQ_IRQn = 5, /*!< 5 USBCTRL_IRQ */
XIP_IRQ_IRQn = 6, /*!< 6 XIP_IRQ */
PIO0_IRQ_0_IRQn = 7, /*!< 7 PIO0_IRQ_0 */
PIO0_IRQ_1_IRQn = 8, /*!< 8 PIO0_IRQ_1 */
PIO1_IRQ_0_IRQn = 9, /*!< 9 PIO1_IRQ_0 */
PIO1_IRQ_1_IRQn = 10, /*!< 10 PIO1_IRQ_1 */
DMA_IRQ_0_IRQn = 11, /*!< 11 DMA_IRQ_0 */
DMA_IRQ_1_IRQn = 12, /*!< 12 DMA_IRQ_1 */
IO_IRQ_BANK0_IRQn = 13, /*!< 13 IO_IRQ_BANK0 */
IO_IRQ_QSPI_IRQn = 14, /*!< 14 IO_IRQ_QSPI */
SIO_IRQ_PROC0_IRQn = 15, /*!< 15 SIO_IRQ_PROC0 */
SIO_IRQ_PROC1_IRQn = 16, /*!< 16 SIO_IRQ_PROC1 */
CLOCKS_IRQ_IRQn = 17, /*!< 17 CLOCKS_IRQ */
SPI0_IRQ_IRQn = 18, /*!< 18 SPI0_IRQ */
SPI1_IRQ_IRQn = 19, /*!< 19 SPI1_IRQ */
UART0_IRQ_IRQn = 20, /*!< 20 UART0_IRQ */
UART1_IRQ_IRQn = 21, /*!< 21 UART1_IRQ */
ADC_IRQ_FIFO_IRQn = 22, /*!< 22 ADC_IRQ_FIFO */
I2C0_IRQ_IRQn = 23, /*!< 23 I2C0_IRQ */
I2C1_IRQ_IRQn = 24, /*!< 24 I2C1_IRQ */
RTC_IRQ_IRQn = 25 /*!< 25 RTC_IRQ */
} IRQn_Type;
/* =========================================================================================================================== */
/* ================ Processor and Core Peripheral Section ================ */
/* =========================================================================================================================== */
/* ========================== Configuration of the ARM Cortex-M0+ Processor and Core Peripherals =========================== */
#define __CM0PLUS_REV 0x0001U /*!< CM0PLUS Core Revision */
#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */
#define __MPU_PRESENT 1 /*!< MPU present */
#define __FPU_PRESENT 0 /*!< FPU present */
/** @} */ /* End of group Configuration_of_CMSIS */
#include "core_cm0plus.h" /*!< ARM Cortex-M0+ processor and core peripherals */
#include "system_RP2040.h" /*!< RP2040 System */
#ifndef __IM /*!< Fallback for older CMSIS versions */
#define __IM __I
#endif
#ifndef __OM /*!< Fallback for older CMSIS versions */
#define __OM __O
#endif
#ifndef __IOM /*!< Fallback for older CMSIS versions */
#define __IOM __IO
#endif
/* =========================================================================================================================== */
/* ================ Device Specific Peripheral Section ================ */
/* =========================================================================================================================== */
/** @addtogroup Device_Peripheral_peripherals
* @{
*/
/* =========================================================================================================================== */
/* ================ XIP_CTRL ================ */
/* =========================================================================================================================== */
/**
* @brief QSPI flash execute-in-place block (XIP_CTRL)
*/
typedef struct { /*!< (@ 0x14000000) XIP_CTRL Structure */
__IOM uint32_t CTRL; /*!< (@ 0x00000000) Cache control */
__IOM uint32_t FLUSH; /*!< (@ 0x00000004) Cache Flush control */
__IOM uint32_t STAT; /*!< (@ 0x00000008) Cache Status */
__IOM uint32_t CTR_HIT; /*!< (@ 0x0000000C) Cache Hit counter
A 32 bit saturating counter that increments
upon each cache hit,
i.e. when an XIP access is serviced directly
from cached data.
Write any value to clear. */
__IOM uint32_t CTR_ACC; /*!< (@ 0x00000010) Cache Access counter
A 32 bit saturating counter that increments
upon each XIP access,
whether the cache is hit or not. This includes
noncacheable accesses.
Write any value to clear. */
__IOM uint32_t STREAM_ADDR; /*!< (@ 0x00000014) FIFO stream address */
__IOM uint32_t STREAM_CTR; /*!< (@ 0x00000018) FIFO stream control */
__IM uint32_t STREAM_FIFO; /*!< (@ 0x0000001C) FIFO stream data
Streamed data is buffered here, for retrieval
by the system DMA.
This FIFO can also be accessed via the XIP_AUX
slave, to avoid exposing
the DMA to bus stalls caused by other XIP
traffic. */
} XIP_CTRL_Type; /*!< Size = 32 (0x20) */
/* =========================================================================================================================== */
/* ================ XIP_SSI ================ */
/* =========================================================================================================================== */
/**
* @brief DW_apb_ssi has the following features:\n
* APB interface – Allows for easy integration into a DesignWare Synthesizable Components for AMBA 2 implementation.\n
* APB3 and APB4 protocol support.\n
* Scalable APB data bus width – Supports APB data bus widths of 8, 16, and 32 bits.\n
* Serial-master or serial-slave operation – Enables serial communication with serial-master or serial-slave peripheral devices.\n
* Programmable Dual/Quad/Octal SPI support in Master Mode.\n
* Dual Data Rate (DDR) and Read Data Strobe (RDS) Support - Enables the DW_apb_ssi master to perform operations with the device in DDR and RDS modes when working in Dual/Quad/Octal mode of operation.\n
* Data Mask Support - Enables the DW_apb_ssi to selectively update the bytes in the device. This feature is applicable only in enhanced SPI modes.\n
* eXecute-In-Place (XIP) support - Enables the DW_apb_ssi master to behave as a memory mapped I/O and fetches the data from the device based on the APB read request. This feature is applicable only in enhanced SPI modes.\n
* DMA Controller Interface – Enables the DW_apb_ssi to interface to a DMA controller over the bus using a handshaking interface for transfer requests.\n
* Independent masking of interrupts – Master collision, transmit FIFO overflow, transmit FIFO empty, receive FIFO full, receive FIFO underflow, and receive FIFO overflow interrupts can all be masked independently.\n
* Multi-master contention detection – Informs the processor of multiple serial-master accesses on the serial bus.\n
* Bypass of meta-stability flip-flops for synchronous clocks – When the APB clock (pclk) and the DW_apb_ssi serial clock (ssi_clk) are synchronous, meta-stable flip-flops are not used when transferring control signals across these clock domains.\n
* Programmable delay on the sample time of the received serial data bit (rxd); enables programmable control of routing delays resulting in higher serial data-bit rates.\n
* Programmable features:\n
- Serial interface operation – Choice of Motorola SPI, Texas Instruments Synchronous Serial Protocol or National Semiconductor Microwire.\n
- Clock bit-rate – Dynamic control of the serial bit rate of the data transfer; used in only serial-master mode of operation.\n
- Data Item size (4 to 32 bits) – Item size of each data transfer under the control of the programmer.\n
* Configured features:\n
- FIFO depth – 16 words deep. The FIFO width is fixed at 32 bits.\n
- 1 slave select output.\n
- Hardware slave-select – Dedicated hardware slave-select line.\n
- Combined interrupt line - one combined interrupt line from the DW_apb_ssi to the interrupt controller.\n
- Interrupt polarity – active high interrupt lines.\n
- Serial clock polarity – low serial-clock polarity directly after reset.\n
- Serial clock phase – capture on first edge of serial-clock directly after reset. (XIP_SSI)
*/
typedef struct { /*!< (@ 0x18000000) XIP_SSI Structure */
__IOM uint32_t CTRLR0; /*!< (@ 0x00000000) Control register 0 */
__IOM uint32_t CTRLR1; /*!< (@ 0x00000004) Master Control register 1 */
__IOM uint32_t SSIENR; /*!< (@ 0x00000008) SSI Enable */
__IOM uint32_t MWCR; /*!< (@ 0x0000000C) Microwire Control */
__IOM uint32_t SER; /*!< (@ 0x00000010) Slave enable */
__IOM uint32_t BAUDR; /*!< (@ 0x00000014) Baud rate */
__IOM uint32_t TXFTLR; /*!< (@ 0x00000018) TX FIFO threshold level */
__IOM uint32_t RXFTLR; /*!< (@ 0x0000001C) RX FIFO threshold level */
__IOM uint32_t TXFLR; /*!< (@ 0x00000020) TX FIFO level */
__IOM uint32_t RXFLR; /*!< (@ 0x00000024) RX FIFO level */
__IOM uint32_t SR; /*!< (@ 0x00000028) Status register */
__IOM uint32_t IMR; /*!< (@ 0x0000002C) Interrupt mask */
__IOM uint32_t ISR; /*!< (@ 0x00000030) Interrupt status */
__IOM uint32_t RISR; /*!< (@ 0x00000034) Raw interrupt status */
__IOM uint32_t TXOICR; /*!< (@ 0x00000038) TX FIFO overflow interrupt clear */
__IOM uint32_t RXOICR; /*!< (@ 0x0000003C) RX FIFO overflow interrupt clear */
__IOM uint32_t RXUICR; /*!< (@ 0x00000040) RX FIFO underflow interrupt clear */
__IOM uint32_t MSTICR; /*!< (@ 0x00000044) Multi-master interrupt clear */
__IOM uint32_t ICR; /*!< (@ 0x00000048) Interrupt clear */
__IOM uint32_t DMACR; /*!< (@ 0x0000004C) DMA control */
__IOM uint32_t DMATDLR; /*!< (@ 0x00000050) DMA TX data level */
__IOM uint32_t DMARDLR; /*!< (@ 0x00000054) DMA RX data level */
__IOM uint32_t IDR; /*!< (@ 0x00000058) Identification register */
__IOM uint32_t SSI_VERSION_ID; /*!< (@ 0x0000005C) Version ID */
__IOM uint32_t DR0; /*!< (@ 0x00000060) Data Register 0 (of 36) */
__IM uint32_t RESERVED[35];
__IOM uint32_t RX_SAMPLE_DLY; /*!< (@ 0x000000F0) RX sample delay */
__IOM uint32_t SPI_CTRLR0; /*!< (@ 0x000000F4) SPI control */
__IOM uint32_t TXD_DRIVE_EDGE; /*!< (@ 0x000000F8) TX drive edge */
} XIP_SSI_Type; /*!< Size = 252 (0xfc) */
/* =========================================================================================================================== */
/* ================ SYSINFO ================ */
/* =========================================================================================================================== */
/**
* @brief SYSINFO (SYSINFO)
*/
typedef struct { /*!< (@ 0x40000000) SYSINFO Structure */
__IOM uint32_t CHIP_ID; /*!< (@ 0x00000000) JEDEC JEP-106 compliant chip identifier. */
__IOM uint32_t PLATFORM; /*!< (@ 0x00000004) Platform register. Allows software to know what
environment it is running in. */
__IM uint32_t RESERVED[14];
__IM uint32_t GITREF_RP2040; /*!< (@ 0x00000040) Git hash of the chip source. Used to identify
chip version. */
} SYSINFO_Type; /*!< Size = 68 (0x44) */
/* =========================================================================================================================== */
/* ================ SYSCFG ================ */
/* =========================================================================================================================== */
/**
* @brief Register block for various chip control signals (SYSCFG)
*/
typedef struct { /*!< (@ 0x40004000) SYSCFG Structure */
__IOM uint32_t PROC0_NMI_MASK; /*!< (@ 0x00000000) Processor core 0 NMI source mask
Set a bit high to enable NMI from that IRQ */
__IOM uint32_t PROC1_NMI_MASK; /*!< (@ 0x00000004) Processor core 1 NMI source mask
Set a bit high to enable NMI from that IRQ */
__IOM uint32_t PROC_CONFIG; /*!< (@ 0x00000008) Configuration for processors */
__IOM uint32_t PROC_IN_SYNC_BYPASS; /*!< (@ 0x0000000C) For each bit, if 1, bypass the input synchronizer
between that GPIO
and the GPIO input register in the SIO.
The input synchronizers should
generally be unbypassed, to avoid injecting
metastabilities into processors.
If you're feeling brave, you can bypass
to save two cycles of input
latency. This register applies to GPIO 0...29. */
__IOM uint32_t PROC_IN_SYNC_BYPASS_HI; /*!< (@ 0x00000010) For each bit, if 1, bypass the input synchronizer
between that GPIO
and the GPIO input register in the SIO.
The input synchronizers should
generally be unbypassed, to avoid injecting
metastabilities into processors.
If you're feeling brave, you can bypass
to save two cycles of input
latency. This register applies to GPIO 30...35
(the QSPI IOs). */
__IOM uint32_t DBGFORCE; /*!< (@ 0x00000014) Directly control the SWD debug port of either
processor */
__IOM uint32_t MEMPOWERDOWN; /*!< (@ 0x00000018) Control power downs to memories. Set high to
power down memories.
Use with extreme caution */
} SYSCFG_Type; /*!< Size = 28 (0x1c) */
/* =========================================================================================================================== */
/* ================ CLOCKS ================ */
/* =========================================================================================================================== */
/**
* @brief CLOCKS (CLOCKS)
*/
typedef struct { /*!< (@ 0x40008000) CLOCKS Structure */
__IOM uint32_t CLK_GPOUT0_CTRL; /*!< (@ 0x00000000) Clock control, can be changed on-the-fly (except
for auxsrc) */
__IOM uint32_t CLK_GPOUT0_DIV; /*!< (@ 0x00000004) Clock divisor, can be changed on-the-fly */
__IM uint32_t CLK_GPOUT0_SELECTED; /*!< (@ 0x00000008) Indicates which SRC is currently selected by
the glitchless mux (one-hot).
This slice does not have a glitchless mux
(only the AUX_SRC field is present, not
SRC) so this register is hardwired to 0x1. */
__IOM uint32_t CLK_GPOUT1_CTRL; /*!< (@ 0x0000000C) Clock control, can be changed on-the-fly (except
for auxsrc) */
__IOM uint32_t CLK_GPOUT1_DIV; /*!< (@ 0x00000010) Clock divisor, can be changed on-the-fly */
__IM uint32_t CLK_GPOUT1_SELECTED; /*!< (@ 0x00000014) Indicates which SRC is currently selected by
the glitchless mux (one-hot).
This slice does not have a glitchless mux
(only the AUX_SRC field is present, not
SRC) so this register is hardwired to 0x1. */
__IOM uint32_t CLK_GPOUT2_CTRL; /*!< (@ 0x00000018) Clock control, can be changed on-the-fly (except
for auxsrc) */
__IOM uint32_t CLK_GPOUT2_DIV; /*!< (@ 0x0000001C) Clock divisor, can be changed on-the-fly */
__IM uint32_t CLK_GPOUT2_SELECTED; /*!< (@ 0x00000020) Indicates which SRC is currently selected by
the glitchless mux (one-hot).
This slice does not have a glitchless mux
(only the AUX_SRC field is present, not
SRC) so this register is hardwired to 0x1. */
__IOM uint32_t CLK_GPOUT3_CTRL; /*!< (@ 0x00000024) Clock control, can be changed on-the-fly (except
for auxsrc) */
__IOM uint32_t CLK_GPOUT3_DIV; /*!< (@ 0x00000028) Clock divisor, can be changed on-the-fly */
__IM uint32_t CLK_GPOUT3_SELECTED; /*!< (@ 0x0000002C) Indicates which SRC is currently selected by
the glitchless mux (one-hot).
This slice does not have a glitchless mux
(only the AUX_SRC field is present, not
SRC) so this register is hardwired to 0x1. */
__IOM uint32_t CLK_REF_CTRL; /*!< (@ 0x00000030) Clock control, can be changed on-the-fly (except
for auxsrc) */
__IOM uint32_t CLK_REF_DIV; /*!< (@ 0x00000034) Clock divisor, can be changed on-the-fly */
__IM uint32_t CLK_REF_SELECTED; /*!< (@ 0x00000038) Indicates which SRC is currently selected by
the glitchless mux (one-hot).
The glitchless multiplexer does not switch
instantaneously (to avoid glitches), so
software should poll this register to wait
for the switch to complete. This register
contains one decoded bit for each of the
clock sources enumerated in the CTRL SRC
field. At most one of these bits will be
set at any time, indicating that clock is
currently present at the output of the glitchless
mux. Whilst switching i */
__IOM uint32_t CLK_SYS_CTRL; /*!< (@ 0x0000003C) Clock control, can be changed on-the-fly (except
for auxsrc) */
__IOM uint32_t CLK_SYS_DIV; /*!< (@ 0x00000040) Clock divisor, can be changed on-the-fly */
__IM uint32_t CLK_SYS_SELECTED; /*!< (@ 0x00000044) Indicates which SRC is currently selected by
the glitchless mux (one-hot).
The glitchless multiplexer does not switch
instantaneously (to avoid glitches), so
software should poll this register to wait
for the switch to complete. This register
contains one decoded bit for each of the
clock sources enumerated in the CTRL SRC
field. At most one of these bits will be
set at any time, indicating that clock is
currently present at the output of the glitchless
mux. Whilst switching i */
__IOM uint32_t CLK_PERI_CTRL; /*!< (@ 0x00000048) Clock control, can be changed on-the-fly (except
for auxsrc) */
__IM uint32_t RESERVED;
__IM uint32_t CLK_PERI_SELECTED; /*!< (@ 0x00000050) Indicates which SRC is currently selected by
the glitchless mux (one-hot).
This slice does not have a glitchless mux
(only the AUX_SRC field is present, not
SRC) so this register is hardwired to 0x1. */
__IOM uint32_t CLK_USB_CTRL; /*!< (@ 0x00000054) Clock control, can be changed on-the-fly (except
for auxsrc) */
__IOM uint32_t CLK_USB_DIV; /*!< (@ 0x00000058) Clock divisor, can be changed on-the-fly */
__IM uint32_t CLK_USB_SELECTED; /*!< (@ 0x0000005C) Indicates which SRC is currently selected by
the glitchless mux (one-hot).
This slice does not have a glitchless mux
(only the AUX_SRC field is present, not
SRC) so this register is hardwired to 0x1. */
__IOM uint32_t CLK_ADC_CTRL; /*!< (@ 0x00000060) Clock control, can be changed on-the-fly (except
for auxsrc) */
__IOM uint32_t CLK_ADC_DIV; /*!< (@ 0x00000064) Clock divisor, can be changed on-the-fly */
__IM uint32_t CLK_ADC_SELECTED; /*!< (@ 0x00000068) Indicates which SRC is currently selected by
the glitchless mux (one-hot).
This slice does not have a glitchless mux
(only the AUX_SRC field is present, not
SRC) so this register is hardwired to 0x1. */
__IOM uint32_t CLK_RTC_CTRL; /*!< (@ 0x0000006C) Clock control, can be changed on-the-fly (except
for auxsrc) */
__IOM uint32_t CLK_RTC_DIV; /*!< (@ 0x00000070) Clock divisor, can be changed on-the-fly */
__IM uint32_t CLK_RTC_SELECTED; /*!< (@ 0x00000074) Indicates which SRC is currently selected by
the glitchless mux (one-hot).
This slice does not have a glitchless mux
(only the AUX_SRC field is present, not
SRC) so this register is hardwired to 0x1. */
__IOM uint32_t CLK_SYS_RESUS_CTRL; /*!< (@ 0x00000078) CLK_SYS_RESUS_CTRL */
__IOM uint32_t CLK_SYS_RESUS_STATUS; /*!< (@ 0x0000007C) CLK_SYS_RESUS_STATUS */
__IOM uint32_t FC0_REF_KHZ; /*!< (@ 0x00000080) Reference clock frequency in kHz */
__IOM uint32_t FC0_MIN_KHZ; /*!< (@ 0x00000084) Minimum pass frequency in kHz. This is optional.
Set to 0 if you are not using the pass/fail
flags */
__IOM uint32_t FC0_MAX_KHZ; /*!< (@ 0x00000088) Maximum pass frequency in kHz. This is optional.
Set to 0x1ffffff if you are not using the
pass/fail flags */
__IOM uint32_t FC0_DELAY; /*!< (@ 0x0000008C) Delays the start of frequency counting to allow
the mux to settle
Delay is measured in multiples of the reference
clock period */
__IOM uint32_t FC0_INTERVAL; /*!< (@ 0x00000090) The test interval is 0.98us * 2**interval, but
let's call it 1us * 2**interval
The default gives a test interval of 250us */
__IOM uint32_t FC0_SRC; /*!< (@ 0x00000094) Clock sent to frequency counter, set to 0 when
not required
Writing to this register initiates the frequency
count */
__IOM uint32_t FC0_STATUS; /*!< (@ 0x00000098) Frequency counter status */
__IOM uint32_t FC0_RESULT; /*!< (@ 0x0000009C) Result of frequency measurement, only valid when
status_done=1 */
__IOM uint32_t WAKE_EN0; /*!< (@ 0x000000A0) enable clock in wake mode */
__IOM uint32_t WAKE_EN1; /*!< (@ 0x000000A4) enable clock in wake mode */
__IOM uint32_t SLEEP_EN0; /*!< (@ 0x000000A8) enable clock in sleep mode */
__IOM uint32_t SLEEP_EN1; /*!< (@ 0x000000AC) enable clock in sleep mode */
__IOM uint32_t ENABLED0; /*!< (@ 0x000000B0) indicates the state of the clock enable */
__IOM uint32_t ENABLED1; /*!< (@ 0x000000B4) indicates the state of the clock enable */
__IOM uint32_t INTR; /*!< (@ 0x000000B8) Raw Interrupts */
__IOM uint32_t INTE; /*!< (@ 0x000000BC) Interrupt Enable */
__IOM uint32_t INTF; /*!< (@ 0x000000C0) Interrupt Force */
__IOM uint32_t INTS; /*!< (@ 0x000000C4) Interrupt status after masking & forcing */
} CLOCKS_Type; /*!< Size = 200 (0xc8) */
/* =========================================================================================================================== */
/* ================ RESETS ================ */
/* =========================================================================================================================== */
/**
* @brief RESETS (RESETS)
*/
typedef struct { /*!< (@ 0x4000C000) RESETS Structure */
__IOM uint32_t RESET; /*!< (@ 0x00000000) Reset control. If a bit is set it means the peripheral
is in reset. 0 means the peripheral's reset
is deasserted. */
__IOM uint32_t WDSEL; /*!< (@ 0x00000004) Watchdog select. If a bit is set then the watchdog
will reset this peripheral when the watchdog
fires. */
__IOM uint32_t RESET_DONE; /*!< (@ 0x00000008) Reset done. If a bit is set then a reset done
signal has been returned by the peripheral.
This indicates that the peripheral's registers
are ready to be accessed. */
} RESETS_Type; /*!< Size = 12 (0xc) */
/* =========================================================================================================================== */
/* ================ PSM ================ */
/* =========================================================================================================================== */
/**
* @brief PSM (PSM)
*/
typedef struct { /*!< (@ 0x40010000) PSM Structure */
__IOM uint32_t FRCE_ON; /*!< (@ 0x00000000) Force block out of reset (i.e. power it on) */
__IOM uint32_t FRCE_OFF; /*!< (@ 0x00000004) Force into reset (i.e. power it off) */
__IOM uint32_t WDSEL; /*!< (@ 0x00000008) Set to 1 if this peripheral should be reset when
the watchdog fires. */
__IOM uint32_t DONE; /*!< (@ 0x0000000C) Indicates the peripheral's registers are ready
to access. */
} PSM_Type; /*!< Size = 16 (0x10) */
/* =========================================================================================================================== */
/* ================ IO_BANK0 ================ */
/* =========================================================================================================================== */
/**
* @brief IO_BANK0 (IO_BANK0)
*/
typedef struct { /*!< (@ 0x40014000) IO_BANK0 Structure */
__IOM uint32_t GPIO0_STATUS; /*!< (@ 0x00000000) GPIO status */
__IOM uint32_t GPIO0_CTRL; /*!< (@ 0x00000004) GPIO control including function select and overrides. */
__IOM uint32_t GPIO1_STATUS; /*!< (@ 0x00000008) GPIO status */
__IOM uint32_t GPIO1_CTRL; /*!< (@ 0x0000000C) GPIO control including function select and overrides. */
__IOM uint32_t GPIO2_STATUS; /*!< (@ 0x00000010) GPIO status */
__IOM uint32_t GPIO2_CTRL; /*!< (@ 0x00000014) GPIO control including function select and overrides. */
__IOM uint32_t GPIO3_STATUS; /*!< (@ 0x00000018) GPIO status */
__IOM uint32_t GPIO3_CTRL; /*!< (@ 0x0000001C) GPIO control including function select and overrides. */
__IOM uint32_t GPIO4_STATUS; /*!< (@ 0x00000020) GPIO status */
__IOM uint32_t GPIO4_CTRL; /*!< (@ 0x00000024) GPIO control including function select and overrides. */
__IOM uint32_t GPIO5_STATUS; /*!< (@ 0x00000028) GPIO status */
__IOM uint32_t GPIO5_CTRL; /*!< (@ 0x0000002C) GPIO control including function select and overrides. */
__IOM uint32_t GPIO6_STATUS; /*!< (@ 0x00000030) GPIO status */
__IOM uint32_t GPIO6_CTRL; /*!< (@ 0x00000034) GPIO control including function select and overrides. */
__IOM uint32_t GPIO7_STATUS; /*!< (@ 0x00000038) GPIO status */
__IOM uint32_t GPIO7_CTRL; /*!< (@ 0x0000003C) GPIO control including function select and overrides. */
__IOM uint32_t GPIO8_STATUS; /*!< (@ 0x00000040) GPIO status */
__IOM uint32_t GPIO8_CTRL; /*!< (@ 0x00000044) GPIO control including function select and overrides. */
__IOM uint32_t GPIO9_STATUS; /*!< (@ 0x00000048) GPIO status */
__IOM uint32_t GPIO9_CTRL; /*!< (@ 0x0000004C) GPIO control including function select and overrides. */
__IOM uint32_t GPIO10_STATUS; /*!< (@ 0x00000050) GPIO status */
__IOM uint32_t GPIO10_CTRL; /*!< (@ 0x00000054) GPIO control including function select and overrides. */
__IOM uint32_t GPIO11_STATUS; /*!< (@ 0x00000058) GPIO status */
__IOM uint32_t GPIO11_CTRL; /*!< (@ 0x0000005C) GPIO control including function select and overrides. */
__IOM uint32_t GPIO12_STATUS; /*!< (@ 0x00000060) GPIO status */
__IOM uint32_t GPIO12_CTRL; /*!< (@ 0x00000064) GPIO control including function select and overrides. */
__IOM uint32_t GPIO13_STATUS; /*!< (@ 0x00000068) GPIO status */
__IOM uint32_t GPIO13_CTRL; /*!< (@ 0x0000006C) GPIO control including function select and overrides. */
__IOM uint32_t GPIO14_STATUS; /*!< (@ 0x00000070) GPIO status */
__IOM uint32_t GPIO14_CTRL; /*!< (@ 0x00000074) GPIO control including function select and overrides. */
__IOM uint32_t GPIO15_STATUS; /*!< (@ 0x00000078) GPIO status */
__IOM uint32_t GPIO15_CTRL; /*!< (@ 0x0000007C) GPIO control including function select and overrides. */
__IOM uint32_t GPIO16_STATUS; /*!< (@ 0x00000080) GPIO status */
__IOM uint32_t GPIO16_CTRL; /*!< (@ 0x00000084) GPIO control including function select and overrides. */
__IOM uint32_t GPIO17_STATUS; /*!< (@ 0x00000088) GPIO status */
__IOM uint32_t GPIO17_CTRL; /*!< (@ 0x0000008C) GPIO control including function select and overrides. */
__IOM uint32_t GPIO18_STATUS; /*!< (@ 0x00000090) GPIO status */
__IOM uint32_t GPIO18_CTRL; /*!< (@ 0x00000094) GPIO control including function select and overrides. */
__IOM uint32_t GPIO19_STATUS; /*!< (@ 0x00000098) GPIO status */
__IOM uint32_t GPIO19_CTRL; /*!< (@ 0x0000009C) GPIO control including function select and overrides. */
__IOM uint32_t GPIO20_STATUS; /*!< (@ 0x000000A0) GPIO status */
__IOM uint32_t GPIO20_CTRL; /*!< (@ 0x000000A4) GPIO control including function select and overrides. */
__IOM uint32_t GPIO21_STATUS; /*!< (@ 0x000000A8) GPIO status */
__IOM uint32_t GPIO21_CTRL; /*!< (@ 0x000000AC) GPIO control including function select and overrides. */
__IOM uint32_t GPIO22_STATUS; /*!< (@ 0x000000B0) GPIO status */
__IOM uint32_t GPIO22_CTRL; /*!< (@ 0x000000B4) GPIO control including function select and overrides. */
__IOM uint32_t GPIO23_STATUS; /*!< (@ 0x000000B8) GPIO status */
__IOM uint32_t GPIO23_CTRL; /*!< (@ 0x000000BC) GPIO control including function select and overrides. */
__IOM uint32_t GPIO24_STATUS; /*!< (@ 0x000000C0) GPIO status */
__IOM uint32_t GPIO24_CTRL; /*!< (@ 0x000000C4) GPIO control including function select and overrides. */
__IOM uint32_t GPIO25_STATUS; /*!< (@ 0x000000C8) GPIO status */
__IOM uint32_t GPIO25_CTRL; /*!< (@ 0x000000CC) GPIO control including function select and overrides. */
__IOM uint32_t GPIO26_STATUS; /*!< (@ 0x000000D0) GPIO status */
__IOM uint32_t GPIO26_CTRL; /*!< (@ 0x000000D4) GPIO control including function select and overrides. */
__IOM uint32_t GPIO27_STATUS; /*!< (@ 0x000000D8) GPIO status */
__IOM uint32_t GPIO27_CTRL; /*!< (@ 0x000000DC) GPIO control including function select and overrides. */
__IOM uint32_t GPIO28_STATUS; /*!< (@ 0x000000E0) GPIO status */
__IOM uint32_t GPIO28_CTRL; /*!< (@ 0x000000E4) GPIO control including function select and overrides. */
__IOM uint32_t GPIO29_STATUS; /*!< (@ 0x000000E8) GPIO status */
__IOM uint32_t GPIO29_CTRL; /*!< (@ 0x000000EC) GPIO control including function select and overrides. */
__IOM uint32_t INTR0; /*!< (@ 0x000000F0) Raw Interrupts */
__IOM uint32_t INTR1; /*!< (@ 0x000000F4) Raw Interrupts */
__IOM uint32_t INTR2; /*!< (@ 0x000000F8) Raw Interrupts */
__IOM uint32_t INTR3; /*!< (@ 0x000000FC) Raw Interrupts */
__IOM uint32_t PROC0_INTE0; /*!< (@ 0x00000100) Interrupt Enable for proc0 */
__IOM uint32_t PROC0_INTE1; /*!< (@ 0x00000104) Interrupt Enable for proc0 */
__IOM uint32_t PROC0_INTE2; /*!< (@ 0x00000108) Interrupt Enable for proc0 */
__IOM uint32_t PROC0_INTE3; /*!< (@ 0x0000010C) Interrupt Enable for proc0 */
__IOM uint32_t PROC0_INTF0; /*!< (@ 0x00000110) Interrupt Force for proc0 */
__IOM uint32_t PROC0_INTF1; /*!< (@ 0x00000114) Interrupt Force for proc0 */
__IOM uint32_t PROC0_INTF2; /*!< (@ 0x00000118) Interrupt Force for proc0 */
__IOM uint32_t PROC0_INTF3; /*!< (@ 0x0000011C) Interrupt Force for proc0 */
__IOM uint32_t PROC0_INTS0; /*!< (@ 0x00000120) Interrupt status after masking & forcing for
proc0 */
__IOM uint32_t PROC0_INTS1; /*!< (@ 0x00000124) Interrupt status after masking & forcing for
proc0 */
__IOM uint32_t PROC0_INTS2; /*!< (@ 0x00000128) Interrupt status after masking & forcing for
proc0 */
__IOM uint32_t PROC0_INTS3; /*!< (@ 0x0000012C) Interrupt status after masking & forcing for
proc0 */
__IOM uint32_t PROC1_INTE0; /*!< (@ 0x00000130) Interrupt Enable for proc1 */
__IOM uint32_t PROC1_INTE1; /*!< (@ 0x00000134) Interrupt Enable for proc1 */
__IOM uint32_t PROC1_INTE2; /*!< (@ 0x00000138) Interrupt Enable for proc1 */
__IOM uint32_t PROC1_INTE3; /*!< (@ 0x0000013C) Interrupt Enable for proc1 */
__IOM uint32_t PROC1_INTF0; /*!< (@ 0x00000140) Interrupt Force for proc1 */
__IOM uint32_t PROC1_INTF1; /*!< (@ 0x00000144) Interrupt Force for proc1 */
__IOM uint32_t PROC1_INTF2; /*!< (@ 0x00000148) Interrupt Force for proc1 */
__IOM uint32_t PROC1_INTF3; /*!< (@ 0x0000014C) Interrupt Force for proc1 */
__IOM uint32_t PROC1_INTS0; /*!< (@ 0x00000150) Interrupt status after masking & forcing for
proc1 */
__IOM uint32_t PROC1_INTS1; /*!< (@ 0x00000154) Interrupt status after masking & forcing for
proc1 */
__IOM uint32_t PROC1_INTS2; /*!< (@ 0x00000158) Interrupt status after masking & forcing for
proc1 */
__IOM uint32_t PROC1_INTS3; /*!< (@ 0x0000015C) Interrupt status after masking & forcing for
proc1 */
__IOM uint32_t DORMANT_WAKE_INTE0; /*!< (@ 0x00000160) Interrupt Enable for dormant_wake */
__IOM uint32_t DORMANT_WAKE_INTE1; /*!< (@ 0x00000164) Interrupt Enable for dormant_wake */
__IOM uint32_t DORMANT_WAKE_INTE2; /*!< (@ 0x00000168) Interrupt Enable for dormant_wake */
__IOM uint32_t DORMANT_WAKE_INTE3; /*!< (@ 0x0000016C) Interrupt Enable for dormant_wake */
__IOM uint32_t DORMANT_WAKE_INTF0; /*!< (@ 0x00000170) Interrupt Force for dormant_wake */
__IOM uint32_t DORMANT_WAKE_INTF1; /*!< (@ 0x00000174) Interrupt Force for dormant_wake */
__IOM uint32_t DORMANT_WAKE_INTF2; /*!< (@ 0x00000178) Interrupt Force for dormant_wake */
__IOM uint32_t DORMANT_WAKE_INTF3; /*!< (@ 0x0000017C) Interrupt Force for dormant_wake */
__IOM uint32_t DORMANT_WAKE_INTS0; /*!< (@ 0x00000180) Interrupt status after masking & forcing for
dormant_wake */
__IOM uint32_t DORMANT_WAKE_INTS1; /*!< (@ 0x00000184) Interrupt status after masking & forcing for
dormant_wake */
__IOM uint32_t DORMANT_WAKE_INTS2; /*!< (@ 0x00000188) Interrupt status after masking & forcing for
dormant_wake */
__IOM uint32_t DORMANT_WAKE_INTS3; /*!< (@ 0x0000018C) Interrupt status after masking & forcing for
dormant_wake */
} IO_BANK0_Type; /*!< Size = 400 (0x190) */
/* =========================================================================================================================== */
/* ================ IO_QSPI ================ */
/* =========================================================================================================================== */
/**
* @brief IO_QSPI (IO_QSPI)
*/
typedef struct { /*!< (@ 0x40018000) IO_QSPI Structure */
__IOM uint32_t GPIO_QSPI_SCLK_STATUS; /*!< (@ 0x00000000) GPIO status */
__IOM uint32_t GPIO_QSPI_SCLK_CTRL; /*!< (@ 0x00000004) GPIO control including function select and overrides. */
__IOM uint32_t GPIO_QSPI_SS_STATUS; /*!< (@ 0x00000008) GPIO status */
__IOM uint32_t GPIO_QSPI_SS_CTRL; /*!< (@ 0x0000000C) GPIO control including function select and overrides. */
__IOM uint32_t GPIO_QSPI_SD0_STATUS; /*!< (@ 0x00000010) GPIO status */
__IOM uint32_t GPIO_QSPI_SD0_CTRL; /*!< (@ 0x00000014) GPIO control including function select and overrides. */
__IOM uint32_t GPIO_QSPI_SD1_STATUS; /*!< (@ 0x00000018) GPIO status */
__IOM uint32_t GPIO_QSPI_SD1_CTRL; /*!< (@ 0x0000001C) GPIO control including function select and overrides. */
__IOM uint32_t GPIO_QSPI_SD2_STATUS; /*!< (@ 0x00000020) GPIO status */
__IOM uint32_t GPIO_QSPI_SD2_CTRL; /*!< (@ 0x00000024) GPIO control including function select and overrides. */
__IOM uint32_t GPIO_QSPI_SD3_STATUS; /*!< (@ 0x00000028) GPIO status */
__IOM uint32_t GPIO_QSPI_SD3_CTRL; /*!< (@ 0x0000002C) GPIO control including function select and overrides. */
__IOM uint32_t INTR; /*!< (@ 0x00000030) Raw Interrupts */
__IOM uint32_t PROC0_INTE; /*!< (@ 0x00000034) Interrupt Enable for proc0 */
__IOM uint32_t PROC0_INTF; /*!< (@ 0x00000038) Interrupt Force for proc0 */
__IOM uint32_t PROC0_INTS; /*!< (@ 0x0000003C) Interrupt status after masking & forcing for
proc0 */
__IOM uint32_t PROC1_INTE; /*!< (@ 0x00000040) Interrupt Enable for proc1 */
__IOM uint32_t PROC1_INTF; /*!< (@ 0x00000044) Interrupt Force for proc1 */
__IOM uint32_t PROC1_INTS; /*!< (@ 0x00000048) Interrupt status after masking & forcing for
proc1 */
__IOM uint32_t DORMANT_WAKE_INTE; /*!< (@ 0x0000004C) Interrupt Enable for dormant_wake */
__IOM uint32_t DORMANT_WAKE_INTF; /*!< (@ 0x00000050) Interrupt Force for dormant_wake */
__IOM uint32_t DORMANT_WAKE_INTS; /*!< (@ 0x00000054) Interrupt status after masking & forcing for
dormant_wake */
} IO_QSPI_Type; /*!< Size = 88 (0x58) */
/* =========================================================================================================================== */
/* ================ PADS_BANK0 ================ */
/* =========================================================================================================================== */
/**
* @brief PADS_BANK0 (PADS_BANK0)
*/
typedef struct { /*!< (@ 0x4001C000) PADS_BANK0 Structure */
__IOM uint32_t VOLTAGE_SELECT; /*!< (@ 0x00000000) Voltage select. Per bank control */
__IOM uint32_t GPIO0; /*!< (@ 0x00000004) Pad control register */
__IOM uint32_t GPIO1; /*!< (@ 0x00000008) Pad control register */
__IOM uint32_t GPIO2; /*!< (@ 0x0000000C) Pad control register */
__IOM uint32_t GPIO3; /*!< (@ 0x00000010) Pad control register */
__IOM uint32_t GPIO4; /*!< (@ 0x00000014) Pad control register */
__IOM uint32_t GPIO5; /*!< (@ 0x00000018) Pad control register */
__IOM uint32_t GPIO6; /*!< (@ 0x0000001C) Pad control register */
__IOM uint32_t GPIO7; /*!< (@ 0x00000020) Pad control register */
__IOM uint32_t GPIO8; /*!< (@ 0x00000024) Pad control register */
__IOM uint32_t GPIO9; /*!< (@ 0x00000028) Pad control register */
__IOM uint32_t GPIO10; /*!< (@ 0x0000002C) Pad control register */
__IOM uint32_t GPIO11; /*!< (@ 0x00000030) Pad control register */
__IOM uint32_t GPIO12; /*!< (@ 0x00000034) Pad control register */
__IOM uint32_t GPIO13; /*!< (@ 0x00000038) Pad control register */
__IOM uint32_t GPIO14; /*!< (@ 0x0000003C) Pad control register */
__IOM uint32_t GPIO15; /*!< (@ 0x00000040) Pad control register */
__IOM uint32_t GPIO16; /*!< (@ 0x00000044) Pad control register */
__IOM uint32_t GPIO17; /*!< (@ 0x00000048) Pad control register */
__IOM uint32_t GPIO18; /*!< (@ 0x0000004C) Pad control register */
__IOM uint32_t GPIO19; /*!< (@ 0x00000050) Pad control register */
__IOM uint32_t GPIO20; /*!< (@ 0x00000054) Pad control register */
__IOM uint32_t GPIO21; /*!< (@ 0x00000058) Pad control register */
__IOM uint32_t GPIO22; /*!< (@ 0x0000005C) Pad control register */
__IOM uint32_t GPIO23; /*!< (@ 0x00000060) Pad control register */
__IOM uint32_t GPIO24; /*!< (@ 0x00000064) Pad control register */
__IOM uint32_t GPIO25; /*!< (@ 0x00000068) Pad control register */
__IOM uint32_t GPIO26; /*!< (@ 0x0000006C) Pad control register */
__IOM uint32_t GPIO27; /*!< (@ 0x00000070) Pad control register */
__IOM uint32_t GPIO28; /*!< (@ 0x00000074) Pad control register */
__IOM uint32_t GPIO29; /*!< (@ 0x00000078) Pad control register */
__IOM uint32_t SWCLK; /*!< (@ 0x0000007C) Pad control register */
__IOM uint32_t SWD; /*!< (@ 0x00000080) Pad control register */
} PADS_BANK0_Type; /*!< Size = 132 (0x84) */
/* =========================================================================================================================== */
/* ================ PADS_QSPI ================ */
/* =========================================================================================================================== */
/**
* @brief PADS_QSPI (PADS_QSPI)
*/
typedef struct { /*!< (@ 0x40020000) PADS_QSPI Structure */
__IOM uint32_t VOLTAGE_SELECT; /*!< (@ 0x00000000) Voltage select. Per bank control */
__IOM uint32_t GPIO_QSPI_SCLK; /*!< (@ 0x00000004) Pad control register */
__IOM uint32_t GPIO_QSPI_SD0; /*!< (@ 0x00000008) Pad control register */
__IOM uint32_t GPIO_QSPI_SD1; /*!< (@ 0x0000000C) Pad control register */
__IOM uint32_t GPIO_QSPI_SD2; /*!< (@ 0x00000010) Pad control register */
__IOM uint32_t GPIO_QSPI_SD3; /*!< (@ 0x00000014) Pad control register */
__IOM uint32_t GPIO_QSPI_SS; /*!< (@ 0x00000018) Pad control register */
} PADS_QSPI_Type; /*!< Size = 28 (0x1c) */
/* =========================================================================================================================== */
/* ================ XOSC ================ */
/* =========================================================================================================================== */
/**
* @brief Controls the crystal oscillator (XOSC)
*/
typedef struct { /*!< (@ 0x40024000) XOSC Structure */
__IOM uint32_t CTRL; /*!< (@ 0x00000000) Crystal Oscillator Control */
__IOM uint32_t STATUS; /*!< (@ 0x00000004) Crystal Oscillator Status */
__IOM uint32_t DORMANT; /*!< (@ 0x00000008) Crystal Oscillator pause control
This is used to save power by pausing the
XOSC
On power-up this field is initialised to
WAKE
An invalid write will also select WAKE
WARNING: stop the PLLs before selecting
dormant mode
WARNING: setup the irq before selecting
dormant mode */
__IOM uint32_t STARTUP; /*!< (@ 0x0000000C) Controls the startup delay */
__IM uint32_t RESERVED[3];
__IOM uint32_t COUNT; /*!< (@ 0x0000001C) A down counter running at the xosc frequency
which counts to zero and stops.
To start the counter write a non-zero value.
Can be used for short software pauses when
setting up time sensitive hardware. */
} XOSC_Type; /*!< Size = 32 (0x20) */
/* =========================================================================================================================== */
/* ================ PLL_SYS ================ */
/* =========================================================================================================================== */
/**
* @brief PLL_SYS (PLL_SYS)
*/
typedef struct { /*!< (@ 0x40028000) PLL_SYS Structure */
__IOM uint32_t CS; /*!< (@ 0x00000000) Control and Status
GENERAL CONSTRAINTS:
Reference clock frequency min=5MHz, max=800MHz
Feedback divider min=16, max=320
VCO frequency min=750MHz, max=1600MHz */
__IOM uint32_t PWR; /*!< (@ 0x00000004) Controls the PLL power modes. */
__IOM uint32_t FBDIV_INT; /*!< (@ 0x00000008) Feedback divisor
(note: this PLL does not support fractional
division) */
__IOM uint32_t PRIM; /*!< (@ 0x0000000C) Controls the PLL post dividers for the primary
output
(note: this PLL does not have a secondary
output)
the primary output is driven from VCO divided
by postdiv1*postdiv2 */
} PLL_SYS_Type; /*!< Size = 16 (0x10) */
/* =========================================================================================================================== */
/* ================ BUSCTRL ================ */
/* =========================================================================================================================== */
/**
* @brief Register block for busfabric control signals and performance counters (BUSCTRL)
*/
typedef struct { /*!< (@ 0x40030000) BUSCTRL Structure */
__IOM uint32_t BUS_PRIORITY; /*!< (@ 0x00000000) Set the priority of each master for bus arbitration. */
__IOM uint32_t BUS_PRIORITY_ACK; /*!< (@ 0x00000004) Bus priority acknowledge */
__IOM uint32_t PERFCTR0; /*!< (@ 0x00000008) Bus fabric performance counter 0 */
__IOM uint32_t PERFSEL0; /*!< (@ 0x0000000C) Bus fabric performance event select for PERFCTR0 */
__IOM uint32_t PERFCTR1; /*!< (@ 0x00000010) Bus fabric performance counter 1 */
__IOM uint32_t PERFSEL1; /*!< (@ 0x00000014) Bus fabric performance event select for PERFCTR1 */
__IOM uint32_t PERFCTR2; /*!< (@ 0x00000018) Bus fabric performance counter 2 */
__IOM uint32_t PERFSEL2; /*!< (@ 0x0000001C) Bus fabric performance event select for PERFCTR2 */
__IOM uint32_t PERFCTR3; /*!< (@ 0x00000020) Bus fabric performance counter 3 */
__IOM uint32_t PERFSEL3; /*!< (@ 0x00000024) Bus fabric performance event select for PERFCTR3 */
} BUSCTRL_Type; /*!< Size = 40 (0x28) */
/* =========================================================================================================================== */
/* ================ UART0 ================ */
/* =========================================================================================================================== */
/**
* @brief UART0 (UART0)
*/
typedef struct { /*!< (@ 0x40034000) UART0 Structure */
__IOM uint32_t UARTDR; /*!< (@ 0x00000000) Data Register, UARTDR */
__IOM uint32_t UARTRSR; /*!< (@ 0x00000004) Receive Status Register/Error Clear Register,
UARTRSR/UARTECR */
__IM uint32_t RESERVED[4];
__IOM uint32_t UARTFR; /*!< (@ 0x00000018) Flag Register, UARTFR */
__IM uint32_t RESERVED1;
__IOM uint32_t UARTILPR; /*!< (@ 0x00000020) IrDA Low-Power Counter Register, UARTILPR */
__IOM uint32_t UARTIBRD; /*!< (@ 0x00000024) Integer Baud Rate Register, UARTIBRD */
__IOM uint32_t UARTFBRD; /*!< (@ 0x00000028) Fractional Baud Rate Register, UARTFBRD */
__IOM uint32_t UARTLCR_H; /*!< (@ 0x0000002C) Line Control Register, UARTLCR_H */
__IOM uint32_t UARTCR; /*!< (@ 0x00000030) Control Register, UARTCR */
__IOM uint32_t UARTIFLS; /*!< (@ 0x00000034) Interrupt FIFO Level Select Register, UARTIFLS */
__IOM uint32_t UARTIMSC; /*!< (@ 0x00000038) Interrupt Mask Set/Clear Register, UARTIMSC */
__IOM uint32_t UARTRIS; /*!< (@ 0x0000003C) Raw Interrupt Status Register, UARTRIS */
__IOM uint32_t UARTMIS; /*!< (@ 0x00000040) Masked Interrupt Status Register, UARTMIS */
__IOM uint32_t UARTICR; /*!< (@ 0x00000044) Interrupt Clear Register, UARTICR */
__IOM uint32_t UARTDMACR; /*!< (@ 0x00000048) DMA Control Register, UARTDMACR */
__IM uint32_t RESERVED2[997];
__IOM uint32_t UARTPERIPHID0; /*!< (@ 0x00000FE0) UARTPeriphID0 Register */
__IOM uint32_t UARTPERIPHID1; /*!< (@ 0x00000FE4) UARTPeriphID1 Register */
__IOM uint32_t UARTPERIPHID2; /*!< (@ 0x00000FE8) UARTPeriphID2 Register */
__IOM uint32_t UARTPERIPHID3; /*!< (@ 0x00000FEC) UARTPeriphID3 Register */
__IOM uint32_t UARTPCELLID0; /*!< (@ 0x00000FF0) UARTPCellID0 Register */
__IOM uint32_t UARTPCELLID1; /*!< (@ 0x00000FF4) UARTPCellID1 Register */
__IOM uint32_t UARTPCELLID2; /*!< (@ 0x00000FF8) UARTPCellID2 Register */
__IOM uint32_t UARTPCELLID3; /*!< (@ 0x00000FFC) UARTPCellID3 Register */
} UART0_Type; /*!< Size = 4096 (0x1000) */
/* =========================================================================================================================== */
/* ================ SPI0 ================ */
/* =========================================================================================================================== */
/**
* @brief SPI0 (SPI0)
*/
typedef struct { /*!< (@ 0x4003C000) SPI0 Structure */
__IOM uint32_t SSPCR0; /*!< (@ 0x00000000) Control register 0, SSPCR0 on page 3-4 */
__IOM uint32_t SSPCR1; /*!< (@ 0x00000004) Control register 1, SSPCR1 on page 3-5 */
__IOM uint32_t SSPDR; /*!< (@ 0x00000008) Data register, SSPDR on page 3-6 */
__IOM uint32_t SSPSR; /*!< (@ 0x0000000C) Status register, SSPSR on page 3-7 */
__IOM uint32_t SSPCPSR; /*!< (@ 0x00000010) Clock prescale register, SSPCPSR on page 3-8 */
__IOM uint32_t SSPIMSC; /*!< (@ 0x00000014) Interrupt mask set or clear register, SSPIMSC
on page 3-9 */
__IOM uint32_t SSPRIS; /*!< (@ 0x00000018) Raw interrupt status register, SSPRIS on page
3-10 */
__IOM uint32_t SSPMIS; /*!< (@ 0x0000001C) Masked interrupt status register, SSPMIS on page
3-11 */
__IOM uint32_t SSPICR; /*!< (@ 0x00000020) Interrupt clear register, SSPICR on page 3-11 */
__IOM uint32_t SSPDMACR; /*!< (@ 0x00000024) DMA control register, SSPDMACR on page 3-12 */
__IM uint32_t RESERVED[1006];
__IOM uint32_t SSPPERIPHID0; /*!< (@ 0x00000FE0) Peripheral identification registers, SSPPeriphID0-3
on page 3-13 */
__IOM uint32_t SSPPERIPHID1; /*!< (@ 0x00000FE4) Peripheral identification registers, SSPPeriphID0-3
on page 3-13 */
__IOM uint32_t SSPPERIPHID2; /*!< (@ 0x00000FE8) Peripheral identification registers, SSPPeriphID0-3
on page 3-13 */
__IOM uint32_t SSPPERIPHID3; /*!< (@ 0x00000FEC) Peripheral identification registers, SSPPeriphID0-3
on page 3-13 */
__IOM uint32_t SSPPCELLID0; /*!< (@ 0x00000FF0) PrimeCell identification registers, SSPPCellID0-3
on page 3-16 */
__IOM uint32_t SSPPCELLID1; /*!< (@ 0x00000FF4) PrimeCell identification registers, SSPPCellID0-3
on page 3-16 */
__IOM uint32_t SSPPCELLID2; /*!< (@ 0x00000FF8) PrimeCell identification registers, SSPPCellID0-3
on page 3-16 */
__IOM uint32_t SSPPCELLID3; /*!< (@ 0x00000FFC) PrimeCell identification registers, SSPPCellID0-3
on page 3-16 */
} SPI0_Type; /*!< Size = 4096 (0x1000) */
/* =========================================================================================================================== */
/* ================ I2C0 ================ */
/* =========================================================================================================================== */
/**
* @brief DW_apb_i2c address block\n\n
List of configuration constants for the Synopsys I2C hardware (you may see references to these in I2C register header; these are *fixed* values, set at hardware design time):\n\n
IC_ULTRA_FAST_MODE ................ 0x0\n
IC_UFM_TBUF_CNT_DEFAULT ........... 0x8\n
IC_UFM_SCL_LOW_COUNT .............. 0x0008\n
IC_UFM_SCL_HIGH_COUNT ............. 0x0006\n
IC_TX_TL .......................... 0x0\n
IC_TX_CMD_BLOCK ................... 0x1\n
IC_HAS_DMA ........................ 0x1\n
IC_HAS_ASYNC_FIFO ................. 0x0\n
IC_SMBUS_ARP ...................... 0x0\n
IC_FIRST_DATA_BYTE_STATUS ......... 0x1\n
IC_INTR_IO ........................ 0x1\n
IC_MASTER_MODE .................... 0x1\n
IC_DEFAULT_ACK_GENERAL_CALL ....... 0x1\n
IC_INTR_POL ....................... 0x1\n
IC_OPTIONAL_SAR ................... 0x0\n
IC_DEFAULT_TAR_SLAVE_ADDR ......... 0x055\n
IC_DEFAULT_SLAVE_ADDR ............. 0x055\n
IC_DEFAULT_HS_SPKLEN .............. 0x1\n
IC_FS_SCL_HIGH_COUNT .............. 0x0006\n
IC_HS_SCL_LOW_COUNT ............... 0x0008\n
IC_DEVICE_ID_VALUE ................ 0x0\n
IC_10BITADDR_MASTER ............... 0x0\n
IC_CLK_FREQ_OPTIMIZATION .......... 0x0\n
IC_DEFAULT_FS_SPKLEN .............. 0x7\n
IC_ADD_ENCODED_PARAMS ............. 0x0\n
IC_DEFAULT_SDA_HOLD ............... 0x000001\n
IC_DEFAULT_SDA_SETUP .............. 0x64\n
IC_AVOID_RX_FIFO_FLUSH_ON_TX_ABRT . 0x0\n
IC_CLOCK_PERIOD ................... 100\n
IC_EMPTYFIFO_HOLD_MASTER_EN ....... 1\n
IC_RESTART_EN ..................... 0x1\n
IC_TX_CMD_BLOCK_DEFAULT ........... 0x0\n
IC_BUS_CLEAR_FEATURE .............. 0x0\n
IC_CAP_LOADING .................... 100\n
IC_FS_SCL_LOW_COUNT ............... 0x000d\n
APB_DATA_WIDTH .................... 32\n
IC_SDA_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff\n
IC_SLV_DATA_NACK_ONLY ............. 0x1\n
IC_10BITADDR_SLAVE ................ 0x0\n
IC_CLK_TYPE ....................... 0x0\n
IC_SMBUS_UDID_MSB ................. 0x0\n
IC_SMBUS_SUSPEND_ALERT ............ 0x0\n
IC_HS_SCL_HIGH_COUNT .............. 0x0006\n
IC_SLV_RESTART_DET_EN ............. 0x1\n
IC_SMBUS .......................... 0x0\n
IC_OPTIONAL_SAR_DEFAULT ........... 0x0\n
IC_PERSISTANT_SLV_ADDR_DEFAULT .... 0x0\n
IC_USE_COUNTS ..................... 0x0\n
IC_RX_BUFFER_DEPTH ................ 16\n
IC_SCL_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff\n
IC_RX_FULL_HLD_BUS_EN ............. 0x1\n
IC_SLAVE_DISABLE .................. 0x1\n
IC_RX_TL .......................... 0x0\n
IC_DEVICE_ID ...................... 0x0\n
IC_HC_COUNT_VALUES ................ 0x0\n
I2C_DYNAMIC_TAR_UPDATE ............ 0\n
IC_SMBUS_CLK_LOW_MEXT_DEFAULT ..... 0xffffffff\n
IC_SMBUS_CLK_LOW_SEXT_DEFAULT ..... 0xffffffff\n
IC_HS_MASTER_CODE ................. 0x1\n
IC_SMBUS_RST_IDLE_CNT_DEFAULT ..... 0xffff\n
IC_SMBUS_UDID_LSB_DEFAULT ......... 0xffffffff\n
IC_SS_SCL_HIGH_COUNT .............. 0x0028\n
IC_SS_SCL_LOW_COUNT ............... 0x002f\n
IC_MAX_SPEED_MODE ................. 0x2\n
IC_STAT_FOR_CLK_STRETCH ........... 0x0\n
IC_STOP_DET_IF_MASTER_ACTIVE ...... 0x0\n
IC_DEFAULT_UFM_SPKLEN ............. 0x1\n
IC_TX_BUFFER_DEPTH ................ 16 (I2C0)
*/
typedef struct { /*!< (@ 0x40044000) I2C0 Structure */
__IOM uint32_t IC_CON; /*!< (@ 0x00000000) I2C Control Register. This register can be written
only when the DW_apb_i2c is disabled, which
corresponds to the IC_ENABLE[0] register
being set to 0. Writes at other times have
no effect.
Read/Write Access: - bit 10 is read only.
- bit 11 is read only - bit 16 is read only
- bit 17 is read only - bits 18 and 19 are
read only. */
__IOM uint32_t IC_TAR; /*!< (@ 0x00000004) I2C Target Address Register
This register is 12 bits wide, and bits
31:12 are reserved. This register can be
written to only when IC_ENABLE[0] is set
to 0.
Note: If the software or application is
aware that the DW_apb_i2c is not using the
TAR address for the pending commands in
the Tx FIFO, then it is possible to update
the TAR address even while the Tx FIFO has
entries (IC_STATUS[2]= 0). - It is not necessary
to perform any write to this register if
DW_apb_ */
__IOM uint32_t IC_SAR; /*!< (@ 0x00000008) I2C Slave Address Register */
__IM uint32_t RESERVED;
__IOM uint32_t IC_DATA_CMD; /*!< (@ 0x00000010) I2C Rx/Tx Data Buffer and Command Register; this
is the register the CPU writes to when filling
the TX FIFO and the CPU reads from when
retrieving bytes from RX FIFO.
The size of the register changes as follows:
Write: - 11 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=1
- 9 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=0
Read: - 12 bits when IC_FIRST_DATA_BYTE_STATUS
= 1 - 8 bits when IC_FIRST_DATA_BYTE_STATUS
= 0 Note: In order for the DW_apb_i2c to
continue acknowledging */
__IOM uint32_t IC_SS_SCL_HCNT; /*!< (@ 0x00000014) Standard Speed I2C Clock SCL High Count Register */
__IOM uint32_t IC_SS_SCL_LCNT; /*!< (@ 0x00000018) Standard Speed I2C Clock SCL Low Count Register */
__IOM uint32_t IC_FS_SCL_HCNT; /*!< (@ 0x0000001C) Fast Mode or Fast Mode Plus I2C Clock SCL High
Count Register */
__IOM uint32_t IC_FS_SCL_LCNT; /*!< (@ 0x00000020) Fast Mode or Fast Mode Plus I2C Clock SCL Low
Count Register */
__IM uint32_t RESERVED1[2];
__IOM uint32_t IC_INTR_STAT; /*!< (@ 0x0000002C) I2C Interrupt Status Register
Each bit in this register has a corresponding
mask bit in the IC_INTR_MASK register. These
bits are cleared by reading the matching
interrupt clear register. The unmasked raw
versions of these bits are available in
the IC_RAW_INTR_STAT register. */
__IOM uint32_t IC_INTR_MASK; /*!< (@ 0x00000030) I2C Interrupt Mask Register.
These bits mask their corresponding interrupt
status bits. This register is active low;
a value of 0 masks the interrupt, whereas
a value of 1 unmasks the interrupt. */
__IOM uint32_t IC_RAW_INTR_STAT; /*!< (@ 0x00000034) I2C Raw Interrupt Status Register
Unlike the IC_INTR_STAT register, these
bits are not masked so they always show
the true status of the DW_apb_i2c. */
__IOM uint32_t IC_RX_TL; /*!< (@ 0x00000038) I2C Receive FIFO Threshold Register */
__IOM uint32_t IC_TX_TL; /*!< (@ 0x0000003C) I2C Transmit FIFO Threshold Register */
__IOM uint32_t IC_CLR_INTR; /*!< (@ 0x00000040) Clear Combined and Individual Interrupt Register */
__IOM uint32_t IC_CLR_RX_UNDER; /*!< (@ 0x00000044) Clear RX_UNDER Interrupt Register */
__IOM uint32_t IC_CLR_RX_OVER; /*!< (@ 0x00000048) Clear RX_OVER Interrupt Register */
__IOM uint32_t IC_CLR_TX_OVER; /*!< (@ 0x0000004C) Clear TX_OVER Interrupt Register */
__IOM uint32_t IC_CLR_RD_REQ; /*!< (@ 0x00000050) Clear RD_REQ Interrupt Register */
__IOM uint32_t IC_CLR_TX_ABRT; /*!< (@ 0x00000054) Clear TX_ABRT Interrupt Register */
__IOM uint32_t IC_CLR_RX_DONE; /*!< (@ 0x00000058) Clear RX_DONE Interrupt Register */
__IOM uint32_t IC_CLR_ACTIVITY; /*!< (@ 0x0000005C) Clear ACTIVITY Interrupt Register */
__IOM uint32_t IC_CLR_STOP_DET; /*!< (@ 0x00000060) Clear STOP_DET Interrupt Register */
__IOM uint32_t IC_CLR_START_DET; /*!< (@ 0x00000064) Clear START_DET Interrupt Register */
__IOM uint32_t IC_CLR_GEN_CALL; /*!< (@ 0x00000068) Clear GEN_CALL Interrupt Register */
__IOM uint32_t IC_ENABLE; /*!< (@ 0x0000006C) I2C Enable Register */
__IOM uint32_t IC_STATUS; /*!< (@ 0x00000070) I2C Status Register
This is a read-only register used to indicate
the current transfer status and FIFO status.
The status register may be read at any time.
None of the bits in this register request
an interrupt.
When the I2C is disabled by writing 0 in
bit 0 of the IC_ENABLE register: - Bits
1 and 2 are set to 1 - Bits 3 and 10 are
set to 0 When the master or slave state
machines goes to idle and ic_en=0: - Bits
5 and 6 are set to 0 */
__IOM uint32_t IC_TXFLR; /*!< (@ 0x00000074) I2C Transmit FIFO Level Register This register
contains the number of valid data entries
in the transmit FIFO buffer. It is cleared
whenever: - The I2C is disabled - There
is a transmit abort - that is, TX_ABRT bit
is set in the IC_RAW_INTR_STAT register
- The slave bulk transmit mode is aborted
The register increments whenever data is
placed into the transmit FIFO and decrements
when data is taken from the transmit FIFO. */
__IOM uint32_t IC_RXFLR; /*!< (@ 0x00000078) I2C Receive FIFO Level Register This register
contains the number of valid data entries
in the receive FIFO buffer. It is cleared
whenever: - The I2C is disabled - Whenever
there is a transmit abort caused by any
of the events tracked in IC_TX_ABRT_SOURCE
The register increments whenever data is
placed into the receive FIFO and decrements
when data is taken from the receive FIFO. */
__IOM uint32_t IC_SDA_HOLD; /*!< (@ 0x0000007C) I2C SDA Hold Time Length Register
The bits [15:0] of this register are used
to control the hold time of SDA during transmit
in both slave and master mode (after SCL
goes from HIGH to LOW).
The bits [23:16] of this register are used
to extend the SDA transition (if any) whenever
SCL is HIGH in the receiver in either master
or slave mode.
Writes to this register succeed only when
IC_ENABLE[0]=0.
The values in this register are */
__IOM uint32_t IC_TX_ABRT_SOURCE; /*!< (@ 0x00000080) I2C Transmit Abort Source Register
This register has 32 bits that indicate
the source of the TX_ABRT bit. Except for
Bit 9, this register is cleared whenever
the IC_CLR_TX_ABRT register or the IC_CLR_INTR
register is read. To clear Bit 9, the source
of the ABRT_SBYTE_NORSTRT must be fixed
first; RESTART must be enabled (IC_CON[5]=1),
the SPECIAL bit must be cleared (IC_TAR[11]),
or the GC_OR_START bit must be cleared (IC_TAR[10]).
Once the source of the ABRT */
__IOM uint32_t IC_SLV_DATA_NACK_ONLY; /*!< (@ 0x00000084) Generate Slave Data NACK Register
The register is used to generate a NACK
for the data part of a transfer when DW_apb_i2c
is acting as a slave-receiver. This register
only exists when the IC_SLV_DATA_NACK_ONLY
parameter is set to 1. When this parameter
disabled, this register does not exist and
writing to the register's address has no
effect.
A write can occur on this register if both
of the following conditions are met: - DW_apb_i2c
is disabled (IC_ENABLE[0 */
__IOM uint32_t IC_DMA_CR; /*!< (@ 0x00000088) DMA Control Register
The register is used to enable the DMA Controller
interface operation. There is a separate
bit for transmit and receive. This can be
programmed regardless of the state of IC_ENABLE. */
__IOM uint32_t IC_DMA_TDLR; /*!< (@ 0x0000008C) DMA Transmit Data Level Register */
__IOM uint32_t IC_DMA_RDLR; /*!< (@ 0x00000090) I2C Receive Data Level Register */
__IOM uint32_t IC_SDA_SETUP; /*!< (@ 0x00000094) I2C SDA Setup Register
This register controls the amount of time
delay (in terms of number of ic_clk clock
periods) introduced in the rising edge of
SCL - relative to SDA changing - when DW_apb_i2c
services a read request in a slave-transmitter
operation. The relevant I2C requirement
is tSU:DAT (note 4) as detailed in the I2C
Bus Specification. This register must be
programmed with a value equal to or greater
than 2.
Writes to this register succeed only when */
__IOM uint32_t IC_ACK_GENERAL_CALL; /*!< (@ 0x00000098) I2C ACK General Call Register
The register controls whether DW_apb_i2c
responds with a ACK or NACK when it receives
an I2C General Call address.
This register is applicable only when the
DW_apb_i2c is in slave mode. */
__IOM uint32_t IC_ENABLE_STATUS; /*!< (@ 0x0000009C) I2C Enable Status Register
The register is used to report the DW_apb_i2c
hardware status when the IC_ENABLE[0] register
is set from 1 to 0; that is, when DW_apb_i2c
is disabled.
If IC_ENABLE[0] has been set to 1, bits
2:1 are forced to 0, and bit 0 is forced
to 1.
If IC_ENABLE[0] has been set to 0, bits
2:1 is only be valid as soon as bit 0 is
read as '0'.
Note: When IC_ENABLE[0] has been set to
0, a delay occurs for bit 0 t */
__IOM uint32_t IC_FS_SPKLEN; /*!< (@ 0x000000A0) I2C SS, FS or FM+ spike suppression limit
This register is used to store the duration,
measured in ic_clk cycles, of the longest
spike that is filtered out by the spike
suppression logic when the component is
operating in SS, FS or FM+ modes. The relevant
I2C requirement is tSP (table 4) as detailed
in the I2C Bus Specification. This register
must be programmed with a minimum value
of 1. */
__IM uint32_t RESERVED2;
__IOM uint32_t IC_CLR_RESTART_DET; /*!< (@ 0x000000A8) Clear RESTART_DET Interrupt Register */
__IM uint32_t RESERVED3[18];
__IOM uint32_t IC_COMP_PARAM_1; /*!< (@ 0x000000F4) Component Parameter Register 1
Note This register is not implemented and
therefore reads as 0. If it was implemented
it would be a constant read-only register
that contains encoded information about
the component's parameter settings. Fields
shown below are the settings for those parameters */
__IOM uint32_t IC_COMP_VERSION; /*!< (@ 0x000000F8) I2C Component Version Register */
__IOM uint32_t IC_COMP_TYPE; /*!< (@ 0x000000FC) I2C Component Type Register */
} I2C0_Type; /*!< Size = 256 (0x100) */
/* =========================================================================================================================== */
/* ================ ADC ================ */
/* =========================================================================================================================== */
/**
* @brief Control and data interface to SAR ADC (ADC)
*/
typedef struct { /*!< (@ 0x4004C000) ADC Structure */
__IOM uint32_t CS; /*!< (@ 0x00000000) ADC Control and Status */
__IOM uint32_t RESULT; /*!< (@ 0x00000004) Result of most recent ADC conversion */
__IOM uint32_t FCS; /*!< (@ 0x00000008) FIFO control and status */
__IOM uint32_t FIFO; /*!< (@ 0x0000000C) Conversion result FIFO */
__IOM uint32_t DIV; /*!< (@ 0x00000010) Clock divider. If non-zero, CS_START_MANY will
start conversions
at regular intervals rather than back-to-back.
The divider is reset when either of these
fields are written.
Total period is 1 + INT + FRAC / 256 */
__IOM uint32_t INTR; /*!< (@ 0x00000014) Raw Interrupts */
__IOM uint32_t INTE; /*!< (@ 0x00000018) Interrupt Enable */
__IOM uint32_t INTF; /*!< (@ 0x0000001C) Interrupt Force */
__IOM uint32_t INTS; /*!< (@ 0x00000020) Interrupt status after masking & forcing */
} ADC_Type; /*!< Size = 36 (0x24) */
/* =========================================================================================================================== */
/* ================ PWM ================ */
/* =========================================================================================================================== */
/**
* @brief Simple PWM (PWM)
*/
typedef struct { /*!< (@ 0x40050000) PWM Structure */
__IOM uint32_t CH0_CSR; /*!< (@ 0x00000000) Control and status register */
__IOM uint32_t CH0_DIV; /*!< (@ 0x00000004) INT and FRAC form a fixed-point fractional number.
Counting rate is system clock frequency
divided by this number.
Fractional division uses simple 1st-order
sigma-delta. */
__IOM uint32_t CH0_CTR; /*!< (@ 0x00000008) Direct access to the PWM counter */
__IOM uint32_t CH0_CC; /*!< (@ 0x0000000C) Counter compare values */
__IOM uint32_t CH0_TOP; /*!< (@ 0x00000010) Counter wrap value */
__IOM uint32_t CH1_CSR; /*!< (@ 0x00000014) Control and status register */
__IOM uint32_t CH1_DIV; /*!< (@ 0x00000018) INT and FRAC form a fixed-point fractional number.
Counting rate is system clock frequency
divided by this number.
Fractional division uses simple 1st-order
sigma-delta. */
__IOM uint32_t CH1_CTR; /*!< (@ 0x0000001C) Direct access to the PWM counter */
__IOM uint32_t CH1_CC; /*!< (@ 0x00000020) Counter compare values */
__IOM uint32_t CH1_TOP; /*!< (@ 0x00000024) Counter wrap value */
__IOM uint32_t CH2_CSR; /*!< (@ 0x00000028) Control and status register */
__IOM uint32_t CH2_DIV; /*!< (@ 0x0000002C) INT and FRAC form a fixed-point fractional number.
Counting rate is system clock frequency
divided by this number.
Fractional division uses simple 1st-order
sigma-delta. */
__IOM uint32_t CH2_CTR; /*!< (@ 0x00000030) Direct access to the PWM counter */
__IOM uint32_t CH2_CC; /*!< (@ 0x00000034) Counter compare values */
__IOM uint32_t CH2_TOP; /*!< (@ 0x00000038) Counter wrap value */
__IOM uint32_t CH3_CSR; /*!< (@ 0x0000003C) Control and status register */
__IOM uint32_t CH3_DIV; /*!< (@ 0x00000040) INT and FRAC form a fixed-point fractional number.
Counting rate is system clock frequency
divided by this number.
Fractional division uses simple 1st-order
sigma-delta. */
__IOM uint32_t CH3_CTR; /*!< (@ 0x00000044) Direct access to the PWM counter */
__IOM uint32_t CH3_CC; /*!< (@ 0x00000048) Counter compare values */
__IOM uint32_t CH3_TOP; /*!< (@ 0x0000004C) Counter wrap value */
__IOM uint32_t CH4_CSR; /*!< (@ 0x00000050) Control and status register */
__IOM uint32_t CH4_DIV; /*!< (@ 0x00000054) INT and FRAC form a fixed-point fractional number.
Counting rate is system clock frequency
divided by this number.
Fractional division uses simple 1st-order
sigma-delta. */
__IOM uint32_t CH4_CTR; /*!< (@ 0x00000058) Direct access to the PWM counter */
__IOM uint32_t CH4_CC; /*!< (@ 0x0000005C) Counter compare values */
__IOM uint32_t CH4_TOP; /*!< (@ 0x00000060) Counter wrap value */
__IOM uint32_t CH5_CSR; /*!< (@ 0x00000064) Control and status register */
__IOM uint32_t CH5_DIV; /*!< (@ 0x00000068) INT and FRAC form a fixed-point fractional number.
Counting rate is system clock frequency
divided by this number.
Fractional division uses simple 1st-order
sigma-delta. */
__IOM uint32_t CH5_CTR; /*!< (@ 0x0000006C) Direct access to the PWM counter */
__IOM uint32_t CH5_CC; /*!< (@ 0x00000070) Counter compare values */
__IOM uint32_t CH5_TOP; /*!< (@ 0x00000074) Counter wrap value */
__IOM uint32_t CH6_CSR; /*!< (@ 0x00000078) Control and status register */
__IOM uint32_t CH6_DIV; /*!< (@ 0x0000007C) INT and FRAC form a fixed-point fractional number.
Counting rate is system clock frequency
divided by this number.
Fractional division uses simple 1st-order
sigma-delta. */
__IOM uint32_t CH6_CTR; /*!< (@ 0x00000080) Direct access to the PWM counter */
__IOM uint32_t CH6_CC; /*!< (@ 0x00000084) Counter compare values */
__IOM uint32_t CH6_TOP; /*!< (@ 0x00000088) Counter wrap value */
__IOM uint32_t CH7_CSR; /*!< (@ 0x0000008C) Control and status register */
__IOM uint32_t CH7_DIV; /*!< (@ 0x00000090) INT and FRAC form a fixed-point fractional number.
Counting rate is system clock frequency
divided by this number.
Fractional division uses simple 1st-order
sigma-delta. */
__IOM uint32_t CH7_CTR; /*!< (@ 0x00000094) Direct access to the PWM counter */
__IOM uint32_t CH7_CC; /*!< (@ 0x00000098) Counter compare values */
__IOM uint32_t CH7_TOP; /*!< (@ 0x0000009C) Counter wrap value */
__IOM uint32_t EN; /*!< (@ 0x000000A0) This register aliases the CSR_EN bits for all
channels.
Writing to this register allows multiple
channels to be enabled
or disabled simultaneously, so they can
run in perfect sync.
For each channel, there is only one physical
EN register bit,
which can be accessed through here or CHx_CSR. */
__IOM uint32_t INTR; /*!< (@ 0x000000A4) Raw Interrupts */
__IOM uint32_t INTE; /*!< (@ 0x000000A8) Interrupt Enable */
__IOM uint32_t INTF; /*!< (@ 0x000000AC) Interrupt Force */
__IOM uint32_t INTS; /*!< (@ 0x000000B0) Interrupt status after masking & forcing */
} PWM_Type; /*!< Size = 180 (0xb4) */
/* =========================================================================================================================== */
/* ================ TIMER ================ */
/* =========================================================================================================================== */
/**
* @brief Controls time and alarms\n
time is a 64 bit value indicating the time in usec since power-on\n
timeh is the top 32 bits of time & timel is the bottom 32 bits\n
to change time write to timelw before timehw\n
to read time read from timelr before timehr\n
An alarm is set by setting alarm_enable and writing to the corresponding alarm register\n
When an alarm is pending, the corresponding alarm_running signal will be high\n
An alarm can be cancelled before it has finished by clearing the alarm_enable\n
When an alarm fires, the corresponding alarm_irq is set and alarm_running is cleared\n
To clear the interrupt write a 1 to the corresponding alarm_irq (TIMER)
*/
typedef struct { /*!< (@ 0x40054000) TIMER Structure */
__OM uint32_t TIMEHW; /*!< (@ 0x00000000) Write to bits 63:32 of time
always write timelw before timehw */
__OM uint32_t TIMELW; /*!< (@ 0x00000004) Write to bits 31:0 of time
writes do not get copied to time until timehw
is written */
__IM uint32_t TIMEHR; /*!< (@ 0x00000008) Read from bits 63:32 of time
always read timelr before timehr */
__IM uint32_t TIMELR; /*!< (@ 0x0000000C) Read from bits 31:0 of time */
__IOM uint32_t ALARM0; /*!< (@ 0x00000010) Arm alarm 0, and configure the time it will fire.
Once armed, the alarm fires when TIMER_ALARM0
== TIMELR.
The alarm will disarm itself once it fires,
and can
be disarmed early using the ARMED status
register. */
__IOM uint32_t ALARM1; /*!< (@ 0x00000014) Arm alarm 1, and configure the time it will fire.
Once armed, the alarm fires when TIMER_ALARM1
== TIMELR.
The alarm will disarm itself once it fires,
and can
be disarmed early using the ARMED status
register. */
__IOM uint32_t ALARM2; /*!< (@ 0x00000018) Arm alarm 2, and configure the time it will fire.
Once armed, the alarm fires when TIMER_ALARM2
== TIMELR.
The alarm will disarm itself once it fires,
and can
be disarmed early using the ARMED status
register. */
__IOM uint32_t ALARM3; /*!< (@ 0x0000001C) Arm alarm 3, and configure the time it will fire.
Once armed, the alarm fires when TIMER_ALARM3
== TIMELR.
The alarm will disarm itself once it fires,
and can
be disarmed early using the ARMED status
register. */
__IOM uint32_t ARMED; /*!< (@ 0x00000020) Indicates the armed/disarmed status of each alarm.
A write to the corresponding ALARMx register
arms the alarm.
Alarms automatically disarm upon firing,
but writing ones here
will disarm immediately without waiting
to fire. */
__IM uint32_t TIMERAWH; /*!< (@ 0x00000024) Raw read from bits 63:32 of time (no side effects) */
__IM uint32_t TIMERAWL; /*!< (@ 0x00000028) Raw read from bits 31:0 of time (no side effects) */
__IOM uint32_t DBGPAUSE; /*!< (@ 0x0000002C) Set bits high to enable pause when the corresponding
debug ports are active */
__IOM uint32_t PAUSE; /*!< (@ 0x00000030) Set high to pause the timer */
__IOM uint32_t INTR; /*!< (@ 0x00000034) Raw Interrupts */
__IOM uint32_t INTE; /*!< (@ 0x00000038) Interrupt Enable */
__IOM uint32_t INTF; /*!< (@ 0x0000003C) Interrupt Force */
__IOM uint32_t INTS; /*!< (@ 0x00000040) Interrupt status after masking & forcing */
} TIMER_Type; /*!< Size = 68 (0x44) */
/* =========================================================================================================================== */
/* ================ WATCHDOG ================ */
/* =========================================================================================================================== */
/**
* @brief WATCHDOG (WATCHDOG)
*/
typedef struct { /*!< (@ 0x40058000) WATCHDOG Structure */
__IOM uint32_t CTRL; /*!< (@ 0x00000000) Watchdog control
The rst_wdsel register determines which
subsystems are reset when the watchdog is
triggered.
The watchdog can be triggered in software. */
__IOM uint32_t LOAD; /*!< (@ 0x00000004) Load the watchdog timer. The maximum setting
is 0xffffff which corresponds to 0xffffff
/ 2 ticks before triggering a watchdog reset
(see errata RP2040-E1). */
__IOM uint32_t REASON; /*!< (@ 0x00000008) Logs the reason for the last reset. Both bits
are zero for the case of a hardware reset. */
__IOM uint32_t SCRATCH0; /*!< (@ 0x0000000C) Scratch register. Information persists through
soft reset of the chip. */
__IOM uint32_t SCRATCH1; /*!< (@ 0x00000010) Scratch register. Information persists through
soft reset of the chip. */
__IOM uint32_t SCRATCH2; /*!< (@ 0x00000014) Scratch register. Information persists through
soft reset of the chip. */
__IOM uint32_t SCRATCH3; /*!< (@ 0x00000018) Scratch register. Information persists through
soft reset of the chip. */
__IOM uint32_t SCRATCH4; /*!< (@ 0x0000001C) Scratch register. Information persists through
soft reset of the chip. */
__IOM uint32_t SCRATCH5; /*!< (@ 0x00000020) Scratch register. Information persists through
soft reset of the chip. */
__IOM uint32_t SCRATCH6; /*!< (@ 0x00000024) Scratch register. Information persists through
soft reset of the chip. */
__IOM uint32_t SCRATCH7; /*!< (@ 0x00000028) Scratch register. Information persists through
soft reset of the chip. */
__IOM uint32_t TICK; /*!< (@ 0x0000002C) Controls the tick generator */
} WATCHDOG_Type; /*!< Size = 48 (0x30) */
/* =========================================================================================================================== */
/* ================ RTC ================ */
/* =========================================================================================================================== */
/**
* @brief Register block to control RTC (RTC)
*/
typedef struct { /*!< (@ 0x4005C000) RTC Structure */
__IOM uint32_t CLKDIV_M1; /*!< (@ 0x00000000) Divider minus 1 for the 1 second counter. Safe
to change the value when RTC is not enabled. */
__IOM uint32_t SETUP_0; /*!< (@ 0x00000004) RTC setup register 0 */
__IOM uint32_t SETUP_1; /*!< (@ 0x00000008) RTC setup register 1 */
__IOM uint32_t CTRL; /*!< (@ 0x0000000C) RTC Control and status */
__IOM uint32_t IRQ_SETUP_0; /*!< (@ 0x00000010) Interrupt setup register 0 */
__IOM uint32_t IRQ_SETUP_1; /*!< (@ 0x00000014) Interrupt setup register 1 */
__IOM uint32_t RTC_1; /*!< (@ 0x00000018) RTC register 1. */
__IOM uint32_t RTC_0; /*!< (@ 0x0000001C) RTC register 0
Read this before RTC 1! */
__IOM uint32_t INTR; /*!< (@ 0x00000020) Raw Interrupts */
__IOM uint32_t INTE; /*!< (@ 0x00000024) Interrupt Enable */
__IOM uint32_t INTF; /*!< (@ 0x00000028) Interrupt Force */
__IOM uint32_t INTS; /*!< (@ 0x0000002C) Interrupt status after masking & forcing */
} RTC_Type; /*!< Size = 48 (0x30) */
/* =========================================================================================================================== */
/* ================ ROSC ================ */
/* =========================================================================================================================== */
/**
* @brief ROSC (ROSC)
*/
typedef struct { /*!< (@ 0x40060000) ROSC Structure */
__IOM uint32_t CTRL; /*!< (@ 0x00000000) Ring Oscillator control */
__IOM uint32_t FREQA; /*!< (@ 0x00000004) The FREQA & FREQB registers control the frequency
by controlling the drive strength of each
stage
The drive strength has 4 levels determined
by the number of bits set
Increasing the number of bits set increases
the drive strength and increases the oscillation
frequency
0 bits set is the default drive strength
1 bit set doubles the drive strength
2 bits set triples drive strength
3 bits set quadruples dr */
__IOM uint32_t FREQB; /*!< (@ 0x00000008) For a detailed description see freqa register */
__IOM uint32_t DORMANT; /*!< (@ 0x0000000C) Ring Oscillator pause control
This is used to save power by pausing the
ROSC
On power-up this field is initialised to
WAKE
An invalid write will also select WAKE
Warning: setup the irq before selecting
dormant mode */
__IOM uint32_t DIV; /*!< (@ 0x00000010) Controls the output divider */
__IOM uint32_t PHASE; /*!< (@ 0x00000014) Controls the phase shifted output */
__IOM uint32_t STATUS; /*!< (@ 0x00000018) Ring Oscillator Status */
__IOM uint32_t RANDOMBIT; /*!< (@ 0x0000001C) This just reads the state of the oscillator output
so randomness is compromised if the ring
oscillator is stopped or run at a harmonic
of the bus frequency */
__IOM uint32_t COUNT; /*!< (@ 0x00000020) A down counter running at the ROSC frequency
which counts to zero and stops.
To start the counter write a non-zero value.
Can be used for short software pauses when
setting up time sensitive hardware. */
} ROSC_Type; /*!< Size = 36 (0x24) */
/* =========================================================================================================================== */
/* ================ VREG_AND_CHIP_RESET ================ */
/* =========================================================================================================================== */
/**
* @brief control and status for on-chip voltage regulator and chip level reset subsystem (VREG_AND_CHIP_RESET)
*/
typedef struct { /*!< (@ 0x40064000) VREG_AND_CHIP_RESET Structure */
__IOM uint32_t VREG; /*!< (@ 0x00000000) Voltage regulator control and status */
__IOM uint32_t BOD; /*!< (@ 0x00000004) brown-out detection control */
__IOM uint32_t CHIP_RESET; /*!< (@ 0x00000008) Chip reset control and status */
} VREG_AND_CHIP_RESET_Type; /*!< Size = 12 (0xc) */
/* =========================================================================================================================== */
/* ================ TBMAN ================ */
/* =========================================================================================================================== */
/**
* @brief Testbench manager. Allows the programmer to know what platform their software is running on. (TBMAN)
*/
typedef struct { /*!< (@ 0x4006C000) TBMAN Structure */
__IOM uint32_t PLATFORM; /*!< (@ 0x00000000) Indicates the type of platform in use */
} TBMAN_Type; /*!< Size = 4 (0x4) */
/* =========================================================================================================================== */
/* ================ DMA ================ */
/* =========================================================================================================================== */
/**
* @brief DMA with separate read and write masters (DMA)
*/
typedef struct { /*!< (@ 0x50000000) DMA Structure */
__IOM uint32_t CH0_READ_ADDR; /*!< (@ 0x00000000) DMA Channel 0 Read Address pointer
This register updates automatically each
time a read completes. The current value
is the next address to be read by this channel. */
__IOM uint32_t CH0_WRITE_ADDR; /*!< (@ 0x00000004) DMA Channel 0 Write Address pointer
This register updates automatically each
time a write completes. The current value
is the next address to be written by this
channel. */
__IOM uint32_t CH0_TRANS_COUNT; /*!< (@ 0x00000008) DMA Channel 0 Transfer Count
Program the number of bus transfers a channel
will perform before halting. Note that,
if transfers are larger than one byte in
size, this is not equal to the number of
bytes transferred (see CTRL_DATA_SIZE).
When the channel is active, reading this
register shows the number of transfers remaining,
updating automatically each time a write
transfer completes.
Writing this register sets the RELOAD value
for the transf */
__IOM uint32_t CH0_CTRL_TRIG; /*!< (@ 0x0000000C) DMA Channel 0 Control and Status */
__IOM uint32_t CH0_AL1_CTRL; /*!< (@ 0x00000010) Alias for channel 0 CTRL register */
__IOM uint32_t CH0_AL1_READ_ADDR; /*!< (@ 0x00000014) Alias for channel 0 READ_ADDR register */
__IOM uint32_t CH0_AL1_WRITE_ADDR; /*!< (@ 0x00000018) Alias for channel 0 WRITE_ADDR register */
__IOM uint32_t CH0_AL1_TRANS_COUNT_TRIG; /*!< (@ 0x0000001C) Alias for channel 0 TRANS_COUNT register
This is a trigger register (0xc). Writing
a nonzero value will
reload the channel counter and start the
channel. */
__IOM uint32_t CH0_AL2_CTRL; /*!< (@ 0x00000020) Alias for channel 0 CTRL register */
__IOM uint32_t CH0_AL2_TRANS_COUNT; /*!< (@ 0x00000024) Alias for channel 0 TRANS_COUNT register */
__IOM uint32_t CH0_AL2_READ_ADDR; /*!< (@ 0x00000028) Alias for channel 0 READ_ADDR register */
__IOM uint32_t CH0_AL2_WRITE_ADDR_TRIG; /*!< (@ 0x0000002C) Alias for channel 0 WRITE_ADDR register
This is a trigger register (0xc). Writing
a nonzero value will
reload the channel counter and start the
channel. */
__IOM uint32_t CH0_AL3_CTRL; /*!< (@ 0x00000030) Alias for channel 0 CTRL register */
__IOM uint32_t CH0_AL3_WRITE_ADDR; /*!< (@ 0x00000034) Alias for channel 0 WRITE_ADDR register */
__IOM uint32_t CH0_AL3_TRANS_COUNT; /*!< (@ 0x00000038) Alias for channel 0 TRANS_COUNT register */
__IOM uint32_t CH0_AL3_READ_ADDR_TRIG; /*!< (@ 0x0000003C) Alias for channel 0 READ_ADDR register
This is a trigger register (0xc). Writing
a nonzero value will
reload the channel counter and start the
channel. */
__IOM uint32_t CH1_READ_ADDR; /*!< (@ 0x00000040) DMA Channel 1 Read Address pointer
This register updates automatically each
time a read completes. The current value
is the next address to be read by this channel. */
__IOM uint32_t CH1_WRITE_ADDR; /*!< (@ 0x00000044) DMA Channel 1 Write Address pointer
This register updates automatically each
time a write completes. The current value
is the next address to be written by this
channel. */
__IOM uint32_t CH1_TRANS_COUNT; /*!< (@ 0x00000048) DMA Channel 1 Transfer Count
Program the number of bus transfers a channel
will perform before halting. Note that,
if transfers are larger than one byte in
size, this is not equal to the number of
bytes transferred (see CTRL_DATA_SIZE).
When the channel is active, reading this
register shows the number of transfers remaining,
updating automatically each time a write
transfer completes.
Writing this register sets the RELOAD value
for the transf */
__IOM uint32_t CH1_CTRL_TRIG; /*!< (@ 0x0000004C) DMA Channel 1 Control and Status */
__IOM uint32_t CH1_AL1_CTRL; /*!< (@ 0x00000050) Alias for channel 1 CTRL register */
__IOM uint32_t CH1_AL1_READ_ADDR; /*!< (@ 0x00000054) Alias for channel 1 READ_ADDR register */
__IOM uint32_t CH1_AL1_WRITE_ADDR; /*!< (@ 0x00000058) Alias for channel 1 WRITE_ADDR register */
__IOM uint32_t CH1_AL1_TRANS_COUNT_TRIG; /*!< (@ 0x0000005C) Alias for channel 1 TRANS_COUNT register
This is a trigger register (0xc). Writing
a nonzero value will
reload the channel counter and start the
channel. */
__IOM uint32_t CH1_AL2_CTRL; /*!< (@ 0x00000060) Alias for channel 1 CTRL register */
__IOM uint32_t CH1_AL2_TRANS_COUNT; /*!< (@ 0x00000064) Alias for channel 1 TRANS_COUNT register */
__IOM uint32_t CH1_AL2_READ_ADDR; /*!< (@ 0x00000068) Alias for channel 1 READ_ADDR register */
__IOM uint32_t CH1_AL2_WRITE_ADDR_TRIG; /*!< (@ 0x0000006C) Alias for channel 1 WRITE_ADDR register
This is a trigger register (0xc). Writing
a nonzero value will
reload the channel counter and start the
channel. */
__IOM uint32_t CH1_AL3_CTRL; /*!< (@ 0x00000070) Alias for channel 1 CTRL register */
__IOM uint32_t CH1_AL3_WRITE_ADDR; /*!< (@ 0x00000074) Alias for channel 1 WRITE_ADDR register */
__IOM uint32_t CH1_AL3_TRANS_COUNT; /*!< (@ 0x00000078) Alias for channel 1 TRANS_COUNT register */
__IOM uint32_t CH1_AL3_READ_ADDR_TRIG; /*!< (@ 0x0000007C) Alias for channel 1 READ_ADDR register
This is a trigger register (0xc). Writing
a nonzero value will
reload the channel counter and start the
channel. */
__IOM uint32_t CH2_READ_ADDR; /*!< (@ 0x00000080) DMA Channel 2 Read Address pointer
This register updates automatically each
time a read completes. The current value
is the next address to be read by this channel. */
__IOM uint32_t CH2_WRITE_ADDR; /*!< (@ 0x00000084) DMA Channel 2 Write Address pointer
This register updates automatically each
time a write completes. The current value
is the next address to be written by this
channel. */
__IOM uint32_t CH2_TRANS_COUNT; /*!< (@ 0x00000088) DMA Channel 2 Transfer Count
Program the number of bus transfers a channel
will perform before halting. Note that,
if transfers are larger than one byte in
size, this is not equal to the number of
bytes transferred (see CTRL_DATA_SIZE).
When the channel is active, reading this
register shows the number of transfers remaining,
updating automatically each time a write
transfer completes.
Writing this register sets the RELOAD value
for the transf */
__IOM uint32_t CH2_CTRL_TRIG; /*!< (@ 0x0000008C) DMA Channel 2 Control and Status */
__IOM uint32_t CH2_AL1_CTRL; /*!< (@ 0x00000090) Alias for channel 2 CTRL register */
__IOM uint32_t CH2_AL1_READ_ADDR; /*!< (@ 0x00000094) Alias for channel 2 READ_ADDR register */
__IOM uint32_t CH2_AL1_WRITE_ADDR; /*!< (@ 0x00000098) Alias for channel 2 WRITE_ADDR register */
__IOM uint32_t CH2_AL1_TRANS_COUNT_TRIG; /*!< (@ 0x0000009C) Alias for channel 2 TRANS_COUNT register
This is a trigger register (0xc). Writing
a nonzero value will
reload the channel counter and start the
channel. */
__IOM uint32_t CH2_AL2_CTRL; /*!< (@ 0x000000A0) Alias for channel 2 CTRL register */
__IOM uint32_t CH2_AL2_TRANS_COUNT; /*!< (@ 0x000000A4) Alias for channel 2 TRANS_COUNT register */
__IOM uint32_t CH2_AL2_READ_ADDR; /*!< (@ 0x000000A8) Alias for channel 2 READ_ADDR register */
__IOM uint32_t CH2_AL2_WRITE_ADDR_TRIG; /*!< (@ 0x000000AC) Alias for channel 2 WRITE_ADDR register
This is a trigger register (0xc). Writing
a nonzero value will
reload the channel counter and start the
channel. */
__IOM uint32_t CH2_AL3_CTRL; /*!< (@ 0x000000B0) Alias for channel 2 CTRL register */
__IOM uint32_t CH2_AL3_WRITE_ADDR; /*!< (@ 0x000000B4) Alias for channel 2 WRITE_ADDR register */
__IOM uint32_t CH2_AL3_TRANS_COUNT; /*!< (@ 0x000000B8) Alias for channel 2 TRANS_COUNT register */
__IOM uint32_t CH2_AL3_READ_ADDR_TRIG; /*!< (@ 0x000000BC) Alias for channel 2 READ_ADDR register
This is a trigger register (0xc). Writing
a nonzero value will
reload the channel counter and start the
channel. */
__IOM uint32_t CH3_READ_ADDR; /*!< (@ 0x000000C0) DMA Channel 3 Read Address pointer
This register updates automatically each
time a read completes. The current value
is the next address to be read by this channel. */
__IOM uint32_t CH3_WRITE_ADDR; /*!< (@ 0x000000C4) DMA Channel 3 Write Address pointer
This register updates automatically each
time a write completes. The current value
is the next address to be written by this
channel. */
__IOM uint32_t CH3_TRANS_COUNT; /*!< (@ 0x000000C8) DMA Channel 3 Transfer Count
Program the number of bus transfers a channel
will perform before halting. Note that,
if transfers are larger than one byte in
size, this is not equal to the number of
bytes transferred (see CTRL_DATA_SIZE).
When the channel is active, reading this
register shows the number of transfers remaining,
updating automatically each time a write
transfer completes.
Writing this register sets the RELOAD value
for the transf */
__IOM uint32_t CH3_CTRL_TRIG; /*!< (@ 0x000000CC) DMA Channel 3 Control and Status */
__IOM uint32_t CH3_AL1_CTRL; /*!< (@ 0x000000D0) Alias for channel 3 CTRL register */
__IOM uint32_t CH3_AL1_READ_ADDR; /*!< (@ 0x000000D4) Alias for channel 3 READ_ADDR register */
__IOM uint32_t CH3_AL1_WRITE_ADDR; /*!< (@ 0x000000D8) Alias for channel 3 WRITE_ADDR register */
__IOM uint32_t CH3_AL1_TRANS_COUNT_TRIG; /*!< (@ 0x000000DC) Alias for channel 3 TRANS_COUNT register
This is a trigger register (0xc). Writing
a nonzero value will
reload the channel counter and start the
channel. */
__IOM uint32_t CH3_AL2_CTRL; /*!< (@ 0x000000E0) Alias for channel 3 CTRL register */
__IOM uint32_t CH3_AL2_TRANS_COUNT; /*!< (@ 0x000000E4) Alias for channel 3 TRANS_COUNT register */
__IOM uint32_t CH3_AL2_READ_ADDR; /*!< (@ 0x000000E8) Alias for channel 3 READ_ADDR register */
__IOM uint32_t CH3_AL2_WRITE_ADDR_TRIG; /*!< (@ 0x000000EC) Alias for channel 3 WRITE_ADDR register
This is a trigger register (0xc). Writing
a nonzero value will
reload the channel counter and start the
channel. */
__IOM uint32_t CH3_AL3_CTRL; /*!< (@ 0x000000F0) Alias for channel 3 CTRL register */
__IOM uint32_t CH3_AL3_WRITE_ADDR; /*!< (@ 0x000000F4) Alias for channel 3 WRITE_ADDR register */
__IOM uint32_t CH3_AL3_TRANS_COUNT; /*!< (@ 0x000000F8) Alias for channel 3 TRANS_COUNT register */
__IOM uint32_t CH3_AL3_READ_ADDR_TRIG; /*!< (@ 0x000000FC) Alias for channel 3 READ_ADDR register
This is a trigger register (0xc). Writing
a nonzero value will
reload the channel counter and start the
channel. */
__IOM uint32_t CH4_READ_ADDR; /*!< (@ 0x00000100) DMA Channel 4 Read Address pointer
This register updates automatically each
time a read completes. The current value
is the next address to be read by this channel. */
__IOM uint32_t CH4_WRITE_ADDR; /*!< (@ 0x00000104) DMA Channel 4 Write Address pointer
This register updates automatically each
time a write completes. The current value
is the next address to be written by this
channel. */
__IOM uint32_t CH4_TRANS_COUNT; /*!< (@ 0x00000108) DMA Channel 4 Transfer Count
Program the number of bus transfers a channel
will perform before halting. Note that,
if transfers are larger than one byte in
size, this is not equal to the number of
bytes transferred (see CTRL_DATA_SIZE).
When the channel is active, reading this
register shows the number of transfers remaining,
updating automatically each time a write
transfer completes.
Writing this register sets the RELOAD value
for the transf */
__IOM uint32_t CH4_CTRL_TRIG; /*!< (@ 0x0000010C) DMA Channel 4 Control and Status */
__IOM uint32_t CH4_AL1_CTRL; /*!< (@ 0x00000110) Alias for channel 4 CTRL register */
__IOM uint32_t CH4_AL1_READ_ADDR; /*!< (@ 0x00000114) Alias for channel 4 READ_ADDR register */
__IOM uint32_t CH4_AL1_WRITE_ADDR; /*!< (@ 0x00000118) Alias for channel 4 WRITE_ADDR register */
__IOM uint32_t CH4_AL1_TRANS_COUNT_TRIG; /*!< (@ 0x0000011C) Alias for channel 4 TRANS_COUNT register
This is a trigger register (0xc). Writing
a nonzero value will
reload the channel counter and start the
channel. */
__IOM uint32_t CH4_AL2_CTRL; /*!< (@ 0x00000120) Alias for channel 4 CTRL register */
__IOM uint32_t CH4_AL2_TRANS_COUNT; /*!< (@ 0x00000124) Alias for channel 4 TRANS_COUNT register */
__IOM uint32_t CH4_AL2_READ_ADDR; /*!< (@ 0x00000128) Alias for channel 4 READ_ADDR register */
__IOM uint32_t CH4_AL2_WRITE_ADDR_TRIG; /*!< (@ 0x0000012C) Alias for channel 4 WRITE_ADDR register
This is a trigger register (0xc). Writing
a nonzero value will
reload the channel counter and start the
channel. */
__IOM uint32_t CH4_AL3_CTRL; /*!< (@ 0x00000130) Alias for channel 4 CTRL register */
__IOM uint32_t CH4_AL3_WRITE_ADDR; /*!< (@ 0x00000134) Alias for channel 4 WRITE_ADDR register */
__IOM uint32_t CH4_AL3_TRANS_COUNT; /*!< (@ 0x00000138) Alias for channel 4 TRANS_COUNT register */
__IOM uint32_t CH4_AL3_READ_ADDR_TRIG; /*!< (@ 0x0000013C) Alias for channel 4 READ_ADDR register
This is a trigger register (0xc). Writing
a nonzero value will
reload the channel counter and start the
channel. */
__IOM uint32_t CH5_READ_ADDR; /*!< (@ 0x00000140) DMA Channel 5 Read Address pointer
This register updates automatically each
time a read completes. The current value
is the next address to be read by this channel. */
__IOM uint32_t CH5_WRITE_ADDR; /*!< (@ 0x00000144) DMA Channel 5 Write Address pointer
This register updates automatically each
time a write completes. The current value
is the next address to be written by this
channel. */
__IOM uint32_t CH5_TRANS_COUNT; /*!< (@ 0x00000148) DMA Channel 5 Transfer Count
Program the number of bus transfers a channel
will perform before halting. Note that,
if transfers are larger than one byte in
size, this is not equal to the number of
bytes transferred (see CTRL_DATA_SIZE).
When the channel is active, reading this
register shows the number of transfers remaining,
updating automatically each time a write
transfer completes.
Writing this register sets the RELOAD value
for the transf */
__IOM uint32_t CH5_CTRL_TRIG; /*!< (@ 0x0000014C) DMA Channel 5 Control and Status */
__IOM uint32_t CH5_AL1_CTRL; /*!< (@ 0x00000150) Alias for channel 5 CTRL register */
__IOM uint32_t CH5_AL1_READ_ADDR; /*!< (@ 0x00000154) Alias for channel 5 READ_ADDR register */
__IOM uint32_t CH5_AL1_WRITE_ADDR; /*!< (@ 0x00000158) Alias for channel 5 WRITE_ADDR register */
__IOM uint32_t CH5_AL1_TRANS_COUNT_TRIG; /*!< (@ 0x0000015C) Alias for channel 5 TRANS_COUNT register
This is a trigger register (0xc). Writing
a nonzero value will
reload the channel counter and start the
channel. */
__IOM uint32_t CH5_AL2_CTRL; /*!< (@ 0x00000160) Alias for channel 5 CTRL register */
__IOM uint32_t CH5_AL2_TRANS_COUNT; /*!< (@ 0x00000164) Alias for channel 5 TRANS_COUNT register */
__IOM uint32_t CH5_AL2_READ_ADDR; /*!< (@ 0x00000168) Alias for channel 5 READ_ADDR register */
__IOM uint32_t CH5_AL2_WRITE_ADDR_TRIG; /*!< (@ 0x0000016C) Alias for channel 5 WRITE_ADDR register
This is a trigger register (0xc). Writing
a nonzero value will
reload the channel counter and start the
channel. */
__IOM uint32_t CH5_AL3_CTRL; /*!< (@ 0x00000170) Alias for channel 5 CTRL register */
__IOM uint32_t CH5_AL3_WRITE_ADDR; /*!< (@ 0x00000174) Alias for channel 5 WRITE_ADDR register */
__IOM uint32_t CH5_AL3_TRANS_COUNT; /*!< (@ 0x00000178) Alias for channel 5 TRANS_COUNT register */
__IOM uint32_t CH5_AL3_READ_ADDR_TRIG; /*!< (@ 0x0000017C) Alias for channel 5 READ_ADDR register
This is a trigger register (0xc). Writing
a nonzero value will
reload the channel counter and start the
channel. */
__IOM uint32_t CH6_READ_ADDR; /*!< (@ 0x00000180) DMA Channel 6 Read Address pointer
This register updates automatically each
time a read completes. The current value
is the next address to be read by this channel. */
__IOM uint32_t CH6_WRITE_ADDR; /*!< (@ 0x00000184) DMA Channel 6 Write Address pointer
This register updates automatically each
time a write completes. The current value
is the next address to be written by this
channel. */
__IOM uint32_t CH6_TRANS_COUNT; /*!< (@ 0x00000188) DMA Channel 6 Transfer Count
Program the number of bus transfers a channel
will perform before halting. Note that,
if transfers are larger than one byte in
size, this is not equal to the number of
bytes transferred (see CTRL_DATA_SIZE).
When the channel is active, reading this
register shows the number of transfers remaining,
updating automatically each time a write
transfer completes.
Writing this register sets the RELOAD value
for the transf */
__IOM uint32_t CH6_CTRL_TRIG; /*!< (@ 0x0000018C) DMA Channel 6 Control and Status */
__IOM uint32_t CH6_AL1_CTRL; /*!< (@ 0x00000190) Alias for channel 6 CTRL register */
__IOM uint32_t CH6_AL1_READ_ADDR; /*!< (@ 0x00000194) Alias for channel 6 READ_ADDR register */
__IOM uint32_t CH6_AL1_WRITE_ADDR; /*!< (@ 0x00000198) Alias for channel 6 WRITE_ADDR register */
__IOM uint32_t CH6_AL1_TRANS_COUNT_TRIG; /*!< (@ 0x0000019C) Alias for channel 6 TRANS_COUNT register
This is a trigger register (0xc). Writing
a nonzero value will
reload the channel counter and start the
channel. */
__IOM uint32_t CH6_AL2_CTRL; /*!< (@ 0x000001A0) Alias for channel 6 CTRL register */
__IOM uint32_t CH6_AL2_TRANS_COUNT; /*!< (@ 0x000001A4) Alias for channel 6 TRANS_COUNT register */
__IOM uint32_t CH6_AL2_READ_ADDR; /*!< (@ 0x000001A8) Alias for channel 6 READ_ADDR register */
__IOM uint32_t CH6_AL2_WRITE_ADDR_TRIG; /*!< (@ 0x000001AC) Alias for channel 6 WRITE_ADDR register
This is a trigger register (0xc). Writing
a nonzero value will
reload the channel counter and start the
channel. */
__IOM uint32_t CH6_AL3_CTRL; /*!< (@ 0x000001B0) Alias for channel 6 CTRL register */
__IOM uint32_t CH6_AL3_WRITE_ADDR; /*!< (@ 0x000001B4) Alias for channel 6 WRITE_ADDR register */
__IOM uint32_t CH6_AL3_TRANS_COUNT; /*!< (@ 0x000001B8) Alias for channel 6 TRANS_COUNT register */
__IOM uint32_t CH6_AL3_READ_ADDR_TRIG; /*!< (@ 0x000001BC) Alias for channel 6 READ_ADDR register
This is a trigger register (0xc). Writing
a nonzero value will
reload the channel counter and start the
channel. */
__IOM uint32_t CH7_READ_ADDR; /*!< (@ 0x000001C0) DMA Channel 7 Read Address pointer
This register updates automatically each
time a read completes. The current value
is the next address to be read by this channel. */
__IOM uint32_t CH7_WRITE_ADDR; /*!< (@ 0x000001C4) DMA Channel 7 Write Address pointer
This register updates automatically each
time a write completes. The current value
is the next address to be written by this
channel. */
__IOM uint32_t CH7_TRANS_COUNT; /*!< (@ 0x000001C8) DMA Channel 7 Transfer Count
Program the number of bus transfers a channel
will perform before halting. Note that,
if transfers are larger than one byte in
size, this is not equal to the number of
bytes transferred (see CTRL_DATA_SIZE).
When the channel is active, reading this
register shows the number of transfers remaining,
updating automatically each time a write
transfer completes.
Writing this register sets the RELOAD value
for the transf */
__IOM uint32_t CH7_CTRL_TRIG; /*!< (@ 0x000001CC) DMA Channel 7 Control and Status */
__IOM uint32_t CH7_AL1_CTRL; /*!< (@ 0x000001D0) Alias for channel 7 CTRL register */
__IOM uint32_t CH7_AL1_READ_ADDR; /*!< (@ 0x000001D4) Alias for channel 7 READ_ADDR register */
__IOM uint32_t CH7_AL1_WRITE_ADDR; /*!< (@ 0x000001D8) Alias for channel 7 WRITE_ADDR register */
__IOM uint32_t CH7_AL1_TRANS_COUNT_TRIG; /*!< (@ 0x000001DC) Alias for channel 7 TRANS_COUNT register
This is a trigger register (0xc). Writing
a nonzero value will
reload the channel counter and start the
channel. */
__IOM uint32_t CH7_AL2_CTRL; /*!< (@ 0x000001E0) Alias for channel 7 CTRL register */
__IOM uint32_t CH7_AL2_TRANS_COUNT; /*!< (@ 0x000001E4) Alias for channel 7 TRANS_COUNT register */
__IOM uint32_t CH7_AL2_READ_ADDR; /*!< (@ 0x000001E8) Alias for channel 7 READ_ADDR register */
__IOM uint32_t CH7_AL2_WRITE_ADDR_TRIG; /*!< (@ 0x000001EC) Alias for channel 7 WRITE_ADDR register
This is a trigger register (0xc). Writing
a nonzero value will
reload the channel counter and start the
channel. */
__IOM uint32_t CH7_AL3_CTRL; /*!< (@ 0x000001F0) Alias for channel 7 CTRL register */
__IOM uint32_t CH7_AL3_WRITE_ADDR; /*!< (@ 0x000001F4) Alias for channel 7 WRITE_ADDR register */
__IOM uint32_t CH7_AL3_TRANS_COUNT; /*!< (@ 0x000001F8) Alias for channel 7 TRANS_COUNT register */
__IOM uint32_t CH7_AL3_READ_ADDR_TRIG; /*!< (@ 0x000001FC) Alias for channel 7 READ_ADDR register
This is a trigger register (0xc). Writing
a nonzero value will
reload the channel counter and start the
channel. */
__IOM uint32_t CH8_READ_ADDR; /*!< (@ 0x00000200) DMA Channel 8 Read Address pointer
This register updates automatically each
time a read completes. The current value
is the next address to be read by this channel. */
__IOM uint32_t CH8_WRITE_ADDR; /*!< (@ 0x00000204) DMA Channel 8 Write Address pointer
This register updates automatically each
time a write completes. The current value
is the next address to be written by this
channel. */
__IOM uint32_t CH8_TRANS_COUNT; /*!< (@ 0x00000208) DMA Channel 8 Transfer Count
Program the number of bus transfers a channel
will perform before halting. Note that,
if transfers are larger than one byte in
size, this is not equal to the number of
bytes transferred (see CTRL_DATA_SIZE).
When the channel is active, reading this
register shows the number of transfers remaining,
updating automatically each time a write
transfer completes.
Writing this register sets the RELOAD value
for the transf */
__IOM uint32_t CH8_CTRL_TRIG; /*!< (@ 0x0000020C) DMA Channel 8 Control and Status */
__IOM uint32_t CH8_AL1_CTRL; /*!< (@ 0x00000210) Alias for channel 8 CTRL register */
__IOM uint32_t CH8_AL1_READ_ADDR; /*!< (@ 0x00000214) Alias for channel 8 READ_ADDR register */
__IOM uint32_t CH8_AL1_WRITE_ADDR; /*!< (@ 0x00000218) Alias for channel 8 WRITE_ADDR register */
__IOM uint32_t CH8_AL1_TRANS_COUNT_TRIG; /*!< (@ 0x0000021C) Alias for channel 8 TRANS_COUNT register
This is a trigger register (0xc). Writing
a nonzero value will
reload the channel counter and start the
channel. */
__IOM uint32_t CH8_AL2_CTRL; /*!< (@ 0x00000220) Alias for channel 8 CTRL register */
__IOM uint32_t CH8_AL2_TRANS_COUNT; /*!< (@ 0x00000224) Alias for channel 8 TRANS_COUNT register */
__IOM uint32_t CH8_AL2_READ_ADDR; /*!< (@ 0x00000228) Alias for channel 8 READ_ADDR register */
__IOM uint32_t CH8_AL2_WRITE_ADDR_TRIG; /*!< (@ 0x0000022C) Alias for channel 8 WRITE_ADDR register
This is a trigger register (0xc). Writing
a nonzero value will
reload the channel counter and start the
channel. */
__IOM uint32_t CH8_AL3_CTRL; /*!< (@ 0x00000230) Alias for channel 8 CTRL register */
__IOM uint32_t CH8_AL3_WRITE_ADDR; /*!< (@ 0x00000234) Alias for channel 8 WRITE_ADDR register */
__IOM uint32_t CH8_AL3_TRANS_COUNT; /*!< (@ 0x00000238) Alias for channel 8 TRANS_COUNT register */
__IOM uint32_t CH8_AL3_READ_ADDR_TRIG; /*!< (@ 0x0000023C) Alias for channel 8 READ_ADDR register
This is a trigger register (0xc). Writing
a nonzero value will
reload the channel counter and start the
channel. */
__IOM uint32_t CH9_READ_ADDR; /*!< (@ 0x00000240) DMA Channel 9 Read Address pointer
This register updates automatically each
time a read completes. The current value
is the next address to be read by this channel. */
__IOM uint32_t CH9_WRITE_ADDR; /*!< (@ 0x00000244) DMA Channel 9 Write Address pointer
This register updates automatically each
time a write completes. The current value
is the next address to be written by this
channel. */
__IOM uint32_t CH9_TRANS_COUNT; /*!< (@ 0x00000248) DMA Channel 9 Transfer Count
Program the number of bus transfers a channel
will perform before halting. Note that,
if transfers are larger than one byte in
size, this is not equal to the number of
bytes transferred (see CTRL_DATA_SIZE).
When the channel is active, reading this
register shows the number of transfers remaining,
updating automatically each time a write
transfer completes.
Writing this register sets the RELOAD value
for the transf */
__IOM uint32_t CH9_CTRL_TRIG; /*!< (@ 0x0000024C) DMA Channel 9 Control and Status */
__IOM uint32_t CH9_AL1_CTRL; /*!< (@ 0x00000250) Alias for channel 9 CTRL register */
__IOM uint32_t CH9_AL1_READ_ADDR; /*!< (@ 0x00000254) Alias for channel 9 READ_ADDR register */
__IOM uint32_t CH9_AL1_WRITE_ADDR; /*!< (@ 0x00000258) Alias for channel 9 WRITE_ADDR register */
__IOM uint32_t CH9_AL1_TRANS_COUNT_TRIG; /*!< (@ 0x0000025C) Alias for channel 9 TRANS_COUNT register
This is a trigger register (0xc). Writing
a nonzero value will
reload the channel counter and start the
channel. */
__IOM uint32_t CH9_AL2_CTRL; /*!< (@ 0x00000260) Alias for channel 9 CTRL register */
__IOM uint32_t CH9_AL2_TRANS_COUNT; /*!< (@ 0x00000264) Alias for channel 9 TRANS_COUNT register */
__IOM uint32_t CH9_AL2_READ_ADDR; /*!< (@ 0x00000268) Alias for channel 9 READ_ADDR register */
__IOM uint32_t CH9_AL2_WRITE_ADDR_TRIG; /*!< (@ 0x0000026C) Alias for channel 9 WRITE_ADDR register
This is a trigger register (0xc). Writing
a nonzero value will
reload the channel counter and start the
channel. */
__IOM uint32_t CH9_AL3_CTRL; /*!< (@ 0x00000270) Alias for channel 9 CTRL register */
__IOM uint32_t CH9_AL3_WRITE_ADDR; /*!< (@ 0x00000274) Alias for channel 9 WRITE_ADDR register */
__IOM uint32_t CH9_AL3_TRANS_COUNT; /*!< (@ 0x00000278) Alias for channel 9 TRANS_COUNT register */
__IOM uint32_t CH9_AL3_READ_ADDR_TRIG; /*!< (@ 0x0000027C) Alias for channel 9 READ_ADDR register
This is a trigger register (0xc). Writing
a nonzero value will
reload the channel counter and start the
channel. */
__IOM uint32_t CH10_READ_ADDR; /*!< (@ 0x00000280) DMA Channel 10 Read Address pointer
This register updates automatically each
time a read completes. The current value
is the next address to be read by this channel. */
__IOM uint32_t CH10_WRITE_ADDR; /*!< (@ 0x00000284) DMA Channel 10 Write Address pointer
This register updates automatically each
time a write completes. The current value
is the next address to be written by this
channel. */
__IOM uint32_t CH10_TRANS_COUNT; /*!< (@ 0x00000288) DMA Channel 10 Transfer Count
Program the number of bus transfers a channel
will perform before halting. Note that,
if transfers are larger than one byte in
size, this is not equal to the number of
bytes transferred (see CTRL_DATA_SIZE).
When the channel is active, reading this
register shows the number of transfers remaining,
updating automatically each time a write
transfer completes.
Writing this register sets the RELOAD value
for the trans */
__IOM uint32_t CH10_CTRL_TRIG; /*!< (@ 0x0000028C) DMA Channel 10 Control and Status */
__IOM uint32_t CH10_AL1_CTRL; /*!< (@ 0x00000290) Alias for channel 10 CTRL register */
__IOM uint32_t CH10_AL1_READ_ADDR; /*!< (@ 0x00000294) Alias for channel 10 READ_ADDR register */
__IOM uint32_t CH10_AL1_WRITE_ADDR; /*!< (@ 0x00000298) Alias for channel 10 WRITE_ADDR register */
__IOM uint32_t CH10_AL1_TRANS_COUNT_TRIG; /*!< (@ 0x0000029C) Alias for channel 10 TRANS_COUNT register
This is a trigger register (0xc). Writing
a nonzero value will
reload the channel counter and start the
channel. */
__IOM uint32_t CH10_AL2_CTRL; /*!< (@ 0x000002A0) Alias for channel 10 CTRL register */
__IOM uint32_t CH10_AL2_TRANS_COUNT; /*!< (@ 0x000002A4) Alias for channel 10 TRANS_COUNT register */
__IOM uint32_t CH10_AL2_READ_ADDR; /*!< (@ 0x000002A8) Alias for channel 10 READ_ADDR register */
__IOM uint32_t CH10_AL2_WRITE_ADDR_TRIG; /*!< (@ 0x000002AC) Alias for channel 10 WRITE_ADDR register
This is a trigger register (0xc). Writing
a nonzero value will
reload the channel counter and start the
channel. */
__IOM uint32_t CH10_AL3_CTRL; /*!< (@ 0x000002B0) Alias for channel 10 CTRL register */
__IOM uint32_t CH10_AL3_WRITE_ADDR; /*!< (@ 0x000002B4) Alias for channel 10 WRITE_ADDR register */
__IOM uint32_t CH10_AL3_TRANS_COUNT; /*!< (@ 0x000002B8) Alias for channel 10 TRANS_COUNT register */
__IOM uint32_t CH10_AL3_READ_ADDR_TRIG; /*!< (@ 0x000002BC) Alias for channel 10 READ_ADDR register
This is a trigger register (0xc). Writing
a nonzero value will
reload the channel counter and start the
channel. */
__IOM uint32_t CH11_READ_ADDR; /*!< (@ 0x000002C0) DMA Channel 11 Read Address pointer
This register updates automatically each
time a read completes. The current value
is the next address to be read by this channel. */
__IOM uint32_t CH11_WRITE_ADDR; /*!< (@ 0x000002C4) DMA Channel 11 Write Address pointer
This register updates automatically each
time a write completes. The current value
is the next address to be written by this
channel. */
__IOM uint32_t CH11_TRANS_COUNT; /*!< (@ 0x000002C8) DMA Channel 11 Transfer Count
Program the number of bus transfers a channel
will perform before halting. Note that,
if transfers are larger than one byte in
size, this is not equal to the number of
bytes transferred (see CTRL_DATA_SIZE).
When the channel is active, reading this
register shows the number of transfers remaining,
updating automatically each time a write
transfer completes.
Writing this register sets the RELOAD value
for the trans */
__IOM uint32_t CH11_CTRL_TRIG; /*!< (@ 0x000002CC) DMA Channel 11 Control and Status */
__IOM uint32_t CH11_AL1_CTRL; /*!< (@ 0x000002D0) Alias for channel 11 CTRL register */
__IOM uint32_t CH11_AL1_READ_ADDR; /*!< (@ 0x000002D4) Alias for channel 11 READ_ADDR register */
__IOM uint32_t CH11_AL1_WRITE_ADDR; /*!< (@ 0x000002D8) Alias for channel 11 WRITE_ADDR register */
__IOM uint32_t CH11_AL1_TRANS_COUNT_TRIG; /*!< (@ 0x000002DC) Alias for channel 11 TRANS_COUNT register
This is a trigger register (0xc). Writing
a nonzero value will
reload the channel counter and start the
channel. */
__IOM uint32_t CH11_AL2_CTRL; /*!< (@ 0x000002E0) Alias for channel 11 CTRL register */
__IOM uint32_t CH11_AL2_TRANS_COUNT; /*!< (@ 0x000002E4) Alias for channel 11 TRANS_COUNT register */
__IOM uint32_t CH11_AL2_READ_ADDR; /*!< (@ 0x000002E8) Alias for channel 11 READ_ADDR register */
__IOM uint32_t CH11_AL2_WRITE_ADDR_TRIG; /*!< (@ 0x000002EC) Alias for channel 11 WRITE_ADDR register
This is a trigger register (0xc). Writing
a nonzero value will
reload the channel counter and start the
channel. */
__IOM uint32_t CH11_AL3_CTRL; /*!< (@ 0x000002F0) Alias for channel 11 CTRL register */
__IOM uint32_t CH11_AL3_WRITE_ADDR; /*!< (@ 0x000002F4) Alias for channel 11 WRITE_ADDR register */
__IOM uint32_t CH11_AL3_TRANS_COUNT; /*!< (@ 0x000002F8) Alias for channel 11 TRANS_COUNT register */
__IOM uint32_t CH11_AL3_READ_ADDR_TRIG; /*!< (@ 0x000002FC) Alias for channel 11 READ_ADDR register
This is a trigger register (0xc). Writing
a nonzero value will
reload the channel counter and start the
channel. */
__IM uint32_t RESERVED[64];
__IOM uint32_t INTR; /*!< (@ 0x00000400) Interrupt Status (raw) */
__IOM uint32_t INTE0; /*!< (@ 0x00000404) Interrupt Enables for IRQ 0 */
__IOM uint32_t INTF0; /*!< (@ 0x00000408) Force Interrupts */
__IOM uint32_t INTS0; /*!< (@ 0x0000040C) Interrupt Status for IRQ 0 */
__IM uint32_t RESERVED1;
__IOM uint32_t INTE1; /*!< (@ 0x00000414) Interrupt Enables for IRQ 1 */
__IOM uint32_t INTF1; /*!< (@ 0x00000418) Force Interrupts for IRQ 1 */
__IOM uint32_t INTS1; /*!< (@ 0x0000041C) Interrupt Status (masked) for IRQ 1 */
__IOM uint32_t TIMER0; /*!< (@ 0x00000420) Pacing (X/Y) Fractional Timer
The pacing timer produces TREQ assertions
at a rate set by ((X/Y) * sys_clk). This
equation is evaluated every sys_clk cycles
and therefore can only generate TREQs at
a rate of 1 per sys_clk (i.e. permanent
TREQ) or less. */
__IOM uint32_t TIMER1; /*!< (@ 0x00000424) Pacing (X/Y) Fractional Timer
The pacing timer produces TREQ assertions
at a rate set by ((X/Y) * sys_clk). This
equation is evaluated every sys_clk cycles
and therefore can only generate TREQs at
a rate of 1 per sys_clk (i.e. permanent
TREQ) or less. */
__IOM uint32_t TIMER2; /*!< (@ 0x00000428) Pacing (X/Y) Fractional Timer
The pacing timer produces TREQ assertions
at a rate set by ((X/Y) * sys_clk). This
equation is evaluated every sys_clk cycles
and therefore can only generate TREQs at
a rate of 1 per sys_clk (i.e. permanent
TREQ) or less. */
__IOM uint32_t TIMER3; /*!< (@ 0x0000042C) Pacing (X/Y) Fractional Timer
The pacing timer produces TREQ assertions
at a rate set by ((X/Y) * sys_clk). This
equation is evaluated every sys_clk cycles
and therefore can only generate TREQs at
a rate of 1 per sys_clk (i.e. permanent
TREQ) or less. */
__IOM uint32_t MULTI_CHAN_TRIGGER; /*!< (@ 0x00000430) Trigger one or more channels simultaneously */
__IOM uint32_t SNIFF_CTRL; /*!< (@ 0x00000434) Sniffer Control */
__IOM uint32_t SNIFF_DATA; /*!< (@ 0x00000438) Data accumulator for sniff hardware
Write an initial seed value here before
starting a DMA transfer on the channel indicated
by SNIFF_CTRL_DMACH. The hardware will update
this register each time it observes a read
from the indicated channel. Once the channel
completes, the final result can be read
from this register. */
__IM uint32_t RESERVED2;
__IOM uint32_t FIFO_LEVELS; /*!< (@ 0x00000440) Debug RAF, WAF, TDF levels */
__IOM uint32_t CHAN_ABORT; /*!< (@ 0x00000444) Abort an in-progress transfer sequence on one
or more channels */
__IOM uint32_t N_CHANNELS; /*!< (@ 0x00000448) The number of channels this DMA instance is equipped
with. This DMA supports up to 16 hardware
channels, but can be configured with as
few as one, to minimise silicon area. */
__IM uint32_t RESERVED3[237];
__IOM uint32_t CH0_DBG_CTDREQ; /*!< (@ 0x00000800) Read: get channel DREQ counter (i.e. how many
accesses the DMA expects it can perform
on the peripheral without overflow/underflow.
Write any value: clears the counter, and
cause channel to re-initiate DREQ handshake. */
__IM uint32_t CH0_DBG_TCR; /*!< (@ 0x00000804) Read to get channel TRANS_COUNT reload value,
i.e. the length of the next transfer */
__IM uint32_t RESERVED4[14];
__IOM uint32_t CH1_DBG_CTDREQ; /*!< (@ 0x00000840) Read: get channel DREQ counter (i.e. how many
accesses the DMA expects it can perform
on the peripheral without overflow/underflow.
Write any value: clears the counter, and
cause channel to re-initiate DREQ handshake. */
__IM uint32_t CH1_DBG_TCR; /*!< (@ 0x00000844) Read to get channel TRANS_COUNT reload value,
i.e. the length of the next transfer */
__IM uint32_t RESERVED5[14];
__IOM uint32_t CH2_DBG_CTDREQ; /*!< (@ 0x00000880) Read: get channel DREQ counter (i.e. how many
accesses the DMA expects it can perform
on the peripheral without overflow/underflow.
Write any value: clears the counter, and
cause channel to re-initiate DREQ handshake. */
__IM uint32_t CH2_DBG_TCR; /*!< (@ 0x00000884) Read to get channel TRANS_COUNT reload value,
i.e. the length of the next transfer */
__IM uint32_t RESERVED6[14];
__IOM uint32_t CH3_DBG_CTDREQ; /*!< (@ 0x000008C0) Read: get channel DREQ counter (i.e. how many
accesses the DMA expects it can perform
on the peripheral without overflow/underflow.
Write any value: clears the counter, and
cause channel to re-initiate DREQ handshake. */
__IM uint32_t CH3_DBG_TCR; /*!< (@ 0x000008C4) Read to get channel TRANS_COUNT reload value,
i.e. the length of the next transfer */
__IM uint32_t RESERVED7[14];
__IOM uint32_t CH4_DBG_CTDREQ; /*!< (@ 0x00000900) Read: get channel DREQ counter (i.e. how many
accesses the DMA expects it can perform
on the peripheral without overflow/underflow.
Write any value: clears the counter, and
cause channel to re-initiate DREQ handshake. */
__IM uint32_t CH4_DBG_TCR; /*!< (@ 0x00000904) Read to get channel TRANS_COUNT reload value,
i.e. the length of the next transfer */
__IM uint32_t RESERVED8[14];
__IOM uint32_t CH5_DBG_CTDREQ; /*!< (@ 0x00000940) Read: get channel DREQ counter (i.e. how many
accesses the DMA expects it can perform
on the peripheral without overflow/underflow.
Write any value: clears the counter, and
cause channel to re-initiate DREQ handshake. */
__IM uint32_t CH5_DBG_TCR; /*!< (@ 0x00000944) Read to get channel TRANS_COUNT reload value,
i.e. the length of the next transfer */
__IM uint32_t RESERVED9[14];
__IOM uint32_t CH6_DBG_CTDREQ; /*!< (@ 0x00000980) Read: get channel DREQ counter (i.e. how many
accesses the DMA expects it can perform
on the peripheral without overflow/underflow.
Write any value: clears the counter, and
cause channel to re-initiate DREQ handshake. */
__IM uint32_t CH6_DBG_TCR; /*!< (@ 0x00000984) Read to get channel TRANS_COUNT reload value,
i.e. the length of the next transfer */
__IM uint32_t RESERVED10[14];
__IOM uint32_t CH7_DBG_CTDREQ; /*!< (@ 0x000009C0) Read: get channel DREQ counter (i.e. how many
accesses the DMA expects it can perform
on the peripheral without overflow/underflow.
Write any value: clears the counter, and
cause channel to re-initiate DREQ handshake. */
__IM uint32_t CH7_DBG_TCR; /*!< (@ 0x000009C4) Read to get channel TRANS_COUNT reload value,
i.e. the length of the next transfer */
__IM uint32_t RESERVED11[14];
__IOM uint32_t CH8_DBG_CTDREQ; /*!< (@ 0x00000A00) Read: get channel DREQ counter (i.e. how many
accesses the DMA expects it can perform
on the peripheral without overflow/underflow.
Write any value: clears the counter, and
cause channel to re-initiate DREQ handshake. */
__IM uint32_t CH8_DBG_TCR; /*!< (@ 0x00000A04) Read to get channel TRANS_COUNT reload value,
i.e. the length of the next transfer */
__IM uint32_t RESERVED12[14];
__IOM uint32_t CH9_DBG_CTDREQ; /*!< (@ 0x00000A40) Read: get channel DREQ counter (i.e. how many
accesses the DMA expects it can perform
on the peripheral without overflow/underflow.
Write any value: clears the counter, and
cause channel to re-initiate DREQ handshake. */
__IM uint32_t CH9_DBG_TCR; /*!< (@ 0x00000A44) Read to get channel TRANS_COUNT reload value,
i.e. the length of the next transfer */
__IM uint32_t RESERVED13[14];
__IOM uint32_t CH10_DBG_CTDREQ; /*!< (@ 0x00000A80) Read: get channel DREQ counter (i.e. how many
accesses the DMA expects it can perform
on the peripheral without overflow/underflow.
Write any value: clears the counter, and
cause channel to re-initiate DREQ handshake. */
__IM uint32_t CH10_DBG_TCR; /*!< (@ 0x00000A84) Read to get channel TRANS_COUNT reload value,
i.e. the length of the next transfer */
__IM uint32_t RESERVED14[14];
__IOM uint32_t CH11_DBG_CTDREQ; /*!< (@ 0x00000AC0) Read: get channel DREQ counter (i.e. how many
accesses the DMA expects it can perform
on the peripheral without overflow/underflow.
Write any value: clears the counter, and
cause channel to re-initiate DREQ handshake. */
__IM uint32_t CH11_DBG_TCR; /*!< (@ 0x00000AC4) Read to get channel TRANS_COUNT reload value,
i.e. the length of the next transfer */
} DMA_Type; /*!< Size = 2760 (0xac8) */
/* =========================================================================================================================== */
/* ================ USBCTRL_DPRAM ================ */
/* =========================================================================================================================== */
/**
* @brief DPRAM layout for USB device. (USBCTRL_DPRAM)
*/
typedef struct { /*!< (@ 0x50100000) USBCTRL_DPRAM Structure */
__IOM uint32_t SETUP_PACKET_LOW; /*!< (@ 0x00000000) Bytes 0-3 of the SETUP packet from the host. */
__IOM uint32_t SETUP_PACKET_HIGH; /*!< (@ 0x00000004) Bytes 4-7 of the setup packet from the host. */
__IOM uint32_t EP1_IN_CONTROL; /*!< (@ 0x00000008) EP1_IN_CONTROL */
__IOM uint32_t EP1_OUT_CONTROL; /*!< (@ 0x0000000C) EP1_OUT_CONTROL */
__IOM uint32_t EP2_IN_CONTROL; /*!< (@ 0x00000010) EP2_IN_CONTROL */
__IOM uint32_t EP2_OUT_CONTROL; /*!< (@ 0x00000014) EP2_OUT_CONTROL */
__IOM uint32_t EP3_IN_CONTROL; /*!< (@ 0x00000018) EP3_IN_CONTROL */
__IOM uint32_t EP3_OUT_CONTROL; /*!< (@ 0x0000001C) EP3_OUT_CONTROL */
__IOM uint32_t EP4_IN_CONTROL; /*!< (@ 0x00000020) EP4_IN_CONTROL */
__IOM uint32_t EP4_OUT_CONTROL; /*!< (@ 0x00000024) EP4_OUT_CONTROL */
__IOM uint32_t EP5_IN_CONTROL; /*!< (@ 0x00000028) EP5_IN_CONTROL */
__IOM uint32_t EP5_OUT_CONTROL; /*!< (@ 0x0000002C) EP5_OUT_CONTROL */
__IOM uint32_t EP6_IN_CONTROL; /*!< (@ 0x00000030) EP6_IN_CONTROL */
__IOM uint32_t EP6_OUT_CONTROL; /*!< (@ 0x00000034) EP6_OUT_CONTROL */
__IOM uint32_t EP7_IN_CONTROL; /*!< (@ 0x00000038) EP7_IN_CONTROL */
__IOM uint32_t EP7_OUT_CONTROL; /*!< (@ 0x0000003C) EP7_OUT_CONTROL */
__IOM uint32_t EP8_IN_CONTROL; /*!< (@ 0x00000040) EP8_IN_CONTROL */
__IOM uint32_t EP8_OUT_CONTROL; /*!< (@ 0x00000044) EP8_OUT_CONTROL */
__IOM uint32_t EP9_IN_CONTROL; /*!< (@ 0x00000048) EP9_IN_CONTROL */
__IOM uint32_t EP9_OUT_CONTROL; /*!< (@ 0x0000004C) EP9_OUT_CONTROL */
__IOM uint32_t EP10_IN_CONTROL; /*!< (@ 0x00000050) EP10_IN_CONTROL */
__IOM uint32_t EP10_OUT_CONTROL; /*!< (@ 0x00000054) EP10_OUT_CONTROL */
__IOM uint32_t EP11_IN_CONTROL; /*!< (@ 0x00000058) EP11_IN_CONTROL */
__IOM uint32_t EP11_OUT_CONTROL; /*!< (@ 0x0000005C) EP11_OUT_CONTROL */
__IOM uint32_t EP12_IN_CONTROL; /*!< (@ 0x00000060) EP12_IN_CONTROL */
__IOM uint32_t EP12_OUT_CONTROL; /*!< (@ 0x00000064) EP12_OUT_CONTROL */
__IOM uint32_t EP13_IN_CONTROL; /*!< (@ 0x00000068) EP13_IN_CONTROL */
__IOM uint32_t EP13_OUT_CONTROL; /*!< (@ 0x0000006C) EP13_OUT_CONTROL */
__IOM uint32_t EP14_IN_CONTROL; /*!< (@ 0x00000070) EP14_IN_CONTROL */
__IOM uint32_t EP14_OUT_CONTROL; /*!< (@ 0x00000074) EP14_OUT_CONTROL */
__IOM uint32_t EP15_IN_CONTROL; /*!< (@ 0x00000078) EP15_IN_CONTROL */
__IOM uint32_t EP15_OUT_CONTROL; /*!< (@ 0x0000007C) EP15_OUT_CONTROL */
__IOM uint32_t EP0_IN_BUFFER_CONTROL; /*!< (@ 0x00000080) Buffer control for both buffers of an endpoint.
Fields ending in a _1 are for buffer 1.
Fields ending in a _0 are for buffer 0.
Buffer 1 controls are only valid if the
endpoint is in double buffered mode. */
__IOM uint32_t EP0_OUT_BUFFER_CONTROL; /*!< (@ 0x00000084) Buffer control for both buffers of an endpoint.
Fields ending in a _1 are for buffer 1.
Fields ending in a _0 are for buffer 0.
Buffer 1 controls are only valid if the
endpoint is in double buffered mode. */
__IOM uint32_t EP1_IN_BUFFER_CONTROL; /*!< (@ 0x00000088) Buffer control for both buffers of an endpoint.
Fields ending in a _1 are for buffer 1.
Fields ending in a _0 are for buffer 0.
Buffer 1 controls are only valid if the
endpoint is in double buffered mode. */
__IOM uint32_t EP1_OUT_BUFFER_CONTROL; /*!< (@ 0x0000008C) Buffer control for both buffers of an endpoint.
Fields ending in a _1 are for buffer 1.
Fields ending in a _0 are for buffer 0.
Buffer 1 controls are only valid if the
endpoint is in double buffered mode. */
__IOM uint32_t EP2_IN_BUFFER_CONTROL; /*!< (@ 0x00000090) Buffer control for both buffers of an endpoint.
Fields ending in a _1 are for buffer 1.
Fields ending in a _0 are for buffer 0.
Buffer 1 controls are only valid if the
endpoint is in double buffered mode. */
__IOM uint32_t EP2_OUT_BUFFER_CONTROL; /*!< (@ 0x00000094) Buffer control for both buffers of an endpoint.
Fields ending in a _1 are for buffer 1.
Fields ending in a _0 are for buffer 0.
Buffer 1 controls are only valid if the
endpoint is in double buffered mode. */
__IOM uint32_t EP3_IN_BUFFER_CONTROL; /*!< (@ 0x00000098) Buffer control for both buffers of an endpoint.
Fields ending in a _1 are for buffer 1.
Fields ending in a _0 are for buffer 0.
Buffer 1 controls are only valid if the
endpoint is in double buffered mode. */
__IOM uint32_t EP3_OUT_BUFFER_CONTROL; /*!< (@ 0x0000009C) Buffer control for both buffers of an endpoint.
Fields ending in a _1 are for buffer 1.
Fields ending in a _0 are for buffer 0.
Buffer 1 controls are only valid if the
endpoint is in double buffered mode. */
__IOM uint32_t EP4_IN_BUFFER_CONTROL; /*!< (@ 0x000000A0) Buffer control for both buffers of an endpoint.
Fields ending in a _1 are for buffer 1.
Fields ending in a _0 are for buffer 0.
Buffer 1 controls are only valid if the
endpoint is in double buffered mode. */
__IOM uint32_t EP4_OUT_BUFFER_CONTROL; /*!< (@ 0x000000A4) Buffer control for both buffers of an endpoint.
Fields ending in a _1 are for buffer 1.
Fields ending in a _0 are for buffer 0.
Buffer 1 controls are only valid if the
endpoint is in double buffered mode. */
__IOM uint32_t EP5_IN_BUFFER_CONTROL; /*!< (@ 0x000000A8) Buffer control for both buffers of an endpoint.
Fields ending in a _1 are for buffer 1.
Fields ending in a _0 are for buffer 0.
Buffer 1 controls are only valid if the
endpoint is in double buffered mode. */
__IOM uint32_t EP5_OUT_BUFFER_CONTROL; /*!< (@ 0x000000AC) Buffer control for both buffers of an endpoint.
Fields ending in a _1 are for buffer 1.
Fields ending in a _0 are for buffer 0.
Buffer 1 controls are only valid if the
endpoint is in double buffered mode. */
__IOM uint32_t EP6_IN_BUFFER_CONTROL; /*!< (@ 0x000000B0) Buffer control for both buffers of an endpoint.
Fields ending in a _1 are for buffer 1.
Fields ending in a _0 are for buffer 0.
Buffer 1 controls are only valid if the
endpoint is in double buffered mode. */
__IOM uint32_t EP6_OUT_BUFFER_CONTROL; /*!< (@ 0x000000B4) Buffer control for both buffers of an endpoint.
Fields ending in a _1 are for buffer 1.
Fields ending in a _0 are for buffer 0.
Buffer 1 controls are only valid if the
endpoint is in double buffered mode. */
__IOM uint32_t EP7_IN_BUFFER_CONTROL; /*!< (@ 0x000000B8) Buffer control for both buffers of an endpoint.
Fields ending in a _1 are for buffer 1.
Fields ending in a _0 are for buffer 0.
Buffer 1 controls are only valid if the
endpoint is in double buffered mode. */
__IOM uint32_t EP7_OUT_BUFFER_CONTROL; /*!< (@ 0x000000BC) Buffer control for both buffers of an endpoint.
Fields ending in a _1 are for buffer 1.
Fields ending in a _0 are for buffer 0.
Buffer 1 controls are only valid if the
endpoint is in double buffered mode. */
__IOM uint32_t EP8_IN_BUFFER_CONTROL; /*!< (@ 0x000000C0) Buffer control for both buffers of an endpoint.
Fields ending in a _1 are for buffer 1.
Fields ending in a _0 are for buffer 0.
Buffer 1 controls are only valid if the
endpoint is in double buffered mode. */
__IOM uint32_t EP8_OUT_BUFFER_CONTROL; /*!< (@ 0x000000C4) Buffer control for both buffers of an endpoint.
Fields ending in a _1 are for buffer 1.
Fields ending in a _0 are for buffer 0.
Buffer 1 controls are only valid if the
endpoint is in double buffered mode. */
__IOM uint32_t EP9_IN_BUFFER_CONTROL; /*!< (@ 0x000000C8) Buffer control for both buffers of an endpoint.
Fields ending in a _1 are for buffer 1.
Fields ending in a _0 are for buffer 0.
Buffer 1 controls are only valid if the
endpoint is in double buffered mode. */
__IOM uint32_t EP9_OUT_BUFFER_CONTROL; /*!< (@ 0x000000CC) Buffer control for both buffers of an endpoint.
Fields ending in a _1 are for buffer 1.
Fields ending in a _0 are for buffer 0.
Buffer 1 controls are only valid if the
endpoint is in double buffered mode. */
__IOM uint32_t EP10_IN_BUFFER_CONTROL; /*!< (@ 0x000000D0) Buffer control for both buffers of an endpoint.
Fields ending in a _1 are for buffer 1.
Fields ending in a _0 are for buffer 0.
Buffer 1 controls are only valid if the
endpoint is in double buffered mode. */
__IOM uint32_t EP10_OUT_BUFFER_CONTROL; /*!< (@ 0x000000D4) Buffer control for both buffers of an endpoint.
Fields ending in a _1 are for buffer 1.
Fields ending in a _0 are for buffer 0.
Buffer 1 controls are only valid if the
endpoint is in double buffered mode. */
__IOM uint32_t EP11_IN_BUFFER_CONTROL; /*!< (@ 0x000000D8) Buffer control for both buffers of an endpoint.
Fields ending in a _1 are for buffer 1.
Fields ending in a _0 are for buffer 0.
Buffer 1 controls are only valid if the
endpoint is in double buffered mode. */
__IOM uint32_t EP11_OUT_BUFFER_CONTROL; /*!< (@ 0x000000DC) Buffer control for both buffers of an endpoint.
Fields ending in a _1 are for buffer 1.
Fields ending in a _0 are for buffer 0.
Buffer 1 controls are only valid if the
endpoint is in double buffered mode. */
__IOM uint32_t EP12_IN_BUFFER_CONTROL; /*!< (@ 0x000000E0) Buffer control for both buffers of an endpoint.
Fields ending in a _1 are for buffer 1.
Fields ending in a _0 are for buffer 0.
Buffer 1 controls are only valid if the
endpoint is in double buffered mode. */
__IOM uint32_t EP12_OUT_BUFFER_CONTROL; /*!< (@ 0x000000E4) Buffer control for both buffers of an endpoint.
Fields ending in a _1 are for buffer 1.
Fields ending in a _0 are for buffer 0.
Buffer 1 controls are only valid if the
endpoint is in double buffered mode. */
__IOM uint32_t EP13_IN_BUFFER_CONTROL; /*!< (@ 0x000000E8) Buffer control for both buffers of an endpoint.
Fields ending in a _1 are for buffer 1.
Fields ending in a _0 are for buffer 0.
Buffer 1 controls are only valid if the
endpoint is in double buffered mode. */
__IOM uint32_t EP13_OUT_BUFFER_CONTROL; /*!< (@ 0x000000EC) Buffer control for both buffers of an endpoint.
Fields ending in a _1 are for buffer 1.
Fields ending in a _0 are for buffer 0.
Buffer 1 controls are only valid if the
endpoint is in double buffered mode. */
__IOM uint32_t EP14_IN_BUFFER_CONTROL; /*!< (@ 0x000000F0) Buffer control for both buffers of an endpoint.
Fields ending in a _1 are for buffer 1.
Fields ending in a _0 are for buffer 0.
Buffer 1 controls are only valid if the
endpoint is in double buffered mode. */
__IOM uint32_t EP14_OUT_BUFFER_CONTROL; /*!< (@ 0x000000F4) Buffer control for both buffers of an endpoint.
Fields ending in a _1 are for buffer 1.
Fields ending in a _0 are for buffer 0.
Buffer 1 controls are only valid if the
endpoint is in double buffered mode. */
__IOM uint32_t EP15_IN_BUFFER_CONTROL; /*!< (@ 0x000000F8) Buffer control for both buffers of an endpoint.
Fields ending in a _1 are for buffer 1.
Fields ending in a _0 are for buffer 0.
Buffer 1 controls are only valid if the
endpoint is in double buffered mode. */
__IOM uint32_t EP15_OUT_BUFFER_CONTROL; /*!< (@ 0x000000FC) Buffer control for both buffers of an endpoint.
Fields ending in a _1 are for buffer 1.
Fields ending in a _0 are for buffer 0.
Buffer 1 controls are only valid if the
endpoint is in double buffered mode. */
} USBCTRL_DPRAM_Type; /*!< Size = 256 (0x100) */
/* =========================================================================================================================== */
/* ================ USBCTRL_REGS ================ */
/* =========================================================================================================================== */
/**
* @brief USB FS/LS controller device registers (USBCTRL_REGS)
*/
typedef struct { /*!< (@ 0x50110000) USBCTRL_REGS Structure */
__IOM uint32_t ADDR_ENDP; /*!< (@ 0x00000000) Device address and endpoint control */
__IOM uint32_t ADDR_ENDP1; /*!< (@ 0x00000004) Interrupt endpoint 1. Only valid for HOST mode. */
__IOM uint32_t ADDR_ENDP2; /*!< (@ 0x00000008) Interrupt endpoint 2. Only valid for HOST mode. */
__IOM uint32_t ADDR_ENDP3; /*!< (@ 0x0000000C) Interrupt endpoint 3. Only valid for HOST mode. */
__IOM uint32_t ADDR_ENDP4; /*!< (@ 0x00000010) Interrupt endpoint 4. Only valid for HOST mode. */
__IOM uint32_t ADDR_ENDP5; /*!< (@ 0x00000014) Interrupt endpoint 5. Only valid for HOST mode. */
__IOM uint32_t ADDR_ENDP6; /*!< (@ 0x00000018) Interrupt endpoint 6. Only valid for HOST mode. */
__IOM uint32_t ADDR_ENDP7; /*!< (@ 0x0000001C) Interrupt endpoint 7. Only valid for HOST mode. */
__IOM uint32_t ADDR_ENDP8; /*!< (@ 0x00000020) Interrupt endpoint 8. Only valid for HOST mode. */
__IOM uint32_t ADDR_ENDP9; /*!< (@ 0x00000024) Interrupt endpoint 9. Only valid for HOST mode. */
__IOM uint32_t ADDR_ENDP10; /*!< (@ 0x00000028) Interrupt endpoint 10. Only valid for HOST mode. */
__IOM uint32_t ADDR_ENDP11; /*!< (@ 0x0000002C) Interrupt endpoint 11. Only valid for HOST mode. */
__IOM uint32_t ADDR_ENDP12; /*!< (@ 0x00000030) Interrupt endpoint 12. Only valid for HOST mode. */
__IOM uint32_t ADDR_ENDP13; /*!< (@ 0x00000034) Interrupt endpoint 13. Only valid for HOST mode. */
__IOM uint32_t ADDR_ENDP14; /*!< (@ 0x00000038) Interrupt endpoint 14. Only valid for HOST mode. */
__IOM uint32_t ADDR_ENDP15; /*!< (@ 0x0000003C) Interrupt endpoint 15. Only valid for HOST mode. */
__IOM uint32_t MAIN_CTRL; /*!< (@ 0x00000040) Main control register */
__IOM uint32_t SOF_WR; /*!< (@ 0x00000044) Set the SOF (Start of Frame) frame number in
the host controller. The SOF packet is sent
every 1ms and the host will increment the
frame number by 1 each time. */
__IOM uint32_t SOF_RD; /*!< (@ 0x00000048) Read the last SOF (Start of Frame) frame number
seen. In device mode the last SOF received
from the host. In host mode the last SOF
sent by the host. */
__IOM uint32_t SIE_CTRL; /*!< (@ 0x0000004C) SIE control register */
__IOM uint32_t SIE_STATUS; /*!< (@ 0x00000050) SIE status register */
__IOM uint32_t INT_EP_CTRL; /*!< (@ 0x00000054) interrupt endpoint control register */
__IOM uint32_t BUFF_STATUS; /*!< (@ 0x00000058) Buffer status register. A bit set here indicates
that a buffer has completed on the endpoint
(if the buffer interrupt is enabled). It
is possible for 2 buffers to be completed,
so clearing the buffer status bit may instantly
re set it on the next clock cycle. */
__IOM uint32_t BUFF_CPU_SHOULD_HANDLE; /*!< (@ 0x0000005C) Which of the double buffers should be handled.
Only valid if using an interrupt per buffer
(i.e. not per 2 buffers). Not valid for
host interrupt endpoint polling because
they are only single buffered. */
__IOM uint32_t EP_ABORT; /*!< (@ 0x00000060) Device only: Can be set to ignore the buffer
control register for this endpoint in case
you would like to revoke a buffer. A NAK
will be sent for every access to the endpoint
until this bit is cleared. A corresponding
bit in `EP_ABORT_DONE` is set when it is
safe to modify the buffer control register. */
__IOM uint32_t EP_ABORT_DONE; /*!< (@ 0x00000064) Device only: Used in conjunction with `EP_ABORT`.
Set once an endpoint is idle so the programmer
knows it is safe to modify the buffer control
register. */
__IOM uint32_t EP_STALL_ARM; /*!< (@ 0x00000068) Device: this bit must be set in conjunction with
the `STALL` bit in the buffer control register
to send a STALL on EP0. The device controller
clears these bits when a SETUP packet is
received because the USB spec requires that
a STALL condition is cleared when a SETUP
packet is received. */
__IOM uint32_t NAK_POLL; /*!< (@ 0x0000006C) Used by the host controller. Sets the wait time
in microseconds before trying again if the
device replies with a NAK. */
__IOM uint32_t EP_STATUS_STALL_NAK; /*!< (@ 0x00000070) Device: bits are set when the `IRQ_ON_NAK` or
`IRQ_ON_STALL` bits are set. For EP0 this
comes from `SIE_CTRL`. For all other endpoints
it comes from the endpoint control register. */
__IOM uint32_t USB_MUXING; /*!< (@ 0x00000074) Where to connect the USB controller. Should be
to_phy by default. */
__IOM uint32_t USB_PWR; /*!< (@ 0x00000078) Overrides for the power signals in the event
that the VBUS signals are not hooked up
to GPIO. Set the value of the override and
then the override enable to switch over
to the override value. */
__IOM uint32_t USBPHY_DIRECT; /*!< (@ 0x0000007C) This register allows for direct control of the
USB phy. Use in conjunction with usbphy_direct_override
register to enable each override bit. */
__IOM uint32_t USBPHY_DIRECT_OVERRIDE; /*!< (@ 0x00000080) Override enable for each control in usbphy_direct */
__IOM uint32_t USBPHY_TRIM; /*!< (@ 0x00000084) Used to adjust trim values of USB phy pull down
resistors. */
__IM uint32_t RESERVED;
__IOM uint32_t INTR; /*!< (@ 0x0000008C) Raw Interrupts */
__IOM uint32_t INTE; /*!< (@ 0x00000090) Interrupt Enable */
__IOM uint32_t INTF; /*!< (@ 0x00000094) Interrupt Force */
__IOM uint32_t INTS; /*!< (@ 0x00000098) Interrupt status after masking & forcing */
} USBCTRL_REGS_Type; /*!< Size = 156 (0x9c) */
/* =========================================================================================================================== */
/* ================ PIO0 ================ */
/* =========================================================================================================================== */
/**
* @brief Programmable IO block (PIO0)
*/
typedef struct { /*!< (@ 0x50200000) PIO0 Structure */
__IOM uint32_t CTRL; /*!< (@ 0x00000000) PIO control register */
__IOM uint32_t FSTAT; /*!< (@ 0x00000004) FIFO status register */
__IOM uint32_t FDEBUG; /*!< (@ 0x00000008) FIFO debug register */
__IOM uint32_t FLEVEL; /*!< (@ 0x0000000C) FIFO levels */
__OM uint32_t TXF0; /*!< (@ 0x00000010) Direct write access to the TX FIFO for this state
machine. Each write pushes one word to the
FIFO. Attempting to write to a full FIFO
has no effect on the FIFO state or contents,
and sets the sticky FDEBUG_TXOVER error
flag for this FIFO. */
__OM uint32_t TXF1; /*!< (@ 0x00000014) Direct write access to the TX FIFO for this state
machine. Each write pushes one word to the
FIFO. Attempting to write to a full FIFO
has no effect on the FIFO state or contents,
and sets the sticky FDEBUG_TXOVER error
flag for this FIFO. */
__OM uint32_t TXF2; /*!< (@ 0x00000018) Direct write access to the TX FIFO for this state
machine. Each write pushes one word to the
FIFO. Attempting to write to a full FIFO
has no effect on the FIFO state or contents,
and sets the sticky FDEBUG_TXOVER error
flag for this FIFO. */
__OM uint32_t TXF3; /*!< (@ 0x0000001C) Direct write access to the TX FIFO for this state
machine. Each write pushes one word to the
FIFO. Attempting to write to a full FIFO
has no effect on the FIFO state or contents,
and sets the sticky FDEBUG_TXOVER error
flag for this FIFO. */
__IM uint32_t RXF0; /*!< (@ 0x00000020) Direct read access to the RX FIFO for this state
machine. Each read pops one word from the
FIFO. Attempting to read from an empty FIFO
has no effect on the FIFO state, and sets
the sticky FDEBUG_RXUNDER error flag for
this FIFO. The data returned to the system
on a read from an empty FIFO is undefined. */
__IM uint32_t RXF1; /*!< (@ 0x00000024) Direct read access to the RX FIFO for this state
machine. Each read pops one word from the
FIFO. Attempting to read from an empty FIFO
has no effect on the FIFO state, and sets
the sticky FDEBUG_RXUNDER error flag for
this FIFO. The data returned to the system
on a read from an empty FIFO is undefined. */
__IM uint32_t RXF2; /*!< (@ 0x00000028) Direct read access to the RX FIFO for this state
machine. Each read pops one word from the
FIFO. Attempting to read from an empty FIFO
has no effect on the FIFO state, and sets
the sticky FDEBUG_RXUNDER error flag for
this FIFO. The data returned to the system
on a read from an empty FIFO is undefined. */
__IM uint32_t RXF3; /*!< (@ 0x0000002C) Direct read access to the RX FIFO for this state
machine. Each read pops one word from the
FIFO. Attempting to read from an empty FIFO
has no effect on the FIFO state, and sets
the sticky FDEBUG_RXUNDER error flag for
this FIFO. The data returned to the system
on a read from an empty FIFO is undefined. */
__IOM uint32_t IRQ; /*!< (@ 0x00000030) State machine IRQ flags register. Write 1 to
clear. There are 8 state machine IRQ flags,
which can be set, cleared, and waited on
by the state machines. There's no fixed
association between flags and state machines
-- any state machine can use any flag.
Any of the 8 flags can be used for timing
synchronisation between state machines,
using IRQ and WAIT instructions. The lower
four of these flags are also routed out
to system-level interrupt requests, alongside
FIFO status in */
__IOM uint32_t IRQ_FORCE; /*!< (@ 0x00000034) Writing a 1 to each of these bits will forcibly
assert the corresponding IRQ. Note this
is different to the INTF register: writing
here affects PIO internal state. INTF just
asserts the processor-facing IRQ signal
for testing ISRs, and is not visible to
the state machines. */
__IOM uint32_t INPUT_SYNC_BYPASS; /*!< (@ 0x00000038) There is a 2-flipflop synchronizer on each GPIO
input, which protects PIO logic from metastabilities.
This increases input delay, and for fast
synchronous IO (e.g. SPI) these synchronizers
may need to be bypassed. Each bit in this
register corresponds to one GPIO.
0 -> input is synchronized (default)
1 -> synchronizer is bypassed
If in doubt, leave this register as all
zeroes. */
__IM uint32_t DBG_PADOUT; /*!< (@ 0x0000003C) Read to sample the pad output values PIO is currently
driving to the GPIOs. On RP2040 there are
30 GPIOs, so the two most significant bits
are hardwired to 0. */
__IM uint32_t DBG_PADOE; /*!< (@ 0x00000040) Read to sample the pad output enables (direction)
PIO is currently driving to the GPIOs. On
RP2040 there are 30 GPIOs, so the two most
significant bits are hardwired to 0. */
__IOM uint32_t DBG_CFGINFO; /*!< (@ 0x00000044) The PIO hardware has some free parameters that
may vary between chip products.
These should be provided in the chip datasheet,
but are also exposed here. */
__IOM uint32_t INSTR_MEM0; /*!< (@ 0x00000048) Write-only access to instruction memory location
0 */
__IOM uint32_t INSTR_MEM1; /*!< (@ 0x0000004C) Write-only access to instruction memory location
1 */
__IOM uint32_t INSTR_MEM2; /*!< (@ 0x00000050) Write-only access to instruction memory location
2 */
__IOM uint32_t INSTR_MEM3; /*!< (@ 0x00000054) Write-only access to instruction memory location
3 */
__IOM uint32_t INSTR_MEM4; /*!< (@ 0x00000058) Write-only access to instruction memory location
4 */
__IOM uint32_t INSTR_MEM5; /*!< (@ 0x0000005C) Write-only access to instruction memory location
5 */
__IOM uint32_t INSTR_MEM6; /*!< (@ 0x00000060) Write-only access to instruction memory location
6 */
__IOM uint32_t INSTR_MEM7; /*!< (@ 0x00000064) Write-only access to instruction memory location
7 */
__IOM uint32_t INSTR_MEM8; /*!< (@ 0x00000068) Write-only access to instruction memory location
8 */
__IOM uint32_t INSTR_MEM9; /*!< (@ 0x0000006C) Write-only access to instruction memory location
9 */
__IOM uint32_t INSTR_MEM10; /*!< (@ 0x00000070) Write-only access to instruction memory location
10 */
__IOM uint32_t INSTR_MEM11; /*!< (@ 0x00000074) Write-only access to instruction memory location
11 */
__IOM uint32_t INSTR_MEM12; /*!< (@ 0x00000078) Write-only access to instruction memory location
12 */
__IOM uint32_t INSTR_MEM13; /*!< (@ 0x0000007C) Write-only access to instruction memory location
13 */
__IOM uint32_t INSTR_MEM14; /*!< (@ 0x00000080) Write-only access to instruction memory location
14 */
__IOM uint32_t INSTR_MEM15; /*!< (@ 0x00000084) Write-only access to instruction memory location
15 */
__IOM uint32_t INSTR_MEM16; /*!< (@ 0x00000088) Write-only access to instruction memory location
16 */
__IOM uint32_t INSTR_MEM17; /*!< (@ 0x0000008C) Write-only access to instruction memory location
17 */
__IOM uint32_t INSTR_MEM18; /*!< (@ 0x00000090) Write-only access to instruction memory location
18 */
__IOM uint32_t INSTR_MEM19; /*!< (@ 0x00000094) Write-only access to instruction memory location
19 */
__IOM uint32_t INSTR_MEM20; /*!< (@ 0x00000098) Write-only access to instruction memory location
20 */
__IOM uint32_t INSTR_MEM21; /*!< (@ 0x0000009C) Write-only access to instruction memory location
21 */
__IOM uint32_t INSTR_MEM22; /*!< (@ 0x000000A0) Write-only access to instruction memory location
22 */
__IOM uint32_t INSTR_MEM23; /*!< (@ 0x000000A4) Write-only access to instruction memory location
23 */
__IOM uint32_t INSTR_MEM24; /*!< (@ 0x000000A8) Write-only access to instruction memory location
24 */
__IOM uint32_t INSTR_MEM25; /*!< (@ 0x000000AC) Write-only access to instruction memory location
25 */
__IOM uint32_t INSTR_MEM26; /*!< (@ 0x000000B0) Write-only access to instruction memory location
26 */
__IOM uint32_t INSTR_MEM27; /*!< (@ 0x000000B4) Write-only access to instruction memory location
27 */
__IOM uint32_t INSTR_MEM28; /*!< (@ 0x000000B8) Write-only access to instruction memory location
28 */
__IOM uint32_t INSTR_MEM29; /*!< (@ 0x000000BC) Write-only access to instruction memory location
29 */
__IOM uint32_t INSTR_MEM30; /*!< (@ 0x000000C0) Write-only access to instruction memory location
30 */
__IOM uint32_t INSTR_MEM31; /*!< (@ 0x000000C4) Write-only access to instruction memory location
31 */
__IOM uint32_t SM0_CLKDIV; /*!< (@ 0x000000C8) Clock divisor register for state machine 0
Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC
/ 256) */
__IOM uint32_t SM0_EXECCTRL; /*!< (@ 0x000000CC) Execution/behavioural settings for state machine
0 */
__IOM uint32_t SM0_SHIFTCTRL; /*!< (@ 0x000000D0) Control behaviour of the input/output shift registers
for state machine 0 */
__IOM uint32_t SM0_ADDR; /*!< (@ 0x000000D4) Current instruction address of state machine
0 */
__IOM uint32_t SM0_INSTR; /*!< (@ 0x000000D8) Read to see the instruction currently addressed
by state machine 0's program counter
Write to execute an instruction immediately
(including jumps) and then resume execution. */
__IOM uint32_t SM0_PINCTRL; /*!< (@ 0x000000DC) State machine pin control */
__IOM uint32_t SM1_CLKDIV; /*!< (@ 0x000000E0) Clock divisor register for state machine 1
Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC
/ 256) */
__IOM uint32_t SM1_EXECCTRL; /*!< (@ 0x000000E4) Execution/behavioural settings for state machine
1 */
__IOM uint32_t SM1_SHIFTCTRL; /*!< (@ 0x000000E8) Control behaviour of the input/output shift registers
for state machine 1 */
__IOM uint32_t SM1_ADDR; /*!< (@ 0x000000EC) Current instruction address of state machine
1 */
__IOM uint32_t SM1_INSTR; /*!< (@ 0x000000F0) Read to see the instruction currently addressed
by state machine 1's program counter
Write to execute an instruction immediately
(including jumps) and then resume execution. */
__IOM uint32_t SM1_PINCTRL; /*!< (@ 0x000000F4) State machine pin control */
__IOM uint32_t SM2_CLKDIV; /*!< (@ 0x000000F8) Clock divisor register for state machine 2
Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC
/ 256) */
__IOM uint32_t SM2_EXECCTRL; /*!< (@ 0x000000FC) Execution/behavioural settings for state machine
2 */
__IOM uint32_t SM2_SHIFTCTRL; /*!< (@ 0x00000100) Control behaviour of the input/output shift registers
for state machine 2 */
__IOM uint32_t SM2_ADDR; /*!< (@ 0x00000104) Current instruction address of state machine
2 */
__IOM uint32_t SM2_INSTR; /*!< (@ 0x00000108) Read to see the instruction currently addressed
by state machine 2's program counter
Write to execute an instruction immediately
(including jumps) and then resume execution. */
__IOM uint32_t SM2_PINCTRL; /*!< (@ 0x0000010C) State machine pin control */
__IOM uint32_t SM3_CLKDIV; /*!< (@ 0x00000110) Clock divisor register for state machine 3
Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC
/ 256) */
__IOM uint32_t SM3_EXECCTRL; /*!< (@ 0x00000114) Execution/behavioural settings for state machine
3 */
__IOM uint32_t SM3_SHIFTCTRL; /*!< (@ 0x00000118) Control behaviour of the input/output shift registers
for state machine 3 */
__IOM uint32_t SM3_ADDR; /*!< (@ 0x0000011C) Current instruction address of state machine
3 */
__IOM uint32_t SM3_INSTR; /*!< (@ 0x00000120) Read to see the instruction currently addressed
by state machine 3's program counter
Write to execute an instruction immediately
(including jumps) and then resume execution. */
__IOM uint32_t SM3_PINCTRL; /*!< (@ 0x00000124) State machine pin control */
__IOM uint32_t INTR; /*!< (@ 0x00000128) Raw Interrupts */
__IOM uint32_t IRQ0_INTE; /*!< (@ 0x0000012C) Interrupt Enable for irq0 */
__IOM uint32_t IRQ0_INTF; /*!< (@ 0x00000130) Interrupt Force for irq0 */
__IOM uint32_t IRQ0_INTS; /*!< (@ 0x00000134) Interrupt status after masking & forcing for
irq0 */
__IOM uint32_t IRQ1_INTE; /*!< (@ 0x00000138) Interrupt Enable for irq1 */
__IOM uint32_t IRQ1_INTF; /*!< (@ 0x0000013C) Interrupt Force for irq1 */
__IOM uint32_t IRQ1_INTS; /*!< (@ 0x00000140) Interrupt status after masking & forcing for
irq1 */
} PIO0_Type; /*!< Size = 324 (0x144) */
/* =========================================================================================================================== */
/* ================ SIO ================ */
/* =========================================================================================================================== */
/**
* @brief Single-cycle IO block\n
Provides core-local and inter-core hardware for the two processors, with single-cycle access. (SIO)
*/
typedef struct { /*!< (@ 0xD0000000) SIO Structure */
__IM uint32_t CPUID; /*!< (@ 0x00000000) Processor core identifier
Value is 0 when read from processor core
0, and 1 when read from processor core 1. */
__IOM uint32_t GPIO_IN; /*!< (@ 0x00000004) Input value for GPIO pins */
__IOM uint32_t GPIO_HI_IN; /*!< (@ 0x00000008) Input value for QSPI pins */
__IM uint32_t RESERVED;
__IOM uint32_t GPIO_OUT; /*!< (@ 0x00000010) GPIO output value */
__IOM uint32_t GPIO_OUT_SET; /*!< (@ 0x00000014) GPIO output value set */
__IOM uint32_t GPIO_OUT_CLR; /*!< (@ 0x00000018) GPIO output value clear */
__IOM uint32_t GPIO_OUT_XOR; /*!< (@ 0x0000001C) GPIO output value XOR */
__IOM uint32_t GPIO_OE; /*!< (@ 0x00000020) GPIO output enable */
__IOM uint32_t GPIO_OE_SET; /*!< (@ 0x00000024) GPIO output enable set */
__IOM uint32_t GPIO_OE_CLR; /*!< (@ 0x00000028) GPIO output enable clear */
__IOM uint32_t GPIO_OE_XOR; /*!< (@ 0x0000002C) GPIO output enable XOR */
__IOM uint32_t GPIO_HI_OUT; /*!< (@ 0x00000030) QSPI output value */
__IOM uint32_t GPIO_HI_OUT_SET; /*!< (@ 0x00000034) QSPI output value set */
__IOM uint32_t GPIO_HI_OUT_CLR; /*!< (@ 0x00000038) QSPI output value clear */
__IOM uint32_t GPIO_HI_OUT_XOR; /*!< (@ 0x0000003C) QSPI output value XOR */
__IOM uint32_t GPIO_HI_OE; /*!< (@ 0x00000040) QSPI output enable */
__IOM uint32_t GPIO_HI_OE_SET; /*!< (@ 0x00000044) QSPI output enable set */
__IOM uint32_t GPIO_HI_OE_CLR; /*!< (@ 0x00000048) QSPI output enable clear */
__IOM uint32_t GPIO_HI_OE_XOR; /*!< (@ 0x0000004C) QSPI output enable XOR */
__IOM uint32_t FIFO_ST; /*!< (@ 0x00000050) Status register for inter-core FIFOs (mailboxes).
There is one FIFO in the core 0 -> core
1 direction, and one core 1 -> core 0. Both
are 32 bits wide and 8 words deep.
Core 0 can see the read side of the 1->0
FIFO (RX), and the write side of 0->1 FIFO
(TX).
Core 1 can see the read side of the 0->1
FIFO (RX), and the write side of 1->0 FIFO
(TX).
The SIO IRQ for each core is the logical
OR of the VLD, WOF and ROE fields of its
FIFO_ */
__OM uint32_t FIFO_WR; /*!< (@ 0x00000054) Write access to this core's TX FIFO */
__IM uint32_t FIFO_RD; /*!< (@ 0x00000058) Read access to this core's RX FIFO */
__IM uint32_t SPINLOCK_ST; /*!< (@ 0x0000005C) Spinlock state
A bitmap containing the state of all 32
spinlocks (1=locked).
Mainly intended for debugging. */
__IOM uint32_t DIV_UDIVIDEND; /*!< (@ 0x00000060) Divider unsigned dividend
Write to the DIVIDEND operand of the divider,
i.e. the p in `p / q`.
Any operand write starts a new calculation.
The results appear in QUOTIENT, REMAINDER.
UDIVIDEND/SDIVIDEND are aliases of the same
internal register. The U alias starts an
unsigned calculation, and the S alias starts
a signed calculation. */
__IOM uint32_t DIV_UDIVISOR; /*!< (@ 0x00000064) Divider unsigned divisor
Write to the DIVISOR operand of the divider,
i.e. the q in `p / q`.
Any operand write starts a new calculation.
The results appear in QUOTIENT, REMAINDER.
UDIVISOR/SDIVISOR are aliases of the same
internal register. The U alias starts an
unsigned calculation, and the S alias starts
a signed calculation. */
__IOM uint32_t DIV_SDIVIDEND; /*!< (@ 0x00000068) Divider signed dividend
The same as UDIVIDEND, but starts a signed
calculation, rather than unsigned. */
__IOM uint32_t DIV_SDIVISOR; /*!< (@ 0x0000006C) Divider signed divisor
The same as UDIVISOR, but starts a signed
calculation, rather than unsigned. */
__IOM uint32_t DIV_QUOTIENT; /*!< (@ 0x00000070) Divider result quotient
The result of `DIVIDEND / DIVISOR` (division).
Contents undefined while CSR_READY is low.
For signed calculations, QUOTIENT is negative
when the signs of DIVIDEND and DIVISOR differ.
This register can be written to directly,
for context save/restore purposes. This
halts any
in-progress calculation and sets the CSR_READY
and CSR_DIRTY flags.
Reading from QUOTIENT clears the CSR_DIRTY
flag, so sh */
__IOM uint32_t DIV_REMAINDER; /*!< (@ 0x00000074) Divider result remainder
The result of `DIVIDEND % DIVISOR` (modulo).
Contents undefined while CSR_READY is low.
For signed calculations, REMAINDER is negative
only when DIVIDEND is negative.
This register can be written to directly,
for context save/restore purposes. This
halts any
in-progress calculation and sets the CSR_READY
and CSR_DIRTY flags. */
__IOM uint32_t DIV_CSR; /*!< (@ 0x00000078) Control and status register for divider. */
__IM uint32_t RESERVED1;
__IOM uint32_t INTERP0_ACCUM0; /*!< (@ 0x00000080) Read/write access to accumulator 0 */
__IOM uint32_t INTERP0_ACCUM1; /*!< (@ 0x00000084) Read/write access to accumulator 1 */
__IOM uint32_t INTERP0_BASE0; /*!< (@ 0x00000088) Read/write access to BASE0 register. */
__IOM uint32_t INTERP0_BASE1; /*!< (@ 0x0000008C) Read/write access to BASE1 register. */
__IOM uint32_t INTERP0_BASE2; /*!< (@ 0x00000090) Read/write access to BASE2 register. */
__IM uint32_t INTERP0_POP_LANE0; /*!< (@ 0x00000094) Read LANE0 result, and simultaneously write lane
results to both accumulators (POP). */
__IM uint32_t INTERP0_POP_LANE1; /*!< (@ 0x00000098) Read LANE1 result, and simultaneously write lane
results to both accumulators (POP). */
__IM uint32_t INTERP0_POP_FULL; /*!< (@ 0x0000009C) Read FULL result, and simultaneously write lane
results to both accumulators (POP). */
__IM uint32_t INTERP0_PEEK_LANE0; /*!< (@ 0x000000A0) Read LANE0 result, without altering any internal
state (PEEK). */
__IM uint32_t INTERP0_PEEK_LANE1; /*!< (@ 0x000000A4) Read LANE1 result, without altering any internal
state (PEEK). */
__IM uint32_t INTERP0_PEEK_FULL; /*!< (@ 0x000000A8) Read FULL result, without altering any internal
state (PEEK). */
__IOM uint32_t INTERP0_CTRL_LANE0; /*!< (@ 0x000000AC) Control register for lane 0 */
__IOM uint32_t INTERP0_CTRL_LANE1; /*!< (@ 0x000000B0) Control register for lane 1 */
__IOM uint32_t INTERP0_ACCUM0_ADD; /*!< (@ 0x000000B4) Values written here are atomically added to ACCUM0
Reading yields lane 0's raw shift and mask
value (BASE0 not added). */
__IOM uint32_t INTERP0_ACCUM1_ADD; /*!< (@ 0x000000B8) Values written here are atomically added to ACCUM1
Reading yields lane 1's raw shift and mask
value (BASE1 not added). */
__OM uint32_t INTERP0_BASE_1AND0; /*!< (@ 0x000000BC) On write, the lower 16 bits go to BASE0, upper
bits to BASE1 simultaneously.
Each half is sign-extended to 32 bits if
that lane's SIGNED flag is set. */
__IOM uint32_t INTERP1_ACCUM0; /*!< (@ 0x000000C0) Read/write access to accumulator 0 */
__IOM uint32_t INTERP1_ACCUM1; /*!< (@ 0x000000C4) Read/write access to accumulator 1 */
__IOM uint32_t INTERP1_BASE0; /*!< (@ 0x000000C8) Read/write access to BASE0 register. */
__IOM uint32_t INTERP1_BASE1; /*!< (@ 0x000000CC) Read/write access to BASE1 register. */
__IOM uint32_t INTERP1_BASE2; /*!< (@ 0x000000D0) Read/write access to BASE2 register. */
__IM uint32_t INTERP1_POP_LANE0; /*!< (@ 0x000000D4) Read LANE0 result, and simultaneously write lane
results to both accumulators (POP). */
__IM uint32_t INTERP1_POP_LANE1; /*!< (@ 0x000000D8) Read LANE1 result, and simultaneously write lane
results to both accumulators (POP). */
__IM uint32_t INTERP1_POP_FULL; /*!< (@ 0x000000DC) Read FULL result, and simultaneously write lane
results to both accumulators (POP). */
__IM uint32_t INTERP1_PEEK_LANE0; /*!< (@ 0x000000E0) Read LANE0 result, without altering any internal
state (PEEK). */
__IM uint32_t INTERP1_PEEK_LANE1; /*!< (@ 0x000000E4) Read LANE1 result, without altering any internal
state (PEEK). */
__IM uint32_t INTERP1_PEEK_FULL; /*!< (@ 0x000000E8) Read FULL result, without altering any internal
state (PEEK). */
__IOM uint32_t INTERP1_CTRL_LANE0; /*!< (@ 0x000000EC) Control register for lane 0 */
__IOM uint32_t INTERP1_CTRL_LANE1; /*!< (@ 0x000000F0) Control register for lane 1 */
__IOM uint32_t INTERP1_ACCUM0_ADD; /*!< (@ 0x000000F4) Values written here are atomically added to ACCUM0
Reading yields lane 0's raw shift and mask
value (BASE0 not added). */
__IOM uint32_t INTERP1_ACCUM1_ADD; /*!< (@ 0x000000F8) Values written here are atomically added to ACCUM1
Reading yields lane 1's raw shift and mask
value (BASE1 not added). */
__OM uint32_t INTERP1_BASE_1AND0; /*!< (@ 0x000000FC) On write, the lower 16 bits go to BASE0, upper
bits to BASE1 simultaneously.
Each half is sign-extended to 32 bits if
that lane's SIGNED flag is set. */
__IOM uint32_t SPINLOCK0; /*!< (@ 0x00000100) Reading from a spinlock address will:
- Return 0 if lock is already locked
- Otherwise return nonzero, and simultaneously
claim the lock
Writing (any value) releases the lock.
If core 0 and core 1 attempt to claim the
same lock simultaneously, core 0 wins.
The value returned on success is 0x1 <<
lock number. */
__IOM uint32_t SPINLOCK1; /*!< (@ 0x00000104) Reading from a spinlock address will:
- Return 0 if lock is already locked
- Otherwise return nonzero, and simultaneously
claim the lock
Writing (any value) releases the lock.
If core 0 and core 1 attempt to claim the
same lock simultaneously, core 0 wins.
The value returned on success is 0x1 <<
lock number. */
__IOM uint32_t SPINLOCK2; /*!< (@ 0x00000108) Reading from a spinlock address will:
- Return 0 if lock is already locked
- Otherwise return nonzero, and simultaneously
claim the lock
Writing (any value) releases the lock.
If core 0 and core 1 attempt to claim the
same lock simultaneously, core 0 wins.
The value returned on success is 0x1 <<
lock number. */
__IOM uint32_t SPINLOCK3; /*!< (@ 0x0000010C) Reading from a spinlock address will:
- Return 0 if lock is already locked
- Otherwise return nonzero, and simultaneously
claim the lock
Writing (any value) releases the lock.
If core 0 and core 1 attempt to claim the
same lock simultaneously, core 0 wins.
The value returned on success is 0x1 <<
lock number. */
__IOM uint32_t SPINLOCK4; /*!< (@ 0x00000110) Reading from a spinlock address will:
- Return 0 if lock is already locked
- Otherwise return nonzero, and simultaneously
claim the lock
Writing (any value) releases the lock.
If core 0 and core 1 attempt to claim the
same lock simultaneously, core 0 wins.
The value returned on success is 0x1 <<
lock number. */
__IOM uint32_t SPINLOCK5; /*!< (@ 0x00000114) Reading from a spinlock address will:
- Return 0 if lock is already locked
- Otherwise return nonzero, and simultaneously
claim the lock
Writing (any value) releases the lock.
If core 0 and core 1 attempt to claim the
same lock simultaneously, core 0 wins.
The value returned on success is 0x1 <<
lock number. */
__IOM uint32_t SPINLOCK6; /*!< (@ 0x00000118) Reading from a spinlock address will:
- Return 0 if lock is already locked
- Otherwise return nonzero, and simultaneously
claim the lock
Writing (any value) releases the lock.
If core 0 and core 1 attempt to claim the
same lock simultaneously, core 0 wins.
The value returned on success is 0x1 <<
lock number. */
__IOM uint32_t SPINLOCK7; /*!< (@ 0x0000011C) Reading from a spinlock address will:
- Return 0 if lock is already locked
- Otherwise return nonzero, and simultaneously
claim the lock
Writing (any value) releases the lock.
If core 0 and core 1 attempt to claim the
same lock simultaneously, core 0 wins.
The value returned on success is 0x1 <<
lock number. */
__IOM uint32_t SPINLOCK8; /*!< (@ 0x00000120) Reading from a spinlock address will:
- Return 0 if lock is already locked
- Otherwise return nonzero, and simultaneously
claim the lock
Writing (any value) releases the lock.
If core 0 and core 1 attempt to claim the
same lock simultaneously, core 0 wins.
The value returned on success is 0x1 <<
lock number. */
__IOM uint32_t SPINLOCK9; /*!< (@ 0x00000124) Reading from a spinlock address will:
- Return 0 if lock is already locked
- Otherwise return nonzero, and simultaneously
claim the lock
Writing (any value) releases the lock.
If core 0 and core 1 attempt to claim the
same lock simultaneously, core 0 wins.
The value returned on success is 0x1 <<
lock number. */
__IOM uint32_t SPINLOCK10; /*!< (@ 0x00000128) Reading from a spinlock address will:
- Return 0 if lock is already locked
- Otherwise return nonzero, and simultaneously
claim the lock
Writing (any value) releases the lock.
If core 0 and core 1 attempt to claim the
same lock simultaneously, core 0 wins.
The value returned on success is 0x1 <<
lock number. */
__IOM uint32_t SPINLOCK11; /*!< (@ 0x0000012C) Reading from a spinlock address will:
- Return 0 if lock is already locked
- Otherwise return nonzero, and simultaneously
claim the lock
Writing (any value) releases the lock.
If core 0 and core 1 attempt to claim the
same lock simultaneously, core 0 wins.
The value returned on success is 0x1 <<
lock number. */
__IOM uint32_t SPINLOCK12; /*!< (@ 0x00000130) Reading from a spinlock address will:
- Return 0 if lock is already locked
- Otherwise return nonzero, and simultaneously
claim the lock
Writing (any value) releases the lock.
If core 0 and core 1 attempt to claim the
same lock simultaneously, core 0 wins.
The value returned on success is 0x1 <<
lock number. */
__IOM uint32_t SPINLOCK13; /*!< (@ 0x00000134) Reading from a spinlock address will:
- Return 0 if lock is already locked
- Otherwise return nonzero, and simultaneously
claim the lock
Writing (any value) releases the lock.
If core 0 and core 1 attempt to claim the
same lock simultaneously, core 0 wins.
The value returned on success is 0x1 <<
lock number. */
__IOM uint32_t SPINLOCK14; /*!< (@ 0x00000138) Reading from a spinlock address will:
- Return 0 if lock is already locked
- Otherwise return nonzero, and simultaneously
claim the lock
Writing (any value) releases the lock.
If core 0 and core 1 attempt to claim the
same lock simultaneously, core 0 wins.
The value returned on success is 0x1 <<
lock number. */
__IOM uint32_t SPINLOCK15; /*!< (@ 0x0000013C) Reading from a spinlock address will:
- Return 0 if lock is already locked
- Otherwise return nonzero, and simultaneously
claim the lock
Writing (any value) releases the lock.
If core 0 and core 1 attempt to claim the
same lock simultaneously, core 0 wins.
The value returned on success is 0x1 <<
lock number. */
__IOM uint32_t SPINLOCK16; /*!< (@ 0x00000140) Reading from a spinlock address will:
- Return 0 if lock is already locked
- Otherwise return nonzero, and simultaneously
claim the lock
Writing (any value) releases the lock.
If core 0 and core 1 attempt to claim the
same lock simultaneously, core 0 wins.
The value returned on success is 0x1 <<
lock number. */
__IOM uint32_t SPINLOCK17; /*!< (@ 0x00000144) Reading from a spinlock address will:
- Return 0 if lock is already locked
- Otherwise return nonzero, and simultaneously
claim the lock
Writing (any value) releases the lock.
If core 0 and core 1 attempt to claim the
same lock simultaneously, core 0 wins.
The value returned on success is 0x1 <<
lock number. */
__IOM uint32_t SPINLOCK18; /*!< (@ 0x00000148) Reading from a spinlock address will:
- Return 0 if lock is already locked
- Otherwise return nonzero, and simultaneously
claim the lock
Writing (any value) releases the lock.
If core 0 and core 1 attempt to claim the
same lock simultaneously, core 0 wins.
The value returned on success is 0x1 <<
lock number. */
__IOM uint32_t SPINLOCK19; /*!< (@ 0x0000014C) Reading from a spinlock address will:
- Return 0 if lock is already locked
- Otherwise return nonzero, and simultaneously
claim the lock
Writing (any value) releases the lock.
If core 0 and core 1 attempt to claim the
same lock simultaneously, core 0 wins.
The value returned on success is 0x1 <<
lock number. */
__IOM uint32_t SPINLOCK20; /*!< (@ 0x00000150) Reading from a spinlock address will:
- Return 0 if lock is already locked
- Otherwise return nonzero, and simultaneously
claim the lock
Writing (any value) releases the lock.
If core 0 and core 1 attempt to claim the
same lock simultaneously, core 0 wins.
The value returned on success is 0x1 <<
lock number. */
__IOM uint32_t SPINLOCK21; /*!< (@ 0x00000154) Reading from a spinlock address will:
- Return 0 if lock is already locked
- Otherwise return nonzero, and simultaneously
claim the lock
Writing (any value) releases the lock.
If core 0 and core 1 attempt to claim the
same lock simultaneously, core 0 wins.
The value returned on success is 0x1 <<
lock number. */
__IOM uint32_t SPINLOCK22; /*!< (@ 0x00000158) Reading from a spinlock address will:
- Return 0 if lock is already locked
- Otherwise return nonzero, and simultaneously
claim the lock
Writing (any value) releases the lock.
If core 0 and core 1 attempt to claim the
same lock simultaneously, core 0 wins.
The value returned on success is 0x1 <<
lock number. */
__IOM uint32_t SPINLOCK23; /*!< (@ 0x0000015C) Reading from a spinlock address will:
- Return 0 if lock is already locked
- Otherwise return nonzero, and simultaneously
claim the lock
Writing (any value) releases the lock.
If core 0 and core 1 attempt to claim the
same lock simultaneously, core 0 wins.
The value returned on success is 0x1 <<
lock number. */
__IOM uint32_t SPINLOCK24; /*!< (@ 0x00000160) Reading from a spinlock address will:
- Return 0 if lock is already locked
- Otherwise return nonzero, and simultaneously
claim the lock
Writing (any value) releases the lock.
If core 0 and core 1 attempt to claim the
same lock simultaneously, core 0 wins.
The value returned on success is 0x1 <<
lock number. */
__IOM uint32_t SPINLOCK25; /*!< (@ 0x00000164) Reading from a spinlock address will:
- Return 0 if lock is already locked
- Otherwise return nonzero, and simultaneously
claim the lock
Writing (any value) releases the lock.
If core 0 and core 1 attempt to claim the
same lock simultaneously, core 0 wins.
The value returned on success is 0x1 <<
lock number. */
__IOM uint32_t SPINLOCK26; /*!< (@ 0x00000168) Reading from a spinlock address will:
- Return 0 if lock is already locked
- Otherwise return nonzero, and simultaneously
claim the lock
Writing (any value) releases the lock.
If core 0 and core 1 attempt to claim the
same lock simultaneously, core 0 wins.
The value returned on success is 0x1 <<
lock number. */
__IOM uint32_t SPINLOCK27; /*!< (@ 0x0000016C) Reading from a spinlock address will:
- Return 0 if lock is already locked
- Otherwise return nonzero, and simultaneously
claim the lock
Writing (any value) releases the lock.
If core 0 and core 1 attempt to claim the
same lock simultaneously, core 0 wins.
The value returned on success is 0x1 <<
lock number. */
__IOM uint32_t SPINLOCK28; /*!< (@ 0x00000170) Reading from a spinlock address will:
- Return 0 if lock is already locked
- Otherwise return nonzero, and simultaneously
claim the lock
Writing (any value) releases the lock.
If core 0 and core 1 attempt to claim the
same lock simultaneously, core 0 wins.
The value returned on success is 0x1 <<
lock number. */
__IOM uint32_t SPINLOCK29; /*!< (@ 0x00000174) Reading from a spinlock address will:
- Return 0 if lock is already locked
- Otherwise return nonzero, and simultaneously
claim the lock
Writing (any value) releases the lock.
If core 0 and core 1 attempt to claim the
same lock simultaneously, core 0 wins.
The value returned on success is 0x1 <<
lock number. */
__IOM uint32_t SPINLOCK30; /*!< (@ 0x00000178) Reading from a spinlock address will:
- Return 0 if lock is already locked
- Otherwise return nonzero, and simultaneously
claim the lock
Writing (any value) releases the lock.
If core 0 and core 1 attempt to claim the
same lock simultaneously, core 0 wins.
The value returned on success is 0x1 <<
lock number. */
__IOM uint32_t SPINLOCK31; /*!< (@ 0x0000017C) Reading from a spinlock address will:
- Return 0 if lock is already locked
- Otherwise return nonzero, and simultaneously
claim the lock
Writing (any value) releases the lock.
If core 0 and core 1 attempt to claim the
same lock simultaneously, core 0 wins.
The value returned on success is 0x1 <<
lock number. */
} SIO_Type; /*!< Size = 384 (0x180) */
/* =========================================================================================================================== */
/* ================ PPB ================ */
/* =========================================================================================================================== */
/**
* @brief PPB (PPB)
*/
typedef struct { /*!< (@ 0xE0000000) PPB Structure */
__IM uint32_t RESERVED[14340];
__IOM uint32_t SYST_CSR; /*!< (@ 0x0000E010) Use the SysTick Control and Status Register to
enable the SysTick features. */
__IOM uint32_t SYST_RVR; /*!< (@ 0x0000E014) Use the SysTick Reload Value Register to specify
the start value to load into the current
value register when the counter reaches
0. It can be any value between 0 and 0x00FFFFFF.
A start value of 0 is possible, but has
no effect because the SysTick interrupt
and COUNTFLAG are activated when counting
from 1 to 0. The reset value of this register
is UNKNOWN.
To generate a multi-shot timer with a period
of N processor clock cycles, use a RELOAD
value of N-1. For example, if the S */
__IOM uint32_t SYST_CVR; /*!< (@ 0x0000E018) Use the SysTick Current Value Register to find
the current value in the register. The reset
value of this register is UNKNOWN. */
__IOM uint32_t SYST_CALIB; /*!< (@ 0x0000E01C) Use the SysTick Calibration Value Register to
enable software to scale to any required
speed using divide and multiply. */
__IM uint32_t RESERVED1[56];
__IOM uint32_t NVIC_ISER; /*!< (@ 0x0000E100) Use the Interrupt Set-Enable Register to enable
interrupts and determine which interrupts
are currently enabled.
If a pending interrupt is enabled, the NVIC
activates the interrupt based on its priority.
If an interrupt is not enabled, asserting
its interrupt signal changes the interrupt
state to pending, but the NVIC never activates
the interrupt, regardless of its priority. */
__IM uint32_t RESERVED2[31];
__IOM uint32_t NVIC_ICER; /*!< (@ 0x0000E180) Use the Interrupt Clear-Enable Registers to disable
interrupts and determine which interrupts
are currently enabled. */
__IM uint32_t RESERVED3[31];
__IOM uint32_t NVIC_ISPR; /*!< (@ 0x0000E200) The NVIC_ISPR forces interrupts into the pending
state, and shows which interrupts are pending. */
__IM uint32_t RESERVED4[31];
__IOM uint32_t NVIC_ICPR; /*!< (@ 0x0000E280) Use the Interrupt Clear-Pending Register to clear
pending interrupts and determine which interrupts
are currently pending. */
__IM uint32_t RESERVED5[95];
__IOM uint32_t NVIC_IPR0; /*!< (@ 0x0000E400) Use the Interrupt Priority Registers to assign
a priority from 0 to 3 to each of the available
interrupts. 0 is the highest priority, and
3 is the lowest.
Note: Writing 1 to an NVIC_ICPR bit does
not affect the active state of the corresponding
interrupt.
These registers are only word-accessible */
__IOM uint32_t NVIC_IPR1; /*!< (@ 0x0000E404) Use the Interrupt Priority Registers to assign
a priority from 0 to 3 to each of the available
interrupts. 0 is the highest priority, and
3 is the lowest. */
__IOM uint32_t NVIC_IPR2; /*!< (@ 0x0000E408) Use the Interrupt Priority Registers to assign
a priority from 0 to 3 to each of the available
interrupts. 0 is the highest priority, and
3 is the lowest. */
__IOM uint32_t NVIC_IPR3; /*!< (@ 0x0000E40C) Use the Interrupt Priority Registers to assign
a priority from 0 to 3 to each of the available
interrupts. 0 is the highest priority, and
3 is the lowest. */
__IOM uint32_t NVIC_IPR4; /*!< (@ 0x0000E410) Use the Interrupt Priority Registers to assign
a priority from 0 to 3 to each of the available
interrupts. 0 is the highest priority, and
3 is the lowest. */
__IOM uint32_t NVIC_IPR5; /*!< (@ 0x0000E414) Use the Interrupt Priority Registers to assign
a priority from 0 to 3 to each of the available
interrupts. 0 is the highest priority, and
3 is the lowest. */
__IOM uint32_t NVIC_IPR6; /*!< (@ 0x0000E418) Use the Interrupt Priority Registers to assign
a priority from 0 to 3 to each of the available
interrupts. 0 is the highest priority, and
3 is the lowest. */
__IOM uint32_t NVIC_IPR7; /*!< (@ 0x0000E41C) Use the Interrupt Priority Registers to assign
a priority from 0 to 3 to each of the available
interrupts. 0 is the highest priority, and
3 is the lowest. */
__IM uint32_t RESERVED6[568];
__IOM uint32_t CPUID; /*!< (@ 0x0000ED00) Read the CPU ID Base Register to determine: the
ID number of the processor core, the version
number of the processor core, the implementation
details of the processor core. */
__IOM uint32_t ICSR; /*!< (@ 0x0000ED04) Use the Interrupt Control State Register to set
a pending Non-Maskable Interrupt (NMI),
set or clear a pending PendSV, set or clear
a pending SysTick, check for pending exceptions,
check the vector number of the highest priority
pended exception, check the vector number
of the active exception. */
__IOM uint32_t VTOR; /*!< (@ 0x0000ED08) The VTOR holds the vector table offset address. */
__IOM uint32_t AIRCR; /*!< (@ 0x0000ED0C) Use the Application Interrupt and Reset Control
Register to: determine data endianness,
clear all active state information from
debug halt mode, request a system reset. */
__IOM uint32_t SCR; /*!< (@ 0x0000ED10) System Control Register. Use the System Control
Register for power-management functions:
signal to the system when the processor
can enter a low power state, control how
the processor enters and exits low power
states. */
__IOM uint32_t CCR; /*!< (@ 0x0000ED14) The Configuration and Control Register permanently
enables stack alignment and causes unaligned
accesses to result in a Hard Fault. */
__IM uint32_t RESERVED7;
__IOM uint32_t SHPR2; /*!< (@ 0x0000ED1C) System handlers are a special class of exception
handler that can have their priority set
to any of the priority levels. Use the System
Handler Priority Register 2 to set the priority
of SVCall. */
__IOM uint32_t SHPR3; /*!< (@ 0x0000ED20) System handlers are a special class of exception
handler that can have their priority set
to any of the priority levels. Use the System
Handler Priority Register 3 to set the priority
of PendSV and SysTick. */
__IOM uint32_t SHCSR; /*!< (@ 0x0000ED24) Use the System Handler Control and State Register
to determine or clear the pending status
of SVCall. */
__IM uint32_t RESERVED8[26];
__IOM uint32_t MPU_TYPE; /*!< (@ 0x0000ED90) Read the MPU Type Register to determine if the
processor implements an MPU, and how many
regions the MPU supports. */
__IOM uint32_t MPU_CTRL; /*!< (@ 0x0000ED94) Use the MPU Control Register to enable and disable
the MPU, and to control whether the default
memory map is enabled as a background region
for privileged accesses, and whether the
MPU is enabled for HardFaults and NMIs. */
__IOM uint32_t MPU_RNR; /*!< (@ 0x0000ED98) Use the MPU Region Number Register to select
the region currently accessed by MPU_RBAR
and MPU_RASR. */
__IOM uint32_t MPU_RBAR; /*!< (@ 0x0000ED9C) Read the MPU Region Base Address Register to
determine the base address of the region
identified by MPU_RNR. Write to update the
base address of said region or that of a
specified region, with whose number MPU_RNR
will also be updated. */
__IOM uint32_t MPU_RASR; /*!< (@ 0x0000EDA0) Use the MPU Region Attribute and Size Register
to define the size, access behaviour and
memory type of the region identified by
MPU_RNR, and enable that region. */
} PPB_Type; /*!< Size = 60836 (0xeda4) */
/** @} */ /* End of group Device_Peripheral_peripherals */
/* =========================================================================================================================== */
/* ================ Device Specific Peripheral Address Map ================ */
/* =========================================================================================================================== */
/** @addtogroup Device_Peripheral_peripheralAddr
* @{
*/
#define XIP_CTRL_BASE 0x14000000UL
#define XIP_SSI_BASE 0x18000000UL
#define SYSINFO_BASE 0x40000000UL
#define SYSCFG_BASE 0x40004000UL
#define CLOCKS_BASE 0x40008000UL
#define RESETS_BASE 0x4000C000UL
#define PSM_BASE 0x40010000UL
#define IO_BANK0_BASE 0x40014000UL
#define IO_QSPI_BASE 0x40018000UL
#define PADS_BANK0_BASE 0x4001C000UL
#define PADS_QSPI_BASE 0x40020000UL
#define XOSC_BASE 0x40024000UL
#define PLL_SYS_BASE 0x40028000UL
#define PLL_USB_BASE 0x4002C000UL
#define BUSCTRL_BASE 0x40030000UL
#define UART0_BASE 0x40034000UL
#define UART1_BASE 0x40038000UL
#define SPI0_BASE 0x4003C000UL
#define SPI1_BASE 0x40040000UL
#define I2C0_BASE 0x40044000UL
#define I2C1_BASE 0x40048000UL
#define ADC_BASE 0x4004C000UL
#define PWM_BASE 0x40050000UL
#define TIMER_BASE 0x40054000UL
#define WATCHDOG_BASE 0x40058000UL
#define RTC_BASE 0x4005C000UL
#define ROSC_BASE 0x40060000UL
#define VREG_AND_CHIP_RESET_BASE 0x40064000UL
#define TBMAN_BASE 0x4006C000UL
#define DMA_BASE 0x50000000UL
#define USBCTRL_DPRAM_BASE 0x50100000UL
#define USBCTRL_REGS_BASE 0x50110000UL
#define PIO0_BASE 0x50200000UL
#define PIO1_BASE 0x50300000UL
#define SIO_BASE 0xD0000000UL
#define PPB_BASE 0xE0000000UL
/** @} */ /* End of group Device_Peripheral_peripheralAddr */
/* =========================================================================================================================== */
/* ================ Peripheral declaration ================ */
/* =========================================================================================================================== */
/** @addtogroup Device_Peripheral_declaration
* @{
*/
#define XIP_CTRL ((XIP_CTRL_Type*) XIP_CTRL_BASE)
#define XIP_SSI ((XIP_SSI_Type*) XIP_SSI_BASE)
#define SYSINFO ((SYSINFO_Type*) SYSINFO_BASE)
#define SYSCFG ((SYSCFG_Type*) SYSCFG_BASE)
#define CLOCKS ((CLOCKS_Type*) CLOCKS_BASE)
#define RESETS ((RESETS_Type*) RESETS_BASE)
#define PSM ((PSM_Type*) PSM_BASE)
#define IO_BANK0 ((IO_BANK0_Type*) IO_BANK0_BASE)
#define IO_QSPI ((IO_QSPI_Type*) IO_QSPI_BASE)
#define PADS_BANK0 ((PADS_BANK0_Type*) PADS_BANK0_BASE)
#define PADS_QSPI ((PADS_QSPI_Type*) PADS_QSPI_BASE)
#define XOSC ((XOSC_Type*) XOSC_BASE)
#define PLL_SYS ((PLL_SYS_Type*) PLL_SYS_BASE)
#define PLL_USB ((PLL_SYS_Type*) PLL_USB_BASE)
#define BUSCTRL ((BUSCTRL_Type*) BUSCTRL_BASE)
#define UART0 ((UART0_Type*) UART0_BASE)
#define UART1 ((UART0_Type*) UART1_BASE)
#define SPI0 ((SPI0_Type*) SPI0_BASE)
#define SPI1 ((SPI0_Type*) SPI1_BASE)
#define I2C0 ((I2C0_Type*) I2C0_BASE)
#define I2C1 ((I2C0_Type*) I2C1_BASE)
#define ADC ((ADC_Type*) ADC_BASE)
#define PWM ((PWM_Type*) PWM_BASE)
#define TIMER ((TIMER_Type*) TIMER_BASE)
#define WATCHDOG ((WATCHDOG_Type*) WATCHDOG_BASE)
#define RTC ((RTC_Type*) RTC_BASE)
#define ROSC ((ROSC_Type*) ROSC_BASE)
#define VREG_AND_CHIP_RESET ((VREG_AND_CHIP_RESET_Type*) VREG_AND_CHIP_RESET_BASE)
#define TBMAN ((TBMAN_Type*) TBMAN_BASE)
#define DMA ((DMA_Type*) DMA_BASE)
#define USBCTRL_DPRAM ((USBCTRL_DPRAM_Type*) USBCTRL_DPRAM_BASE)
#define USBCTRL_REGS ((USBCTRL_REGS_Type*) USBCTRL_REGS_BASE)
#define PIO0 ((PIO0_Type*) PIO0_BASE)
#define PIO1 ((PIO0_Type*) PIO1_BASE)
#define SIO ((SIO_Type*) SIO_BASE)
#define PPB ((PPB_Type*) PPB_BASE)
/** @} */ /* End of group Device_Peripheral_declaration */
/* =========================================================================================================================== */
/* ================ Pos/Mask Peripheral Section ================ */
/* =========================================================================================================================== */
/** @addtogroup PosMask_peripherals
* @{
*/
/* =========================================================================================================================== */
/* ================ XIP_CTRL ================ */
/* =========================================================================================================================== */
/* ========================================================= CTRL ========================================================== */
#define XIP_CTRL_CTRL_POWER_DOWN_Pos (3UL) /*!< POWER_DOWN (Bit 3) */
#define XIP_CTRL_CTRL_POWER_DOWN_Msk (0x8UL) /*!< POWER_DOWN (Bitfield-Mask: 0x01) */
#define XIP_CTRL_CTRL_ERR_BADWRITE_Pos (1UL) /*!< ERR_BADWRITE (Bit 1) */
#define XIP_CTRL_CTRL_ERR_BADWRITE_Msk (0x2UL) /*!< ERR_BADWRITE (Bitfield-Mask: 0x01) */
#define XIP_CTRL_CTRL_EN_Pos (0UL) /*!< EN (Bit 0) */
#define XIP_CTRL_CTRL_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */
/* ========================================================= FLUSH ========================================================= */
#define XIP_CTRL_FLUSH_FLUSH_Pos (0UL) /*!< FLUSH (Bit 0) */
#define XIP_CTRL_FLUSH_FLUSH_Msk (0x1UL) /*!< FLUSH (Bitfield-Mask: 0x01) */
/* ========================================================= STAT ========================================================== */
#define XIP_CTRL_STAT_FIFO_FULL_Pos (2UL) /*!< FIFO_FULL (Bit 2) */
#define XIP_CTRL_STAT_FIFO_FULL_Msk (0x4UL) /*!< FIFO_FULL (Bitfield-Mask: 0x01) */
#define XIP_CTRL_STAT_FIFO_EMPTY_Pos (1UL) /*!< FIFO_EMPTY (Bit 1) */
#define XIP_CTRL_STAT_FIFO_EMPTY_Msk (0x2UL) /*!< FIFO_EMPTY (Bitfield-Mask: 0x01) */
#define XIP_CTRL_STAT_FLUSH_READY_Pos (0UL) /*!< FLUSH_READY (Bit 0) */
#define XIP_CTRL_STAT_FLUSH_READY_Msk (0x1UL) /*!< FLUSH_READY (Bitfield-Mask: 0x01) */
/* ======================================================== CTR_HIT ======================================================== */
/* ======================================================== CTR_ACC ======================================================== */
/* ====================================================== STREAM_ADDR ====================================================== */
#define XIP_CTRL_STREAM_ADDR_STREAM_ADDR_Pos (2UL) /*!< STREAM_ADDR (Bit 2) */
#define XIP_CTRL_STREAM_ADDR_STREAM_ADDR_Msk (0xfffffffcUL) /*!< STREAM_ADDR (Bitfield-Mask: 0x3fffffff) */
/* ====================================================== STREAM_CTR ======================================================= */
#define XIP_CTRL_STREAM_CTR_STREAM_CTR_Pos (0UL) /*!< STREAM_CTR (Bit 0) */
#define XIP_CTRL_STREAM_CTR_STREAM_CTR_Msk (0x3fffffUL) /*!< STREAM_CTR (Bitfield-Mask: 0x3fffff) */
/* ====================================================== STREAM_FIFO ====================================================== */
/* =========================================================================================================================== */
/* ================ XIP_SSI ================ */
/* =========================================================================================================================== */
/* ======================================================== CTRLR0 ========================================================= */
#define XIP_SSI_CTRLR0_SSTE_Pos (24UL) /*!< SSTE (Bit 24) */
#define XIP_SSI_CTRLR0_SSTE_Msk (0x1000000UL) /*!< SSTE (Bitfield-Mask: 0x01) */
#define XIP_SSI_CTRLR0_SPI_FRF_Pos (21UL) /*!< SPI_FRF (Bit 21) */
#define XIP_SSI_CTRLR0_SPI_FRF_Msk (0x600000UL) /*!< SPI_FRF (Bitfield-Mask: 0x03) */
#define XIP_SSI_CTRLR0_DFS_32_Pos (16UL) /*!< DFS_32 (Bit 16) */
#define XIP_SSI_CTRLR0_DFS_32_Msk (0x1f0000UL) /*!< DFS_32 (Bitfield-Mask: 0x1f) */
#define XIP_SSI_CTRLR0_CFS_Pos (12UL) /*!< CFS (Bit 12) */
#define XIP_SSI_CTRLR0_CFS_Msk (0xf000UL) /*!< CFS (Bitfield-Mask: 0x0f) */
#define XIP_SSI_CTRLR0_SRL_Pos (11UL) /*!< SRL (Bit 11) */
#define XIP_SSI_CTRLR0_SRL_Msk (0x800UL) /*!< SRL (Bitfield-Mask: 0x01) */
#define XIP_SSI_CTRLR0_SLV_OE_Pos (10UL) /*!< SLV_OE (Bit 10) */
#define XIP_SSI_CTRLR0_SLV_OE_Msk (0x400UL) /*!< SLV_OE (Bitfield-Mask: 0x01) */
#define XIP_SSI_CTRLR0_TMOD_Pos (8UL) /*!< TMOD (Bit 8) */
#define XIP_SSI_CTRLR0_TMOD_Msk (0x300UL) /*!< TMOD (Bitfield-Mask: 0x03) */
#define XIP_SSI_CTRLR0_SCPOL_Pos (7UL) /*!< SCPOL (Bit 7) */
#define XIP_SSI_CTRLR0_SCPOL_Msk (0x80UL) /*!< SCPOL (Bitfield-Mask: 0x01) */
#define XIP_SSI_CTRLR0_SCPH_Pos (6UL) /*!< SCPH (Bit 6) */
#define XIP_SSI_CTRLR0_SCPH_Msk (0x40UL) /*!< SCPH (Bitfield-Mask: 0x01) */
#define XIP_SSI_CTRLR0_FRF_Pos (4UL) /*!< FRF (Bit 4) */
#define XIP_SSI_CTRLR0_FRF_Msk (0x30UL) /*!< FRF (Bitfield-Mask: 0x03) */
#define XIP_SSI_CTRLR0_DFS_Pos (0UL) /*!< DFS (Bit 0) */
#define XIP_SSI_CTRLR0_DFS_Msk (0xfUL) /*!< DFS (Bitfield-Mask: 0x0f) */
/* ======================================================== CTRLR1 ========================================================= */
#define XIP_SSI_CTRLR1_NDF_Pos (0UL) /*!< NDF (Bit 0) */
#define XIP_SSI_CTRLR1_NDF_Msk (0xffffUL) /*!< NDF (Bitfield-Mask: 0xffff) */
/* ======================================================== SSIENR ========================================================= */
#define XIP_SSI_SSIENR_SSI_EN_Pos (0UL) /*!< SSI_EN (Bit 0) */
#define XIP_SSI_SSIENR_SSI_EN_Msk (0x1UL) /*!< SSI_EN (Bitfield-Mask: 0x01) */
/* ========================================================= MWCR ========================================================== */
#define XIP_SSI_MWCR_MHS_Pos (2UL) /*!< MHS (Bit 2) */
#define XIP_SSI_MWCR_MHS_Msk (0x4UL) /*!< MHS (Bitfield-Mask: 0x01) */
#define XIP_SSI_MWCR_MDD_Pos (1UL) /*!< MDD (Bit 1) */
#define XIP_SSI_MWCR_MDD_Msk (0x2UL) /*!< MDD (Bitfield-Mask: 0x01) */
#define XIP_SSI_MWCR_MWMOD_Pos (0UL) /*!< MWMOD (Bit 0) */
#define XIP_SSI_MWCR_MWMOD_Msk (0x1UL) /*!< MWMOD (Bitfield-Mask: 0x01) */
/* ========================================================== SER ========================================================== */
#define XIP_SSI_SER_SER_Pos (0UL) /*!< SER (Bit 0) */
#define XIP_SSI_SER_SER_Msk (0x1UL) /*!< SER (Bitfield-Mask: 0x01) */
/* ========================================================= BAUDR ========================================================= */
#define XIP_SSI_BAUDR_SCKDV_Pos (0UL) /*!< SCKDV (Bit 0) */
#define XIP_SSI_BAUDR_SCKDV_Msk (0xffffUL) /*!< SCKDV (Bitfield-Mask: 0xffff) */
/* ======================================================== TXFTLR ========================================================= */
#define XIP_SSI_TXFTLR_TFT_Pos (0UL) /*!< TFT (Bit 0) */
#define XIP_SSI_TXFTLR_TFT_Msk (0xffUL) /*!< TFT (Bitfield-Mask: 0xff) */
/* ======================================================== RXFTLR ========================================================= */
#define XIP_SSI_RXFTLR_RFT_Pos (0UL) /*!< RFT (Bit 0) */
#define XIP_SSI_RXFTLR_RFT_Msk (0xffUL) /*!< RFT (Bitfield-Mask: 0xff) */
/* ========================================================= TXFLR ========================================================= */
#define XIP_SSI_TXFLR_TFTFL_Pos (0UL) /*!< TFTFL (Bit 0) */
#define XIP_SSI_TXFLR_TFTFL_Msk (0xffUL) /*!< TFTFL (Bitfield-Mask: 0xff) */
/* ========================================================= RXFLR ========================================================= */
#define XIP_SSI_RXFLR_RXTFL_Pos (0UL) /*!< RXTFL (Bit 0) */
#define XIP_SSI_RXFLR_RXTFL_Msk (0xffUL) /*!< RXTFL (Bitfield-Mask: 0xff) */
/* ========================================================== SR =========================================================== */
#define XIP_SSI_SR_DCOL_Pos (6UL) /*!< DCOL (Bit 6) */
#define XIP_SSI_SR_DCOL_Msk (0x40UL) /*!< DCOL (Bitfield-Mask: 0x01) */
#define XIP_SSI_SR_TXE_Pos (5UL) /*!< TXE (Bit 5) */
#define XIP_SSI_SR_TXE_Msk (0x20UL) /*!< TXE (Bitfield-Mask: 0x01) */
#define XIP_SSI_SR_RFF_Pos (4UL) /*!< RFF (Bit 4) */
#define XIP_SSI_SR_RFF_Msk (0x10UL) /*!< RFF (Bitfield-Mask: 0x01) */
#define XIP_SSI_SR_RFNE_Pos (3UL) /*!< RFNE (Bit 3) */
#define XIP_SSI_SR_RFNE_Msk (0x8UL) /*!< RFNE (Bitfield-Mask: 0x01) */
#define XIP_SSI_SR_TFE_Pos (2UL) /*!< TFE (Bit 2) */
#define XIP_SSI_SR_TFE_Msk (0x4UL) /*!< TFE (Bitfield-Mask: 0x01) */
#define XIP_SSI_SR_TFNF_Pos (1UL) /*!< TFNF (Bit 1) */
#define XIP_SSI_SR_TFNF_Msk (0x2UL) /*!< TFNF (Bitfield-Mask: 0x01) */
#define XIP_SSI_SR_BUSY_Pos (0UL) /*!< BUSY (Bit 0) */
#define XIP_SSI_SR_BUSY_Msk (0x1UL) /*!< BUSY (Bitfield-Mask: 0x01) */
/* ========================================================== IMR ========================================================== */
#define XIP_SSI_IMR_MSTIM_Pos (5UL) /*!< MSTIM (Bit 5) */
#define XIP_SSI_IMR_MSTIM_Msk (0x20UL) /*!< MSTIM (Bitfield-Mask: 0x01) */
#define XIP_SSI_IMR_RXFIM_Pos (4UL) /*!< RXFIM (Bit 4) */
#define XIP_SSI_IMR_RXFIM_Msk (0x10UL) /*!< RXFIM (Bitfield-Mask: 0x01) */
#define XIP_SSI_IMR_RXOIM_Pos (3UL) /*!< RXOIM (Bit 3) */
#define XIP_SSI_IMR_RXOIM_Msk (0x8UL) /*!< RXOIM (Bitfield-Mask: 0x01) */
#define XIP_SSI_IMR_RXUIM_Pos (2UL) /*!< RXUIM (Bit 2) */
#define XIP_SSI_IMR_RXUIM_Msk (0x4UL) /*!< RXUIM (Bitfield-Mask: 0x01) */
#define XIP_SSI_IMR_TXOIM_Pos (1UL) /*!< TXOIM (Bit 1) */
#define XIP_SSI_IMR_TXOIM_Msk (0x2UL) /*!< TXOIM (Bitfield-Mask: 0x01) */
#define XIP_SSI_IMR_TXEIM_Pos (0UL) /*!< TXEIM (Bit 0) */
#define XIP_SSI_IMR_TXEIM_Msk (0x1UL) /*!< TXEIM (Bitfield-Mask: 0x01) */
/* ========================================================== ISR ========================================================== */
#define XIP_SSI_ISR_MSTIS_Pos (5UL) /*!< MSTIS (Bit 5) */
#define XIP_SSI_ISR_MSTIS_Msk (0x20UL) /*!< MSTIS (Bitfield-Mask: 0x01) */
#define XIP_SSI_ISR_RXFIS_Pos (4UL) /*!< RXFIS (Bit 4) */
#define XIP_SSI_ISR_RXFIS_Msk (0x10UL) /*!< RXFIS (Bitfield-Mask: 0x01) */
#define XIP_SSI_ISR_RXOIS_Pos (3UL) /*!< RXOIS (Bit 3) */
#define XIP_SSI_ISR_RXOIS_Msk (0x8UL) /*!< RXOIS (Bitfield-Mask: 0x01) */
#define XIP_SSI_ISR_RXUIS_Pos (2UL) /*!< RXUIS (Bit 2) */
#define XIP_SSI_ISR_RXUIS_Msk (0x4UL) /*!< RXUIS (Bitfield-Mask: 0x01) */
#define XIP_SSI_ISR_TXOIS_Pos (1UL) /*!< TXOIS (Bit 1) */
#define XIP_SSI_ISR_TXOIS_Msk (0x2UL) /*!< TXOIS (Bitfield-Mask: 0x01) */
#define XIP_SSI_ISR_TXEIS_Pos (0UL) /*!< TXEIS (Bit 0) */
#define XIP_SSI_ISR_TXEIS_Msk (0x1UL) /*!< TXEIS (Bitfield-Mask: 0x01) */
/* ========================================================= RISR ========================================================== */
#define XIP_SSI_RISR_MSTIR_Pos (5UL) /*!< MSTIR (Bit 5) */
#define XIP_SSI_RISR_MSTIR_Msk (0x20UL) /*!< MSTIR (Bitfield-Mask: 0x01) */
#define XIP_SSI_RISR_RXFIR_Pos (4UL) /*!< RXFIR (Bit 4) */
#define XIP_SSI_RISR_RXFIR_Msk (0x10UL) /*!< RXFIR (Bitfield-Mask: 0x01) */
#define XIP_SSI_RISR_RXOIR_Pos (3UL) /*!< RXOIR (Bit 3) */
#define XIP_SSI_RISR_RXOIR_Msk (0x8UL) /*!< RXOIR (Bitfield-Mask: 0x01) */
#define XIP_SSI_RISR_RXUIR_Pos (2UL) /*!< RXUIR (Bit 2) */
#define XIP_SSI_RISR_RXUIR_Msk (0x4UL) /*!< RXUIR (Bitfield-Mask: 0x01) */
#define XIP_SSI_RISR_TXOIR_Pos (1UL) /*!< TXOIR (Bit 1) */
#define XIP_SSI_RISR_TXOIR_Msk (0x2UL) /*!< TXOIR (Bitfield-Mask: 0x01) */
#define XIP_SSI_RISR_TXEIR_Pos (0UL) /*!< TXEIR (Bit 0) */
#define XIP_SSI_RISR_TXEIR_Msk (0x1UL) /*!< TXEIR (Bitfield-Mask: 0x01) */
/* ======================================================== TXOICR ========================================================= */
#define XIP_SSI_TXOICR_TXOICR_Pos (0UL) /*!< TXOICR (Bit 0) */
#define XIP_SSI_TXOICR_TXOICR_Msk (0x1UL) /*!< TXOICR (Bitfield-Mask: 0x01) */
/* ======================================================== RXOICR ========================================================= */
#define XIP_SSI_RXOICR_RXOICR_Pos (0UL) /*!< RXOICR (Bit 0) */
#define XIP_SSI_RXOICR_RXOICR_Msk (0x1UL) /*!< RXOICR (Bitfield-Mask: 0x01) */
/* ======================================================== RXUICR ========================================================= */
#define XIP_SSI_RXUICR_RXUICR_Pos (0UL) /*!< RXUICR (Bit 0) */
#define XIP_SSI_RXUICR_RXUICR_Msk (0x1UL) /*!< RXUICR (Bitfield-Mask: 0x01) */
/* ======================================================== MSTICR ========================================================= */
#define XIP_SSI_MSTICR_MSTICR_Pos (0UL) /*!< MSTICR (Bit 0) */
#define XIP_SSI_MSTICR_MSTICR_Msk (0x1UL) /*!< MSTICR (Bitfield-Mask: 0x01) */
/* ========================================================== ICR ========================================================== */
#define XIP_SSI_ICR_ICR_Pos (0UL) /*!< ICR (Bit 0) */
#define XIP_SSI_ICR_ICR_Msk (0x1UL) /*!< ICR (Bitfield-Mask: 0x01) */
/* ========================================================= DMACR ========================================================= */
#define XIP_SSI_DMACR_TDMAE_Pos (1UL) /*!< TDMAE (Bit 1) */
#define XIP_SSI_DMACR_TDMAE_Msk (0x2UL) /*!< TDMAE (Bitfield-Mask: 0x01) */
#define XIP_SSI_DMACR_RDMAE_Pos (0UL) /*!< RDMAE (Bit 0) */
#define XIP_SSI_DMACR_RDMAE_Msk (0x1UL) /*!< RDMAE (Bitfield-Mask: 0x01) */
/* ======================================================== DMATDLR ======================================================== */
#define XIP_SSI_DMATDLR_DMATDL_Pos (0UL) /*!< DMATDL (Bit 0) */
#define XIP_SSI_DMATDLR_DMATDL_Msk (0xffUL) /*!< DMATDL (Bitfield-Mask: 0xff) */
/* ======================================================== DMARDLR ======================================================== */
#define XIP_SSI_DMARDLR_DMARDL_Pos (0UL) /*!< DMARDL (Bit 0) */
#define XIP_SSI_DMARDLR_DMARDL_Msk (0xffUL) /*!< DMARDL (Bitfield-Mask: 0xff) */
/* ========================================================== IDR ========================================================== */
#define XIP_SSI_IDR_IDCODE_Pos (0UL) /*!< IDCODE (Bit 0) */
#define XIP_SSI_IDR_IDCODE_Msk (0xffffffffUL) /*!< IDCODE (Bitfield-Mask: 0xffffffff) */
/* ==================================================== SSI_VERSION_ID ===================================================== */
#define XIP_SSI_SSI_VERSION_ID_SSI_COMP_VERSION_Pos (0UL) /*!< SSI_COMP_VERSION (Bit 0) */
#define XIP_SSI_SSI_VERSION_ID_SSI_COMP_VERSION_Msk (0xffffffffUL) /*!< SSI_COMP_VERSION (Bitfield-Mask: 0xffffffff) */
/* ========================================================== DR0 ========================================================== */
#define XIP_SSI_DR0_DR_Pos (0UL) /*!< DR (Bit 0) */
#define XIP_SSI_DR0_DR_Msk (0xffffffffUL) /*!< DR (Bitfield-Mask: 0xffffffff) */
/* ===================================================== RX_SAMPLE_DLY ===================================================== */
#define XIP_SSI_RX_SAMPLE_DLY_RSD_Pos (0UL) /*!< RSD (Bit 0) */
#define XIP_SSI_RX_SAMPLE_DLY_RSD_Msk (0xffUL) /*!< RSD (Bitfield-Mask: 0xff) */
/* ====================================================== SPI_CTRLR0 ======================================================= */
#define XIP_SSI_SPI_CTRLR0_XIP_CMD_Pos (24UL) /*!< XIP_CMD (Bit 24) */
#define XIP_SSI_SPI_CTRLR0_XIP_CMD_Msk (0xff000000UL) /*!< XIP_CMD (Bitfield-Mask: 0xff) */
#define XIP_SSI_SPI_CTRLR0_SPI_RXDS_EN_Pos (18UL) /*!< SPI_RXDS_EN (Bit 18) */
#define XIP_SSI_SPI_CTRLR0_SPI_RXDS_EN_Msk (0x40000UL) /*!< SPI_RXDS_EN (Bitfield-Mask: 0x01) */
#define XIP_SSI_SPI_CTRLR0_INST_DDR_EN_Pos (17UL) /*!< INST_DDR_EN (Bit 17) */
#define XIP_SSI_SPI_CTRLR0_INST_DDR_EN_Msk (0x20000UL) /*!< INST_DDR_EN (Bitfield-Mask: 0x01) */
#define XIP_SSI_SPI_CTRLR0_SPI_DDR_EN_Pos (16UL) /*!< SPI_DDR_EN (Bit 16) */
#define XIP_SSI_SPI_CTRLR0_SPI_DDR_EN_Msk (0x10000UL) /*!< SPI_DDR_EN (Bitfield-Mask: 0x01) */
#define XIP_SSI_SPI_CTRLR0_WAIT_CYCLES_Pos (11UL) /*!< WAIT_CYCLES (Bit 11) */
#define XIP_SSI_SPI_CTRLR0_WAIT_CYCLES_Msk (0xf800UL) /*!< WAIT_CYCLES (Bitfield-Mask: 0x1f) */
#define XIP_SSI_SPI_CTRLR0_INST_L_Pos (8UL) /*!< INST_L (Bit 8) */
#define XIP_SSI_SPI_CTRLR0_INST_L_Msk (0x300UL) /*!< INST_L (Bitfield-Mask: 0x03) */
#define XIP_SSI_SPI_CTRLR0_ADDR_L_Pos (2UL) /*!< ADDR_L (Bit 2) */
#define XIP_SSI_SPI_CTRLR0_ADDR_L_Msk (0x3cUL) /*!< ADDR_L (Bitfield-Mask: 0x0f) */
#define XIP_SSI_SPI_CTRLR0_TRANS_TYPE_Pos (0UL) /*!< TRANS_TYPE (Bit 0) */
#define XIP_SSI_SPI_CTRLR0_TRANS_TYPE_Msk (0x3UL) /*!< TRANS_TYPE (Bitfield-Mask: 0x03) */
/* ==================================================== TXD_DRIVE_EDGE ===================================================== */
#define XIP_SSI_TXD_DRIVE_EDGE_TDE_Pos (0UL) /*!< TDE (Bit 0) */
#define XIP_SSI_TXD_DRIVE_EDGE_TDE_Msk (0xffUL) /*!< TDE (Bitfield-Mask: 0xff) */
/* =========================================================================================================================== */
/* ================ SYSINFO ================ */
/* =========================================================================================================================== */
/* ======================================================== CHIP_ID ======================================================== */
#define SYSINFO_CHIP_ID_REVISION_Pos (28UL) /*!< REVISION (Bit 28) */
#define SYSINFO_CHIP_ID_REVISION_Msk (0xf0000000UL) /*!< REVISION (Bitfield-Mask: 0x0f) */
#define SYSINFO_CHIP_ID_PART_Pos (12UL) /*!< PART (Bit 12) */
#define SYSINFO_CHIP_ID_PART_Msk (0xffff000UL) /*!< PART (Bitfield-Mask: 0xffff) */
#define SYSINFO_CHIP_ID_MANUFACTURER_Pos (0UL) /*!< MANUFACTURER (Bit 0) */
#define SYSINFO_CHIP_ID_MANUFACTURER_Msk (0xfffUL) /*!< MANUFACTURER (Bitfield-Mask: 0xfff) */
/* ======================================================= PLATFORM ======================================================== */
#define SYSINFO_PLATFORM_ASIC_Pos (1UL) /*!< ASIC (Bit 1) */
#define SYSINFO_PLATFORM_ASIC_Msk (0x2UL) /*!< ASIC (Bitfield-Mask: 0x01) */
#define SYSINFO_PLATFORM_FPGA_Pos (0UL) /*!< FPGA (Bit 0) */
#define SYSINFO_PLATFORM_FPGA_Msk (0x1UL) /*!< FPGA (Bitfield-Mask: 0x01) */
/* ===================================================== GITREF_RP2040 ===================================================== */
/* =========================================================================================================================== */
/* ================ SYSCFG ================ */
/* =========================================================================================================================== */
/* ==================================================== PROC0_NMI_MASK ===================================================== */
/* ==================================================== PROC1_NMI_MASK ===================================================== */
/* ====================================================== PROC_CONFIG ====================================================== */
#define SYSCFG_PROC_CONFIG_PROC1_DAP_INSTID_Pos (28UL) /*!< PROC1_DAP_INSTID (Bit 28) */
#define SYSCFG_PROC_CONFIG_PROC1_DAP_INSTID_Msk (0xf0000000UL) /*!< PROC1_DAP_INSTID (Bitfield-Mask: 0x0f) */
#define SYSCFG_PROC_CONFIG_PROC0_DAP_INSTID_Pos (24UL) /*!< PROC0_DAP_INSTID (Bit 24) */
#define SYSCFG_PROC_CONFIG_PROC0_DAP_INSTID_Msk (0xf000000UL) /*!< PROC0_DAP_INSTID (Bitfield-Mask: 0x0f) */
#define SYSCFG_PROC_CONFIG_PROC1_HALTED_Pos (1UL) /*!< PROC1_HALTED (Bit 1) */
#define SYSCFG_PROC_CONFIG_PROC1_HALTED_Msk (0x2UL) /*!< PROC1_HALTED (Bitfield-Mask: 0x01) */
#define SYSCFG_PROC_CONFIG_PROC0_HALTED_Pos (0UL) /*!< PROC0_HALTED (Bit 0) */
#define SYSCFG_PROC_CONFIG_PROC0_HALTED_Msk (0x1UL) /*!< PROC0_HALTED (Bitfield-Mask: 0x01) */
/* ================================================== PROC_IN_SYNC_BYPASS ================================================== */
#define SYSCFG_PROC_IN_SYNC_BYPASS_PROC_IN_SYNC_BYPASS_Pos (0UL) /*!< PROC_IN_SYNC_BYPASS (Bit 0) */
#define SYSCFG_PROC_IN_SYNC_BYPASS_PROC_IN_SYNC_BYPASS_Msk (0x3fffffffUL) /*!< PROC_IN_SYNC_BYPASS (Bitfield-Mask: 0x3fffffff) */
/* ================================================ PROC_IN_SYNC_BYPASS_HI ================================================= */
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_PROC_IN_SYNC_BYPASS_HI_Pos (0UL) /*!< PROC_IN_SYNC_BYPASS_HI (Bit 0) */
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_PROC_IN_SYNC_BYPASS_HI_Msk (0x3fUL) /*!< PROC_IN_SYNC_BYPASS_HI (Bitfield-Mask: 0x3f) */
/* ======================================================= DBGFORCE ======================================================== */
#define SYSCFG_DBGFORCE_PROC1_ATTACH_Pos (7UL) /*!< PROC1_ATTACH (Bit 7) */
#define SYSCFG_DBGFORCE_PROC1_ATTACH_Msk (0x80UL) /*!< PROC1_ATTACH (Bitfield-Mask: 0x01) */
#define SYSCFG_DBGFORCE_PROC1_SWCLK_Pos (6UL) /*!< PROC1_SWCLK (Bit 6) */
#define SYSCFG_DBGFORCE_PROC1_SWCLK_Msk (0x40UL) /*!< PROC1_SWCLK (Bitfield-Mask: 0x01) */
#define SYSCFG_DBGFORCE_PROC1_SWDI_Pos (5UL) /*!< PROC1_SWDI (Bit 5) */
#define SYSCFG_DBGFORCE_PROC1_SWDI_Msk (0x20UL) /*!< PROC1_SWDI (Bitfield-Mask: 0x01) */
#define SYSCFG_DBGFORCE_PROC1_SWDO_Pos (4UL) /*!< PROC1_SWDO (Bit 4) */
#define SYSCFG_DBGFORCE_PROC1_SWDO_Msk (0x10UL) /*!< PROC1_SWDO (Bitfield-Mask: 0x01) */
#define SYSCFG_DBGFORCE_PROC0_ATTACH_Pos (3UL) /*!< PROC0_ATTACH (Bit 3) */
#define SYSCFG_DBGFORCE_PROC0_ATTACH_Msk (0x8UL) /*!< PROC0_ATTACH (Bitfield-Mask: 0x01) */
#define SYSCFG_DBGFORCE_PROC0_SWCLK_Pos (2UL) /*!< PROC0_SWCLK (Bit 2) */
#define SYSCFG_DBGFORCE_PROC0_SWCLK_Msk (0x4UL) /*!< PROC0_SWCLK (Bitfield-Mask: 0x01) */
#define SYSCFG_DBGFORCE_PROC0_SWDI_Pos (1UL) /*!< PROC0_SWDI (Bit 1) */
#define SYSCFG_DBGFORCE_PROC0_SWDI_Msk (0x2UL) /*!< PROC0_SWDI (Bitfield-Mask: 0x01) */
#define SYSCFG_DBGFORCE_PROC0_SWDO_Pos (0UL) /*!< PROC0_SWDO (Bit 0) */
#define SYSCFG_DBGFORCE_PROC0_SWDO_Msk (0x1UL) /*!< PROC0_SWDO (Bitfield-Mask: 0x01) */
/* ===================================================== MEMPOWERDOWN ====================================================== */
#define SYSCFG_MEMPOWERDOWN_ROM_Pos (7UL) /*!< ROM (Bit 7) */
#define SYSCFG_MEMPOWERDOWN_ROM_Msk (0x80UL) /*!< ROM (Bitfield-Mask: 0x01) */
#define SYSCFG_MEMPOWERDOWN_USB_Pos (6UL) /*!< USB (Bit 6) */
#define SYSCFG_MEMPOWERDOWN_USB_Msk (0x40UL) /*!< USB (Bitfield-Mask: 0x01) */
#define SYSCFG_MEMPOWERDOWN_SRAM5_Pos (5UL) /*!< SRAM5 (Bit 5) */
#define SYSCFG_MEMPOWERDOWN_SRAM5_Msk (0x20UL) /*!< SRAM5 (Bitfield-Mask: 0x01) */
#define SYSCFG_MEMPOWERDOWN_SRAM4_Pos (4UL) /*!< SRAM4 (Bit 4) */
#define SYSCFG_MEMPOWERDOWN_SRAM4_Msk (0x10UL) /*!< SRAM4 (Bitfield-Mask: 0x01) */
#define SYSCFG_MEMPOWERDOWN_SRAM3_Pos (3UL) /*!< SRAM3 (Bit 3) */
#define SYSCFG_MEMPOWERDOWN_SRAM3_Msk (0x8UL) /*!< SRAM3 (Bitfield-Mask: 0x01) */
#define SYSCFG_MEMPOWERDOWN_SRAM2_Pos (2UL) /*!< SRAM2 (Bit 2) */
#define SYSCFG_MEMPOWERDOWN_SRAM2_Msk (0x4UL) /*!< SRAM2 (Bitfield-Mask: 0x01) */
#define SYSCFG_MEMPOWERDOWN_SRAM1_Pos (1UL) /*!< SRAM1 (Bit 1) */
#define SYSCFG_MEMPOWERDOWN_SRAM1_Msk (0x2UL) /*!< SRAM1 (Bitfield-Mask: 0x01) */
#define SYSCFG_MEMPOWERDOWN_SRAM0_Pos (0UL) /*!< SRAM0 (Bit 0) */
#define SYSCFG_MEMPOWERDOWN_SRAM0_Msk (0x1UL) /*!< SRAM0 (Bitfield-Mask: 0x01) */
/* =========================================================================================================================== */
/* ================ CLOCKS ================ */
/* =========================================================================================================================== */
/* ==================================================== CLK_GPOUT0_CTRL ==================================================== */
#define CLOCKS_CLK_GPOUT0_CTRL_NUDGE_Pos (20UL) /*!< NUDGE (Bit 20) */
#define CLOCKS_CLK_GPOUT0_CTRL_NUDGE_Msk (0x100000UL) /*!< NUDGE (Bitfield-Mask: 0x01) */
#define CLOCKS_CLK_GPOUT0_CTRL_PHASE_Pos (16UL) /*!< PHASE (Bit 16) */
#define CLOCKS_CLK_GPOUT0_CTRL_PHASE_Msk (0x30000UL) /*!< PHASE (Bitfield-Mask: 0x03) */
#define CLOCKS_CLK_GPOUT0_CTRL_DC50_Pos (12UL) /*!< DC50 (Bit 12) */
#define CLOCKS_CLK_GPOUT0_CTRL_DC50_Msk (0x1000UL) /*!< DC50 (Bitfield-Mask: 0x01) */
#define CLOCKS_CLK_GPOUT0_CTRL_ENABLE_Pos (11UL) /*!< ENABLE (Bit 11) */
#define CLOCKS_CLK_GPOUT0_CTRL_ENABLE_Msk (0x800UL) /*!< ENABLE (Bitfield-Mask: 0x01) */
#define CLOCKS_CLK_GPOUT0_CTRL_KILL_Pos (10UL) /*!< KILL (Bit 10) */
#define CLOCKS_CLK_GPOUT0_CTRL_KILL_Msk (0x400UL) /*!< KILL (Bitfield-Mask: 0x01) */
#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_Pos (5UL) /*!< AUXSRC (Bit 5) */
#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_Msk (0x1e0UL) /*!< AUXSRC (Bitfield-Mask: 0x0f) */
/* ==================================================== CLK_GPOUT0_DIV ===================================================== */
#define CLOCKS_CLK_GPOUT0_DIV_INT_Pos (8UL) /*!< INT (Bit 8) */
#define CLOCKS_CLK_GPOUT0_DIV_INT_Msk (0xffffff00UL) /*!< INT (Bitfield-Mask: 0xffffff) */
#define CLOCKS_CLK_GPOUT0_DIV_FRAC_Pos (0UL) /*!< FRAC (Bit 0) */
#define CLOCKS_CLK_GPOUT0_DIV_FRAC_Msk (0xffUL) /*!< FRAC (Bitfield-Mask: 0xff) */
/* ================================================== CLK_GPOUT0_SELECTED ================================================== */
/* ==================================================== CLK_GPOUT1_CTRL ==================================================== */
#define CLOCKS_CLK_GPOUT1_CTRL_NUDGE_Pos (20UL) /*!< NUDGE (Bit 20) */
#define CLOCKS_CLK_GPOUT1_CTRL_NUDGE_Msk (0x100000UL) /*!< NUDGE (Bitfield-Mask: 0x01) */
#define CLOCKS_CLK_GPOUT1_CTRL_PHASE_Pos (16UL) /*!< PHASE (Bit 16) */
#define CLOCKS_CLK_GPOUT1_CTRL_PHASE_Msk (0x30000UL) /*!< PHASE (Bitfield-Mask: 0x03) */
#define CLOCKS_CLK_GPOUT1_CTRL_DC50_Pos (12UL) /*!< DC50 (Bit 12) */
#define CLOCKS_CLK_GPOUT1_CTRL_DC50_Msk (0x1000UL) /*!< DC50 (Bitfield-Mask: 0x01) */
#define CLOCKS_CLK_GPOUT1_CTRL_ENABLE_Pos (11UL) /*!< ENABLE (Bit 11) */
#define CLOCKS_CLK_GPOUT1_CTRL_ENABLE_Msk (0x800UL) /*!< ENABLE (Bitfield-Mask: 0x01) */
#define CLOCKS_CLK_GPOUT1_CTRL_KILL_Pos (10UL) /*!< KILL (Bit 10) */
#define CLOCKS_CLK_GPOUT1_CTRL_KILL_Msk (0x400UL) /*!< KILL (Bitfield-Mask: 0x01) */
#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_Pos (5UL) /*!< AUXSRC (Bit 5) */
#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_Msk (0x1e0UL) /*!< AUXSRC (Bitfield-Mask: 0x0f) */
/* ==================================================== CLK_GPOUT1_DIV ===================================================== */
#define CLOCKS_CLK_GPOUT1_DIV_INT_Pos (8UL) /*!< INT (Bit 8) */
#define CLOCKS_CLK_GPOUT1_DIV_INT_Msk (0xffffff00UL) /*!< INT (Bitfield-Mask: 0xffffff) */
#define CLOCKS_CLK_GPOUT1_DIV_FRAC_Pos (0UL) /*!< FRAC (Bit 0) */
#define CLOCKS_CLK_GPOUT1_DIV_FRAC_Msk (0xffUL) /*!< FRAC (Bitfield-Mask: 0xff) */
/* ================================================== CLK_GPOUT1_SELECTED ================================================== */
/* ==================================================== CLK_GPOUT2_CTRL ==================================================== */
#define CLOCKS_CLK_GPOUT2_CTRL_NUDGE_Pos (20UL) /*!< NUDGE (Bit 20) */
#define CLOCKS_CLK_GPOUT2_CTRL_NUDGE_Msk (0x100000UL) /*!< NUDGE (Bitfield-Mask: 0x01) */
#define CLOCKS_CLK_GPOUT2_CTRL_PHASE_Pos (16UL) /*!< PHASE (Bit 16) */
#define CLOCKS_CLK_GPOUT2_CTRL_PHASE_Msk (0x30000UL) /*!< PHASE (Bitfield-Mask: 0x03) */
#define CLOCKS_CLK_GPOUT2_CTRL_DC50_Pos (12UL) /*!< DC50 (Bit 12) */
#define CLOCKS_CLK_GPOUT2_CTRL_DC50_Msk (0x1000UL) /*!< DC50 (Bitfield-Mask: 0x01) */
#define CLOCKS_CLK_GPOUT2_CTRL_ENABLE_Pos (11UL) /*!< ENABLE (Bit 11) */
#define CLOCKS_CLK_GPOUT2_CTRL_ENABLE_Msk (0x800UL) /*!< ENABLE (Bitfield-Mask: 0x01) */
#define CLOCKS_CLK_GPOUT2_CTRL_KILL_Pos (10UL) /*!< KILL (Bit 10) */
#define CLOCKS_CLK_GPOUT2_CTRL_KILL_Msk (0x400UL) /*!< KILL (Bitfield-Mask: 0x01) */
#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_Pos (5UL) /*!< AUXSRC (Bit 5) */
#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_Msk (0x1e0UL) /*!< AUXSRC (Bitfield-Mask: 0x0f) */
/* ==================================================== CLK_GPOUT2_DIV ===================================================== */
#define CLOCKS_CLK_GPOUT2_DIV_INT_Pos (8UL) /*!< INT (Bit 8) */
#define CLOCKS_CLK_GPOUT2_DIV_INT_Msk (0xffffff00UL) /*!< INT (Bitfield-Mask: 0xffffff) */
#define CLOCKS_CLK_GPOUT2_DIV_FRAC_Pos (0UL) /*!< FRAC (Bit 0) */
#define CLOCKS_CLK_GPOUT2_DIV_FRAC_Msk (0xffUL) /*!< FRAC (Bitfield-Mask: 0xff) */
/* ================================================== CLK_GPOUT2_SELECTED ================================================== */
/* ==================================================== CLK_GPOUT3_CTRL ==================================================== */
#define CLOCKS_CLK_GPOUT3_CTRL_NUDGE_Pos (20UL) /*!< NUDGE (Bit 20) */
#define CLOCKS_CLK_GPOUT3_CTRL_NUDGE_Msk (0x100000UL) /*!< NUDGE (Bitfield-Mask: 0x01) */
#define CLOCKS_CLK_GPOUT3_CTRL_PHASE_Pos (16UL) /*!< PHASE (Bit 16) */
#define CLOCKS_CLK_GPOUT3_CTRL_PHASE_Msk (0x30000UL) /*!< PHASE (Bitfield-Mask: 0x03) */
#define CLOCKS_CLK_GPOUT3_CTRL_DC50_Pos (12UL) /*!< DC50 (Bit 12) */
#define CLOCKS_CLK_GPOUT3_CTRL_DC50_Msk (0x1000UL) /*!< DC50 (Bitfield-Mask: 0x01) */
#define CLOCKS_CLK_GPOUT3_CTRL_ENABLE_Pos (11UL) /*!< ENABLE (Bit 11) */
#define CLOCKS_CLK_GPOUT3_CTRL_ENABLE_Msk (0x800UL) /*!< ENABLE (Bitfield-Mask: 0x01) */
#define CLOCKS_CLK_GPOUT3_CTRL_KILL_Pos (10UL) /*!< KILL (Bit 10) */
#define CLOCKS_CLK_GPOUT3_CTRL_KILL_Msk (0x400UL) /*!< KILL (Bitfield-Mask: 0x01) */
#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_Pos (5UL) /*!< AUXSRC (Bit 5) */
#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_Msk (0x1e0UL) /*!< AUXSRC (Bitfield-Mask: 0x0f) */
/* ==================================================== CLK_GPOUT3_DIV ===================================================== */
#define CLOCKS_CLK_GPOUT3_DIV_INT_Pos (8UL) /*!< INT (Bit 8) */
#define CLOCKS_CLK_GPOUT3_DIV_INT_Msk (0xffffff00UL) /*!< INT (Bitfield-Mask: 0xffffff) */
#define CLOCKS_CLK_GPOUT3_DIV_FRAC_Pos (0UL) /*!< FRAC (Bit 0) */
#define CLOCKS_CLK_GPOUT3_DIV_FRAC_Msk (0xffUL) /*!< FRAC (Bitfield-Mask: 0xff) */
/* ================================================== CLK_GPOUT3_SELECTED ================================================== */
/* ===================================================== CLK_REF_CTRL ====================================================== */
#define CLOCKS_CLK_REF_CTRL_AUXSRC_Pos (5UL) /*!< AUXSRC (Bit 5) */
#define CLOCKS_CLK_REF_CTRL_AUXSRC_Msk (0x60UL) /*!< AUXSRC (Bitfield-Mask: 0x03) */
#define CLOCKS_CLK_REF_CTRL_SRC_Pos (0UL) /*!< SRC (Bit 0) */
#define CLOCKS_CLK_REF_CTRL_SRC_Msk (0x3UL) /*!< SRC (Bitfield-Mask: 0x03) */
/* ====================================================== CLK_REF_DIV ====================================================== */
#define CLOCKS_CLK_REF_DIV_INT_Pos (8UL) /*!< INT (Bit 8) */
#define CLOCKS_CLK_REF_DIV_INT_Msk (0x300UL) /*!< INT (Bitfield-Mask: 0x03) */
/* =================================================== CLK_REF_SELECTED ==================================================== */
/* ===================================================== CLK_SYS_CTRL ====================================================== */
#define CLOCKS_CLK_SYS_CTRL_AUXSRC_Pos (5UL) /*!< AUXSRC (Bit 5) */
#define CLOCKS_CLK_SYS_CTRL_AUXSRC_Msk (0xe0UL) /*!< AUXSRC (Bitfield-Mask: 0x07) */
#define CLOCKS_CLK_SYS_CTRL_SRC_Pos (0UL) /*!< SRC (Bit 0) */
#define CLOCKS_CLK_SYS_CTRL_SRC_Msk (0x1UL) /*!< SRC (Bitfield-Mask: 0x01) */
/* ====================================================== CLK_SYS_DIV ====================================================== */
#define CLOCKS_CLK_SYS_DIV_INT_Pos (8UL) /*!< INT (Bit 8) */
#define CLOCKS_CLK_SYS_DIV_INT_Msk (0xffffff00UL) /*!< INT (Bitfield-Mask: 0xffffff) */
#define CLOCKS_CLK_SYS_DIV_FRAC_Pos (0UL) /*!< FRAC (Bit 0) */
#define CLOCKS_CLK_SYS_DIV_FRAC_Msk (0xffUL) /*!< FRAC (Bitfield-Mask: 0xff) */
/* =================================================== CLK_SYS_SELECTED ==================================================== */
/* ===================================================== CLK_PERI_CTRL ===================================================== */
#define CLOCKS_CLK_PERI_CTRL_ENABLE_Pos (11UL) /*!< ENABLE (Bit 11) */
#define CLOCKS_CLK_PERI_CTRL_ENABLE_Msk (0x800UL) /*!< ENABLE (Bitfield-Mask: 0x01) */
#define CLOCKS_CLK_PERI_CTRL_KILL_Pos (10UL) /*!< KILL (Bit 10) */
#define CLOCKS_CLK_PERI_CTRL_KILL_Msk (0x400UL) /*!< KILL (Bitfield-Mask: 0x01) */
#define CLOCKS_CLK_PERI_CTRL_AUXSRC_Pos (5UL) /*!< AUXSRC (Bit 5) */
#define CLOCKS_CLK_PERI_CTRL_AUXSRC_Msk (0xe0UL) /*!< AUXSRC (Bitfield-Mask: 0x07) */
/* =================================================== CLK_PERI_SELECTED =================================================== */
/* ===================================================== CLK_USB_CTRL ====================================================== */
#define CLOCKS_CLK_USB_CTRL_NUDGE_Pos (20UL) /*!< NUDGE (Bit 20) */
#define CLOCKS_CLK_USB_CTRL_NUDGE_Msk (0x100000UL) /*!< NUDGE (Bitfield-Mask: 0x01) */
#define CLOCKS_CLK_USB_CTRL_PHASE_Pos (16UL) /*!< PHASE (Bit 16) */
#define CLOCKS_CLK_USB_CTRL_PHASE_Msk (0x30000UL) /*!< PHASE (Bitfield-Mask: 0x03) */
#define CLOCKS_CLK_USB_CTRL_ENABLE_Pos (11UL) /*!< ENABLE (Bit 11) */
#define CLOCKS_CLK_USB_CTRL_ENABLE_Msk (0x800UL) /*!< ENABLE (Bitfield-Mask: 0x01) */
#define CLOCKS_CLK_USB_CTRL_KILL_Pos (10UL) /*!< KILL (Bit 10) */
#define CLOCKS_CLK_USB_CTRL_KILL_Msk (0x400UL) /*!< KILL (Bitfield-Mask: 0x01) */
#define CLOCKS_CLK_USB_CTRL_AUXSRC_Pos (5UL) /*!< AUXSRC (Bit 5) */
#define CLOCKS_CLK_USB_CTRL_AUXSRC_Msk (0xe0UL) /*!< AUXSRC (Bitfield-Mask: 0x07) */
/* ====================================================== CLK_USB_DIV ====================================================== */
#define CLOCKS_CLK_USB_DIV_INT_Pos (8UL) /*!< INT (Bit 8) */
#define CLOCKS_CLK_USB_DIV_INT_Msk (0x300UL) /*!< INT (Bitfield-Mask: 0x03) */
/* =================================================== CLK_USB_SELECTED ==================================================== */
/* ===================================================== CLK_ADC_CTRL ====================================================== */
#define CLOCKS_CLK_ADC_CTRL_NUDGE_Pos (20UL) /*!< NUDGE (Bit 20) */
#define CLOCKS_CLK_ADC_CTRL_NUDGE_Msk (0x100000UL) /*!< NUDGE (Bitfield-Mask: 0x01) */
#define CLOCKS_CLK_ADC_CTRL_PHASE_Pos (16UL) /*!< PHASE (Bit 16) */
#define CLOCKS_CLK_ADC_CTRL_PHASE_Msk (0x30000UL) /*!< PHASE (Bitfield-Mask: 0x03) */
#define CLOCKS_CLK_ADC_CTRL_ENABLE_Pos (11UL) /*!< ENABLE (Bit 11) */
#define CLOCKS_CLK_ADC_CTRL_ENABLE_Msk (0x800UL) /*!< ENABLE (Bitfield-Mask: 0x01) */
#define CLOCKS_CLK_ADC_CTRL_KILL_Pos (10UL) /*!< KILL (Bit 10) */
#define CLOCKS_CLK_ADC_CTRL_KILL_Msk (0x400UL) /*!< KILL (Bitfield-Mask: 0x01) */
#define CLOCKS_CLK_ADC_CTRL_AUXSRC_Pos (5UL) /*!< AUXSRC (Bit 5) */
#define CLOCKS_CLK_ADC_CTRL_AUXSRC_Msk (0xe0UL) /*!< AUXSRC (Bitfield-Mask: 0x07) */
/* ====================================================== CLK_ADC_DIV ====================================================== */
#define CLOCKS_CLK_ADC_DIV_INT_Pos (8UL) /*!< INT (Bit 8) */
#define CLOCKS_CLK_ADC_DIV_INT_Msk (0x300UL) /*!< INT (Bitfield-Mask: 0x03) */
/* =================================================== CLK_ADC_SELECTED ==================================================== */
/* ===================================================== CLK_RTC_CTRL ====================================================== */
#define CLOCKS_CLK_RTC_CTRL_NUDGE_Pos (20UL) /*!< NUDGE (Bit 20) */
#define CLOCKS_CLK_RTC_CTRL_NUDGE_Msk (0x100000UL) /*!< NUDGE (Bitfield-Mask: 0x01) */
#define CLOCKS_CLK_RTC_CTRL_PHASE_Pos (16UL) /*!< PHASE (Bit 16) */
#define CLOCKS_CLK_RTC_CTRL_PHASE_Msk (0x30000UL) /*!< PHASE (Bitfield-Mask: 0x03) */
#define CLOCKS_CLK_RTC_CTRL_ENABLE_Pos (11UL) /*!< ENABLE (Bit 11) */
#define CLOCKS_CLK_RTC_CTRL_ENABLE_Msk (0x800UL) /*!< ENABLE (Bitfield-Mask: 0x01) */
#define CLOCKS_CLK_RTC_CTRL_KILL_Pos (10UL) /*!< KILL (Bit 10) */
#define CLOCKS_CLK_RTC_CTRL_KILL_Msk (0x400UL) /*!< KILL (Bitfield-Mask: 0x01) */
#define CLOCKS_CLK_RTC_CTRL_AUXSRC_Pos (5UL) /*!< AUXSRC (Bit 5) */
#define CLOCKS_CLK_RTC_CTRL_AUXSRC_Msk (0xe0UL) /*!< AUXSRC (Bitfield-Mask: 0x07) */
/* ====================================================== CLK_RTC_DIV ====================================================== */
#define CLOCKS_CLK_RTC_DIV_INT_Pos (8UL) /*!< INT (Bit 8) */
#define CLOCKS_CLK_RTC_DIV_INT_Msk (0xffffff00UL) /*!< INT (Bitfield-Mask: 0xffffff) */
#define CLOCKS_CLK_RTC_DIV_FRAC_Pos (0UL) /*!< FRAC (Bit 0) */
#define CLOCKS_CLK_RTC_DIV_FRAC_Msk (0xffUL) /*!< FRAC (Bitfield-Mask: 0xff) */
/* =================================================== CLK_RTC_SELECTED ==================================================== */
/* ================================================== CLK_SYS_RESUS_CTRL =================================================== */
#define CLOCKS_CLK_SYS_RESUS_CTRL_CLEAR_Pos (16UL) /*!< CLEAR (Bit 16) */
#define CLOCKS_CLK_SYS_RESUS_CTRL_CLEAR_Msk (0x10000UL) /*!< CLEAR (Bitfield-Mask: 0x01) */
#define CLOCKS_CLK_SYS_RESUS_CTRL_FRCE_Pos (12UL) /*!< FRCE (Bit 12) */
#define CLOCKS_CLK_SYS_RESUS_CTRL_FRCE_Msk (0x1000UL) /*!< FRCE (Bitfield-Mask: 0x01) */
#define CLOCKS_CLK_SYS_RESUS_CTRL_ENABLE_Pos (8UL) /*!< ENABLE (Bit 8) */
#define CLOCKS_CLK_SYS_RESUS_CTRL_ENABLE_Msk (0x100UL) /*!< ENABLE (Bitfield-Mask: 0x01) */
#define CLOCKS_CLK_SYS_RESUS_CTRL_TIMEOUT_Pos (0UL) /*!< TIMEOUT (Bit 0) */
#define CLOCKS_CLK_SYS_RESUS_CTRL_TIMEOUT_Msk (0xffUL) /*!< TIMEOUT (Bitfield-Mask: 0xff) */
/* ================================================= CLK_SYS_RESUS_STATUS ================================================== */
#define CLOCKS_CLK_SYS_RESUS_STATUS_RESUSSED_Pos (0UL) /*!< RESUSSED (Bit 0) */
#define CLOCKS_CLK_SYS_RESUS_STATUS_RESUSSED_Msk (0x1UL) /*!< RESUSSED (Bitfield-Mask: 0x01) */
/* ====================================================== FC0_REF_KHZ ====================================================== */
#define CLOCKS_FC0_REF_KHZ_FC0_REF_KHZ_Pos (0UL) /*!< FC0_REF_KHZ (Bit 0) */
#define CLOCKS_FC0_REF_KHZ_FC0_REF_KHZ_Msk (0xfffffUL) /*!< FC0_REF_KHZ (Bitfield-Mask: 0xfffff) */
/* ====================================================== FC0_MIN_KHZ ====================================================== */
#define CLOCKS_FC0_MIN_KHZ_FC0_MIN_KHZ_Pos (0UL) /*!< FC0_MIN_KHZ (Bit 0) */
#define CLOCKS_FC0_MIN_KHZ_FC0_MIN_KHZ_Msk (0x1ffffffUL) /*!< FC0_MIN_KHZ (Bitfield-Mask: 0x1ffffff) */
/* ====================================================== FC0_MAX_KHZ ====================================================== */
#define CLOCKS_FC0_MAX_KHZ_FC0_MAX_KHZ_Pos (0UL) /*!< FC0_MAX_KHZ (Bit 0) */
#define CLOCKS_FC0_MAX_KHZ_FC0_MAX_KHZ_Msk (0x1ffffffUL) /*!< FC0_MAX_KHZ (Bitfield-Mask: 0x1ffffff) */
/* ======================================================= FC0_DELAY ======================================================= */
#define CLOCKS_FC0_DELAY_FC0_DELAY_Pos (0UL) /*!< FC0_DELAY (Bit 0) */
#define CLOCKS_FC0_DELAY_FC0_DELAY_Msk (0x7UL) /*!< FC0_DELAY (Bitfield-Mask: 0x07) */
/* ===================================================== FC0_INTERVAL ====================================================== */
#define CLOCKS_FC0_INTERVAL_FC0_INTERVAL_Pos (0UL) /*!< FC0_INTERVAL (Bit 0) */
#define CLOCKS_FC0_INTERVAL_FC0_INTERVAL_Msk (0xfUL) /*!< FC0_INTERVAL (Bitfield-Mask: 0x0f) */
/* ======================================================== FC0_SRC ======================================================== */
#define CLOCKS_FC0_SRC_FC0_SRC_Pos (0UL) /*!< FC0_SRC (Bit 0) */
#define CLOCKS_FC0_SRC_FC0_SRC_Msk (0xffUL) /*!< FC0_SRC (Bitfield-Mask: 0xff) */
/* ====================================================== FC0_STATUS ======================================================= */
#define CLOCKS_FC0_STATUS_DIED_Pos (28UL) /*!< DIED (Bit 28) */
#define CLOCKS_FC0_STATUS_DIED_Msk (0x10000000UL) /*!< DIED (Bitfield-Mask: 0x01) */
#define CLOCKS_FC0_STATUS_FAST_Pos (24UL) /*!< FAST (Bit 24) */
#define CLOCKS_FC0_STATUS_FAST_Msk (0x1000000UL) /*!< FAST (Bitfield-Mask: 0x01) */
#define CLOCKS_FC0_STATUS_SLOW_Pos (20UL) /*!< SLOW (Bit 20) */
#define CLOCKS_FC0_STATUS_SLOW_Msk (0x100000UL) /*!< SLOW (Bitfield-Mask: 0x01) */
#define CLOCKS_FC0_STATUS_FAIL_Pos (16UL) /*!< FAIL (Bit 16) */
#define CLOCKS_FC0_STATUS_FAIL_Msk (0x10000UL) /*!< FAIL (Bitfield-Mask: 0x01) */
#define CLOCKS_FC0_STATUS_WAITING_Pos (12UL) /*!< WAITING (Bit 12) */
#define CLOCKS_FC0_STATUS_WAITING_Msk (0x1000UL) /*!< WAITING (Bitfield-Mask: 0x01) */
#define CLOCKS_FC0_STATUS_RUNNING_Pos (8UL) /*!< RUNNING (Bit 8) */
#define CLOCKS_FC0_STATUS_RUNNING_Msk (0x100UL) /*!< RUNNING (Bitfield-Mask: 0x01) */
#define CLOCKS_FC0_STATUS_DONE_Pos (4UL) /*!< DONE (Bit 4) */
#define CLOCKS_FC0_STATUS_DONE_Msk (0x10UL) /*!< DONE (Bitfield-Mask: 0x01) */
#define CLOCKS_FC0_STATUS_PASS_Pos (0UL) /*!< PASS (Bit 0) */
#define CLOCKS_FC0_STATUS_PASS_Msk (0x1UL) /*!< PASS (Bitfield-Mask: 0x01) */
/* ====================================================== FC0_RESULT ======================================================= */
#define CLOCKS_FC0_RESULT_KHZ_Pos (5UL) /*!< KHZ (Bit 5) */
#define CLOCKS_FC0_RESULT_KHZ_Msk (0x3fffffe0UL) /*!< KHZ (Bitfield-Mask: 0x1ffffff) */
#define CLOCKS_FC0_RESULT_FRAC_Pos (0UL) /*!< FRAC (Bit 0) */
#define CLOCKS_FC0_RESULT_FRAC_Msk (0x1fUL) /*!< FRAC (Bitfield-Mask: 0x1f) */
/* ======================================================= WAKE_EN0 ======================================================== */
#define CLOCKS_WAKE_EN0_clk_sys_sram3_Pos (31UL) /*!< clk_sys_sram3 (Bit 31) */
#define CLOCKS_WAKE_EN0_clk_sys_sram3_Msk (0x80000000UL) /*!< clk_sys_sram3 (Bitfield-Mask: 0x01) */
#define CLOCKS_WAKE_EN0_clk_sys_sram2_Pos (30UL) /*!< clk_sys_sram2 (Bit 30) */
#define CLOCKS_WAKE_EN0_clk_sys_sram2_Msk (0x40000000UL) /*!< clk_sys_sram2 (Bitfield-Mask: 0x01) */
#define CLOCKS_WAKE_EN0_clk_sys_sram1_Pos (29UL) /*!< clk_sys_sram1 (Bit 29) */
#define CLOCKS_WAKE_EN0_clk_sys_sram1_Msk (0x20000000UL) /*!< clk_sys_sram1 (Bitfield-Mask: 0x01) */
#define CLOCKS_WAKE_EN0_clk_sys_sram0_Pos (28UL) /*!< clk_sys_sram0 (Bit 28) */
#define CLOCKS_WAKE_EN0_clk_sys_sram0_Msk (0x10000000UL) /*!< clk_sys_sram0 (Bitfield-Mask: 0x01) */
#define CLOCKS_WAKE_EN0_clk_sys_spi1_Pos (27UL) /*!< clk_sys_spi1 (Bit 27) */
#define CLOCKS_WAKE_EN0_clk_sys_spi1_Msk (0x8000000UL) /*!< clk_sys_spi1 (Bitfield-Mask: 0x01) */
#define CLOCKS_WAKE_EN0_clk_peri_spi1_Pos (26UL) /*!< clk_peri_spi1 (Bit 26) */
#define CLOCKS_WAKE_EN0_clk_peri_spi1_Msk (0x4000000UL) /*!< clk_peri_spi1 (Bitfield-Mask: 0x01) */
#define CLOCKS_WAKE_EN0_clk_sys_spi0_Pos (25UL) /*!< clk_sys_spi0 (Bit 25) */
#define CLOCKS_WAKE_EN0_clk_sys_spi0_Msk (0x2000000UL) /*!< clk_sys_spi0 (Bitfield-Mask: 0x01) */
#define CLOCKS_WAKE_EN0_clk_peri_spi0_Pos (24UL) /*!< clk_peri_spi0 (Bit 24) */
#define CLOCKS_WAKE_EN0_clk_peri_spi0_Msk (0x1000000UL) /*!< clk_peri_spi0 (Bitfield-Mask: 0x01) */
#define CLOCKS_WAKE_EN0_clk_sys_sio_Pos (23UL) /*!< clk_sys_sio (Bit 23) */
#define CLOCKS_WAKE_EN0_clk_sys_sio_Msk (0x800000UL) /*!< clk_sys_sio (Bitfield-Mask: 0x01) */
#define CLOCKS_WAKE_EN0_clk_sys_rtc_Pos (22UL) /*!< clk_sys_rtc (Bit 22) */
#define CLOCKS_WAKE_EN0_clk_sys_rtc_Msk (0x400000UL) /*!< clk_sys_rtc (Bitfield-Mask: 0x01) */
#define CLOCKS_WAKE_EN0_clk_rtc_rtc_Pos (21UL) /*!< clk_rtc_rtc (Bit 21) */
#define CLOCKS_WAKE_EN0_clk_rtc_rtc_Msk (0x200000UL) /*!< clk_rtc_rtc (Bitfield-Mask: 0x01) */
#define CLOCKS_WAKE_EN0_clk_sys_rosc_Pos (20UL) /*!< clk_sys_rosc (Bit 20) */
#define CLOCKS_WAKE_EN0_clk_sys_rosc_Msk (0x100000UL) /*!< clk_sys_rosc (Bitfield-Mask: 0x01) */
#define CLOCKS_WAKE_EN0_clk_sys_rom_Pos (19UL) /*!< clk_sys_rom (Bit 19) */
#define CLOCKS_WAKE_EN0_clk_sys_rom_Msk (0x80000UL) /*!< clk_sys_rom (Bitfield-Mask: 0x01) */
#define CLOCKS_WAKE_EN0_clk_sys_resets_Pos (18UL) /*!< clk_sys_resets (Bit 18) */
#define CLOCKS_WAKE_EN0_clk_sys_resets_Msk (0x40000UL) /*!< clk_sys_resets (Bitfield-Mask: 0x01) */
#define CLOCKS_WAKE_EN0_clk_sys_pwm_Pos (17UL) /*!< clk_sys_pwm (Bit 17) */
#define CLOCKS_WAKE_EN0_clk_sys_pwm_Msk (0x20000UL) /*!< clk_sys_pwm (Bitfield-Mask: 0x01) */
#define CLOCKS_WAKE_EN0_clk_sys_psm_Pos (16UL) /*!< clk_sys_psm (Bit 16) */
#define CLOCKS_WAKE_EN0_clk_sys_psm_Msk (0x10000UL) /*!< clk_sys_psm (Bitfield-Mask: 0x01) */
#define CLOCKS_WAKE_EN0_clk_sys_pll_usb_Pos (15UL) /*!< clk_sys_pll_usb (Bit 15) */
#define CLOCKS_WAKE_EN0_clk_sys_pll_usb_Msk (0x8000UL) /*!< clk_sys_pll_usb (Bitfield-Mask: 0x01) */
#define CLOCKS_WAKE_EN0_clk_sys_pll_sys_Pos (14UL) /*!< clk_sys_pll_sys (Bit 14) */
#define CLOCKS_WAKE_EN0_clk_sys_pll_sys_Msk (0x4000UL) /*!< clk_sys_pll_sys (Bitfield-Mask: 0x01) */
#define CLOCKS_WAKE_EN0_clk_sys_pio1_Pos (13UL) /*!< clk_sys_pio1 (Bit 13) */
#define CLOCKS_WAKE_EN0_clk_sys_pio1_Msk (0x2000UL) /*!< clk_sys_pio1 (Bitfield-Mask: 0x01) */
#define CLOCKS_WAKE_EN0_clk_sys_pio0_Pos (12UL) /*!< clk_sys_pio0 (Bit 12) */
#define CLOCKS_WAKE_EN0_clk_sys_pio0_Msk (0x1000UL) /*!< clk_sys_pio0 (Bitfield-Mask: 0x01) */
#define CLOCKS_WAKE_EN0_clk_sys_pads_Pos (11UL) /*!< clk_sys_pads (Bit 11) */
#define CLOCKS_WAKE_EN0_clk_sys_pads_Msk (0x800UL) /*!< clk_sys_pads (Bitfield-Mask: 0x01) */
#define CLOCKS_WAKE_EN0_clk_sys_vreg_and_chip_reset_Pos (10UL) /*!< clk_sys_vreg_and_chip_reset (Bit 10) */
#define CLOCKS_WAKE_EN0_clk_sys_vreg_and_chip_reset_Msk (0x400UL) /*!< clk_sys_vreg_and_chip_reset (Bitfield-Mask: 0x01) */
#define CLOCKS_WAKE_EN0_clk_sys_jtag_Pos (9UL) /*!< clk_sys_jtag (Bit 9) */
#define CLOCKS_WAKE_EN0_clk_sys_jtag_Msk (0x200UL) /*!< clk_sys_jtag (Bitfield-Mask: 0x01) */
#define CLOCKS_WAKE_EN0_clk_sys_io_Pos (8UL) /*!< clk_sys_io (Bit 8) */
#define CLOCKS_WAKE_EN0_clk_sys_io_Msk (0x100UL) /*!< clk_sys_io (Bitfield-Mask: 0x01) */
#define CLOCKS_WAKE_EN0_clk_sys_i2c1_Pos (7UL) /*!< clk_sys_i2c1 (Bit 7) */
#define CLOCKS_WAKE_EN0_clk_sys_i2c1_Msk (0x80UL) /*!< clk_sys_i2c1 (Bitfield-Mask: 0x01) */
#define CLOCKS_WAKE_EN0_clk_sys_i2c0_Pos (6UL) /*!< clk_sys_i2c0 (Bit 6) */
#define CLOCKS_WAKE_EN0_clk_sys_i2c0_Msk (0x40UL) /*!< clk_sys_i2c0 (Bitfield-Mask: 0x01) */
#define CLOCKS_WAKE_EN0_clk_sys_dma_Pos (5UL) /*!< clk_sys_dma (Bit 5) */
#define CLOCKS_WAKE_EN0_clk_sys_dma_Msk (0x20UL) /*!< clk_sys_dma (Bitfield-Mask: 0x01) */
#define CLOCKS_WAKE_EN0_clk_sys_busfabric_Pos (4UL) /*!< clk_sys_busfabric (Bit 4) */
#define CLOCKS_WAKE_EN0_clk_sys_busfabric_Msk (0x10UL) /*!< clk_sys_busfabric (Bitfield-Mask: 0x01) */
#define CLOCKS_WAKE_EN0_clk_sys_busctrl_Pos (3UL) /*!< clk_sys_busctrl (Bit 3) */
#define CLOCKS_WAKE_EN0_clk_sys_busctrl_Msk (0x8UL) /*!< clk_sys_busctrl (Bitfield-Mask: 0x01) */
#define CLOCKS_WAKE_EN0_clk_sys_adc_Pos (2UL) /*!< clk_sys_adc (Bit 2) */
#define CLOCKS_WAKE_EN0_clk_sys_adc_Msk (0x4UL) /*!< clk_sys_adc (Bitfield-Mask: 0x01) */
#define CLOCKS_WAKE_EN0_clk_adc_adc_Pos (1UL) /*!< clk_adc_adc (Bit 1) */
#define CLOCKS_WAKE_EN0_clk_adc_adc_Msk (0x2UL) /*!< clk_adc_adc (Bitfield-Mask: 0x01) */
#define CLOCKS_WAKE_EN0_clk_sys_clocks_Pos (0UL) /*!< clk_sys_clocks (Bit 0) */
#define CLOCKS_WAKE_EN0_clk_sys_clocks_Msk (0x1UL) /*!< clk_sys_clocks (Bitfield-Mask: 0x01) */
/* ======================================================= WAKE_EN1 ======================================================== */
#define CLOCKS_WAKE_EN1_clk_sys_xosc_Pos (14UL) /*!< clk_sys_xosc (Bit 14) */
#define CLOCKS_WAKE_EN1_clk_sys_xosc_Msk (0x4000UL) /*!< clk_sys_xosc (Bitfield-Mask: 0x01) */
#define CLOCKS_WAKE_EN1_clk_sys_xip_Pos (13UL) /*!< clk_sys_xip (Bit 13) */
#define CLOCKS_WAKE_EN1_clk_sys_xip_Msk (0x2000UL) /*!< clk_sys_xip (Bitfield-Mask: 0x01) */
#define CLOCKS_WAKE_EN1_clk_sys_watchdog_Pos (12UL) /*!< clk_sys_watchdog (Bit 12) */
#define CLOCKS_WAKE_EN1_clk_sys_watchdog_Msk (0x1000UL) /*!< clk_sys_watchdog (Bitfield-Mask: 0x01) */
#define CLOCKS_WAKE_EN1_clk_usb_usbctrl_Pos (11UL) /*!< clk_usb_usbctrl (Bit 11) */
#define CLOCKS_WAKE_EN1_clk_usb_usbctrl_Msk (0x800UL) /*!< clk_usb_usbctrl (Bitfield-Mask: 0x01) */
#define CLOCKS_WAKE_EN1_clk_sys_usbctrl_Pos (10UL) /*!< clk_sys_usbctrl (Bit 10) */
#define CLOCKS_WAKE_EN1_clk_sys_usbctrl_Msk (0x400UL) /*!< clk_sys_usbctrl (Bitfield-Mask: 0x01) */
#define CLOCKS_WAKE_EN1_clk_sys_uart1_Pos (9UL) /*!< clk_sys_uart1 (Bit 9) */
#define CLOCKS_WAKE_EN1_clk_sys_uart1_Msk (0x200UL) /*!< clk_sys_uart1 (Bitfield-Mask: 0x01) */
#define CLOCKS_WAKE_EN1_clk_peri_uart1_Pos (8UL) /*!< clk_peri_uart1 (Bit 8) */
#define CLOCKS_WAKE_EN1_clk_peri_uart1_Msk (0x100UL) /*!< clk_peri_uart1 (Bitfield-Mask: 0x01) */
#define CLOCKS_WAKE_EN1_clk_sys_uart0_Pos (7UL) /*!< clk_sys_uart0 (Bit 7) */
#define CLOCKS_WAKE_EN1_clk_sys_uart0_Msk (0x80UL) /*!< clk_sys_uart0 (Bitfield-Mask: 0x01) */
#define CLOCKS_WAKE_EN1_clk_peri_uart0_Pos (6UL) /*!< clk_peri_uart0 (Bit 6) */
#define CLOCKS_WAKE_EN1_clk_peri_uart0_Msk (0x40UL) /*!< clk_peri_uart0 (Bitfield-Mask: 0x01) */
#define CLOCKS_WAKE_EN1_clk_sys_timer_Pos (5UL) /*!< clk_sys_timer (Bit 5) */
#define CLOCKS_WAKE_EN1_clk_sys_timer_Msk (0x20UL) /*!< clk_sys_timer (Bitfield-Mask: 0x01) */
#define CLOCKS_WAKE_EN1_clk_sys_tbman_Pos (4UL) /*!< clk_sys_tbman (Bit 4) */
#define CLOCKS_WAKE_EN1_clk_sys_tbman_Msk (0x10UL) /*!< clk_sys_tbman (Bitfield-Mask: 0x01) */
#define CLOCKS_WAKE_EN1_clk_sys_sysinfo_Pos (3UL) /*!< clk_sys_sysinfo (Bit 3) */
#define CLOCKS_WAKE_EN1_clk_sys_sysinfo_Msk (0x8UL) /*!< clk_sys_sysinfo (Bitfield-Mask: 0x01) */
#define CLOCKS_WAKE_EN1_clk_sys_syscfg_Pos (2UL) /*!< clk_sys_syscfg (Bit 2) */
#define CLOCKS_WAKE_EN1_clk_sys_syscfg_Msk (0x4UL) /*!< clk_sys_syscfg (Bitfield-Mask: 0x01) */
#define CLOCKS_WAKE_EN1_clk_sys_sram5_Pos (1UL) /*!< clk_sys_sram5 (Bit 1) */
#define CLOCKS_WAKE_EN1_clk_sys_sram5_Msk (0x2UL) /*!< clk_sys_sram5 (Bitfield-Mask: 0x01) */
#define CLOCKS_WAKE_EN1_clk_sys_sram4_Pos (0UL) /*!< clk_sys_sram4 (Bit 0) */
#define CLOCKS_WAKE_EN1_clk_sys_sram4_Msk (0x1UL) /*!< clk_sys_sram4 (Bitfield-Mask: 0x01) */
/* ======================================================= SLEEP_EN0 ======================================================= */
#define CLOCKS_SLEEP_EN0_clk_sys_sram3_Pos (31UL) /*!< clk_sys_sram3 (Bit 31) */
#define CLOCKS_SLEEP_EN0_clk_sys_sram3_Msk (0x80000000UL) /*!< clk_sys_sram3 (Bitfield-Mask: 0x01) */
#define CLOCKS_SLEEP_EN0_clk_sys_sram2_Pos (30UL) /*!< clk_sys_sram2 (Bit 30) */
#define CLOCKS_SLEEP_EN0_clk_sys_sram2_Msk (0x40000000UL) /*!< clk_sys_sram2 (Bitfield-Mask: 0x01) */
#define CLOCKS_SLEEP_EN0_clk_sys_sram1_Pos (29UL) /*!< clk_sys_sram1 (Bit 29) */
#define CLOCKS_SLEEP_EN0_clk_sys_sram1_Msk (0x20000000UL) /*!< clk_sys_sram1 (Bitfield-Mask: 0x01) */
#define CLOCKS_SLEEP_EN0_clk_sys_sram0_Pos (28UL) /*!< clk_sys_sram0 (Bit 28) */
#define CLOCKS_SLEEP_EN0_clk_sys_sram0_Msk (0x10000000UL) /*!< clk_sys_sram0 (Bitfield-Mask: 0x01) */
#define CLOCKS_SLEEP_EN0_clk_sys_spi1_Pos (27UL) /*!< clk_sys_spi1 (Bit 27) */
#define CLOCKS_SLEEP_EN0_clk_sys_spi1_Msk (0x8000000UL) /*!< clk_sys_spi1 (Bitfield-Mask: 0x01) */
#define CLOCKS_SLEEP_EN0_clk_peri_spi1_Pos (26UL) /*!< clk_peri_spi1 (Bit 26) */
#define CLOCKS_SLEEP_EN0_clk_peri_spi1_Msk (0x4000000UL) /*!< clk_peri_spi1 (Bitfield-Mask: 0x01) */
#define CLOCKS_SLEEP_EN0_clk_sys_spi0_Pos (25UL) /*!< clk_sys_spi0 (Bit 25) */
#define CLOCKS_SLEEP_EN0_clk_sys_spi0_Msk (0x2000000UL) /*!< clk_sys_spi0 (Bitfield-Mask: 0x01) */
#define CLOCKS_SLEEP_EN0_clk_peri_spi0_Pos (24UL) /*!< clk_peri_spi0 (Bit 24) */
#define CLOCKS_SLEEP_EN0_clk_peri_spi0_Msk (0x1000000UL) /*!< clk_peri_spi0 (Bitfield-Mask: 0x01) */
#define CLOCKS_SLEEP_EN0_clk_sys_sio_Pos (23UL) /*!< clk_sys_sio (Bit 23) */
#define CLOCKS_SLEEP_EN0_clk_sys_sio_Msk (0x800000UL) /*!< clk_sys_sio (Bitfield-Mask: 0x01) */
#define CLOCKS_SLEEP_EN0_clk_sys_rtc_Pos (22UL) /*!< clk_sys_rtc (Bit 22) */
#define CLOCKS_SLEEP_EN0_clk_sys_rtc_Msk (0x400000UL) /*!< clk_sys_rtc (Bitfield-Mask: 0x01) */
#define CLOCKS_SLEEP_EN0_clk_rtc_rtc_Pos (21UL) /*!< clk_rtc_rtc (Bit 21) */
#define CLOCKS_SLEEP_EN0_clk_rtc_rtc_Msk (0x200000UL) /*!< clk_rtc_rtc (Bitfield-Mask: 0x01) */
#define CLOCKS_SLEEP_EN0_clk_sys_rosc_Pos (20UL) /*!< clk_sys_rosc (Bit 20) */
#define CLOCKS_SLEEP_EN0_clk_sys_rosc_Msk (0x100000UL) /*!< clk_sys_rosc (Bitfield-Mask: 0x01) */
#define CLOCKS_SLEEP_EN0_clk_sys_rom_Pos (19UL) /*!< clk_sys_rom (Bit 19) */
#define CLOCKS_SLEEP_EN0_clk_sys_rom_Msk (0x80000UL) /*!< clk_sys_rom (Bitfield-Mask: 0x01) */
#define CLOCKS_SLEEP_EN0_clk_sys_resets_Pos (18UL) /*!< clk_sys_resets (Bit 18) */
#define CLOCKS_SLEEP_EN0_clk_sys_resets_Msk (0x40000UL) /*!< clk_sys_resets (Bitfield-Mask: 0x01) */
#define CLOCKS_SLEEP_EN0_clk_sys_pwm_Pos (17UL) /*!< clk_sys_pwm (Bit 17) */
#define CLOCKS_SLEEP_EN0_clk_sys_pwm_Msk (0x20000UL) /*!< clk_sys_pwm (Bitfield-Mask: 0x01) */
#define CLOCKS_SLEEP_EN0_clk_sys_psm_Pos (16UL) /*!< clk_sys_psm (Bit 16) */
#define CLOCKS_SLEEP_EN0_clk_sys_psm_Msk (0x10000UL) /*!< clk_sys_psm (Bitfield-Mask: 0x01) */
#define CLOCKS_SLEEP_EN0_clk_sys_pll_usb_Pos (15UL) /*!< clk_sys_pll_usb (Bit 15) */
#define CLOCKS_SLEEP_EN0_clk_sys_pll_usb_Msk (0x8000UL) /*!< clk_sys_pll_usb (Bitfield-Mask: 0x01) */
#define CLOCKS_SLEEP_EN0_clk_sys_pll_sys_Pos (14UL) /*!< clk_sys_pll_sys (Bit 14) */
#define CLOCKS_SLEEP_EN0_clk_sys_pll_sys_Msk (0x4000UL) /*!< clk_sys_pll_sys (Bitfield-Mask: 0x01) */
#define CLOCKS_SLEEP_EN0_clk_sys_pio1_Pos (13UL) /*!< clk_sys_pio1 (Bit 13) */
#define CLOCKS_SLEEP_EN0_clk_sys_pio1_Msk (0x2000UL) /*!< clk_sys_pio1 (Bitfield-Mask: 0x01) */
#define CLOCKS_SLEEP_EN0_clk_sys_pio0_Pos (12UL) /*!< clk_sys_pio0 (Bit 12) */
#define CLOCKS_SLEEP_EN0_clk_sys_pio0_Msk (0x1000UL) /*!< clk_sys_pio0 (Bitfield-Mask: 0x01) */
#define CLOCKS_SLEEP_EN0_clk_sys_pads_Pos (11UL) /*!< clk_sys_pads (Bit 11) */
#define CLOCKS_SLEEP_EN0_clk_sys_pads_Msk (0x800UL) /*!< clk_sys_pads (Bitfield-Mask: 0x01) */
#define CLOCKS_SLEEP_EN0_clk_sys_vreg_and_chip_reset_Pos (10UL) /*!< clk_sys_vreg_and_chip_reset (Bit 10) */
#define CLOCKS_SLEEP_EN0_clk_sys_vreg_and_chip_reset_Msk (0x400UL) /*!< clk_sys_vreg_and_chip_reset (Bitfield-Mask: 0x01) */
#define CLOCKS_SLEEP_EN0_clk_sys_jtag_Pos (9UL) /*!< clk_sys_jtag (Bit 9) */
#define CLOCKS_SLEEP_EN0_clk_sys_jtag_Msk (0x200UL) /*!< clk_sys_jtag (Bitfield-Mask: 0x01) */
#define CLOCKS_SLEEP_EN0_clk_sys_io_Pos (8UL) /*!< clk_sys_io (Bit 8) */
#define CLOCKS_SLEEP_EN0_clk_sys_io_Msk (0x100UL) /*!< clk_sys_io (Bitfield-Mask: 0x01) */
#define CLOCKS_SLEEP_EN0_clk_sys_i2c1_Pos (7UL) /*!< clk_sys_i2c1 (Bit 7) */
#define CLOCKS_SLEEP_EN0_clk_sys_i2c1_Msk (0x80UL) /*!< clk_sys_i2c1 (Bitfield-Mask: 0x01) */
#define CLOCKS_SLEEP_EN0_clk_sys_i2c0_Pos (6UL) /*!< clk_sys_i2c0 (Bit 6) */
#define CLOCKS_SLEEP_EN0_clk_sys_i2c0_Msk (0x40UL) /*!< clk_sys_i2c0 (Bitfield-Mask: 0x01) */
#define CLOCKS_SLEEP_EN0_clk_sys_dma_Pos (5UL) /*!< clk_sys_dma (Bit 5) */
#define CLOCKS_SLEEP_EN0_clk_sys_dma_Msk (0x20UL) /*!< clk_sys_dma (Bitfield-Mask: 0x01) */
#define CLOCKS_SLEEP_EN0_clk_sys_busfabric_Pos (4UL) /*!< clk_sys_busfabric (Bit 4) */
#define CLOCKS_SLEEP_EN0_clk_sys_busfabric_Msk (0x10UL) /*!< clk_sys_busfabric (Bitfield-Mask: 0x01) */
#define CLOCKS_SLEEP_EN0_clk_sys_busctrl_Pos (3UL) /*!< clk_sys_busctrl (Bit 3) */
#define CLOCKS_SLEEP_EN0_clk_sys_busctrl_Msk (0x8UL) /*!< clk_sys_busctrl (Bitfield-Mask: 0x01) */
#define CLOCKS_SLEEP_EN0_clk_sys_adc_Pos (2UL) /*!< clk_sys_adc (Bit 2) */
#define CLOCKS_SLEEP_EN0_clk_sys_adc_Msk (0x4UL) /*!< clk_sys_adc (Bitfield-Mask: 0x01) */
#define CLOCKS_SLEEP_EN0_clk_adc_adc_Pos (1UL) /*!< clk_adc_adc (Bit 1) */
#define CLOCKS_SLEEP_EN0_clk_adc_adc_Msk (0x2UL) /*!< clk_adc_adc (Bitfield-Mask: 0x01) */
#define CLOCKS_SLEEP_EN0_clk_sys_clocks_Pos (0UL) /*!< clk_sys_clocks (Bit 0) */
#define CLOCKS_SLEEP_EN0_clk_sys_clocks_Msk (0x1UL) /*!< clk_sys_clocks (Bitfield-Mask: 0x01) */
/* ======================================================= SLEEP_EN1 ======================================================= */
#define CLOCKS_SLEEP_EN1_clk_sys_xosc_Pos (14UL) /*!< clk_sys_xosc (Bit 14) */
#define CLOCKS_SLEEP_EN1_clk_sys_xosc_Msk (0x4000UL) /*!< clk_sys_xosc (Bitfield-Mask: 0x01) */
#define CLOCKS_SLEEP_EN1_clk_sys_xip_Pos (13UL) /*!< clk_sys_xip (Bit 13) */
#define CLOCKS_SLEEP_EN1_clk_sys_xip_Msk (0x2000UL) /*!< clk_sys_xip (Bitfield-Mask: 0x01) */
#define CLOCKS_SLEEP_EN1_clk_sys_watchdog_Pos (12UL) /*!< clk_sys_watchdog (Bit 12) */
#define CLOCKS_SLEEP_EN1_clk_sys_watchdog_Msk (0x1000UL) /*!< clk_sys_watchdog (Bitfield-Mask: 0x01) */
#define CLOCKS_SLEEP_EN1_clk_usb_usbctrl_Pos (11UL) /*!< clk_usb_usbctrl (Bit 11) */
#define CLOCKS_SLEEP_EN1_clk_usb_usbctrl_Msk (0x800UL) /*!< clk_usb_usbctrl (Bitfield-Mask: 0x01) */
#define CLOCKS_SLEEP_EN1_clk_sys_usbctrl_Pos (10UL) /*!< clk_sys_usbctrl (Bit 10) */
#define CLOCKS_SLEEP_EN1_clk_sys_usbctrl_Msk (0x400UL) /*!< clk_sys_usbctrl (Bitfield-Mask: 0x01) */
#define CLOCKS_SLEEP_EN1_clk_sys_uart1_Pos (9UL) /*!< clk_sys_uart1 (Bit 9) */
#define CLOCKS_SLEEP_EN1_clk_sys_uart1_Msk (0x200UL) /*!< clk_sys_uart1 (Bitfield-Mask: 0x01) */
#define CLOCKS_SLEEP_EN1_clk_peri_uart1_Pos (8UL) /*!< clk_peri_uart1 (Bit 8) */
#define CLOCKS_SLEEP_EN1_clk_peri_uart1_Msk (0x100UL) /*!< clk_peri_uart1 (Bitfield-Mask: 0x01) */
#define CLOCKS_SLEEP_EN1_clk_sys_uart0_Pos (7UL) /*!< clk_sys_uart0 (Bit 7) */
#define CLOCKS_SLEEP_EN1_clk_sys_uart0_Msk (0x80UL) /*!< clk_sys_uart0 (Bitfield-Mask: 0x01) */
#define CLOCKS_SLEEP_EN1_clk_peri_uart0_Pos (6UL) /*!< clk_peri_uart0 (Bit 6) */
#define CLOCKS_SLEEP_EN1_clk_peri_uart0_Msk (0x40UL) /*!< clk_peri_uart0 (Bitfield-Mask: 0x01) */
#define CLOCKS_SLEEP_EN1_clk_sys_timer_Pos (5UL) /*!< clk_sys_timer (Bit 5) */
#define CLOCKS_SLEEP_EN1_clk_sys_timer_Msk (0x20UL) /*!< clk_sys_timer (Bitfield-Mask: 0x01) */
#define CLOCKS_SLEEP_EN1_clk_sys_tbman_Pos (4UL) /*!< clk_sys_tbman (Bit 4) */
#define CLOCKS_SLEEP_EN1_clk_sys_tbman_Msk (0x10UL) /*!< clk_sys_tbman (Bitfield-Mask: 0x01) */
#define CLOCKS_SLEEP_EN1_clk_sys_sysinfo_Pos (3UL) /*!< clk_sys_sysinfo (Bit 3) */
#define CLOCKS_SLEEP_EN1_clk_sys_sysinfo_Msk (0x8UL) /*!< clk_sys_sysinfo (Bitfield-Mask: 0x01) */
#define CLOCKS_SLEEP_EN1_clk_sys_syscfg_Pos (2UL) /*!< clk_sys_syscfg (Bit 2) */
#define CLOCKS_SLEEP_EN1_clk_sys_syscfg_Msk (0x4UL) /*!< clk_sys_syscfg (Bitfield-Mask: 0x01) */
#define CLOCKS_SLEEP_EN1_clk_sys_sram5_Pos (1UL) /*!< clk_sys_sram5 (Bit 1) */
#define CLOCKS_SLEEP_EN1_clk_sys_sram5_Msk (0x2UL) /*!< clk_sys_sram5 (Bitfield-Mask: 0x01) */
#define CLOCKS_SLEEP_EN1_clk_sys_sram4_Pos (0UL) /*!< clk_sys_sram4 (Bit 0) */
#define CLOCKS_SLEEP_EN1_clk_sys_sram4_Msk (0x1UL) /*!< clk_sys_sram4 (Bitfield-Mask: 0x01) */
/* ======================================================= ENABLED0 ======================================================== */
#define CLOCKS_ENABLED0_clk_sys_sram3_Pos (31UL) /*!< clk_sys_sram3 (Bit 31) */
#define CLOCKS_ENABLED0_clk_sys_sram3_Msk (0x80000000UL) /*!< clk_sys_sram3 (Bitfield-Mask: 0x01) */
#define CLOCKS_ENABLED0_clk_sys_sram2_Pos (30UL) /*!< clk_sys_sram2 (Bit 30) */
#define CLOCKS_ENABLED0_clk_sys_sram2_Msk (0x40000000UL) /*!< clk_sys_sram2 (Bitfield-Mask: 0x01) */
#define CLOCKS_ENABLED0_clk_sys_sram1_Pos (29UL) /*!< clk_sys_sram1 (Bit 29) */
#define CLOCKS_ENABLED0_clk_sys_sram1_Msk (0x20000000UL) /*!< clk_sys_sram1 (Bitfield-Mask: 0x01) */
#define CLOCKS_ENABLED0_clk_sys_sram0_Pos (28UL) /*!< clk_sys_sram0 (Bit 28) */
#define CLOCKS_ENABLED0_clk_sys_sram0_Msk (0x10000000UL) /*!< clk_sys_sram0 (Bitfield-Mask: 0x01) */
#define CLOCKS_ENABLED0_clk_sys_spi1_Pos (27UL) /*!< clk_sys_spi1 (Bit 27) */
#define CLOCKS_ENABLED0_clk_sys_spi1_Msk (0x8000000UL) /*!< clk_sys_spi1 (Bitfield-Mask: 0x01) */
#define CLOCKS_ENABLED0_clk_peri_spi1_Pos (26UL) /*!< clk_peri_spi1 (Bit 26) */
#define CLOCKS_ENABLED0_clk_peri_spi1_Msk (0x4000000UL) /*!< clk_peri_spi1 (Bitfield-Mask: 0x01) */
#define CLOCKS_ENABLED0_clk_sys_spi0_Pos (25UL) /*!< clk_sys_spi0 (Bit 25) */
#define CLOCKS_ENABLED0_clk_sys_spi0_Msk (0x2000000UL) /*!< clk_sys_spi0 (Bitfield-Mask: 0x01) */
#define CLOCKS_ENABLED0_clk_peri_spi0_Pos (24UL) /*!< clk_peri_spi0 (Bit 24) */
#define CLOCKS_ENABLED0_clk_peri_spi0_Msk (0x1000000UL) /*!< clk_peri_spi0 (Bitfield-Mask: 0x01) */
#define CLOCKS_ENABLED0_clk_sys_sio_Pos (23UL) /*!< clk_sys_sio (Bit 23) */
#define CLOCKS_ENABLED0_clk_sys_sio_Msk (0x800000UL) /*!< clk_sys_sio (Bitfield-Mask: 0x01) */
#define CLOCKS_ENABLED0_clk_sys_rtc_Pos (22UL) /*!< clk_sys_rtc (Bit 22) */
#define CLOCKS_ENABLED0_clk_sys_rtc_Msk (0x400000UL) /*!< clk_sys_rtc (Bitfield-Mask: 0x01) */
#define CLOCKS_ENABLED0_clk_rtc_rtc_Pos (21UL) /*!< clk_rtc_rtc (Bit 21) */
#define CLOCKS_ENABLED0_clk_rtc_rtc_Msk (0x200000UL) /*!< clk_rtc_rtc (Bitfield-Mask: 0x01) */
#define CLOCKS_ENABLED0_clk_sys_rosc_Pos (20UL) /*!< clk_sys_rosc (Bit 20) */
#define CLOCKS_ENABLED0_clk_sys_rosc_Msk (0x100000UL) /*!< clk_sys_rosc (Bitfield-Mask: 0x01) */
#define CLOCKS_ENABLED0_clk_sys_rom_Pos (19UL) /*!< clk_sys_rom (Bit 19) */
#define CLOCKS_ENABLED0_clk_sys_rom_Msk (0x80000UL) /*!< clk_sys_rom (Bitfield-Mask: 0x01) */
#define CLOCKS_ENABLED0_clk_sys_resets_Pos (18UL) /*!< clk_sys_resets (Bit 18) */
#define CLOCKS_ENABLED0_clk_sys_resets_Msk (0x40000UL) /*!< clk_sys_resets (Bitfield-Mask: 0x01) */
#define CLOCKS_ENABLED0_clk_sys_pwm_Pos (17UL) /*!< clk_sys_pwm (Bit 17) */
#define CLOCKS_ENABLED0_clk_sys_pwm_Msk (0x20000UL) /*!< clk_sys_pwm (Bitfield-Mask: 0x01) */
#define CLOCKS_ENABLED0_clk_sys_psm_Pos (16UL) /*!< clk_sys_psm (Bit 16) */
#define CLOCKS_ENABLED0_clk_sys_psm_Msk (0x10000UL) /*!< clk_sys_psm (Bitfield-Mask: 0x01) */
#define CLOCKS_ENABLED0_clk_sys_pll_usb_Pos (15UL) /*!< clk_sys_pll_usb (Bit 15) */
#define CLOCKS_ENABLED0_clk_sys_pll_usb_Msk (0x8000UL) /*!< clk_sys_pll_usb (Bitfield-Mask: 0x01) */
#define CLOCKS_ENABLED0_clk_sys_pll_sys_Pos (14UL) /*!< clk_sys_pll_sys (Bit 14) */
#define CLOCKS_ENABLED0_clk_sys_pll_sys_Msk (0x4000UL) /*!< clk_sys_pll_sys (Bitfield-Mask: 0x01) */
#define CLOCKS_ENABLED0_clk_sys_pio1_Pos (13UL) /*!< clk_sys_pio1 (Bit 13) */
#define CLOCKS_ENABLED0_clk_sys_pio1_Msk (0x2000UL) /*!< clk_sys_pio1 (Bitfield-Mask: 0x01) */
#define CLOCKS_ENABLED0_clk_sys_pio0_Pos (12UL) /*!< clk_sys_pio0 (Bit 12) */
#define CLOCKS_ENABLED0_clk_sys_pio0_Msk (0x1000UL) /*!< clk_sys_pio0 (Bitfield-Mask: 0x01) */
#define CLOCKS_ENABLED0_clk_sys_pads_Pos (11UL) /*!< clk_sys_pads (Bit 11) */
#define CLOCKS_ENABLED0_clk_sys_pads_Msk (0x800UL) /*!< clk_sys_pads (Bitfield-Mask: 0x01) */
#define CLOCKS_ENABLED0_clk_sys_vreg_and_chip_reset_Pos (10UL) /*!< clk_sys_vreg_and_chip_reset (Bit 10) */
#define CLOCKS_ENABLED0_clk_sys_vreg_and_chip_reset_Msk (0x400UL) /*!< clk_sys_vreg_and_chip_reset (Bitfield-Mask: 0x01) */
#define CLOCKS_ENABLED0_clk_sys_jtag_Pos (9UL) /*!< clk_sys_jtag (Bit 9) */
#define CLOCKS_ENABLED0_clk_sys_jtag_Msk (0x200UL) /*!< clk_sys_jtag (Bitfield-Mask: 0x01) */
#define CLOCKS_ENABLED0_clk_sys_io_Pos (8UL) /*!< clk_sys_io (Bit 8) */
#define CLOCKS_ENABLED0_clk_sys_io_Msk (0x100UL) /*!< clk_sys_io (Bitfield-Mask: 0x01) */
#define CLOCKS_ENABLED0_clk_sys_i2c1_Pos (7UL) /*!< clk_sys_i2c1 (Bit 7) */
#define CLOCKS_ENABLED0_clk_sys_i2c1_Msk (0x80UL) /*!< clk_sys_i2c1 (Bitfield-Mask: 0x01) */
#define CLOCKS_ENABLED0_clk_sys_i2c0_Pos (6UL) /*!< clk_sys_i2c0 (Bit 6) */
#define CLOCKS_ENABLED0_clk_sys_i2c0_Msk (0x40UL) /*!< clk_sys_i2c0 (Bitfield-Mask: 0x01) */
#define CLOCKS_ENABLED0_clk_sys_dma_Pos (5UL) /*!< clk_sys_dma (Bit 5) */
#define CLOCKS_ENABLED0_clk_sys_dma_Msk (0x20UL) /*!< clk_sys_dma (Bitfield-Mask: 0x01) */
#define CLOCKS_ENABLED0_clk_sys_busfabric_Pos (4UL) /*!< clk_sys_busfabric (Bit 4) */
#define CLOCKS_ENABLED0_clk_sys_busfabric_Msk (0x10UL) /*!< clk_sys_busfabric (Bitfield-Mask: 0x01) */
#define CLOCKS_ENABLED0_clk_sys_busctrl_Pos (3UL) /*!< clk_sys_busctrl (Bit 3) */
#define CLOCKS_ENABLED0_clk_sys_busctrl_Msk (0x8UL) /*!< clk_sys_busctrl (Bitfield-Mask: 0x01) */
#define CLOCKS_ENABLED0_clk_sys_adc_Pos (2UL) /*!< clk_sys_adc (Bit 2) */
#define CLOCKS_ENABLED0_clk_sys_adc_Msk (0x4UL) /*!< clk_sys_adc (Bitfield-Mask: 0x01) */
#define CLOCKS_ENABLED0_clk_adc_adc_Pos (1UL) /*!< clk_adc_adc (Bit 1) */
#define CLOCKS_ENABLED0_clk_adc_adc_Msk (0x2UL) /*!< clk_adc_adc (Bitfield-Mask: 0x01) */
#define CLOCKS_ENABLED0_clk_sys_clocks_Pos (0UL) /*!< clk_sys_clocks (Bit 0) */
#define CLOCKS_ENABLED0_clk_sys_clocks_Msk (0x1UL) /*!< clk_sys_clocks (Bitfield-Mask: 0x01) */
/* ======================================================= ENABLED1 ======================================================== */
#define CLOCKS_ENABLED1_clk_sys_xosc_Pos (14UL) /*!< clk_sys_xosc (Bit 14) */
#define CLOCKS_ENABLED1_clk_sys_xosc_Msk (0x4000UL) /*!< clk_sys_xosc (Bitfield-Mask: 0x01) */
#define CLOCKS_ENABLED1_clk_sys_xip_Pos (13UL) /*!< clk_sys_xip (Bit 13) */
#define CLOCKS_ENABLED1_clk_sys_xip_Msk (0x2000UL) /*!< clk_sys_xip (Bitfield-Mask: 0x01) */
#define CLOCKS_ENABLED1_clk_sys_watchdog_Pos (12UL) /*!< clk_sys_watchdog (Bit 12) */
#define CLOCKS_ENABLED1_clk_sys_watchdog_Msk (0x1000UL) /*!< clk_sys_watchdog (Bitfield-Mask: 0x01) */
#define CLOCKS_ENABLED1_clk_usb_usbctrl_Pos (11UL) /*!< clk_usb_usbctrl (Bit 11) */
#define CLOCKS_ENABLED1_clk_usb_usbctrl_Msk (0x800UL) /*!< clk_usb_usbctrl (Bitfield-Mask: 0x01) */
#define CLOCKS_ENABLED1_clk_sys_usbctrl_Pos (10UL) /*!< clk_sys_usbctrl (Bit 10) */
#define CLOCKS_ENABLED1_clk_sys_usbctrl_Msk (0x400UL) /*!< clk_sys_usbctrl (Bitfield-Mask: 0x01) */
#define CLOCKS_ENABLED1_clk_sys_uart1_Pos (9UL) /*!< clk_sys_uart1 (Bit 9) */
#define CLOCKS_ENABLED1_clk_sys_uart1_Msk (0x200UL) /*!< clk_sys_uart1 (Bitfield-Mask: 0x01) */
#define CLOCKS_ENABLED1_clk_peri_uart1_Pos (8UL) /*!< clk_peri_uart1 (Bit 8) */
#define CLOCKS_ENABLED1_clk_peri_uart1_Msk (0x100UL) /*!< clk_peri_uart1 (Bitfield-Mask: 0x01) */
#define CLOCKS_ENABLED1_clk_sys_uart0_Pos (7UL) /*!< clk_sys_uart0 (Bit 7) */
#define CLOCKS_ENABLED1_clk_sys_uart0_Msk (0x80UL) /*!< clk_sys_uart0 (Bitfield-Mask: 0x01) */
#define CLOCKS_ENABLED1_clk_peri_uart0_Pos (6UL) /*!< clk_peri_uart0 (Bit 6) */
#define CLOCKS_ENABLED1_clk_peri_uart0_Msk (0x40UL) /*!< clk_peri_uart0 (Bitfield-Mask: 0x01) */
#define CLOCKS_ENABLED1_clk_sys_timer_Pos (5UL) /*!< clk_sys_timer (Bit 5) */
#define CLOCKS_ENABLED1_clk_sys_timer_Msk (0x20UL) /*!< clk_sys_timer (Bitfield-Mask: 0x01) */
#define CLOCKS_ENABLED1_clk_sys_tbman_Pos (4UL) /*!< clk_sys_tbman (Bit 4) */
#define CLOCKS_ENABLED1_clk_sys_tbman_Msk (0x10UL) /*!< clk_sys_tbman (Bitfield-Mask: 0x01) */
#define CLOCKS_ENABLED1_clk_sys_sysinfo_Pos (3UL) /*!< clk_sys_sysinfo (Bit 3) */
#define CLOCKS_ENABLED1_clk_sys_sysinfo_Msk (0x8UL) /*!< clk_sys_sysinfo (Bitfield-Mask: 0x01) */
#define CLOCKS_ENABLED1_clk_sys_syscfg_Pos (2UL) /*!< clk_sys_syscfg (Bit 2) */
#define CLOCKS_ENABLED1_clk_sys_syscfg_Msk (0x4UL) /*!< clk_sys_syscfg (Bitfield-Mask: 0x01) */
#define CLOCKS_ENABLED1_clk_sys_sram5_Pos (1UL) /*!< clk_sys_sram5 (Bit 1) */
#define CLOCKS_ENABLED1_clk_sys_sram5_Msk (0x2UL) /*!< clk_sys_sram5 (Bitfield-Mask: 0x01) */
#define CLOCKS_ENABLED1_clk_sys_sram4_Pos (0UL) /*!< clk_sys_sram4 (Bit 0) */
#define CLOCKS_ENABLED1_clk_sys_sram4_Msk (0x1UL) /*!< clk_sys_sram4 (Bitfield-Mask: 0x01) */
/* ========================================================= INTR ========================================================== */
#define CLOCKS_INTR_CLK_SYS_RESUS_Pos (0UL) /*!< CLK_SYS_RESUS (Bit 0) */
#define CLOCKS_INTR_CLK_SYS_RESUS_Msk (0x1UL) /*!< CLK_SYS_RESUS (Bitfield-Mask: 0x01) */
/* ========================================================= INTE ========================================================== */
#define CLOCKS_INTE_CLK_SYS_RESUS_Pos (0UL) /*!< CLK_SYS_RESUS (Bit 0) */
#define CLOCKS_INTE_CLK_SYS_RESUS_Msk (0x1UL) /*!< CLK_SYS_RESUS (Bitfield-Mask: 0x01) */
/* ========================================================= INTF ========================================================== */
#define CLOCKS_INTF_CLK_SYS_RESUS_Pos (0UL) /*!< CLK_SYS_RESUS (Bit 0) */
#define CLOCKS_INTF_CLK_SYS_RESUS_Msk (0x1UL) /*!< CLK_SYS_RESUS (Bitfield-Mask: 0x01) */
/* ========================================================= INTS ========================================================== */
#define CLOCKS_INTS_CLK_SYS_RESUS_Pos (0UL) /*!< CLK_SYS_RESUS (Bit 0) */
#define CLOCKS_INTS_CLK_SYS_RESUS_Msk (0x1UL) /*!< CLK_SYS_RESUS (Bitfield-Mask: 0x01) */
/* =========================================================================================================================== */
/* ================ RESETS ================ */
/* =========================================================================================================================== */
/* ========================================================= RESET ========================================================= */
#define RESETS_RESET_usbctrl_Pos (24UL) /*!< usbctrl (Bit 24) */
#define RESETS_RESET_usbctrl_Msk (0x1000000UL) /*!< usbctrl (Bitfield-Mask: 0x01) */
#define RESETS_RESET_uart1_Pos (23UL) /*!< uart1 (Bit 23) */
#define RESETS_RESET_uart1_Msk (0x800000UL) /*!< uart1 (Bitfield-Mask: 0x01) */
#define RESETS_RESET_uart0_Pos (22UL) /*!< uart0 (Bit 22) */
#define RESETS_RESET_uart0_Msk (0x400000UL) /*!< uart0 (Bitfield-Mask: 0x01) */
#define RESETS_RESET_timer_Pos (21UL) /*!< timer (Bit 21) */
#define RESETS_RESET_timer_Msk (0x200000UL) /*!< timer (Bitfield-Mask: 0x01) */
#define RESETS_RESET_tbman_Pos (20UL) /*!< tbman (Bit 20) */
#define RESETS_RESET_tbman_Msk (0x100000UL) /*!< tbman (Bitfield-Mask: 0x01) */
#define RESETS_RESET_sysinfo_Pos (19UL) /*!< sysinfo (Bit 19) */
#define RESETS_RESET_sysinfo_Msk (0x80000UL) /*!< sysinfo (Bitfield-Mask: 0x01) */
#define RESETS_RESET_syscfg_Pos (18UL) /*!< syscfg (Bit 18) */
#define RESETS_RESET_syscfg_Msk (0x40000UL) /*!< syscfg (Bitfield-Mask: 0x01) */
#define RESETS_RESET_spi1_Pos (17UL) /*!< spi1 (Bit 17) */
#define RESETS_RESET_spi1_Msk (0x20000UL) /*!< spi1 (Bitfield-Mask: 0x01) */
#define RESETS_RESET_spi0_Pos (16UL) /*!< spi0 (Bit 16) */
#define RESETS_RESET_spi0_Msk (0x10000UL) /*!< spi0 (Bitfield-Mask: 0x01) */
#define RESETS_RESET_rtc_Pos (15UL) /*!< rtc (Bit 15) */
#define RESETS_RESET_rtc_Msk (0x8000UL) /*!< rtc (Bitfield-Mask: 0x01) */
#define RESETS_RESET_pwm_Pos (14UL) /*!< pwm (Bit 14) */
#define RESETS_RESET_pwm_Msk (0x4000UL) /*!< pwm (Bitfield-Mask: 0x01) */
#define RESETS_RESET_pll_usb_Pos (13UL) /*!< pll_usb (Bit 13) */
#define RESETS_RESET_pll_usb_Msk (0x2000UL) /*!< pll_usb (Bitfield-Mask: 0x01) */
#define RESETS_RESET_pll_sys_Pos (12UL) /*!< pll_sys (Bit 12) */
#define RESETS_RESET_pll_sys_Msk (0x1000UL) /*!< pll_sys (Bitfield-Mask: 0x01) */
#define RESETS_RESET_pio1_Pos (11UL) /*!< pio1 (Bit 11) */
#define RESETS_RESET_pio1_Msk (0x800UL) /*!< pio1 (Bitfield-Mask: 0x01) */
#define RESETS_RESET_pio0_Pos (10UL) /*!< pio0 (Bit 10) */
#define RESETS_RESET_pio0_Msk (0x400UL) /*!< pio0 (Bitfield-Mask: 0x01) */
#define RESETS_RESET_pads_qspi_Pos (9UL) /*!< pads_qspi (Bit 9) */
#define RESETS_RESET_pads_qspi_Msk (0x200UL) /*!< pads_qspi (Bitfield-Mask: 0x01) */
#define RESETS_RESET_pads_bank0_Pos (8UL) /*!< pads_bank0 (Bit 8) */
#define RESETS_RESET_pads_bank0_Msk (0x100UL) /*!< pads_bank0 (Bitfield-Mask: 0x01) */
#define RESETS_RESET_jtag_Pos (7UL) /*!< jtag (Bit 7) */
#define RESETS_RESET_jtag_Msk (0x80UL) /*!< jtag (Bitfield-Mask: 0x01) */
#define RESETS_RESET_io_qspi_Pos (6UL) /*!< io_qspi (Bit 6) */
#define RESETS_RESET_io_qspi_Msk (0x40UL) /*!< io_qspi (Bitfield-Mask: 0x01) */
#define RESETS_RESET_io_bank0_Pos (5UL) /*!< io_bank0 (Bit 5) */
#define RESETS_RESET_io_bank0_Msk (0x20UL) /*!< io_bank0 (Bitfield-Mask: 0x01) */
#define RESETS_RESET_i2c1_Pos (4UL) /*!< i2c1 (Bit 4) */
#define RESETS_RESET_i2c1_Msk (0x10UL) /*!< i2c1 (Bitfield-Mask: 0x01) */
#define RESETS_RESET_i2c0_Pos (3UL) /*!< i2c0 (Bit 3) */
#define RESETS_RESET_i2c0_Msk (0x8UL) /*!< i2c0 (Bitfield-Mask: 0x01) */
#define RESETS_RESET_dma_Pos (2UL) /*!< dma (Bit 2) */
#define RESETS_RESET_dma_Msk (0x4UL) /*!< dma (Bitfield-Mask: 0x01) */
#define RESETS_RESET_busctrl_Pos (1UL) /*!< busctrl (Bit 1) */
#define RESETS_RESET_busctrl_Msk (0x2UL) /*!< busctrl (Bitfield-Mask: 0x01) */
#define RESETS_RESET_adc_Pos (0UL) /*!< adc (Bit 0) */
#define RESETS_RESET_adc_Msk (0x1UL) /*!< adc (Bitfield-Mask: 0x01) */
/* ========================================================= WDSEL ========================================================= */
#define RESETS_WDSEL_usbctrl_Pos (24UL) /*!< usbctrl (Bit 24) */
#define RESETS_WDSEL_usbctrl_Msk (0x1000000UL) /*!< usbctrl (Bitfield-Mask: 0x01) */
#define RESETS_WDSEL_uart1_Pos (23UL) /*!< uart1 (Bit 23) */
#define RESETS_WDSEL_uart1_Msk (0x800000UL) /*!< uart1 (Bitfield-Mask: 0x01) */
#define RESETS_WDSEL_uart0_Pos (22UL) /*!< uart0 (Bit 22) */
#define RESETS_WDSEL_uart0_Msk (0x400000UL) /*!< uart0 (Bitfield-Mask: 0x01) */
#define RESETS_WDSEL_timer_Pos (21UL) /*!< timer (Bit 21) */
#define RESETS_WDSEL_timer_Msk (0x200000UL) /*!< timer (Bitfield-Mask: 0x01) */
#define RESETS_WDSEL_tbman_Pos (20UL) /*!< tbman (Bit 20) */
#define RESETS_WDSEL_tbman_Msk (0x100000UL) /*!< tbman (Bitfield-Mask: 0x01) */
#define RESETS_WDSEL_sysinfo_Pos (19UL) /*!< sysinfo (Bit 19) */
#define RESETS_WDSEL_sysinfo_Msk (0x80000UL) /*!< sysinfo (Bitfield-Mask: 0x01) */
#define RESETS_WDSEL_syscfg_Pos (18UL) /*!< syscfg (Bit 18) */
#define RESETS_WDSEL_syscfg_Msk (0x40000UL) /*!< syscfg (Bitfield-Mask: 0x01) */
#define RESETS_WDSEL_spi1_Pos (17UL) /*!< spi1 (Bit 17) */
#define RESETS_WDSEL_spi1_Msk (0x20000UL) /*!< spi1 (Bitfield-Mask: 0x01) */
#define RESETS_WDSEL_spi0_Pos (16UL) /*!< spi0 (Bit 16) */
#define RESETS_WDSEL_spi0_Msk (0x10000UL) /*!< spi0 (Bitfield-Mask: 0x01) */
#define RESETS_WDSEL_rtc_Pos (15UL) /*!< rtc (Bit 15) */
#define RESETS_WDSEL_rtc_Msk (0x8000UL) /*!< rtc (Bitfield-Mask: 0x01) */
#define RESETS_WDSEL_pwm_Pos (14UL) /*!< pwm (Bit 14) */
#define RESETS_WDSEL_pwm_Msk (0x4000UL) /*!< pwm (Bitfield-Mask: 0x01) */
#define RESETS_WDSEL_pll_usb_Pos (13UL) /*!< pll_usb (Bit 13) */
#define RESETS_WDSEL_pll_usb_Msk (0x2000UL) /*!< pll_usb (Bitfield-Mask: 0x01) */
#define RESETS_WDSEL_pll_sys_Pos (12UL) /*!< pll_sys (Bit 12) */
#define RESETS_WDSEL_pll_sys_Msk (0x1000UL) /*!< pll_sys (Bitfield-Mask: 0x01) */
#define RESETS_WDSEL_pio1_Pos (11UL) /*!< pio1 (Bit 11) */
#define RESETS_WDSEL_pio1_Msk (0x800UL) /*!< pio1 (Bitfield-Mask: 0x01) */
#define RESETS_WDSEL_pio0_Pos (10UL) /*!< pio0 (Bit 10) */
#define RESETS_WDSEL_pio0_Msk (0x400UL) /*!< pio0 (Bitfield-Mask: 0x01) */
#define RESETS_WDSEL_pads_qspi_Pos (9UL) /*!< pads_qspi (Bit 9) */
#define RESETS_WDSEL_pads_qspi_Msk (0x200UL) /*!< pads_qspi (Bitfield-Mask: 0x01) */
#define RESETS_WDSEL_pads_bank0_Pos (8UL) /*!< pads_bank0 (Bit 8) */
#define RESETS_WDSEL_pads_bank0_Msk (0x100UL) /*!< pads_bank0 (Bitfield-Mask: 0x01) */
#define RESETS_WDSEL_jtag_Pos (7UL) /*!< jtag (Bit 7) */
#define RESETS_WDSEL_jtag_Msk (0x80UL) /*!< jtag (Bitfield-Mask: 0x01) */
#define RESETS_WDSEL_io_qspi_Pos (6UL) /*!< io_qspi (Bit 6) */
#define RESETS_WDSEL_io_qspi_Msk (0x40UL) /*!< io_qspi (Bitfield-Mask: 0x01) */
#define RESETS_WDSEL_io_bank0_Pos (5UL) /*!< io_bank0 (Bit 5) */
#define RESETS_WDSEL_io_bank0_Msk (0x20UL) /*!< io_bank0 (Bitfield-Mask: 0x01) */
#define RESETS_WDSEL_i2c1_Pos (4UL) /*!< i2c1 (Bit 4) */
#define RESETS_WDSEL_i2c1_Msk (0x10UL) /*!< i2c1 (Bitfield-Mask: 0x01) */
#define RESETS_WDSEL_i2c0_Pos (3UL) /*!< i2c0 (Bit 3) */
#define RESETS_WDSEL_i2c0_Msk (0x8UL) /*!< i2c0 (Bitfield-Mask: 0x01) */
#define RESETS_WDSEL_dma_Pos (2UL) /*!< dma (Bit 2) */
#define RESETS_WDSEL_dma_Msk (0x4UL) /*!< dma (Bitfield-Mask: 0x01) */
#define RESETS_WDSEL_busctrl_Pos (1UL) /*!< busctrl (Bit 1) */
#define RESETS_WDSEL_busctrl_Msk (0x2UL) /*!< busctrl (Bitfield-Mask: 0x01) */
#define RESETS_WDSEL_adc_Pos (0UL) /*!< adc (Bit 0) */
#define RESETS_WDSEL_adc_Msk (0x1UL) /*!< adc (Bitfield-Mask: 0x01) */
/* ====================================================== RESET_DONE ======================================================= */
#define RESETS_RESET_DONE_usbctrl_Pos (24UL) /*!< usbctrl (Bit 24) */
#define RESETS_RESET_DONE_usbctrl_Msk (0x1000000UL) /*!< usbctrl (Bitfield-Mask: 0x01) */
#define RESETS_RESET_DONE_uart1_Pos (23UL) /*!< uart1 (Bit 23) */
#define RESETS_RESET_DONE_uart1_Msk (0x800000UL) /*!< uart1 (Bitfield-Mask: 0x01) */
#define RESETS_RESET_DONE_uart0_Pos (22UL) /*!< uart0 (Bit 22) */
#define RESETS_RESET_DONE_uart0_Msk (0x400000UL) /*!< uart0 (Bitfield-Mask: 0x01) */
#define RESETS_RESET_DONE_timer_Pos (21UL) /*!< timer (Bit 21) */
#define RESETS_RESET_DONE_timer_Msk (0x200000UL) /*!< timer (Bitfield-Mask: 0x01) */
#define RESETS_RESET_DONE_tbman_Pos (20UL) /*!< tbman (Bit 20) */
#define RESETS_RESET_DONE_tbman_Msk (0x100000UL) /*!< tbman (Bitfield-Mask: 0x01) */
#define RESETS_RESET_DONE_sysinfo_Pos (19UL) /*!< sysinfo (Bit 19) */
#define RESETS_RESET_DONE_sysinfo_Msk (0x80000UL) /*!< sysinfo (Bitfield-Mask: 0x01) */
#define RESETS_RESET_DONE_syscfg_Pos (18UL) /*!< syscfg (Bit 18) */
#define RESETS_RESET_DONE_syscfg_Msk (0x40000UL) /*!< syscfg (Bitfield-Mask: 0x01) */
#define RESETS_RESET_DONE_spi1_Pos (17UL) /*!< spi1 (Bit 17) */
#define RESETS_RESET_DONE_spi1_Msk (0x20000UL) /*!< spi1 (Bitfield-Mask: 0x01) */
#define RESETS_RESET_DONE_spi0_Pos (16UL) /*!< spi0 (Bit 16) */
#define RESETS_RESET_DONE_spi0_Msk (0x10000UL) /*!< spi0 (Bitfield-Mask: 0x01) */
#define RESETS_RESET_DONE_rtc_Pos (15UL) /*!< rtc (Bit 15) */
#define RESETS_RESET_DONE_rtc_Msk (0x8000UL) /*!< rtc (Bitfield-Mask: 0x01) */
#define RESETS_RESET_DONE_pwm_Pos (14UL) /*!< pwm (Bit 14) */
#define RESETS_RESET_DONE_pwm_Msk (0x4000UL) /*!< pwm (Bitfield-Mask: 0x01) */
#define RESETS_RESET_DONE_pll_usb_Pos (13UL) /*!< pll_usb (Bit 13) */
#define RESETS_RESET_DONE_pll_usb_Msk (0x2000UL) /*!< pll_usb (Bitfield-Mask: 0x01) */
#define RESETS_RESET_DONE_pll_sys_Pos (12UL) /*!< pll_sys (Bit 12) */
#define RESETS_RESET_DONE_pll_sys_Msk (0x1000UL) /*!< pll_sys (Bitfield-Mask: 0x01) */
#define RESETS_RESET_DONE_pio1_Pos (11UL) /*!< pio1 (Bit 11) */
#define RESETS_RESET_DONE_pio1_Msk (0x800UL) /*!< pio1 (Bitfield-Mask: 0x01) */
#define RESETS_RESET_DONE_pio0_Pos (10UL) /*!< pio0 (Bit 10) */
#define RESETS_RESET_DONE_pio0_Msk (0x400UL) /*!< pio0 (Bitfield-Mask: 0x01) */
#define RESETS_RESET_DONE_pads_qspi_Pos (9UL) /*!< pads_qspi (Bit 9) */
#define RESETS_RESET_DONE_pads_qspi_Msk (0x200UL) /*!< pads_qspi (Bitfield-Mask: 0x01) */
#define RESETS_RESET_DONE_pads_bank0_Pos (8UL) /*!< pads_bank0 (Bit 8) */
#define RESETS_RESET_DONE_pads_bank0_Msk (0x100UL) /*!< pads_bank0 (Bitfield-Mask: 0x01) */
#define RESETS_RESET_DONE_jtag_Pos (7UL) /*!< jtag (Bit 7) */
#define RESETS_RESET_DONE_jtag_Msk (0x80UL) /*!< jtag (Bitfield-Mask: 0x01) */
#define RESETS_RESET_DONE_io_qspi_Pos (6UL) /*!< io_qspi (Bit 6) */
#define RESETS_RESET_DONE_io_qspi_Msk (0x40UL) /*!< io_qspi (Bitfield-Mask: 0x01) */
#define RESETS_RESET_DONE_io_bank0_Pos (5UL) /*!< io_bank0 (Bit 5) */
#define RESETS_RESET_DONE_io_bank0_Msk (0x20UL) /*!< io_bank0 (Bitfield-Mask: 0x01) */
#define RESETS_RESET_DONE_i2c1_Pos (4UL) /*!< i2c1 (Bit 4) */
#define RESETS_RESET_DONE_i2c1_Msk (0x10UL) /*!< i2c1 (Bitfield-Mask: 0x01) */
#define RESETS_RESET_DONE_i2c0_Pos (3UL) /*!< i2c0 (Bit 3) */
#define RESETS_RESET_DONE_i2c0_Msk (0x8UL) /*!< i2c0 (Bitfield-Mask: 0x01) */
#define RESETS_RESET_DONE_dma_Pos (2UL) /*!< dma (Bit 2) */
#define RESETS_RESET_DONE_dma_Msk (0x4UL) /*!< dma (Bitfield-Mask: 0x01) */
#define RESETS_RESET_DONE_busctrl_Pos (1UL) /*!< busctrl (Bit 1) */
#define RESETS_RESET_DONE_busctrl_Msk (0x2UL) /*!< busctrl (Bitfield-Mask: 0x01) */
#define RESETS_RESET_DONE_adc_Pos (0UL) /*!< adc (Bit 0) */
#define RESETS_RESET_DONE_adc_Msk (0x1UL) /*!< adc (Bitfield-Mask: 0x01) */
/* =========================================================================================================================== */
/* ================ PSM ================ */
/* =========================================================================================================================== */
/* ======================================================== FRCE_ON ======================================================== */
#define PSM_FRCE_ON_proc1_Pos (16UL) /*!< proc1 (Bit 16) */
#define PSM_FRCE_ON_proc1_Msk (0x10000UL) /*!< proc1 (Bitfield-Mask: 0x01) */
#define PSM_FRCE_ON_proc0_Pos (15UL) /*!< proc0 (Bit 15) */
#define PSM_FRCE_ON_proc0_Msk (0x8000UL) /*!< proc0 (Bitfield-Mask: 0x01) */
#define PSM_FRCE_ON_sio_Pos (14UL) /*!< sio (Bit 14) */
#define PSM_FRCE_ON_sio_Msk (0x4000UL) /*!< sio (Bitfield-Mask: 0x01) */
#define PSM_FRCE_ON_vreg_and_chip_reset_Pos (13UL) /*!< vreg_and_chip_reset (Bit 13) */
#define PSM_FRCE_ON_vreg_and_chip_reset_Msk (0x2000UL) /*!< vreg_and_chip_reset (Bitfield-Mask: 0x01) */
#define PSM_FRCE_ON_xip_Pos (12UL) /*!< xip (Bit 12) */
#define PSM_FRCE_ON_xip_Msk (0x1000UL) /*!< xip (Bitfield-Mask: 0x01) */
#define PSM_FRCE_ON_sram5_Pos (11UL) /*!< sram5 (Bit 11) */
#define PSM_FRCE_ON_sram5_Msk (0x800UL) /*!< sram5 (Bitfield-Mask: 0x01) */
#define PSM_FRCE_ON_sram4_Pos (10UL) /*!< sram4 (Bit 10) */
#define PSM_FRCE_ON_sram4_Msk (0x400UL) /*!< sram4 (Bitfield-Mask: 0x01) */
#define PSM_FRCE_ON_sram3_Pos (9UL) /*!< sram3 (Bit 9) */
#define PSM_FRCE_ON_sram3_Msk (0x200UL) /*!< sram3 (Bitfield-Mask: 0x01) */
#define PSM_FRCE_ON_sram2_Pos (8UL) /*!< sram2 (Bit 8) */
#define PSM_FRCE_ON_sram2_Msk (0x100UL) /*!< sram2 (Bitfield-Mask: 0x01) */
#define PSM_FRCE_ON_sram1_Pos (7UL) /*!< sram1 (Bit 7) */
#define PSM_FRCE_ON_sram1_Msk (0x80UL) /*!< sram1 (Bitfield-Mask: 0x01) */
#define PSM_FRCE_ON_sram0_Pos (6UL) /*!< sram0 (Bit 6) */
#define PSM_FRCE_ON_sram0_Msk (0x40UL) /*!< sram0 (Bitfield-Mask: 0x01) */
#define PSM_FRCE_ON_rom_Pos (5UL) /*!< rom (Bit 5) */
#define PSM_FRCE_ON_rom_Msk (0x20UL) /*!< rom (Bitfield-Mask: 0x01) */
#define PSM_FRCE_ON_busfabric_Pos (4UL) /*!< busfabric (Bit 4) */
#define PSM_FRCE_ON_busfabric_Msk (0x10UL) /*!< busfabric (Bitfield-Mask: 0x01) */
#define PSM_FRCE_ON_resets_Pos (3UL) /*!< resets (Bit 3) */
#define PSM_FRCE_ON_resets_Msk (0x8UL) /*!< resets (Bitfield-Mask: 0x01) */
#define PSM_FRCE_ON_clocks_Pos (2UL) /*!< clocks (Bit 2) */
#define PSM_FRCE_ON_clocks_Msk (0x4UL) /*!< clocks (Bitfield-Mask: 0x01) */
#define PSM_FRCE_ON_xosc_Pos (1UL) /*!< xosc (Bit 1) */
#define PSM_FRCE_ON_xosc_Msk (0x2UL) /*!< xosc (Bitfield-Mask: 0x01) */
#define PSM_FRCE_ON_rosc_Pos (0UL) /*!< rosc (Bit 0) */
#define PSM_FRCE_ON_rosc_Msk (0x1UL) /*!< rosc (Bitfield-Mask: 0x01) */
/* ======================================================= FRCE_OFF ======================================================== */
#define PSM_FRCE_OFF_proc1_Pos (16UL) /*!< proc1 (Bit 16) */
#define PSM_FRCE_OFF_proc1_Msk (0x10000UL) /*!< proc1 (Bitfield-Mask: 0x01) */
#define PSM_FRCE_OFF_proc0_Pos (15UL) /*!< proc0 (Bit 15) */
#define PSM_FRCE_OFF_proc0_Msk (0x8000UL) /*!< proc0 (Bitfield-Mask: 0x01) */
#define PSM_FRCE_OFF_sio_Pos (14UL) /*!< sio (Bit 14) */
#define PSM_FRCE_OFF_sio_Msk (0x4000UL) /*!< sio (Bitfield-Mask: 0x01) */
#define PSM_FRCE_OFF_vreg_and_chip_reset_Pos (13UL) /*!< vreg_and_chip_reset (Bit 13) */
#define PSM_FRCE_OFF_vreg_and_chip_reset_Msk (0x2000UL) /*!< vreg_and_chip_reset (Bitfield-Mask: 0x01) */
#define PSM_FRCE_OFF_xip_Pos (12UL) /*!< xip (Bit 12) */
#define PSM_FRCE_OFF_xip_Msk (0x1000UL) /*!< xip (Bitfield-Mask: 0x01) */
#define PSM_FRCE_OFF_sram5_Pos (11UL) /*!< sram5 (Bit 11) */
#define PSM_FRCE_OFF_sram5_Msk (0x800UL) /*!< sram5 (Bitfield-Mask: 0x01) */
#define PSM_FRCE_OFF_sram4_Pos (10UL) /*!< sram4 (Bit 10) */
#define PSM_FRCE_OFF_sram4_Msk (0x400UL) /*!< sram4 (Bitfield-Mask: 0x01) */
#define PSM_FRCE_OFF_sram3_Pos (9UL) /*!< sram3 (Bit 9) */
#define PSM_FRCE_OFF_sram3_Msk (0x200UL) /*!< sram3 (Bitfield-Mask: 0x01) */
#define PSM_FRCE_OFF_sram2_Pos (8UL) /*!< sram2 (Bit 8) */
#define PSM_FRCE_OFF_sram2_Msk (0x100UL) /*!< sram2 (Bitfield-Mask: 0x01) */
#define PSM_FRCE_OFF_sram1_Pos (7UL) /*!< sram1 (Bit 7) */
#define PSM_FRCE_OFF_sram1_Msk (0x80UL) /*!< sram1 (Bitfield-Mask: 0x01) */
#define PSM_FRCE_OFF_sram0_Pos (6UL) /*!< sram0 (Bit 6) */
#define PSM_FRCE_OFF_sram0_Msk (0x40UL) /*!< sram0 (Bitfield-Mask: 0x01) */
#define PSM_FRCE_OFF_rom_Pos (5UL) /*!< rom (Bit 5) */
#define PSM_FRCE_OFF_rom_Msk (0x20UL) /*!< rom (Bitfield-Mask: 0x01) */
#define PSM_FRCE_OFF_busfabric_Pos (4UL) /*!< busfabric (Bit 4) */
#define PSM_FRCE_OFF_busfabric_Msk (0x10UL) /*!< busfabric (Bitfield-Mask: 0x01) */
#define PSM_FRCE_OFF_resets_Pos (3UL) /*!< resets (Bit 3) */
#define PSM_FRCE_OFF_resets_Msk (0x8UL) /*!< resets (Bitfield-Mask: 0x01) */
#define PSM_FRCE_OFF_clocks_Pos (2UL) /*!< clocks (Bit 2) */
#define PSM_FRCE_OFF_clocks_Msk (0x4UL) /*!< clocks (Bitfield-Mask: 0x01) */
#define PSM_FRCE_OFF_xosc_Pos (1UL) /*!< xosc (Bit 1) */
#define PSM_FRCE_OFF_xosc_Msk (0x2UL) /*!< xosc (Bitfield-Mask: 0x01) */
#define PSM_FRCE_OFF_rosc_Pos (0UL) /*!< rosc (Bit 0) */
#define PSM_FRCE_OFF_rosc_Msk (0x1UL) /*!< rosc (Bitfield-Mask: 0x01) */
/* ========================================================= WDSEL ========================================================= */
#define PSM_WDSEL_proc1_Pos (16UL) /*!< proc1 (Bit 16) */
#define PSM_WDSEL_proc1_Msk (0x10000UL) /*!< proc1 (Bitfield-Mask: 0x01) */
#define PSM_WDSEL_proc0_Pos (15UL) /*!< proc0 (Bit 15) */
#define PSM_WDSEL_proc0_Msk (0x8000UL) /*!< proc0 (Bitfield-Mask: 0x01) */
#define PSM_WDSEL_sio_Pos (14UL) /*!< sio (Bit 14) */
#define PSM_WDSEL_sio_Msk (0x4000UL) /*!< sio (Bitfield-Mask: 0x01) */
#define PSM_WDSEL_vreg_and_chip_reset_Pos (13UL) /*!< vreg_and_chip_reset (Bit 13) */
#define PSM_WDSEL_vreg_and_chip_reset_Msk (0x2000UL) /*!< vreg_and_chip_reset (Bitfield-Mask: 0x01) */
#define PSM_WDSEL_xip_Pos (12UL) /*!< xip (Bit 12) */
#define PSM_WDSEL_xip_Msk (0x1000UL) /*!< xip (Bitfield-Mask: 0x01) */
#define PSM_WDSEL_sram5_Pos (11UL) /*!< sram5 (Bit 11) */
#define PSM_WDSEL_sram5_Msk (0x800UL) /*!< sram5 (Bitfield-Mask: 0x01) */
#define PSM_WDSEL_sram4_Pos (10UL) /*!< sram4 (Bit 10) */
#define PSM_WDSEL_sram4_Msk (0x400UL) /*!< sram4 (Bitfield-Mask: 0x01) */
#define PSM_WDSEL_sram3_Pos (9UL) /*!< sram3 (Bit 9) */
#define PSM_WDSEL_sram3_Msk (0x200UL) /*!< sram3 (Bitfield-Mask: 0x01) */
#define PSM_WDSEL_sram2_Pos (8UL) /*!< sram2 (Bit 8) */
#define PSM_WDSEL_sram2_Msk (0x100UL) /*!< sram2 (Bitfield-Mask: 0x01) */
#define PSM_WDSEL_sram1_Pos (7UL) /*!< sram1 (Bit 7) */
#define PSM_WDSEL_sram1_Msk (0x80UL) /*!< sram1 (Bitfield-Mask: 0x01) */
#define PSM_WDSEL_sram0_Pos (6UL) /*!< sram0 (Bit 6) */
#define PSM_WDSEL_sram0_Msk (0x40UL) /*!< sram0 (Bitfield-Mask: 0x01) */
#define PSM_WDSEL_rom_Pos (5UL) /*!< rom (Bit 5) */
#define PSM_WDSEL_rom_Msk (0x20UL) /*!< rom (Bitfield-Mask: 0x01) */
#define PSM_WDSEL_busfabric_Pos (4UL) /*!< busfabric (Bit 4) */
#define PSM_WDSEL_busfabric_Msk (0x10UL) /*!< busfabric (Bitfield-Mask: 0x01) */
#define PSM_WDSEL_resets_Pos (3UL) /*!< resets (Bit 3) */
#define PSM_WDSEL_resets_Msk (0x8UL) /*!< resets (Bitfield-Mask: 0x01) */
#define PSM_WDSEL_clocks_Pos (2UL) /*!< clocks (Bit 2) */
#define PSM_WDSEL_clocks_Msk (0x4UL) /*!< clocks (Bitfield-Mask: 0x01) */
#define PSM_WDSEL_xosc_Pos (1UL) /*!< xosc (Bit 1) */
#define PSM_WDSEL_xosc_Msk (0x2UL) /*!< xosc (Bitfield-Mask: 0x01) */
#define PSM_WDSEL_rosc_Pos (0UL) /*!< rosc (Bit 0) */
#define PSM_WDSEL_rosc_Msk (0x1UL) /*!< rosc (Bitfield-Mask: 0x01) */
/* ========================================================= DONE ========================================================== */
#define PSM_DONE_proc1_Pos (16UL) /*!< proc1 (Bit 16) */
#define PSM_DONE_proc1_Msk (0x10000UL) /*!< proc1 (Bitfield-Mask: 0x01) */
#define PSM_DONE_proc0_Pos (15UL) /*!< proc0 (Bit 15) */
#define PSM_DONE_proc0_Msk (0x8000UL) /*!< proc0 (Bitfield-Mask: 0x01) */
#define PSM_DONE_sio_Pos (14UL) /*!< sio (Bit 14) */
#define PSM_DONE_sio_Msk (0x4000UL) /*!< sio (Bitfield-Mask: 0x01) */
#define PSM_DONE_vreg_and_chip_reset_Pos (13UL) /*!< vreg_and_chip_reset (Bit 13) */
#define PSM_DONE_vreg_and_chip_reset_Msk (0x2000UL) /*!< vreg_and_chip_reset (Bitfield-Mask: 0x01) */
#define PSM_DONE_xip_Pos (12UL) /*!< xip (Bit 12) */
#define PSM_DONE_xip_Msk (0x1000UL) /*!< xip (Bitfield-Mask: 0x01) */
#define PSM_DONE_sram5_Pos (11UL) /*!< sram5 (Bit 11) */
#define PSM_DONE_sram5_Msk (0x800UL) /*!< sram5 (Bitfield-Mask: 0x01) */
#define PSM_DONE_sram4_Pos (10UL) /*!< sram4 (Bit 10) */
#define PSM_DONE_sram4_Msk (0x400UL) /*!< sram4 (Bitfield-Mask: 0x01) */
#define PSM_DONE_sram3_Pos (9UL) /*!< sram3 (Bit 9) */
#define PSM_DONE_sram3_Msk (0x200UL) /*!< sram3 (Bitfield-Mask: 0x01) */
#define PSM_DONE_sram2_Pos (8UL) /*!< sram2 (Bit 8) */
#define PSM_DONE_sram2_Msk (0x100UL) /*!< sram2 (Bitfield-Mask: 0x01) */
#define PSM_DONE_sram1_Pos (7UL) /*!< sram1 (Bit 7) */
#define PSM_DONE_sram1_Msk (0x80UL) /*!< sram1 (Bitfield-Mask: 0x01) */
#define PSM_DONE_sram0_Pos (6UL) /*!< sram0 (Bit 6) */
#define PSM_DONE_sram0_Msk (0x40UL) /*!< sram0 (Bitfield-Mask: 0x01) */
#define PSM_DONE_rom_Pos (5UL) /*!< rom (Bit 5) */
#define PSM_DONE_rom_Msk (0x20UL) /*!< rom (Bitfield-Mask: 0x01) */
#define PSM_DONE_busfabric_Pos (4UL) /*!< busfabric (Bit 4) */
#define PSM_DONE_busfabric_Msk (0x10UL) /*!< busfabric (Bitfield-Mask: 0x01) */
#define PSM_DONE_resets_Pos (3UL) /*!< resets (Bit 3) */
#define PSM_DONE_resets_Msk (0x8UL) /*!< resets (Bitfield-Mask: 0x01) */
#define PSM_DONE_clocks_Pos (2UL) /*!< clocks (Bit 2) */
#define PSM_DONE_clocks_Msk (0x4UL) /*!< clocks (Bitfield-Mask: 0x01) */
#define PSM_DONE_xosc_Pos (1UL) /*!< xosc (Bit 1) */
#define PSM_DONE_xosc_Msk (0x2UL) /*!< xosc (Bitfield-Mask: 0x01) */
#define PSM_DONE_rosc_Pos (0UL) /*!< rosc (Bit 0) */
#define PSM_DONE_rosc_Msk (0x1UL) /*!< rosc (Bitfield-Mask: 0x01) */
/* =========================================================================================================================== */
/* ================ IO_BANK0 ================ */
/* =========================================================================================================================== */
/* ===================================================== GPIO0_STATUS ====================================================== */
#define IO_BANK0_GPIO0_STATUS_IRQTOPROC_Pos (26UL) /*!< IRQTOPROC (Bit 26) */
#define IO_BANK0_GPIO0_STATUS_IRQTOPROC_Msk (0x4000000UL) /*!< IRQTOPROC (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO0_STATUS_IRQFROMPAD_Pos (24UL) /*!< IRQFROMPAD (Bit 24) */
#define IO_BANK0_GPIO0_STATUS_IRQFROMPAD_Msk (0x1000000UL) /*!< IRQFROMPAD (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO0_STATUS_INTOPERI_Pos (19UL) /*!< INTOPERI (Bit 19) */
#define IO_BANK0_GPIO0_STATUS_INTOPERI_Msk (0x80000UL) /*!< INTOPERI (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO0_STATUS_INFROMPAD_Pos (17UL) /*!< INFROMPAD (Bit 17) */
#define IO_BANK0_GPIO0_STATUS_INFROMPAD_Msk (0x20000UL) /*!< INFROMPAD (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO0_STATUS_OETOPAD_Pos (13UL) /*!< OETOPAD (Bit 13) */
#define IO_BANK0_GPIO0_STATUS_OETOPAD_Msk (0x2000UL) /*!< OETOPAD (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO0_STATUS_OEFROMPERI_Pos (12UL) /*!< OEFROMPERI (Bit 12) */
#define IO_BANK0_GPIO0_STATUS_OEFROMPERI_Msk (0x1000UL) /*!< OEFROMPERI (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO0_STATUS_OUTTOPAD_Pos (9UL) /*!< OUTTOPAD (Bit 9) */
#define IO_BANK0_GPIO0_STATUS_OUTTOPAD_Msk (0x200UL) /*!< OUTTOPAD (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO0_STATUS_OUTFROMPERI_Pos (8UL) /*!< OUTFROMPERI (Bit 8) */
#define IO_BANK0_GPIO0_STATUS_OUTFROMPERI_Msk (0x100UL) /*!< OUTFROMPERI (Bitfield-Mask: 0x01) */
/* ====================================================== GPIO0_CTRL ======================================================= */
#define IO_BANK0_GPIO0_CTRL_IRQOVER_Pos (28UL) /*!< IRQOVER (Bit 28) */
#define IO_BANK0_GPIO0_CTRL_IRQOVER_Msk (0x30000000UL) /*!< IRQOVER (Bitfield-Mask: 0x03) */
#define IO_BANK0_GPIO0_CTRL_INOVER_Pos (16UL) /*!< INOVER (Bit 16) */
#define IO_BANK0_GPIO0_CTRL_INOVER_Msk (0x30000UL) /*!< INOVER (Bitfield-Mask: 0x03) */
#define IO_BANK0_GPIO0_CTRL_OEOVER_Pos (12UL) /*!< OEOVER (Bit 12) */
#define IO_BANK0_GPIO0_CTRL_OEOVER_Msk (0x3000UL) /*!< OEOVER (Bitfield-Mask: 0x03) */
#define IO_BANK0_GPIO0_CTRL_OUTOVER_Pos (8UL) /*!< OUTOVER (Bit 8) */
#define IO_BANK0_GPIO0_CTRL_OUTOVER_Msk (0x300UL) /*!< OUTOVER (Bitfield-Mask: 0x03) */
#define IO_BANK0_GPIO0_CTRL_FUNCSEL_Pos (0UL) /*!< FUNCSEL (Bit 0) */
#define IO_BANK0_GPIO0_CTRL_FUNCSEL_Msk (0x1fUL) /*!< FUNCSEL (Bitfield-Mask: 0x1f) */
/* ===================================================== GPIO1_STATUS ====================================================== */
#define IO_BANK0_GPIO1_STATUS_IRQTOPROC_Pos (26UL) /*!< IRQTOPROC (Bit 26) */
#define IO_BANK0_GPIO1_STATUS_IRQTOPROC_Msk (0x4000000UL) /*!< IRQTOPROC (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO1_STATUS_IRQFROMPAD_Pos (24UL) /*!< IRQFROMPAD (Bit 24) */
#define IO_BANK0_GPIO1_STATUS_IRQFROMPAD_Msk (0x1000000UL) /*!< IRQFROMPAD (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO1_STATUS_INTOPERI_Pos (19UL) /*!< INTOPERI (Bit 19) */
#define IO_BANK0_GPIO1_STATUS_INTOPERI_Msk (0x80000UL) /*!< INTOPERI (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO1_STATUS_INFROMPAD_Pos (17UL) /*!< INFROMPAD (Bit 17) */
#define IO_BANK0_GPIO1_STATUS_INFROMPAD_Msk (0x20000UL) /*!< INFROMPAD (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO1_STATUS_OETOPAD_Pos (13UL) /*!< OETOPAD (Bit 13) */
#define IO_BANK0_GPIO1_STATUS_OETOPAD_Msk (0x2000UL) /*!< OETOPAD (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO1_STATUS_OEFROMPERI_Pos (12UL) /*!< OEFROMPERI (Bit 12) */
#define IO_BANK0_GPIO1_STATUS_OEFROMPERI_Msk (0x1000UL) /*!< OEFROMPERI (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO1_STATUS_OUTTOPAD_Pos (9UL) /*!< OUTTOPAD (Bit 9) */
#define IO_BANK0_GPIO1_STATUS_OUTTOPAD_Msk (0x200UL) /*!< OUTTOPAD (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO1_STATUS_OUTFROMPERI_Pos (8UL) /*!< OUTFROMPERI (Bit 8) */
#define IO_BANK0_GPIO1_STATUS_OUTFROMPERI_Msk (0x100UL) /*!< OUTFROMPERI (Bitfield-Mask: 0x01) */
/* ====================================================== GPIO1_CTRL ======================================================= */
#define IO_BANK0_GPIO1_CTRL_IRQOVER_Pos (28UL) /*!< IRQOVER (Bit 28) */
#define IO_BANK0_GPIO1_CTRL_IRQOVER_Msk (0x30000000UL) /*!< IRQOVER (Bitfield-Mask: 0x03) */
#define IO_BANK0_GPIO1_CTRL_INOVER_Pos (16UL) /*!< INOVER (Bit 16) */
#define IO_BANK0_GPIO1_CTRL_INOVER_Msk (0x30000UL) /*!< INOVER (Bitfield-Mask: 0x03) */
#define IO_BANK0_GPIO1_CTRL_OEOVER_Pos (12UL) /*!< OEOVER (Bit 12) */
#define IO_BANK0_GPIO1_CTRL_OEOVER_Msk (0x3000UL) /*!< OEOVER (Bitfield-Mask: 0x03) */
#define IO_BANK0_GPIO1_CTRL_OUTOVER_Pos (8UL) /*!< OUTOVER (Bit 8) */
#define IO_BANK0_GPIO1_CTRL_OUTOVER_Msk (0x300UL) /*!< OUTOVER (Bitfield-Mask: 0x03) */
#define IO_BANK0_GPIO1_CTRL_FUNCSEL_Pos (0UL) /*!< FUNCSEL (Bit 0) */
#define IO_BANK0_GPIO1_CTRL_FUNCSEL_Msk (0x1fUL) /*!< FUNCSEL (Bitfield-Mask: 0x1f) */
/* ===================================================== GPIO2_STATUS ====================================================== */
#define IO_BANK0_GPIO2_STATUS_IRQTOPROC_Pos (26UL) /*!< IRQTOPROC (Bit 26) */
#define IO_BANK0_GPIO2_STATUS_IRQTOPROC_Msk (0x4000000UL) /*!< IRQTOPROC (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO2_STATUS_IRQFROMPAD_Pos (24UL) /*!< IRQFROMPAD (Bit 24) */
#define IO_BANK0_GPIO2_STATUS_IRQFROMPAD_Msk (0x1000000UL) /*!< IRQFROMPAD (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO2_STATUS_INTOPERI_Pos (19UL) /*!< INTOPERI (Bit 19) */
#define IO_BANK0_GPIO2_STATUS_INTOPERI_Msk (0x80000UL) /*!< INTOPERI (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO2_STATUS_INFROMPAD_Pos (17UL) /*!< INFROMPAD (Bit 17) */
#define IO_BANK0_GPIO2_STATUS_INFROMPAD_Msk (0x20000UL) /*!< INFROMPAD (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO2_STATUS_OETOPAD_Pos (13UL) /*!< OETOPAD (Bit 13) */
#define IO_BANK0_GPIO2_STATUS_OETOPAD_Msk (0x2000UL) /*!< OETOPAD (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO2_STATUS_OEFROMPERI_Pos (12UL) /*!< OEFROMPERI (Bit 12) */
#define IO_BANK0_GPIO2_STATUS_OEFROMPERI_Msk (0x1000UL) /*!< OEFROMPERI (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO2_STATUS_OUTTOPAD_Pos (9UL) /*!< OUTTOPAD (Bit 9) */
#define IO_BANK0_GPIO2_STATUS_OUTTOPAD_Msk (0x200UL) /*!< OUTTOPAD (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO2_STATUS_OUTFROMPERI_Pos (8UL) /*!< OUTFROMPERI (Bit 8) */
#define IO_BANK0_GPIO2_STATUS_OUTFROMPERI_Msk (0x100UL) /*!< OUTFROMPERI (Bitfield-Mask: 0x01) */
/* ====================================================== GPIO2_CTRL ======================================================= */
#define IO_BANK0_GPIO2_CTRL_IRQOVER_Pos (28UL) /*!< IRQOVER (Bit 28) */
#define IO_BANK0_GPIO2_CTRL_IRQOVER_Msk (0x30000000UL) /*!< IRQOVER (Bitfield-Mask: 0x03) */
#define IO_BANK0_GPIO2_CTRL_INOVER_Pos (16UL) /*!< INOVER (Bit 16) */
#define IO_BANK0_GPIO2_CTRL_INOVER_Msk (0x30000UL) /*!< INOVER (Bitfield-Mask: 0x03) */
#define IO_BANK0_GPIO2_CTRL_OEOVER_Pos (12UL) /*!< OEOVER (Bit 12) */
#define IO_BANK0_GPIO2_CTRL_OEOVER_Msk (0x3000UL) /*!< OEOVER (Bitfield-Mask: 0x03) */
#define IO_BANK0_GPIO2_CTRL_OUTOVER_Pos (8UL) /*!< OUTOVER (Bit 8) */
#define IO_BANK0_GPIO2_CTRL_OUTOVER_Msk (0x300UL) /*!< OUTOVER (Bitfield-Mask: 0x03) */
#define IO_BANK0_GPIO2_CTRL_FUNCSEL_Pos (0UL) /*!< FUNCSEL (Bit 0) */
#define IO_BANK0_GPIO2_CTRL_FUNCSEL_Msk (0x1fUL) /*!< FUNCSEL (Bitfield-Mask: 0x1f) */
/* ===================================================== GPIO3_STATUS ====================================================== */
#define IO_BANK0_GPIO3_STATUS_IRQTOPROC_Pos (26UL) /*!< IRQTOPROC (Bit 26) */
#define IO_BANK0_GPIO3_STATUS_IRQTOPROC_Msk (0x4000000UL) /*!< IRQTOPROC (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO3_STATUS_IRQFROMPAD_Pos (24UL) /*!< IRQFROMPAD (Bit 24) */
#define IO_BANK0_GPIO3_STATUS_IRQFROMPAD_Msk (0x1000000UL) /*!< IRQFROMPAD (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO3_STATUS_INTOPERI_Pos (19UL) /*!< INTOPERI (Bit 19) */
#define IO_BANK0_GPIO3_STATUS_INTOPERI_Msk (0x80000UL) /*!< INTOPERI (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO3_STATUS_INFROMPAD_Pos (17UL) /*!< INFROMPAD (Bit 17) */
#define IO_BANK0_GPIO3_STATUS_INFROMPAD_Msk (0x20000UL) /*!< INFROMPAD (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO3_STATUS_OETOPAD_Pos (13UL) /*!< OETOPAD (Bit 13) */
#define IO_BANK0_GPIO3_STATUS_OETOPAD_Msk (0x2000UL) /*!< OETOPAD (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO3_STATUS_OEFROMPERI_Pos (12UL) /*!< OEFROMPERI (Bit 12) */
#define IO_BANK0_GPIO3_STATUS_OEFROMPERI_Msk (0x1000UL) /*!< OEFROMPERI (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO3_STATUS_OUTTOPAD_Pos (9UL) /*!< OUTTOPAD (Bit 9) */
#define IO_BANK0_GPIO3_STATUS_OUTTOPAD_Msk (0x200UL) /*!< OUTTOPAD (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO3_STATUS_OUTFROMPERI_Pos (8UL) /*!< OUTFROMPERI (Bit 8) */
#define IO_BANK0_GPIO3_STATUS_OUTFROMPERI_Msk (0x100UL) /*!< OUTFROMPERI (Bitfield-Mask: 0x01) */
/* ====================================================== GPIO3_CTRL ======================================================= */
#define IO_BANK0_GPIO3_CTRL_IRQOVER_Pos (28UL) /*!< IRQOVER (Bit 28) */
#define IO_BANK0_GPIO3_CTRL_IRQOVER_Msk (0x30000000UL) /*!< IRQOVER (Bitfield-Mask: 0x03) */
#define IO_BANK0_GPIO3_CTRL_INOVER_Pos (16UL) /*!< INOVER (Bit 16) */
#define IO_BANK0_GPIO3_CTRL_INOVER_Msk (0x30000UL) /*!< INOVER (Bitfield-Mask: 0x03) */
#define IO_BANK0_GPIO3_CTRL_OEOVER_Pos (12UL) /*!< OEOVER (Bit 12) */
#define IO_BANK0_GPIO3_CTRL_OEOVER_Msk (0x3000UL) /*!< OEOVER (Bitfield-Mask: 0x03) */
#define IO_BANK0_GPIO3_CTRL_OUTOVER_Pos (8UL) /*!< OUTOVER (Bit 8) */
#define IO_BANK0_GPIO3_CTRL_OUTOVER_Msk (0x300UL) /*!< OUTOVER (Bitfield-Mask: 0x03) */
#define IO_BANK0_GPIO3_CTRL_FUNCSEL_Pos (0UL) /*!< FUNCSEL (Bit 0) */
#define IO_BANK0_GPIO3_CTRL_FUNCSEL_Msk (0x1fUL) /*!< FUNCSEL (Bitfield-Mask: 0x1f) */
/* ===================================================== GPIO4_STATUS ====================================================== */
#define IO_BANK0_GPIO4_STATUS_IRQTOPROC_Pos (26UL) /*!< IRQTOPROC (Bit 26) */
#define IO_BANK0_GPIO4_STATUS_IRQTOPROC_Msk (0x4000000UL) /*!< IRQTOPROC (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO4_STATUS_IRQFROMPAD_Pos (24UL) /*!< IRQFROMPAD (Bit 24) */
#define IO_BANK0_GPIO4_STATUS_IRQFROMPAD_Msk (0x1000000UL) /*!< IRQFROMPAD (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO4_STATUS_INTOPERI_Pos (19UL) /*!< INTOPERI (Bit 19) */
#define IO_BANK0_GPIO4_STATUS_INTOPERI_Msk (0x80000UL) /*!< INTOPERI (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO4_STATUS_INFROMPAD_Pos (17UL) /*!< INFROMPAD (Bit 17) */
#define IO_BANK0_GPIO4_STATUS_INFROMPAD_Msk (0x20000UL) /*!< INFROMPAD (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO4_STATUS_OETOPAD_Pos (13UL) /*!< OETOPAD (Bit 13) */
#define IO_BANK0_GPIO4_STATUS_OETOPAD_Msk (0x2000UL) /*!< OETOPAD (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO4_STATUS_OEFROMPERI_Pos (12UL) /*!< OEFROMPERI (Bit 12) */
#define IO_BANK0_GPIO4_STATUS_OEFROMPERI_Msk (0x1000UL) /*!< OEFROMPERI (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO4_STATUS_OUTTOPAD_Pos (9UL) /*!< OUTTOPAD (Bit 9) */
#define IO_BANK0_GPIO4_STATUS_OUTTOPAD_Msk (0x200UL) /*!< OUTTOPAD (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO4_STATUS_OUTFROMPERI_Pos (8UL) /*!< OUTFROMPERI (Bit 8) */
#define IO_BANK0_GPIO4_STATUS_OUTFROMPERI_Msk (0x100UL) /*!< OUTFROMPERI (Bitfield-Mask: 0x01) */
/* ====================================================== GPIO4_CTRL ======================================================= */
#define IO_BANK0_GPIO4_CTRL_IRQOVER_Pos (28UL) /*!< IRQOVER (Bit 28) */
#define IO_BANK0_GPIO4_CTRL_IRQOVER_Msk (0x30000000UL) /*!< IRQOVER (Bitfield-Mask: 0x03) */
#define IO_BANK0_GPIO4_CTRL_INOVER_Pos (16UL) /*!< INOVER (Bit 16) */
#define IO_BANK0_GPIO4_CTRL_INOVER_Msk (0x30000UL) /*!< INOVER (Bitfield-Mask: 0x03) */
#define IO_BANK0_GPIO4_CTRL_OEOVER_Pos (12UL) /*!< OEOVER (Bit 12) */
#define IO_BANK0_GPIO4_CTRL_OEOVER_Msk (0x3000UL) /*!< OEOVER (Bitfield-Mask: 0x03) */
#define IO_BANK0_GPIO4_CTRL_OUTOVER_Pos (8UL) /*!< OUTOVER (Bit 8) */
#define IO_BANK0_GPIO4_CTRL_OUTOVER_Msk (0x300UL) /*!< OUTOVER (Bitfield-Mask: 0x03) */
#define IO_BANK0_GPIO4_CTRL_FUNCSEL_Pos (0UL) /*!< FUNCSEL (Bit 0) */
#define IO_BANK0_GPIO4_CTRL_FUNCSEL_Msk (0x1fUL) /*!< FUNCSEL (Bitfield-Mask: 0x1f) */
/* ===================================================== GPIO5_STATUS ====================================================== */
#define IO_BANK0_GPIO5_STATUS_IRQTOPROC_Pos (26UL) /*!< IRQTOPROC (Bit 26) */
#define IO_BANK0_GPIO5_STATUS_IRQTOPROC_Msk (0x4000000UL) /*!< IRQTOPROC (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO5_STATUS_IRQFROMPAD_Pos (24UL) /*!< IRQFROMPAD (Bit 24) */
#define IO_BANK0_GPIO5_STATUS_IRQFROMPAD_Msk (0x1000000UL) /*!< IRQFROMPAD (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO5_STATUS_INTOPERI_Pos (19UL) /*!< INTOPERI (Bit 19) */
#define IO_BANK0_GPIO5_STATUS_INTOPERI_Msk (0x80000UL) /*!< INTOPERI (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO5_STATUS_INFROMPAD_Pos (17UL) /*!< INFROMPAD (Bit 17) */
#define IO_BANK0_GPIO5_STATUS_INFROMPAD_Msk (0x20000UL) /*!< INFROMPAD (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO5_STATUS_OETOPAD_Pos (13UL) /*!< OETOPAD (Bit 13) */
#define IO_BANK0_GPIO5_STATUS_OETOPAD_Msk (0x2000UL) /*!< OETOPAD (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO5_STATUS_OEFROMPERI_Pos (12UL) /*!< OEFROMPERI (Bit 12) */
#define IO_BANK0_GPIO5_STATUS_OEFROMPERI_Msk (0x1000UL) /*!< OEFROMPERI (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO5_STATUS_OUTTOPAD_Pos (9UL) /*!< OUTTOPAD (Bit 9) */
#define IO_BANK0_GPIO5_STATUS_OUTTOPAD_Msk (0x200UL) /*!< OUTTOPAD (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO5_STATUS_OUTFROMPERI_Pos (8UL) /*!< OUTFROMPERI (Bit 8) */
#define IO_BANK0_GPIO5_STATUS_OUTFROMPERI_Msk (0x100UL) /*!< OUTFROMPERI (Bitfield-Mask: 0x01) */
/* ====================================================== GPIO5_CTRL ======================================================= */
#define IO_BANK0_GPIO5_CTRL_IRQOVER_Pos (28UL) /*!< IRQOVER (Bit 28) */
#define IO_BANK0_GPIO5_CTRL_IRQOVER_Msk (0x30000000UL) /*!< IRQOVER (Bitfield-Mask: 0x03) */
#define IO_BANK0_GPIO5_CTRL_INOVER_Pos (16UL) /*!< INOVER (Bit 16) */
#define IO_BANK0_GPIO5_CTRL_INOVER_Msk (0x30000UL) /*!< INOVER (Bitfield-Mask: 0x03) */
#define IO_BANK0_GPIO5_CTRL_OEOVER_Pos (12UL) /*!< OEOVER (Bit 12) */
#define IO_BANK0_GPIO5_CTRL_OEOVER_Msk (0x3000UL) /*!< OEOVER (Bitfield-Mask: 0x03) */
#define IO_BANK0_GPIO5_CTRL_OUTOVER_Pos (8UL) /*!< OUTOVER (Bit 8) */
#define IO_BANK0_GPIO5_CTRL_OUTOVER_Msk (0x300UL) /*!< OUTOVER (Bitfield-Mask: 0x03) */
#define IO_BANK0_GPIO5_CTRL_FUNCSEL_Pos (0UL) /*!< FUNCSEL (Bit 0) */
#define IO_BANK0_GPIO5_CTRL_FUNCSEL_Msk (0x1fUL) /*!< FUNCSEL (Bitfield-Mask: 0x1f) */
/* ===================================================== GPIO6_STATUS ====================================================== */
#define IO_BANK0_GPIO6_STATUS_IRQTOPROC_Pos (26UL) /*!< IRQTOPROC (Bit 26) */
#define IO_BANK0_GPIO6_STATUS_IRQTOPROC_Msk (0x4000000UL) /*!< IRQTOPROC (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO6_STATUS_IRQFROMPAD_Pos (24UL) /*!< IRQFROMPAD (Bit 24) */
#define IO_BANK0_GPIO6_STATUS_IRQFROMPAD_Msk (0x1000000UL) /*!< IRQFROMPAD (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO6_STATUS_INTOPERI_Pos (19UL) /*!< INTOPERI (Bit 19) */
#define IO_BANK0_GPIO6_STATUS_INTOPERI_Msk (0x80000UL) /*!< INTOPERI (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO6_STATUS_INFROMPAD_Pos (17UL) /*!< INFROMPAD (Bit 17) */
#define IO_BANK0_GPIO6_STATUS_INFROMPAD_Msk (0x20000UL) /*!< INFROMPAD (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO6_STATUS_OETOPAD_Pos (13UL) /*!< OETOPAD (Bit 13) */
#define IO_BANK0_GPIO6_STATUS_OETOPAD_Msk (0x2000UL) /*!< OETOPAD (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO6_STATUS_OEFROMPERI_Pos (12UL) /*!< OEFROMPERI (Bit 12) */
#define IO_BANK0_GPIO6_STATUS_OEFROMPERI_Msk (0x1000UL) /*!< OEFROMPERI (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO6_STATUS_OUTTOPAD_Pos (9UL) /*!< OUTTOPAD (Bit 9) */
#define IO_BANK0_GPIO6_STATUS_OUTTOPAD_Msk (0x200UL) /*!< OUTTOPAD (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO6_STATUS_OUTFROMPERI_Pos (8UL) /*!< OUTFROMPERI (Bit 8) */
#define IO_BANK0_GPIO6_STATUS_OUTFROMPERI_Msk (0x100UL) /*!< OUTFROMPERI (Bitfield-Mask: 0x01) */
/* ====================================================== GPIO6_CTRL ======================================================= */
#define IO_BANK0_GPIO6_CTRL_IRQOVER_Pos (28UL) /*!< IRQOVER (Bit 28) */
#define IO_BANK0_GPIO6_CTRL_IRQOVER_Msk (0x30000000UL) /*!< IRQOVER (Bitfield-Mask: 0x03) */
#define IO_BANK0_GPIO6_CTRL_INOVER_Pos (16UL) /*!< INOVER (Bit 16) */
#define IO_BANK0_GPIO6_CTRL_INOVER_Msk (0x30000UL) /*!< INOVER (Bitfield-Mask: 0x03) */
#define IO_BANK0_GPIO6_CTRL_OEOVER_Pos (12UL) /*!< OEOVER (Bit 12) */
#define IO_BANK0_GPIO6_CTRL_OEOVER_Msk (0x3000UL) /*!< OEOVER (Bitfield-Mask: 0x03) */
#define IO_BANK0_GPIO6_CTRL_OUTOVER_Pos (8UL) /*!< OUTOVER (Bit 8) */
#define IO_BANK0_GPIO6_CTRL_OUTOVER_Msk (0x300UL) /*!< OUTOVER (Bitfield-Mask: 0x03) */
#define IO_BANK0_GPIO6_CTRL_FUNCSEL_Pos (0UL) /*!< FUNCSEL (Bit 0) */
#define IO_BANK0_GPIO6_CTRL_FUNCSEL_Msk (0x1fUL) /*!< FUNCSEL (Bitfield-Mask: 0x1f) */
/* ===================================================== GPIO7_STATUS ====================================================== */
#define IO_BANK0_GPIO7_STATUS_IRQTOPROC_Pos (26UL) /*!< IRQTOPROC (Bit 26) */
#define IO_BANK0_GPIO7_STATUS_IRQTOPROC_Msk (0x4000000UL) /*!< IRQTOPROC (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO7_STATUS_IRQFROMPAD_Pos (24UL) /*!< IRQFROMPAD (Bit 24) */
#define IO_BANK0_GPIO7_STATUS_IRQFROMPAD_Msk (0x1000000UL) /*!< IRQFROMPAD (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO7_STATUS_INTOPERI_Pos (19UL) /*!< INTOPERI (Bit 19) */
#define IO_BANK0_GPIO7_STATUS_INTOPERI_Msk (0x80000UL) /*!< INTOPERI (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO7_STATUS_INFROMPAD_Pos (17UL) /*!< INFROMPAD (Bit 17) */
#define IO_BANK0_GPIO7_STATUS_INFROMPAD_Msk (0x20000UL) /*!< INFROMPAD (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO7_STATUS_OETOPAD_Pos (13UL) /*!< OETOPAD (Bit 13) */
#define IO_BANK0_GPIO7_STATUS_OETOPAD_Msk (0x2000UL) /*!< OETOPAD (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO7_STATUS_OEFROMPERI_Pos (12UL) /*!< OEFROMPERI (Bit 12) */
#define IO_BANK0_GPIO7_STATUS_OEFROMPERI_Msk (0x1000UL) /*!< OEFROMPERI (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO7_STATUS_OUTTOPAD_Pos (9UL) /*!< OUTTOPAD (Bit 9) */
#define IO_BANK0_GPIO7_STATUS_OUTTOPAD_Msk (0x200UL) /*!< OUTTOPAD (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO7_STATUS_OUTFROMPERI_Pos (8UL) /*!< OUTFROMPERI (Bit 8) */
#define IO_BANK0_GPIO7_STATUS_OUTFROMPERI_Msk (0x100UL) /*!< OUTFROMPERI (Bitfield-Mask: 0x01) */
/* ====================================================== GPIO7_CTRL ======================================================= */
#define IO_BANK0_GPIO7_CTRL_IRQOVER_Pos (28UL) /*!< IRQOVER (Bit 28) */
#define IO_BANK0_GPIO7_CTRL_IRQOVER_Msk (0x30000000UL) /*!< IRQOVER (Bitfield-Mask: 0x03) */
#define IO_BANK0_GPIO7_CTRL_INOVER_Pos (16UL) /*!< INOVER (Bit 16) */
#define IO_BANK0_GPIO7_CTRL_INOVER_Msk (0x30000UL) /*!< INOVER (Bitfield-Mask: 0x03) */
#define IO_BANK0_GPIO7_CTRL_OEOVER_Pos (12UL) /*!< OEOVER (Bit 12) */
#define IO_BANK0_GPIO7_CTRL_OEOVER_Msk (0x3000UL) /*!< OEOVER (Bitfield-Mask: 0x03) */
#define IO_BANK0_GPIO7_CTRL_OUTOVER_Pos (8UL) /*!< OUTOVER (Bit 8) */
#define IO_BANK0_GPIO7_CTRL_OUTOVER_Msk (0x300UL) /*!< OUTOVER (Bitfield-Mask: 0x03) */
#define IO_BANK0_GPIO7_CTRL_FUNCSEL_Pos (0UL) /*!< FUNCSEL (Bit 0) */
#define IO_BANK0_GPIO7_CTRL_FUNCSEL_Msk (0x1fUL) /*!< FUNCSEL (Bitfield-Mask: 0x1f) */
/* ===================================================== GPIO8_STATUS ====================================================== */
#define IO_BANK0_GPIO8_STATUS_IRQTOPROC_Pos (26UL) /*!< IRQTOPROC (Bit 26) */
#define IO_BANK0_GPIO8_STATUS_IRQTOPROC_Msk (0x4000000UL) /*!< IRQTOPROC (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO8_STATUS_IRQFROMPAD_Pos (24UL) /*!< IRQFROMPAD (Bit 24) */
#define IO_BANK0_GPIO8_STATUS_IRQFROMPAD_Msk (0x1000000UL) /*!< IRQFROMPAD (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO8_STATUS_INTOPERI_Pos (19UL) /*!< INTOPERI (Bit 19) */
#define IO_BANK0_GPIO8_STATUS_INTOPERI_Msk (0x80000UL) /*!< INTOPERI (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO8_STATUS_INFROMPAD_Pos (17UL) /*!< INFROMPAD (Bit 17) */
#define IO_BANK0_GPIO8_STATUS_INFROMPAD_Msk (0x20000UL) /*!< INFROMPAD (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO8_STATUS_OETOPAD_Pos (13UL) /*!< OETOPAD (Bit 13) */
#define IO_BANK0_GPIO8_STATUS_OETOPAD_Msk (0x2000UL) /*!< OETOPAD (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO8_STATUS_OEFROMPERI_Pos (12UL) /*!< OEFROMPERI (Bit 12) */
#define IO_BANK0_GPIO8_STATUS_OEFROMPERI_Msk (0x1000UL) /*!< OEFROMPERI (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO8_STATUS_OUTTOPAD_Pos (9UL) /*!< OUTTOPAD (Bit 9) */
#define IO_BANK0_GPIO8_STATUS_OUTTOPAD_Msk (0x200UL) /*!< OUTTOPAD (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO8_STATUS_OUTFROMPERI_Pos (8UL) /*!< OUTFROMPERI (Bit 8) */
#define IO_BANK0_GPIO8_STATUS_OUTFROMPERI_Msk (0x100UL) /*!< OUTFROMPERI (Bitfield-Mask: 0x01) */
/* ====================================================== GPIO8_CTRL ======================================================= */
#define IO_BANK0_GPIO8_CTRL_IRQOVER_Pos (28UL) /*!< IRQOVER (Bit 28) */
#define IO_BANK0_GPIO8_CTRL_IRQOVER_Msk (0x30000000UL) /*!< IRQOVER (Bitfield-Mask: 0x03) */
#define IO_BANK0_GPIO8_CTRL_INOVER_Pos (16UL) /*!< INOVER (Bit 16) */
#define IO_BANK0_GPIO8_CTRL_INOVER_Msk (0x30000UL) /*!< INOVER (Bitfield-Mask: 0x03) */
#define IO_BANK0_GPIO8_CTRL_OEOVER_Pos (12UL) /*!< OEOVER (Bit 12) */
#define IO_BANK0_GPIO8_CTRL_OEOVER_Msk (0x3000UL) /*!< OEOVER (Bitfield-Mask: 0x03) */
#define IO_BANK0_GPIO8_CTRL_OUTOVER_Pos (8UL) /*!< OUTOVER (Bit 8) */
#define IO_BANK0_GPIO8_CTRL_OUTOVER_Msk (0x300UL) /*!< OUTOVER (Bitfield-Mask: 0x03) */
#define IO_BANK0_GPIO8_CTRL_FUNCSEL_Pos (0UL) /*!< FUNCSEL (Bit 0) */
#define IO_BANK0_GPIO8_CTRL_FUNCSEL_Msk (0x1fUL) /*!< FUNCSEL (Bitfield-Mask: 0x1f) */
/* ===================================================== GPIO9_STATUS ====================================================== */
#define IO_BANK0_GPIO9_STATUS_IRQTOPROC_Pos (26UL) /*!< IRQTOPROC (Bit 26) */
#define IO_BANK0_GPIO9_STATUS_IRQTOPROC_Msk (0x4000000UL) /*!< IRQTOPROC (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO9_STATUS_IRQFROMPAD_Pos (24UL) /*!< IRQFROMPAD (Bit 24) */
#define IO_BANK0_GPIO9_STATUS_IRQFROMPAD_Msk (0x1000000UL) /*!< IRQFROMPAD (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO9_STATUS_INTOPERI_Pos (19UL) /*!< INTOPERI (Bit 19) */
#define IO_BANK0_GPIO9_STATUS_INTOPERI_Msk (0x80000UL) /*!< INTOPERI (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO9_STATUS_INFROMPAD_Pos (17UL) /*!< INFROMPAD (Bit 17) */
#define IO_BANK0_GPIO9_STATUS_INFROMPAD_Msk (0x20000UL) /*!< INFROMPAD (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO9_STATUS_OETOPAD_Pos (13UL) /*!< OETOPAD (Bit 13) */
#define IO_BANK0_GPIO9_STATUS_OETOPAD_Msk (0x2000UL) /*!< OETOPAD (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO9_STATUS_OEFROMPERI_Pos (12UL) /*!< OEFROMPERI (Bit 12) */
#define IO_BANK0_GPIO9_STATUS_OEFROMPERI_Msk (0x1000UL) /*!< OEFROMPERI (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO9_STATUS_OUTTOPAD_Pos (9UL) /*!< OUTTOPAD (Bit 9) */
#define IO_BANK0_GPIO9_STATUS_OUTTOPAD_Msk (0x200UL) /*!< OUTTOPAD (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO9_STATUS_OUTFROMPERI_Pos (8UL) /*!< OUTFROMPERI (Bit 8) */
#define IO_BANK0_GPIO9_STATUS_OUTFROMPERI_Msk (0x100UL) /*!< OUTFROMPERI (Bitfield-Mask: 0x01) */
/* ====================================================== GPIO9_CTRL ======================================================= */
#define IO_BANK0_GPIO9_CTRL_IRQOVER_Pos (28UL) /*!< IRQOVER (Bit 28) */
#define IO_BANK0_GPIO9_CTRL_IRQOVER_Msk (0x30000000UL) /*!< IRQOVER (Bitfield-Mask: 0x03) */
#define IO_BANK0_GPIO9_CTRL_INOVER_Pos (16UL) /*!< INOVER (Bit 16) */
#define IO_BANK0_GPIO9_CTRL_INOVER_Msk (0x30000UL) /*!< INOVER (Bitfield-Mask: 0x03) */
#define IO_BANK0_GPIO9_CTRL_OEOVER_Pos (12UL) /*!< OEOVER (Bit 12) */
#define IO_BANK0_GPIO9_CTRL_OEOVER_Msk (0x3000UL) /*!< OEOVER (Bitfield-Mask: 0x03) */
#define IO_BANK0_GPIO9_CTRL_OUTOVER_Pos (8UL) /*!< OUTOVER (Bit 8) */
#define IO_BANK0_GPIO9_CTRL_OUTOVER_Msk (0x300UL) /*!< OUTOVER (Bitfield-Mask: 0x03) */
#define IO_BANK0_GPIO9_CTRL_FUNCSEL_Pos (0UL) /*!< FUNCSEL (Bit 0) */
#define IO_BANK0_GPIO9_CTRL_FUNCSEL_Msk (0x1fUL) /*!< FUNCSEL (Bitfield-Mask: 0x1f) */
/* ===================================================== GPIO10_STATUS ===================================================== */
#define IO_BANK0_GPIO10_STATUS_IRQTOPROC_Pos (26UL) /*!< IRQTOPROC (Bit 26) */
#define IO_BANK0_GPIO10_STATUS_IRQTOPROC_Msk (0x4000000UL) /*!< IRQTOPROC (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO10_STATUS_IRQFROMPAD_Pos (24UL) /*!< IRQFROMPAD (Bit 24) */
#define IO_BANK0_GPIO10_STATUS_IRQFROMPAD_Msk (0x1000000UL) /*!< IRQFROMPAD (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO10_STATUS_INTOPERI_Pos (19UL) /*!< INTOPERI (Bit 19) */
#define IO_BANK0_GPIO10_STATUS_INTOPERI_Msk (0x80000UL) /*!< INTOPERI (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO10_STATUS_INFROMPAD_Pos (17UL) /*!< INFROMPAD (Bit 17) */
#define IO_BANK0_GPIO10_STATUS_INFROMPAD_Msk (0x20000UL) /*!< INFROMPAD (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO10_STATUS_OETOPAD_Pos (13UL) /*!< OETOPAD (Bit 13) */
#define IO_BANK0_GPIO10_STATUS_OETOPAD_Msk (0x2000UL) /*!< OETOPAD (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO10_STATUS_OEFROMPERI_Pos (12UL) /*!< OEFROMPERI (Bit 12) */
#define IO_BANK0_GPIO10_STATUS_OEFROMPERI_Msk (0x1000UL) /*!< OEFROMPERI (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO10_STATUS_OUTTOPAD_Pos (9UL) /*!< OUTTOPAD (Bit 9) */
#define IO_BANK0_GPIO10_STATUS_OUTTOPAD_Msk (0x200UL) /*!< OUTTOPAD (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO10_STATUS_OUTFROMPERI_Pos (8UL) /*!< OUTFROMPERI (Bit 8) */
#define IO_BANK0_GPIO10_STATUS_OUTFROMPERI_Msk (0x100UL) /*!< OUTFROMPERI (Bitfield-Mask: 0x01) */
/* ====================================================== GPIO10_CTRL ====================================================== */
#define IO_BANK0_GPIO10_CTRL_IRQOVER_Pos (28UL) /*!< IRQOVER (Bit 28) */
#define IO_BANK0_GPIO10_CTRL_IRQOVER_Msk (0x30000000UL) /*!< IRQOVER (Bitfield-Mask: 0x03) */
#define IO_BANK0_GPIO10_CTRL_INOVER_Pos (16UL) /*!< INOVER (Bit 16) */
#define IO_BANK0_GPIO10_CTRL_INOVER_Msk (0x30000UL) /*!< INOVER (Bitfield-Mask: 0x03) */
#define IO_BANK0_GPIO10_CTRL_OEOVER_Pos (12UL) /*!< OEOVER (Bit 12) */
#define IO_BANK0_GPIO10_CTRL_OEOVER_Msk (0x3000UL) /*!< OEOVER (Bitfield-Mask: 0x03) */
#define IO_BANK0_GPIO10_CTRL_OUTOVER_Pos (8UL) /*!< OUTOVER (Bit 8) */
#define IO_BANK0_GPIO10_CTRL_OUTOVER_Msk (0x300UL) /*!< OUTOVER (Bitfield-Mask: 0x03) */
#define IO_BANK0_GPIO10_CTRL_FUNCSEL_Pos (0UL) /*!< FUNCSEL (Bit 0) */
#define IO_BANK0_GPIO10_CTRL_FUNCSEL_Msk (0x1fUL) /*!< FUNCSEL (Bitfield-Mask: 0x1f) */
/* ===================================================== GPIO11_STATUS ===================================================== */
#define IO_BANK0_GPIO11_STATUS_IRQTOPROC_Pos (26UL) /*!< IRQTOPROC (Bit 26) */
#define IO_BANK0_GPIO11_STATUS_IRQTOPROC_Msk (0x4000000UL) /*!< IRQTOPROC (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO11_STATUS_IRQFROMPAD_Pos (24UL) /*!< IRQFROMPAD (Bit 24) */
#define IO_BANK0_GPIO11_STATUS_IRQFROMPAD_Msk (0x1000000UL) /*!< IRQFROMPAD (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO11_STATUS_INTOPERI_Pos (19UL) /*!< INTOPERI (Bit 19) */
#define IO_BANK0_GPIO11_STATUS_INTOPERI_Msk (0x80000UL) /*!< INTOPERI (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO11_STATUS_INFROMPAD_Pos (17UL) /*!< INFROMPAD (Bit 17) */
#define IO_BANK0_GPIO11_STATUS_INFROMPAD_Msk (0x20000UL) /*!< INFROMPAD (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO11_STATUS_OETOPAD_Pos (13UL) /*!< OETOPAD (Bit 13) */
#define IO_BANK0_GPIO11_STATUS_OETOPAD_Msk (0x2000UL) /*!< OETOPAD (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO11_STATUS_OEFROMPERI_Pos (12UL) /*!< OEFROMPERI (Bit 12) */
#define IO_BANK0_GPIO11_STATUS_OEFROMPERI_Msk (0x1000UL) /*!< OEFROMPERI (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO11_STATUS_OUTTOPAD_Pos (9UL) /*!< OUTTOPAD (Bit 9) */
#define IO_BANK0_GPIO11_STATUS_OUTTOPAD_Msk (0x200UL) /*!< OUTTOPAD (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO11_STATUS_OUTFROMPERI_Pos (8UL) /*!< OUTFROMPERI (Bit 8) */
#define IO_BANK0_GPIO11_STATUS_OUTFROMPERI_Msk (0x100UL) /*!< OUTFROMPERI (Bitfield-Mask: 0x01) */
/* ====================================================== GPIO11_CTRL ====================================================== */
#define IO_BANK0_GPIO11_CTRL_IRQOVER_Pos (28UL) /*!< IRQOVER (Bit 28) */
#define IO_BANK0_GPIO11_CTRL_IRQOVER_Msk (0x30000000UL) /*!< IRQOVER (Bitfield-Mask: 0x03) */
#define IO_BANK0_GPIO11_CTRL_INOVER_Pos (16UL) /*!< INOVER (Bit 16) */
#define IO_BANK0_GPIO11_CTRL_INOVER_Msk (0x30000UL) /*!< INOVER (Bitfield-Mask: 0x03) */
#define IO_BANK0_GPIO11_CTRL_OEOVER_Pos (12UL) /*!< OEOVER (Bit 12) */
#define IO_BANK0_GPIO11_CTRL_OEOVER_Msk (0x3000UL) /*!< OEOVER (Bitfield-Mask: 0x03) */
#define IO_BANK0_GPIO11_CTRL_OUTOVER_Pos (8UL) /*!< OUTOVER (Bit 8) */
#define IO_BANK0_GPIO11_CTRL_OUTOVER_Msk (0x300UL) /*!< OUTOVER (Bitfield-Mask: 0x03) */
#define IO_BANK0_GPIO11_CTRL_FUNCSEL_Pos (0UL) /*!< FUNCSEL (Bit 0) */
#define IO_BANK0_GPIO11_CTRL_FUNCSEL_Msk (0x1fUL) /*!< FUNCSEL (Bitfield-Mask: 0x1f) */
/* ===================================================== GPIO12_STATUS ===================================================== */
#define IO_BANK0_GPIO12_STATUS_IRQTOPROC_Pos (26UL) /*!< IRQTOPROC (Bit 26) */
#define IO_BANK0_GPIO12_STATUS_IRQTOPROC_Msk (0x4000000UL) /*!< IRQTOPROC (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO12_STATUS_IRQFROMPAD_Pos (24UL) /*!< IRQFROMPAD (Bit 24) */
#define IO_BANK0_GPIO12_STATUS_IRQFROMPAD_Msk (0x1000000UL) /*!< IRQFROMPAD (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO12_STATUS_INTOPERI_Pos (19UL) /*!< INTOPERI (Bit 19) */
#define IO_BANK0_GPIO12_STATUS_INTOPERI_Msk (0x80000UL) /*!< INTOPERI (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO12_STATUS_INFROMPAD_Pos (17UL) /*!< INFROMPAD (Bit 17) */
#define IO_BANK0_GPIO12_STATUS_INFROMPAD_Msk (0x20000UL) /*!< INFROMPAD (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO12_STATUS_OETOPAD_Pos (13UL) /*!< OETOPAD (Bit 13) */
#define IO_BANK0_GPIO12_STATUS_OETOPAD_Msk (0x2000UL) /*!< OETOPAD (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO12_STATUS_OEFROMPERI_Pos (12UL) /*!< OEFROMPERI (Bit 12) */
#define IO_BANK0_GPIO12_STATUS_OEFROMPERI_Msk (0x1000UL) /*!< OEFROMPERI (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO12_STATUS_OUTTOPAD_Pos (9UL) /*!< OUTTOPAD (Bit 9) */
#define IO_BANK0_GPIO12_STATUS_OUTTOPAD_Msk (0x200UL) /*!< OUTTOPAD (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO12_STATUS_OUTFROMPERI_Pos (8UL) /*!< OUTFROMPERI (Bit 8) */
#define IO_BANK0_GPIO12_STATUS_OUTFROMPERI_Msk (0x100UL) /*!< OUTFROMPERI (Bitfield-Mask: 0x01) */
/* ====================================================== GPIO12_CTRL ====================================================== */
#define IO_BANK0_GPIO12_CTRL_IRQOVER_Pos (28UL) /*!< IRQOVER (Bit 28) */
#define IO_BANK0_GPIO12_CTRL_IRQOVER_Msk (0x30000000UL) /*!< IRQOVER (Bitfield-Mask: 0x03) */
#define IO_BANK0_GPIO12_CTRL_INOVER_Pos (16UL) /*!< INOVER (Bit 16) */
#define IO_BANK0_GPIO12_CTRL_INOVER_Msk (0x30000UL) /*!< INOVER (Bitfield-Mask: 0x03) */
#define IO_BANK0_GPIO12_CTRL_OEOVER_Pos (12UL) /*!< OEOVER (Bit 12) */
#define IO_BANK0_GPIO12_CTRL_OEOVER_Msk (0x3000UL) /*!< OEOVER (Bitfield-Mask: 0x03) */
#define IO_BANK0_GPIO12_CTRL_OUTOVER_Pos (8UL) /*!< OUTOVER (Bit 8) */
#define IO_BANK0_GPIO12_CTRL_OUTOVER_Msk (0x300UL) /*!< OUTOVER (Bitfield-Mask: 0x03) */
#define IO_BANK0_GPIO12_CTRL_FUNCSEL_Pos (0UL) /*!< FUNCSEL (Bit 0) */
#define IO_BANK0_GPIO12_CTRL_FUNCSEL_Msk (0x1fUL) /*!< FUNCSEL (Bitfield-Mask: 0x1f) */
/* ===================================================== GPIO13_STATUS ===================================================== */
#define IO_BANK0_GPIO13_STATUS_IRQTOPROC_Pos (26UL) /*!< IRQTOPROC (Bit 26) */
#define IO_BANK0_GPIO13_STATUS_IRQTOPROC_Msk (0x4000000UL) /*!< IRQTOPROC (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO13_STATUS_IRQFROMPAD_Pos (24UL) /*!< IRQFROMPAD (Bit 24) */
#define IO_BANK0_GPIO13_STATUS_IRQFROMPAD_Msk (0x1000000UL) /*!< IRQFROMPAD (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO13_STATUS_INTOPERI_Pos (19UL) /*!< INTOPERI (Bit 19) */
#define IO_BANK0_GPIO13_STATUS_INTOPERI_Msk (0x80000UL) /*!< INTOPERI (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO13_STATUS_INFROMPAD_Pos (17UL) /*!< INFROMPAD (Bit 17) */
#define IO_BANK0_GPIO13_STATUS_INFROMPAD_Msk (0x20000UL) /*!< INFROMPAD (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO13_STATUS_OETOPAD_Pos (13UL) /*!< OETOPAD (Bit 13) */
#define IO_BANK0_GPIO13_STATUS_OETOPAD_Msk (0x2000UL) /*!< OETOPAD (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO13_STATUS_OEFROMPERI_Pos (12UL) /*!< OEFROMPERI (Bit 12) */
#define IO_BANK0_GPIO13_STATUS_OEFROMPERI_Msk (0x1000UL) /*!< OEFROMPERI (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO13_STATUS_OUTTOPAD_Pos (9UL) /*!< OUTTOPAD (Bit 9) */
#define IO_BANK0_GPIO13_STATUS_OUTTOPAD_Msk (0x200UL) /*!< OUTTOPAD (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO13_STATUS_OUTFROMPERI_Pos (8UL) /*!< OUTFROMPERI (Bit 8) */
#define IO_BANK0_GPIO13_STATUS_OUTFROMPERI_Msk (0x100UL) /*!< OUTFROMPERI (Bitfield-Mask: 0x01) */
/* ====================================================== GPIO13_CTRL ====================================================== */
#define IO_BANK0_GPIO13_CTRL_IRQOVER_Pos (28UL) /*!< IRQOVER (Bit 28) */
#define IO_BANK0_GPIO13_CTRL_IRQOVER_Msk (0x30000000UL) /*!< IRQOVER (Bitfield-Mask: 0x03) */
#define IO_BANK0_GPIO13_CTRL_INOVER_Pos (16UL) /*!< INOVER (Bit 16) */
#define IO_BANK0_GPIO13_CTRL_INOVER_Msk (0x30000UL) /*!< INOVER (Bitfield-Mask: 0x03) */
#define IO_BANK0_GPIO13_CTRL_OEOVER_Pos (12UL) /*!< OEOVER (Bit 12) */
#define IO_BANK0_GPIO13_CTRL_OEOVER_Msk (0x3000UL) /*!< OEOVER (Bitfield-Mask: 0x03) */
#define IO_BANK0_GPIO13_CTRL_OUTOVER_Pos (8UL) /*!< OUTOVER (Bit 8) */
#define IO_BANK0_GPIO13_CTRL_OUTOVER_Msk (0x300UL) /*!< OUTOVER (Bitfield-Mask: 0x03) */
#define IO_BANK0_GPIO13_CTRL_FUNCSEL_Pos (0UL) /*!< FUNCSEL (Bit 0) */
#define IO_BANK0_GPIO13_CTRL_FUNCSEL_Msk (0x1fUL) /*!< FUNCSEL (Bitfield-Mask: 0x1f) */
/* ===================================================== GPIO14_STATUS ===================================================== */
#define IO_BANK0_GPIO14_STATUS_IRQTOPROC_Pos (26UL) /*!< IRQTOPROC (Bit 26) */
#define IO_BANK0_GPIO14_STATUS_IRQTOPROC_Msk (0x4000000UL) /*!< IRQTOPROC (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO14_STATUS_IRQFROMPAD_Pos (24UL) /*!< IRQFROMPAD (Bit 24) */
#define IO_BANK0_GPIO14_STATUS_IRQFROMPAD_Msk (0x1000000UL) /*!< IRQFROMPAD (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO14_STATUS_INTOPERI_Pos (19UL) /*!< INTOPERI (Bit 19) */
#define IO_BANK0_GPIO14_STATUS_INTOPERI_Msk (0x80000UL) /*!< INTOPERI (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO14_STATUS_INFROMPAD_Pos (17UL) /*!< INFROMPAD (Bit 17) */
#define IO_BANK0_GPIO14_STATUS_INFROMPAD_Msk (0x20000UL) /*!< INFROMPAD (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO14_STATUS_OETOPAD_Pos (13UL) /*!< OETOPAD (Bit 13) */
#define IO_BANK0_GPIO14_STATUS_OETOPAD_Msk (0x2000UL) /*!< OETOPAD (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO14_STATUS_OEFROMPERI_Pos (12UL) /*!< OEFROMPERI (Bit 12) */
#define IO_BANK0_GPIO14_STATUS_OEFROMPERI_Msk (0x1000UL) /*!< OEFROMPERI (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO14_STATUS_OUTTOPAD_Pos (9UL) /*!< OUTTOPAD (Bit 9) */
#define IO_BANK0_GPIO14_STATUS_OUTTOPAD_Msk (0x200UL) /*!< OUTTOPAD (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO14_STATUS_OUTFROMPERI_Pos (8UL) /*!< OUTFROMPERI (Bit 8) */
#define IO_BANK0_GPIO14_STATUS_OUTFROMPERI_Msk (0x100UL) /*!< OUTFROMPERI (Bitfield-Mask: 0x01) */
/* ====================================================== GPIO14_CTRL ====================================================== */
#define IO_BANK0_GPIO14_CTRL_IRQOVER_Pos (28UL) /*!< IRQOVER (Bit 28) */
#define IO_BANK0_GPIO14_CTRL_IRQOVER_Msk (0x30000000UL) /*!< IRQOVER (Bitfield-Mask: 0x03) */
#define IO_BANK0_GPIO14_CTRL_INOVER_Pos (16UL) /*!< INOVER (Bit 16) */
#define IO_BANK0_GPIO14_CTRL_INOVER_Msk (0x30000UL) /*!< INOVER (Bitfield-Mask: 0x03) */
#define IO_BANK0_GPIO14_CTRL_OEOVER_Pos (12UL) /*!< OEOVER (Bit 12) */
#define IO_BANK0_GPIO14_CTRL_OEOVER_Msk (0x3000UL) /*!< OEOVER (Bitfield-Mask: 0x03) */
#define IO_BANK0_GPIO14_CTRL_OUTOVER_Pos (8UL) /*!< OUTOVER (Bit 8) */
#define IO_BANK0_GPIO14_CTRL_OUTOVER_Msk (0x300UL) /*!< OUTOVER (Bitfield-Mask: 0x03) */
#define IO_BANK0_GPIO14_CTRL_FUNCSEL_Pos (0UL) /*!< FUNCSEL (Bit 0) */
#define IO_BANK0_GPIO14_CTRL_FUNCSEL_Msk (0x1fUL) /*!< FUNCSEL (Bitfield-Mask: 0x1f) */
/* ===================================================== GPIO15_STATUS ===================================================== */
#define IO_BANK0_GPIO15_STATUS_IRQTOPROC_Pos (26UL) /*!< IRQTOPROC (Bit 26) */
#define IO_BANK0_GPIO15_STATUS_IRQTOPROC_Msk (0x4000000UL) /*!< IRQTOPROC (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO15_STATUS_IRQFROMPAD_Pos (24UL) /*!< IRQFROMPAD (Bit 24) */
#define IO_BANK0_GPIO15_STATUS_IRQFROMPAD_Msk (0x1000000UL) /*!< IRQFROMPAD (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO15_STATUS_INTOPERI_Pos (19UL) /*!< INTOPERI (Bit 19) */
#define IO_BANK0_GPIO15_STATUS_INTOPERI_Msk (0x80000UL) /*!< INTOPERI (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO15_STATUS_INFROMPAD_Pos (17UL) /*!< INFROMPAD (Bit 17) */
#define IO_BANK0_GPIO15_STATUS_INFROMPAD_Msk (0x20000UL) /*!< INFROMPAD (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO15_STATUS_OETOPAD_Pos (13UL) /*!< OETOPAD (Bit 13) */
#define IO_BANK0_GPIO15_STATUS_OETOPAD_Msk (0x2000UL) /*!< OETOPAD (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO15_STATUS_OEFROMPERI_Pos (12UL) /*!< OEFROMPERI (Bit 12) */
#define IO_BANK0_GPIO15_STATUS_OEFROMPERI_Msk (0x1000UL) /*!< OEFROMPERI (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO15_STATUS_OUTTOPAD_Pos (9UL) /*!< OUTTOPAD (Bit 9) */
#define IO_BANK0_GPIO15_STATUS_OUTTOPAD_Msk (0x200UL) /*!< OUTTOPAD (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO15_STATUS_OUTFROMPERI_Pos (8UL) /*!< OUTFROMPERI (Bit 8) */
#define IO_BANK0_GPIO15_STATUS_OUTFROMPERI_Msk (0x100UL) /*!< OUTFROMPERI (Bitfield-Mask: 0x01) */
/* ====================================================== GPIO15_CTRL ====================================================== */
#define IO_BANK0_GPIO15_CTRL_IRQOVER_Pos (28UL) /*!< IRQOVER (Bit 28) */
#define IO_BANK0_GPIO15_CTRL_IRQOVER_Msk (0x30000000UL) /*!< IRQOVER (Bitfield-Mask: 0x03) */
#define IO_BANK0_GPIO15_CTRL_INOVER_Pos (16UL) /*!< INOVER (Bit 16) */
#define IO_BANK0_GPIO15_CTRL_INOVER_Msk (0x30000UL) /*!< INOVER (Bitfield-Mask: 0x03) */
#define IO_BANK0_GPIO15_CTRL_OEOVER_Pos (12UL) /*!< OEOVER (Bit 12) */
#define IO_BANK0_GPIO15_CTRL_OEOVER_Msk (0x3000UL) /*!< OEOVER (Bitfield-Mask: 0x03) */
#define IO_BANK0_GPIO15_CTRL_OUTOVER_Pos (8UL) /*!< OUTOVER (Bit 8) */
#define IO_BANK0_GPIO15_CTRL_OUTOVER_Msk (0x300UL) /*!< OUTOVER (Bitfield-Mask: 0x03) */
#define IO_BANK0_GPIO15_CTRL_FUNCSEL_Pos (0UL) /*!< FUNCSEL (Bit 0) */
#define IO_BANK0_GPIO15_CTRL_FUNCSEL_Msk (0x1fUL) /*!< FUNCSEL (Bitfield-Mask: 0x1f) */
/* ===================================================== GPIO16_STATUS ===================================================== */
#define IO_BANK0_GPIO16_STATUS_IRQTOPROC_Pos (26UL) /*!< IRQTOPROC (Bit 26) */
#define IO_BANK0_GPIO16_STATUS_IRQTOPROC_Msk (0x4000000UL) /*!< IRQTOPROC (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO16_STATUS_IRQFROMPAD_Pos (24UL) /*!< IRQFROMPAD (Bit 24) */
#define IO_BANK0_GPIO16_STATUS_IRQFROMPAD_Msk (0x1000000UL) /*!< IRQFROMPAD (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO16_STATUS_INTOPERI_Pos (19UL) /*!< INTOPERI (Bit 19) */
#define IO_BANK0_GPIO16_STATUS_INTOPERI_Msk (0x80000UL) /*!< INTOPERI (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO16_STATUS_INFROMPAD_Pos (17UL) /*!< INFROMPAD (Bit 17) */
#define IO_BANK0_GPIO16_STATUS_INFROMPAD_Msk (0x20000UL) /*!< INFROMPAD (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO16_STATUS_OETOPAD_Pos (13UL) /*!< OETOPAD (Bit 13) */
#define IO_BANK0_GPIO16_STATUS_OETOPAD_Msk (0x2000UL) /*!< OETOPAD (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO16_STATUS_OEFROMPERI_Pos (12UL) /*!< OEFROMPERI (Bit 12) */
#define IO_BANK0_GPIO16_STATUS_OEFROMPERI_Msk (0x1000UL) /*!< OEFROMPERI (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO16_STATUS_OUTTOPAD_Pos (9UL) /*!< OUTTOPAD (Bit 9) */
#define IO_BANK0_GPIO16_STATUS_OUTTOPAD_Msk (0x200UL) /*!< OUTTOPAD (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO16_STATUS_OUTFROMPERI_Pos (8UL) /*!< OUTFROMPERI (Bit 8) */
#define IO_BANK0_GPIO16_STATUS_OUTFROMPERI_Msk (0x100UL) /*!< OUTFROMPERI (Bitfield-Mask: 0x01) */
/* ====================================================== GPIO16_CTRL ====================================================== */
#define IO_BANK0_GPIO16_CTRL_IRQOVER_Pos (28UL) /*!< IRQOVER (Bit 28) */
#define IO_BANK0_GPIO16_CTRL_IRQOVER_Msk (0x30000000UL) /*!< IRQOVER (Bitfield-Mask: 0x03) */
#define IO_BANK0_GPIO16_CTRL_INOVER_Pos (16UL) /*!< INOVER (Bit 16) */
#define IO_BANK0_GPIO16_CTRL_INOVER_Msk (0x30000UL) /*!< INOVER (Bitfield-Mask: 0x03) */
#define IO_BANK0_GPIO16_CTRL_OEOVER_Pos (12UL) /*!< OEOVER (Bit 12) */
#define IO_BANK0_GPIO16_CTRL_OEOVER_Msk (0x3000UL) /*!< OEOVER (Bitfield-Mask: 0x03) */
#define IO_BANK0_GPIO16_CTRL_OUTOVER_Pos (8UL) /*!< OUTOVER (Bit 8) */
#define IO_BANK0_GPIO16_CTRL_OUTOVER_Msk (0x300UL) /*!< OUTOVER (Bitfield-Mask: 0x03) */
#define IO_BANK0_GPIO16_CTRL_FUNCSEL_Pos (0UL) /*!< FUNCSEL (Bit 0) */
#define IO_BANK0_GPIO16_CTRL_FUNCSEL_Msk (0x1fUL) /*!< FUNCSEL (Bitfield-Mask: 0x1f) */
/* ===================================================== GPIO17_STATUS ===================================================== */
#define IO_BANK0_GPIO17_STATUS_IRQTOPROC_Pos (26UL) /*!< IRQTOPROC (Bit 26) */
#define IO_BANK0_GPIO17_STATUS_IRQTOPROC_Msk (0x4000000UL) /*!< IRQTOPROC (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO17_STATUS_IRQFROMPAD_Pos (24UL) /*!< IRQFROMPAD (Bit 24) */
#define IO_BANK0_GPIO17_STATUS_IRQFROMPAD_Msk (0x1000000UL) /*!< IRQFROMPAD (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO17_STATUS_INTOPERI_Pos (19UL) /*!< INTOPERI (Bit 19) */
#define IO_BANK0_GPIO17_STATUS_INTOPERI_Msk (0x80000UL) /*!< INTOPERI (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO17_STATUS_INFROMPAD_Pos (17UL) /*!< INFROMPAD (Bit 17) */
#define IO_BANK0_GPIO17_STATUS_INFROMPAD_Msk (0x20000UL) /*!< INFROMPAD (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO17_STATUS_OETOPAD_Pos (13UL) /*!< OETOPAD (Bit 13) */
#define IO_BANK0_GPIO17_STATUS_OETOPAD_Msk (0x2000UL) /*!< OETOPAD (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO17_STATUS_OEFROMPERI_Pos (12UL) /*!< OEFROMPERI (Bit 12) */
#define IO_BANK0_GPIO17_STATUS_OEFROMPERI_Msk (0x1000UL) /*!< OEFROMPERI (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO17_STATUS_OUTTOPAD_Pos (9UL) /*!< OUTTOPAD (Bit 9) */
#define IO_BANK0_GPIO17_STATUS_OUTTOPAD_Msk (0x200UL) /*!< OUTTOPAD (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO17_STATUS_OUTFROMPERI_Pos (8UL) /*!< OUTFROMPERI (Bit 8) */
#define IO_BANK0_GPIO17_STATUS_OUTFROMPERI_Msk (0x100UL) /*!< OUTFROMPERI (Bitfield-Mask: 0x01) */
/* ====================================================== GPIO17_CTRL ====================================================== */
#define IO_BANK0_GPIO17_CTRL_IRQOVER_Pos (28UL) /*!< IRQOVER (Bit 28) */
#define IO_BANK0_GPIO17_CTRL_IRQOVER_Msk (0x30000000UL) /*!< IRQOVER (Bitfield-Mask: 0x03) */
#define IO_BANK0_GPIO17_CTRL_INOVER_Pos (16UL) /*!< INOVER (Bit 16) */
#define IO_BANK0_GPIO17_CTRL_INOVER_Msk (0x30000UL) /*!< INOVER (Bitfield-Mask: 0x03) */
#define IO_BANK0_GPIO17_CTRL_OEOVER_Pos (12UL) /*!< OEOVER (Bit 12) */
#define IO_BANK0_GPIO17_CTRL_OEOVER_Msk (0x3000UL) /*!< OEOVER (Bitfield-Mask: 0x03) */
#define IO_BANK0_GPIO17_CTRL_OUTOVER_Pos (8UL) /*!< OUTOVER (Bit 8) */
#define IO_BANK0_GPIO17_CTRL_OUTOVER_Msk (0x300UL) /*!< OUTOVER (Bitfield-Mask: 0x03) */
#define IO_BANK0_GPIO17_CTRL_FUNCSEL_Pos (0UL) /*!< FUNCSEL (Bit 0) */
#define IO_BANK0_GPIO17_CTRL_FUNCSEL_Msk (0x1fUL) /*!< FUNCSEL (Bitfield-Mask: 0x1f) */
/* ===================================================== GPIO18_STATUS ===================================================== */
#define IO_BANK0_GPIO18_STATUS_IRQTOPROC_Pos (26UL) /*!< IRQTOPROC (Bit 26) */
#define IO_BANK0_GPIO18_STATUS_IRQTOPROC_Msk (0x4000000UL) /*!< IRQTOPROC (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO18_STATUS_IRQFROMPAD_Pos (24UL) /*!< IRQFROMPAD (Bit 24) */
#define IO_BANK0_GPIO18_STATUS_IRQFROMPAD_Msk (0x1000000UL) /*!< IRQFROMPAD (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO18_STATUS_INTOPERI_Pos (19UL) /*!< INTOPERI (Bit 19) */
#define IO_BANK0_GPIO18_STATUS_INTOPERI_Msk (0x80000UL) /*!< INTOPERI (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO18_STATUS_INFROMPAD_Pos (17UL) /*!< INFROMPAD (Bit 17) */
#define IO_BANK0_GPIO18_STATUS_INFROMPAD_Msk (0x20000UL) /*!< INFROMPAD (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO18_STATUS_OETOPAD_Pos (13UL) /*!< OETOPAD (Bit 13) */
#define IO_BANK0_GPIO18_STATUS_OETOPAD_Msk (0x2000UL) /*!< OETOPAD (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO18_STATUS_OEFROMPERI_Pos (12UL) /*!< OEFROMPERI (Bit 12) */
#define IO_BANK0_GPIO18_STATUS_OEFROMPERI_Msk (0x1000UL) /*!< OEFROMPERI (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO18_STATUS_OUTTOPAD_Pos (9UL) /*!< OUTTOPAD (Bit 9) */
#define IO_BANK0_GPIO18_STATUS_OUTTOPAD_Msk (0x200UL) /*!< OUTTOPAD (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO18_STATUS_OUTFROMPERI_Pos (8UL) /*!< OUTFROMPERI (Bit 8) */
#define IO_BANK0_GPIO18_STATUS_OUTFROMPERI_Msk (0x100UL) /*!< OUTFROMPERI (Bitfield-Mask: 0x01) */
/* ====================================================== GPIO18_CTRL ====================================================== */
#define IO_BANK0_GPIO18_CTRL_IRQOVER_Pos (28UL) /*!< IRQOVER (Bit 28) */
#define IO_BANK0_GPIO18_CTRL_IRQOVER_Msk (0x30000000UL) /*!< IRQOVER (Bitfield-Mask: 0x03) */
#define IO_BANK0_GPIO18_CTRL_INOVER_Pos (16UL) /*!< INOVER (Bit 16) */
#define IO_BANK0_GPIO18_CTRL_INOVER_Msk (0x30000UL) /*!< INOVER (Bitfield-Mask: 0x03) */
#define IO_BANK0_GPIO18_CTRL_OEOVER_Pos (12UL) /*!< OEOVER (Bit 12) */
#define IO_BANK0_GPIO18_CTRL_OEOVER_Msk (0x3000UL) /*!< OEOVER (Bitfield-Mask: 0x03) */
#define IO_BANK0_GPIO18_CTRL_OUTOVER_Pos (8UL) /*!< OUTOVER (Bit 8) */
#define IO_BANK0_GPIO18_CTRL_OUTOVER_Msk (0x300UL) /*!< OUTOVER (Bitfield-Mask: 0x03) */
#define IO_BANK0_GPIO18_CTRL_FUNCSEL_Pos (0UL) /*!< FUNCSEL (Bit 0) */
#define IO_BANK0_GPIO18_CTRL_FUNCSEL_Msk (0x1fUL) /*!< FUNCSEL (Bitfield-Mask: 0x1f) */
/* ===================================================== GPIO19_STATUS ===================================================== */
#define IO_BANK0_GPIO19_STATUS_IRQTOPROC_Pos (26UL) /*!< IRQTOPROC (Bit 26) */
#define IO_BANK0_GPIO19_STATUS_IRQTOPROC_Msk (0x4000000UL) /*!< IRQTOPROC (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO19_STATUS_IRQFROMPAD_Pos (24UL) /*!< IRQFROMPAD (Bit 24) */
#define IO_BANK0_GPIO19_STATUS_IRQFROMPAD_Msk (0x1000000UL) /*!< IRQFROMPAD (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO19_STATUS_INTOPERI_Pos (19UL) /*!< INTOPERI (Bit 19) */
#define IO_BANK0_GPIO19_STATUS_INTOPERI_Msk (0x80000UL) /*!< INTOPERI (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO19_STATUS_INFROMPAD_Pos (17UL) /*!< INFROMPAD (Bit 17) */
#define IO_BANK0_GPIO19_STATUS_INFROMPAD_Msk (0x20000UL) /*!< INFROMPAD (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO19_STATUS_OETOPAD_Pos (13UL) /*!< OETOPAD (Bit 13) */
#define IO_BANK0_GPIO19_STATUS_OETOPAD_Msk (0x2000UL) /*!< OETOPAD (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO19_STATUS_OEFROMPERI_Pos (12UL) /*!< OEFROMPERI (Bit 12) */
#define IO_BANK0_GPIO19_STATUS_OEFROMPERI_Msk (0x1000UL) /*!< OEFROMPERI (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO19_STATUS_OUTTOPAD_Pos (9UL) /*!< OUTTOPAD (Bit 9) */
#define IO_BANK0_GPIO19_STATUS_OUTTOPAD_Msk (0x200UL) /*!< OUTTOPAD (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO19_STATUS_OUTFROMPERI_Pos (8UL) /*!< OUTFROMPERI (Bit 8) */
#define IO_BANK0_GPIO19_STATUS_OUTFROMPERI_Msk (0x100UL) /*!< OUTFROMPERI (Bitfield-Mask: 0x01) */
/* ====================================================== GPIO19_CTRL ====================================================== */
#define IO_BANK0_GPIO19_CTRL_IRQOVER_Pos (28UL) /*!< IRQOVER (Bit 28) */
#define IO_BANK0_GPIO19_CTRL_IRQOVER_Msk (0x30000000UL) /*!< IRQOVER (Bitfield-Mask: 0x03) */
#define IO_BANK0_GPIO19_CTRL_INOVER_Pos (16UL) /*!< INOVER (Bit 16) */
#define IO_BANK0_GPIO19_CTRL_INOVER_Msk (0x30000UL) /*!< INOVER (Bitfield-Mask: 0x03) */
#define IO_BANK0_GPIO19_CTRL_OEOVER_Pos (12UL) /*!< OEOVER (Bit 12) */
#define IO_BANK0_GPIO19_CTRL_OEOVER_Msk (0x3000UL) /*!< OEOVER (Bitfield-Mask: 0x03) */
#define IO_BANK0_GPIO19_CTRL_OUTOVER_Pos (8UL) /*!< OUTOVER (Bit 8) */
#define IO_BANK0_GPIO19_CTRL_OUTOVER_Msk (0x300UL) /*!< OUTOVER (Bitfield-Mask: 0x03) */
#define IO_BANK0_GPIO19_CTRL_FUNCSEL_Pos (0UL) /*!< FUNCSEL (Bit 0) */
#define IO_BANK0_GPIO19_CTRL_FUNCSEL_Msk (0x1fUL) /*!< FUNCSEL (Bitfield-Mask: 0x1f) */
/* ===================================================== GPIO20_STATUS ===================================================== */
#define IO_BANK0_GPIO20_STATUS_IRQTOPROC_Pos (26UL) /*!< IRQTOPROC (Bit 26) */
#define IO_BANK0_GPIO20_STATUS_IRQTOPROC_Msk (0x4000000UL) /*!< IRQTOPROC (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO20_STATUS_IRQFROMPAD_Pos (24UL) /*!< IRQFROMPAD (Bit 24) */
#define IO_BANK0_GPIO20_STATUS_IRQFROMPAD_Msk (0x1000000UL) /*!< IRQFROMPAD (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO20_STATUS_INTOPERI_Pos (19UL) /*!< INTOPERI (Bit 19) */
#define IO_BANK0_GPIO20_STATUS_INTOPERI_Msk (0x80000UL) /*!< INTOPERI (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO20_STATUS_INFROMPAD_Pos (17UL) /*!< INFROMPAD (Bit 17) */
#define IO_BANK0_GPIO20_STATUS_INFROMPAD_Msk (0x20000UL) /*!< INFROMPAD (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO20_STATUS_OETOPAD_Pos (13UL) /*!< OETOPAD (Bit 13) */
#define IO_BANK0_GPIO20_STATUS_OETOPAD_Msk (0x2000UL) /*!< OETOPAD (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO20_STATUS_OEFROMPERI_Pos (12UL) /*!< OEFROMPERI (Bit 12) */
#define IO_BANK0_GPIO20_STATUS_OEFROMPERI_Msk (0x1000UL) /*!< OEFROMPERI (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO20_STATUS_OUTTOPAD_Pos (9UL) /*!< OUTTOPAD (Bit 9) */
#define IO_BANK0_GPIO20_STATUS_OUTTOPAD_Msk (0x200UL) /*!< OUTTOPAD (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO20_STATUS_OUTFROMPERI_Pos (8UL) /*!< OUTFROMPERI (Bit 8) */
#define IO_BANK0_GPIO20_STATUS_OUTFROMPERI_Msk (0x100UL) /*!< OUTFROMPERI (Bitfield-Mask: 0x01) */
/* ====================================================== GPIO20_CTRL ====================================================== */
#define IO_BANK0_GPIO20_CTRL_IRQOVER_Pos (28UL) /*!< IRQOVER (Bit 28) */
#define IO_BANK0_GPIO20_CTRL_IRQOVER_Msk (0x30000000UL) /*!< IRQOVER (Bitfield-Mask: 0x03) */
#define IO_BANK0_GPIO20_CTRL_INOVER_Pos (16UL) /*!< INOVER (Bit 16) */
#define IO_BANK0_GPIO20_CTRL_INOVER_Msk (0x30000UL) /*!< INOVER (Bitfield-Mask: 0x03) */
#define IO_BANK0_GPIO20_CTRL_OEOVER_Pos (12UL) /*!< OEOVER (Bit 12) */
#define IO_BANK0_GPIO20_CTRL_OEOVER_Msk (0x3000UL) /*!< OEOVER (Bitfield-Mask: 0x03) */
#define IO_BANK0_GPIO20_CTRL_OUTOVER_Pos (8UL) /*!< OUTOVER (Bit 8) */
#define IO_BANK0_GPIO20_CTRL_OUTOVER_Msk (0x300UL) /*!< OUTOVER (Bitfield-Mask: 0x03) */
#define IO_BANK0_GPIO20_CTRL_FUNCSEL_Pos (0UL) /*!< FUNCSEL (Bit 0) */
#define IO_BANK0_GPIO20_CTRL_FUNCSEL_Msk (0x1fUL) /*!< FUNCSEL (Bitfield-Mask: 0x1f) */
/* ===================================================== GPIO21_STATUS ===================================================== */
#define IO_BANK0_GPIO21_STATUS_IRQTOPROC_Pos (26UL) /*!< IRQTOPROC (Bit 26) */
#define IO_BANK0_GPIO21_STATUS_IRQTOPROC_Msk (0x4000000UL) /*!< IRQTOPROC (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO21_STATUS_IRQFROMPAD_Pos (24UL) /*!< IRQFROMPAD (Bit 24) */
#define IO_BANK0_GPIO21_STATUS_IRQFROMPAD_Msk (0x1000000UL) /*!< IRQFROMPAD (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO21_STATUS_INTOPERI_Pos (19UL) /*!< INTOPERI (Bit 19) */
#define IO_BANK0_GPIO21_STATUS_INTOPERI_Msk (0x80000UL) /*!< INTOPERI (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO21_STATUS_INFROMPAD_Pos (17UL) /*!< INFROMPAD (Bit 17) */
#define IO_BANK0_GPIO21_STATUS_INFROMPAD_Msk (0x20000UL) /*!< INFROMPAD (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO21_STATUS_OETOPAD_Pos (13UL) /*!< OETOPAD (Bit 13) */
#define IO_BANK0_GPIO21_STATUS_OETOPAD_Msk (0x2000UL) /*!< OETOPAD (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO21_STATUS_OEFROMPERI_Pos (12UL) /*!< OEFROMPERI (Bit 12) */
#define IO_BANK0_GPIO21_STATUS_OEFROMPERI_Msk (0x1000UL) /*!< OEFROMPERI (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO21_STATUS_OUTTOPAD_Pos (9UL) /*!< OUTTOPAD (Bit 9) */
#define IO_BANK0_GPIO21_STATUS_OUTTOPAD_Msk (0x200UL) /*!< OUTTOPAD (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO21_STATUS_OUTFROMPERI_Pos (8UL) /*!< OUTFROMPERI (Bit 8) */
#define IO_BANK0_GPIO21_STATUS_OUTFROMPERI_Msk (0x100UL) /*!< OUTFROMPERI (Bitfield-Mask: 0x01) */
/* ====================================================== GPIO21_CTRL ====================================================== */
#define IO_BANK0_GPIO21_CTRL_IRQOVER_Pos (28UL) /*!< IRQOVER (Bit 28) */
#define IO_BANK0_GPIO21_CTRL_IRQOVER_Msk (0x30000000UL) /*!< IRQOVER (Bitfield-Mask: 0x03) */
#define IO_BANK0_GPIO21_CTRL_INOVER_Pos (16UL) /*!< INOVER (Bit 16) */
#define IO_BANK0_GPIO21_CTRL_INOVER_Msk (0x30000UL) /*!< INOVER (Bitfield-Mask: 0x03) */
#define IO_BANK0_GPIO21_CTRL_OEOVER_Pos (12UL) /*!< OEOVER (Bit 12) */
#define IO_BANK0_GPIO21_CTRL_OEOVER_Msk (0x3000UL) /*!< OEOVER (Bitfield-Mask: 0x03) */
#define IO_BANK0_GPIO21_CTRL_OUTOVER_Pos (8UL) /*!< OUTOVER (Bit 8) */
#define IO_BANK0_GPIO21_CTRL_OUTOVER_Msk (0x300UL) /*!< OUTOVER (Bitfield-Mask: 0x03) */
#define IO_BANK0_GPIO21_CTRL_FUNCSEL_Pos (0UL) /*!< FUNCSEL (Bit 0) */
#define IO_BANK0_GPIO21_CTRL_FUNCSEL_Msk (0x1fUL) /*!< FUNCSEL (Bitfield-Mask: 0x1f) */
/* ===================================================== GPIO22_STATUS ===================================================== */
#define IO_BANK0_GPIO22_STATUS_IRQTOPROC_Pos (26UL) /*!< IRQTOPROC (Bit 26) */
#define IO_BANK0_GPIO22_STATUS_IRQTOPROC_Msk (0x4000000UL) /*!< IRQTOPROC (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO22_STATUS_IRQFROMPAD_Pos (24UL) /*!< IRQFROMPAD (Bit 24) */
#define IO_BANK0_GPIO22_STATUS_IRQFROMPAD_Msk (0x1000000UL) /*!< IRQFROMPAD (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO22_STATUS_INTOPERI_Pos (19UL) /*!< INTOPERI (Bit 19) */
#define IO_BANK0_GPIO22_STATUS_INTOPERI_Msk (0x80000UL) /*!< INTOPERI (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO22_STATUS_INFROMPAD_Pos (17UL) /*!< INFROMPAD (Bit 17) */
#define IO_BANK0_GPIO22_STATUS_INFROMPAD_Msk (0x20000UL) /*!< INFROMPAD (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO22_STATUS_OETOPAD_Pos (13UL) /*!< OETOPAD (Bit 13) */
#define IO_BANK0_GPIO22_STATUS_OETOPAD_Msk (0x2000UL) /*!< OETOPAD (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO22_STATUS_OEFROMPERI_Pos (12UL) /*!< OEFROMPERI (Bit 12) */
#define IO_BANK0_GPIO22_STATUS_OEFROMPERI_Msk (0x1000UL) /*!< OEFROMPERI (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO22_STATUS_OUTTOPAD_Pos (9UL) /*!< OUTTOPAD (Bit 9) */
#define IO_BANK0_GPIO22_STATUS_OUTTOPAD_Msk (0x200UL) /*!< OUTTOPAD (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO22_STATUS_OUTFROMPERI_Pos (8UL) /*!< OUTFROMPERI (Bit 8) */
#define IO_BANK0_GPIO22_STATUS_OUTFROMPERI_Msk (0x100UL) /*!< OUTFROMPERI (Bitfield-Mask: 0x01) */
/* ====================================================== GPIO22_CTRL ====================================================== */
#define IO_BANK0_GPIO22_CTRL_IRQOVER_Pos (28UL) /*!< IRQOVER (Bit 28) */
#define IO_BANK0_GPIO22_CTRL_IRQOVER_Msk (0x30000000UL) /*!< IRQOVER (Bitfield-Mask: 0x03) */
#define IO_BANK0_GPIO22_CTRL_INOVER_Pos (16UL) /*!< INOVER (Bit 16) */
#define IO_BANK0_GPIO22_CTRL_INOVER_Msk (0x30000UL) /*!< INOVER (Bitfield-Mask: 0x03) */
#define IO_BANK0_GPIO22_CTRL_OEOVER_Pos (12UL) /*!< OEOVER (Bit 12) */
#define IO_BANK0_GPIO22_CTRL_OEOVER_Msk (0x3000UL) /*!< OEOVER (Bitfield-Mask: 0x03) */
#define IO_BANK0_GPIO22_CTRL_OUTOVER_Pos (8UL) /*!< OUTOVER (Bit 8) */
#define IO_BANK0_GPIO22_CTRL_OUTOVER_Msk (0x300UL) /*!< OUTOVER (Bitfield-Mask: 0x03) */
#define IO_BANK0_GPIO22_CTRL_FUNCSEL_Pos (0UL) /*!< FUNCSEL (Bit 0) */
#define IO_BANK0_GPIO22_CTRL_FUNCSEL_Msk (0x1fUL) /*!< FUNCSEL (Bitfield-Mask: 0x1f) */
/* ===================================================== GPIO23_STATUS ===================================================== */
#define IO_BANK0_GPIO23_STATUS_IRQTOPROC_Pos (26UL) /*!< IRQTOPROC (Bit 26) */
#define IO_BANK0_GPIO23_STATUS_IRQTOPROC_Msk (0x4000000UL) /*!< IRQTOPROC (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO23_STATUS_IRQFROMPAD_Pos (24UL) /*!< IRQFROMPAD (Bit 24) */
#define IO_BANK0_GPIO23_STATUS_IRQFROMPAD_Msk (0x1000000UL) /*!< IRQFROMPAD (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO23_STATUS_INTOPERI_Pos (19UL) /*!< INTOPERI (Bit 19) */
#define IO_BANK0_GPIO23_STATUS_INTOPERI_Msk (0x80000UL) /*!< INTOPERI (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO23_STATUS_INFROMPAD_Pos (17UL) /*!< INFROMPAD (Bit 17) */
#define IO_BANK0_GPIO23_STATUS_INFROMPAD_Msk (0x20000UL) /*!< INFROMPAD (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO23_STATUS_OETOPAD_Pos (13UL) /*!< OETOPAD (Bit 13) */
#define IO_BANK0_GPIO23_STATUS_OETOPAD_Msk (0x2000UL) /*!< OETOPAD (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO23_STATUS_OEFROMPERI_Pos (12UL) /*!< OEFROMPERI (Bit 12) */
#define IO_BANK0_GPIO23_STATUS_OEFROMPERI_Msk (0x1000UL) /*!< OEFROMPERI (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO23_STATUS_OUTTOPAD_Pos (9UL) /*!< OUTTOPAD (Bit 9) */
#define IO_BANK0_GPIO23_STATUS_OUTTOPAD_Msk (0x200UL) /*!< OUTTOPAD (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO23_STATUS_OUTFROMPERI_Pos (8UL) /*!< OUTFROMPERI (Bit 8) */
#define IO_BANK0_GPIO23_STATUS_OUTFROMPERI_Msk (0x100UL) /*!< OUTFROMPERI (Bitfield-Mask: 0x01) */
/* ====================================================== GPIO23_CTRL ====================================================== */
#define IO_BANK0_GPIO23_CTRL_IRQOVER_Pos (28UL) /*!< IRQOVER (Bit 28) */
#define IO_BANK0_GPIO23_CTRL_IRQOVER_Msk (0x30000000UL) /*!< IRQOVER (Bitfield-Mask: 0x03) */
#define IO_BANK0_GPIO23_CTRL_INOVER_Pos (16UL) /*!< INOVER (Bit 16) */
#define IO_BANK0_GPIO23_CTRL_INOVER_Msk (0x30000UL) /*!< INOVER (Bitfield-Mask: 0x03) */
#define IO_BANK0_GPIO23_CTRL_OEOVER_Pos (12UL) /*!< OEOVER (Bit 12) */
#define IO_BANK0_GPIO23_CTRL_OEOVER_Msk (0x3000UL) /*!< OEOVER (Bitfield-Mask: 0x03) */
#define IO_BANK0_GPIO23_CTRL_OUTOVER_Pos (8UL) /*!< OUTOVER (Bit 8) */
#define IO_BANK0_GPIO23_CTRL_OUTOVER_Msk (0x300UL) /*!< OUTOVER (Bitfield-Mask: 0x03) */
#define IO_BANK0_GPIO23_CTRL_FUNCSEL_Pos (0UL) /*!< FUNCSEL (Bit 0) */
#define IO_BANK0_GPIO23_CTRL_FUNCSEL_Msk (0x1fUL) /*!< FUNCSEL (Bitfield-Mask: 0x1f) */
/* ===================================================== GPIO24_STATUS ===================================================== */
#define IO_BANK0_GPIO24_STATUS_IRQTOPROC_Pos (26UL) /*!< IRQTOPROC (Bit 26) */
#define IO_BANK0_GPIO24_STATUS_IRQTOPROC_Msk (0x4000000UL) /*!< IRQTOPROC (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO24_STATUS_IRQFROMPAD_Pos (24UL) /*!< IRQFROMPAD (Bit 24) */
#define IO_BANK0_GPIO24_STATUS_IRQFROMPAD_Msk (0x1000000UL) /*!< IRQFROMPAD (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO24_STATUS_INTOPERI_Pos (19UL) /*!< INTOPERI (Bit 19) */
#define IO_BANK0_GPIO24_STATUS_INTOPERI_Msk (0x80000UL) /*!< INTOPERI (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO24_STATUS_INFROMPAD_Pos (17UL) /*!< INFROMPAD (Bit 17) */
#define IO_BANK0_GPIO24_STATUS_INFROMPAD_Msk (0x20000UL) /*!< INFROMPAD (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO24_STATUS_OETOPAD_Pos (13UL) /*!< OETOPAD (Bit 13) */
#define IO_BANK0_GPIO24_STATUS_OETOPAD_Msk (0x2000UL) /*!< OETOPAD (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO24_STATUS_OEFROMPERI_Pos (12UL) /*!< OEFROMPERI (Bit 12) */
#define IO_BANK0_GPIO24_STATUS_OEFROMPERI_Msk (0x1000UL) /*!< OEFROMPERI (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO24_STATUS_OUTTOPAD_Pos (9UL) /*!< OUTTOPAD (Bit 9) */
#define IO_BANK0_GPIO24_STATUS_OUTTOPAD_Msk (0x200UL) /*!< OUTTOPAD (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO24_STATUS_OUTFROMPERI_Pos (8UL) /*!< OUTFROMPERI (Bit 8) */
#define IO_BANK0_GPIO24_STATUS_OUTFROMPERI_Msk (0x100UL) /*!< OUTFROMPERI (Bitfield-Mask: 0x01) */
/* ====================================================== GPIO24_CTRL ====================================================== */
#define IO_BANK0_GPIO24_CTRL_IRQOVER_Pos (28UL) /*!< IRQOVER (Bit 28) */
#define IO_BANK0_GPIO24_CTRL_IRQOVER_Msk (0x30000000UL) /*!< IRQOVER (Bitfield-Mask: 0x03) */
#define IO_BANK0_GPIO24_CTRL_INOVER_Pos (16UL) /*!< INOVER (Bit 16) */
#define IO_BANK0_GPIO24_CTRL_INOVER_Msk (0x30000UL) /*!< INOVER (Bitfield-Mask: 0x03) */
#define IO_BANK0_GPIO24_CTRL_OEOVER_Pos (12UL) /*!< OEOVER (Bit 12) */
#define IO_BANK0_GPIO24_CTRL_OEOVER_Msk (0x3000UL) /*!< OEOVER (Bitfield-Mask: 0x03) */
#define IO_BANK0_GPIO24_CTRL_OUTOVER_Pos (8UL) /*!< OUTOVER (Bit 8) */
#define IO_BANK0_GPIO24_CTRL_OUTOVER_Msk (0x300UL) /*!< OUTOVER (Bitfield-Mask: 0x03) */
#define IO_BANK0_GPIO24_CTRL_FUNCSEL_Pos (0UL) /*!< FUNCSEL (Bit 0) */
#define IO_BANK0_GPIO24_CTRL_FUNCSEL_Msk (0x1fUL) /*!< FUNCSEL (Bitfield-Mask: 0x1f) */
/* ===================================================== GPIO25_STATUS ===================================================== */
#define IO_BANK0_GPIO25_STATUS_IRQTOPROC_Pos (26UL) /*!< IRQTOPROC (Bit 26) */
#define IO_BANK0_GPIO25_STATUS_IRQTOPROC_Msk (0x4000000UL) /*!< IRQTOPROC (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO25_STATUS_IRQFROMPAD_Pos (24UL) /*!< IRQFROMPAD (Bit 24) */
#define IO_BANK0_GPIO25_STATUS_IRQFROMPAD_Msk (0x1000000UL) /*!< IRQFROMPAD (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO25_STATUS_INTOPERI_Pos (19UL) /*!< INTOPERI (Bit 19) */
#define IO_BANK0_GPIO25_STATUS_INTOPERI_Msk (0x80000UL) /*!< INTOPERI (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO25_STATUS_INFROMPAD_Pos (17UL) /*!< INFROMPAD (Bit 17) */
#define IO_BANK0_GPIO25_STATUS_INFROMPAD_Msk (0x20000UL) /*!< INFROMPAD (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO25_STATUS_OETOPAD_Pos (13UL) /*!< OETOPAD (Bit 13) */
#define IO_BANK0_GPIO25_STATUS_OETOPAD_Msk (0x2000UL) /*!< OETOPAD (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO25_STATUS_OEFROMPERI_Pos (12UL) /*!< OEFROMPERI (Bit 12) */
#define IO_BANK0_GPIO25_STATUS_OEFROMPERI_Msk (0x1000UL) /*!< OEFROMPERI (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO25_STATUS_OUTTOPAD_Pos (9UL) /*!< OUTTOPAD (Bit 9) */
#define IO_BANK0_GPIO25_STATUS_OUTTOPAD_Msk (0x200UL) /*!< OUTTOPAD (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO25_STATUS_OUTFROMPERI_Pos (8UL) /*!< OUTFROMPERI (Bit 8) */
#define IO_BANK0_GPIO25_STATUS_OUTFROMPERI_Msk (0x100UL) /*!< OUTFROMPERI (Bitfield-Mask: 0x01) */
/* ====================================================== GPIO25_CTRL ====================================================== */
#define IO_BANK0_GPIO25_CTRL_IRQOVER_Pos (28UL) /*!< IRQOVER (Bit 28) */
#define IO_BANK0_GPIO25_CTRL_IRQOVER_Msk (0x30000000UL) /*!< IRQOVER (Bitfield-Mask: 0x03) */
#define IO_BANK0_GPIO25_CTRL_INOVER_Pos (16UL) /*!< INOVER (Bit 16) */
#define IO_BANK0_GPIO25_CTRL_INOVER_Msk (0x30000UL) /*!< INOVER (Bitfield-Mask: 0x03) */
#define IO_BANK0_GPIO25_CTRL_OEOVER_Pos (12UL) /*!< OEOVER (Bit 12) */
#define IO_BANK0_GPIO25_CTRL_OEOVER_Msk (0x3000UL) /*!< OEOVER (Bitfield-Mask: 0x03) */
#define IO_BANK0_GPIO25_CTRL_OUTOVER_Pos (8UL) /*!< OUTOVER (Bit 8) */
#define IO_BANK0_GPIO25_CTRL_OUTOVER_Msk (0x300UL) /*!< OUTOVER (Bitfield-Mask: 0x03) */
#define IO_BANK0_GPIO25_CTRL_FUNCSEL_Pos (0UL) /*!< FUNCSEL (Bit 0) */
#define IO_BANK0_GPIO25_CTRL_FUNCSEL_Msk (0x1fUL) /*!< FUNCSEL (Bitfield-Mask: 0x1f) */
/* ===================================================== GPIO26_STATUS ===================================================== */
#define IO_BANK0_GPIO26_STATUS_IRQTOPROC_Pos (26UL) /*!< IRQTOPROC (Bit 26) */
#define IO_BANK0_GPIO26_STATUS_IRQTOPROC_Msk (0x4000000UL) /*!< IRQTOPROC (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO26_STATUS_IRQFROMPAD_Pos (24UL) /*!< IRQFROMPAD (Bit 24) */
#define IO_BANK0_GPIO26_STATUS_IRQFROMPAD_Msk (0x1000000UL) /*!< IRQFROMPAD (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO26_STATUS_INTOPERI_Pos (19UL) /*!< INTOPERI (Bit 19) */
#define IO_BANK0_GPIO26_STATUS_INTOPERI_Msk (0x80000UL) /*!< INTOPERI (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO26_STATUS_INFROMPAD_Pos (17UL) /*!< INFROMPAD (Bit 17) */
#define IO_BANK0_GPIO26_STATUS_INFROMPAD_Msk (0x20000UL) /*!< INFROMPAD (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO26_STATUS_OETOPAD_Pos (13UL) /*!< OETOPAD (Bit 13) */
#define IO_BANK0_GPIO26_STATUS_OETOPAD_Msk (0x2000UL) /*!< OETOPAD (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO26_STATUS_OEFROMPERI_Pos (12UL) /*!< OEFROMPERI (Bit 12) */
#define IO_BANK0_GPIO26_STATUS_OEFROMPERI_Msk (0x1000UL) /*!< OEFROMPERI (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO26_STATUS_OUTTOPAD_Pos (9UL) /*!< OUTTOPAD (Bit 9) */
#define IO_BANK0_GPIO26_STATUS_OUTTOPAD_Msk (0x200UL) /*!< OUTTOPAD (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO26_STATUS_OUTFROMPERI_Pos (8UL) /*!< OUTFROMPERI (Bit 8) */
#define IO_BANK0_GPIO26_STATUS_OUTFROMPERI_Msk (0x100UL) /*!< OUTFROMPERI (Bitfield-Mask: 0x01) */
/* ====================================================== GPIO26_CTRL ====================================================== */
#define IO_BANK0_GPIO26_CTRL_IRQOVER_Pos (28UL) /*!< IRQOVER (Bit 28) */
#define IO_BANK0_GPIO26_CTRL_IRQOVER_Msk (0x30000000UL) /*!< IRQOVER (Bitfield-Mask: 0x03) */
#define IO_BANK0_GPIO26_CTRL_INOVER_Pos (16UL) /*!< INOVER (Bit 16) */
#define IO_BANK0_GPIO26_CTRL_INOVER_Msk (0x30000UL) /*!< INOVER (Bitfield-Mask: 0x03) */
#define IO_BANK0_GPIO26_CTRL_OEOVER_Pos (12UL) /*!< OEOVER (Bit 12) */
#define IO_BANK0_GPIO26_CTRL_OEOVER_Msk (0x3000UL) /*!< OEOVER (Bitfield-Mask: 0x03) */
#define IO_BANK0_GPIO26_CTRL_OUTOVER_Pos (8UL) /*!< OUTOVER (Bit 8) */
#define IO_BANK0_GPIO26_CTRL_OUTOVER_Msk (0x300UL) /*!< OUTOVER (Bitfield-Mask: 0x03) */
#define IO_BANK0_GPIO26_CTRL_FUNCSEL_Pos (0UL) /*!< FUNCSEL (Bit 0) */
#define IO_BANK0_GPIO26_CTRL_FUNCSEL_Msk (0x1fUL) /*!< FUNCSEL (Bitfield-Mask: 0x1f) */
/* ===================================================== GPIO27_STATUS ===================================================== */
#define IO_BANK0_GPIO27_STATUS_IRQTOPROC_Pos (26UL) /*!< IRQTOPROC (Bit 26) */
#define IO_BANK0_GPIO27_STATUS_IRQTOPROC_Msk (0x4000000UL) /*!< IRQTOPROC (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO27_STATUS_IRQFROMPAD_Pos (24UL) /*!< IRQFROMPAD (Bit 24) */
#define IO_BANK0_GPIO27_STATUS_IRQFROMPAD_Msk (0x1000000UL) /*!< IRQFROMPAD (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO27_STATUS_INTOPERI_Pos (19UL) /*!< INTOPERI (Bit 19) */
#define IO_BANK0_GPIO27_STATUS_INTOPERI_Msk (0x80000UL) /*!< INTOPERI (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO27_STATUS_INFROMPAD_Pos (17UL) /*!< INFROMPAD (Bit 17) */
#define IO_BANK0_GPIO27_STATUS_INFROMPAD_Msk (0x20000UL) /*!< INFROMPAD (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO27_STATUS_OETOPAD_Pos (13UL) /*!< OETOPAD (Bit 13) */
#define IO_BANK0_GPIO27_STATUS_OETOPAD_Msk (0x2000UL) /*!< OETOPAD (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO27_STATUS_OEFROMPERI_Pos (12UL) /*!< OEFROMPERI (Bit 12) */
#define IO_BANK0_GPIO27_STATUS_OEFROMPERI_Msk (0x1000UL) /*!< OEFROMPERI (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO27_STATUS_OUTTOPAD_Pos (9UL) /*!< OUTTOPAD (Bit 9) */
#define IO_BANK0_GPIO27_STATUS_OUTTOPAD_Msk (0x200UL) /*!< OUTTOPAD (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO27_STATUS_OUTFROMPERI_Pos (8UL) /*!< OUTFROMPERI (Bit 8) */
#define IO_BANK0_GPIO27_STATUS_OUTFROMPERI_Msk (0x100UL) /*!< OUTFROMPERI (Bitfield-Mask: 0x01) */
/* ====================================================== GPIO27_CTRL ====================================================== */
#define IO_BANK0_GPIO27_CTRL_IRQOVER_Pos (28UL) /*!< IRQOVER (Bit 28) */
#define IO_BANK0_GPIO27_CTRL_IRQOVER_Msk (0x30000000UL) /*!< IRQOVER (Bitfield-Mask: 0x03) */
#define IO_BANK0_GPIO27_CTRL_INOVER_Pos (16UL) /*!< INOVER (Bit 16) */
#define IO_BANK0_GPIO27_CTRL_INOVER_Msk (0x30000UL) /*!< INOVER (Bitfield-Mask: 0x03) */
#define IO_BANK0_GPIO27_CTRL_OEOVER_Pos (12UL) /*!< OEOVER (Bit 12) */
#define IO_BANK0_GPIO27_CTRL_OEOVER_Msk (0x3000UL) /*!< OEOVER (Bitfield-Mask: 0x03) */
#define IO_BANK0_GPIO27_CTRL_OUTOVER_Pos (8UL) /*!< OUTOVER (Bit 8) */
#define IO_BANK0_GPIO27_CTRL_OUTOVER_Msk (0x300UL) /*!< OUTOVER (Bitfield-Mask: 0x03) */
#define IO_BANK0_GPIO27_CTRL_FUNCSEL_Pos (0UL) /*!< FUNCSEL (Bit 0) */
#define IO_BANK0_GPIO27_CTRL_FUNCSEL_Msk (0x1fUL) /*!< FUNCSEL (Bitfield-Mask: 0x1f) */
/* ===================================================== GPIO28_STATUS ===================================================== */
#define IO_BANK0_GPIO28_STATUS_IRQTOPROC_Pos (26UL) /*!< IRQTOPROC (Bit 26) */
#define IO_BANK0_GPIO28_STATUS_IRQTOPROC_Msk (0x4000000UL) /*!< IRQTOPROC (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO28_STATUS_IRQFROMPAD_Pos (24UL) /*!< IRQFROMPAD (Bit 24) */
#define IO_BANK0_GPIO28_STATUS_IRQFROMPAD_Msk (0x1000000UL) /*!< IRQFROMPAD (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO28_STATUS_INTOPERI_Pos (19UL) /*!< INTOPERI (Bit 19) */
#define IO_BANK0_GPIO28_STATUS_INTOPERI_Msk (0x80000UL) /*!< INTOPERI (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO28_STATUS_INFROMPAD_Pos (17UL) /*!< INFROMPAD (Bit 17) */
#define IO_BANK0_GPIO28_STATUS_INFROMPAD_Msk (0x20000UL) /*!< INFROMPAD (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO28_STATUS_OETOPAD_Pos (13UL) /*!< OETOPAD (Bit 13) */
#define IO_BANK0_GPIO28_STATUS_OETOPAD_Msk (0x2000UL) /*!< OETOPAD (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO28_STATUS_OEFROMPERI_Pos (12UL) /*!< OEFROMPERI (Bit 12) */
#define IO_BANK0_GPIO28_STATUS_OEFROMPERI_Msk (0x1000UL) /*!< OEFROMPERI (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO28_STATUS_OUTTOPAD_Pos (9UL) /*!< OUTTOPAD (Bit 9) */
#define IO_BANK0_GPIO28_STATUS_OUTTOPAD_Msk (0x200UL) /*!< OUTTOPAD (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO28_STATUS_OUTFROMPERI_Pos (8UL) /*!< OUTFROMPERI (Bit 8) */
#define IO_BANK0_GPIO28_STATUS_OUTFROMPERI_Msk (0x100UL) /*!< OUTFROMPERI (Bitfield-Mask: 0x01) */
/* ====================================================== GPIO28_CTRL ====================================================== */
#define IO_BANK0_GPIO28_CTRL_IRQOVER_Pos (28UL) /*!< IRQOVER (Bit 28) */
#define IO_BANK0_GPIO28_CTRL_IRQOVER_Msk (0x30000000UL) /*!< IRQOVER (Bitfield-Mask: 0x03) */
#define IO_BANK0_GPIO28_CTRL_INOVER_Pos (16UL) /*!< INOVER (Bit 16) */
#define IO_BANK0_GPIO28_CTRL_INOVER_Msk (0x30000UL) /*!< INOVER (Bitfield-Mask: 0x03) */
#define IO_BANK0_GPIO28_CTRL_OEOVER_Pos (12UL) /*!< OEOVER (Bit 12) */
#define IO_BANK0_GPIO28_CTRL_OEOVER_Msk (0x3000UL) /*!< OEOVER (Bitfield-Mask: 0x03) */
#define IO_BANK0_GPIO28_CTRL_OUTOVER_Pos (8UL) /*!< OUTOVER (Bit 8) */
#define IO_BANK0_GPIO28_CTRL_OUTOVER_Msk (0x300UL) /*!< OUTOVER (Bitfield-Mask: 0x03) */
#define IO_BANK0_GPIO28_CTRL_FUNCSEL_Pos (0UL) /*!< FUNCSEL (Bit 0) */
#define IO_BANK0_GPIO28_CTRL_FUNCSEL_Msk (0x1fUL) /*!< FUNCSEL (Bitfield-Mask: 0x1f) */
/* ===================================================== GPIO29_STATUS ===================================================== */
#define IO_BANK0_GPIO29_STATUS_IRQTOPROC_Pos (26UL) /*!< IRQTOPROC (Bit 26) */
#define IO_BANK0_GPIO29_STATUS_IRQTOPROC_Msk (0x4000000UL) /*!< IRQTOPROC (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO29_STATUS_IRQFROMPAD_Pos (24UL) /*!< IRQFROMPAD (Bit 24) */
#define IO_BANK0_GPIO29_STATUS_IRQFROMPAD_Msk (0x1000000UL) /*!< IRQFROMPAD (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO29_STATUS_INTOPERI_Pos (19UL) /*!< INTOPERI (Bit 19) */
#define IO_BANK0_GPIO29_STATUS_INTOPERI_Msk (0x80000UL) /*!< INTOPERI (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO29_STATUS_INFROMPAD_Pos (17UL) /*!< INFROMPAD (Bit 17) */
#define IO_BANK0_GPIO29_STATUS_INFROMPAD_Msk (0x20000UL) /*!< INFROMPAD (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO29_STATUS_OETOPAD_Pos (13UL) /*!< OETOPAD (Bit 13) */
#define IO_BANK0_GPIO29_STATUS_OETOPAD_Msk (0x2000UL) /*!< OETOPAD (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO29_STATUS_OEFROMPERI_Pos (12UL) /*!< OEFROMPERI (Bit 12) */
#define IO_BANK0_GPIO29_STATUS_OEFROMPERI_Msk (0x1000UL) /*!< OEFROMPERI (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO29_STATUS_OUTTOPAD_Pos (9UL) /*!< OUTTOPAD (Bit 9) */
#define IO_BANK0_GPIO29_STATUS_OUTTOPAD_Msk (0x200UL) /*!< OUTTOPAD (Bitfield-Mask: 0x01) */
#define IO_BANK0_GPIO29_STATUS_OUTFROMPERI_Pos (8UL) /*!< OUTFROMPERI (Bit 8) */
#define IO_BANK0_GPIO29_STATUS_OUTFROMPERI_Msk (0x100UL) /*!< OUTFROMPERI (Bitfield-Mask: 0x01) */
/* ====================================================== GPIO29_CTRL ====================================================== */
#define IO_BANK0_GPIO29_CTRL_IRQOVER_Pos (28UL) /*!< IRQOVER (Bit 28) */
#define IO_BANK0_GPIO29_CTRL_IRQOVER_Msk (0x30000000UL) /*!< IRQOVER (Bitfield-Mask: 0x03) */
#define IO_BANK0_GPIO29_CTRL_INOVER_Pos (16UL) /*!< INOVER (Bit 16) */
#define IO_BANK0_GPIO29_CTRL_INOVER_Msk (0x30000UL) /*!< INOVER (Bitfield-Mask: 0x03) */
#define IO_BANK0_GPIO29_CTRL_OEOVER_Pos (12UL) /*!< OEOVER (Bit 12) */
#define IO_BANK0_GPIO29_CTRL_OEOVER_Msk (0x3000UL) /*!< OEOVER (Bitfield-Mask: 0x03) */
#define IO_BANK0_GPIO29_CTRL_OUTOVER_Pos (8UL) /*!< OUTOVER (Bit 8) */
#define IO_BANK0_GPIO29_CTRL_OUTOVER_Msk (0x300UL) /*!< OUTOVER (Bitfield-Mask: 0x03) */
#define IO_BANK0_GPIO29_CTRL_FUNCSEL_Pos (0UL) /*!< FUNCSEL (Bit 0) */
#define IO_BANK0_GPIO29_CTRL_FUNCSEL_Msk (0x1fUL) /*!< FUNCSEL (Bitfield-Mask: 0x1f) */
/* ========================================================= INTR0 ========================================================= */
#define IO_BANK0_INTR0_GPIO7_EDGE_HIGH_Pos (31UL) /*!< GPIO7_EDGE_HIGH (Bit 31) */
#define IO_BANK0_INTR0_GPIO7_EDGE_HIGH_Msk (0x80000000UL) /*!< GPIO7_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_INTR0_GPIO7_EDGE_LOW_Pos (30UL) /*!< GPIO7_EDGE_LOW (Bit 30) */
#define IO_BANK0_INTR0_GPIO7_EDGE_LOW_Msk (0x40000000UL) /*!< GPIO7_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_INTR0_GPIO7_LEVEL_HIGH_Pos (29UL) /*!< GPIO7_LEVEL_HIGH (Bit 29) */
#define IO_BANK0_INTR0_GPIO7_LEVEL_HIGH_Msk (0x20000000UL) /*!< GPIO7_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_INTR0_GPIO7_LEVEL_LOW_Pos (28UL) /*!< GPIO7_LEVEL_LOW (Bit 28) */
#define IO_BANK0_INTR0_GPIO7_LEVEL_LOW_Msk (0x10000000UL) /*!< GPIO7_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_INTR0_GPIO6_EDGE_HIGH_Pos (27UL) /*!< GPIO6_EDGE_HIGH (Bit 27) */
#define IO_BANK0_INTR0_GPIO6_EDGE_HIGH_Msk (0x8000000UL) /*!< GPIO6_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_INTR0_GPIO6_EDGE_LOW_Pos (26UL) /*!< GPIO6_EDGE_LOW (Bit 26) */
#define IO_BANK0_INTR0_GPIO6_EDGE_LOW_Msk (0x4000000UL) /*!< GPIO6_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_INTR0_GPIO6_LEVEL_HIGH_Pos (25UL) /*!< GPIO6_LEVEL_HIGH (Bit 25) */
#define IO_BANK0_INTR0_GPIO6_LEVEL_HIGH_Msk (0x2000000UL) /*!< GPIO6_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_INTR0_GPIO6_LEVEL_LOW_Pos (24UL) /*!< GPIO6_LEVEL_LOW (Bit 24) */
#define IO_BANK0_INTR0_GPIO6_LEVEL_LOW_Msk (0x1000000UL) /*!< GPIO6_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_INTR0_GPIO5_EDGE_HIGH_Pos (23UL) /*!< GPIO5_EDGE_HIGH (Bit 23) */
#define IO_BANK0_INTR0_GPIO5_EDGE_HIGH_Msk (0x800000UL) /*!< GPIO5_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_INTR0_GPIO5_EDGE_LOW_Pos (22UL) /*!< GPIO5_EDGE_LOW (Bit 22) */
#define IO_BANK0_INTR0_GPIO5_EDGE_LOW_Msk (0x400000UL) /*!< GPIO5_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_INTR0_GPIO5_LEVEL_HIGH_Pos (21UL) /*!< GPIO5_LEVEL_HIGH (Bit 21) */
#define IO_BANK0_INTR0_GPIO5_LEVEL_HIGH_Msk (0x200000UL) /*!< GPIO5_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_INTR0_GPIO5_LEVEL_LOW_Pos (20UL) /*!< GPIO5_LEVEL_LOW (Bit 20) */
#define IO_BANK0_INTR0_GPIO5_LEVEL_LOW_Msk (0x100000UL) /*!< GPIO5_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_INTR0_GPIO4_EDGE_HIGH_Pos (19UL) /*!< GPIO4_EDGE_HIGH (Bit 19) */
#define IO_BANK0_INTR0_GPIO4_EDGE_HIGH_Msk (0x80000UL) /*!< GPIO4_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_INTR0_GPIO4_EDGE_LOW_Pos (18UL) /*!< GPIO4_EDGE_LOW (Bit 18) */
#define IO_BANK0_INTR0_GPIO4_EDGE_LOW_Msk (0x40000UL) /*!< GPIO4_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_INTR0_GPIO4_LEVEL_HIGH_Pos (17UL) /*!< GPIO4_LEVEL_HIGH (Bit 17) */
#define IO_BANK0_INTR0_GPIO4_LEVEL_HIGH_Msk (0x20000UL) /*!< GPIO4_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_INTR0_GPIO4_LEVEL_LOW_Pos (16UL) /*!< GPIO4_LEVEL_LOW (Bit 16) */
#define IO_BANK0_INTR0_GPIO4_LEVEL_LOW_Msk (0x10000UL) /*!< GPIO4_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_INTR0_GPIO3_EDGE_HIGH_Pos (15UL) /*!< GPIO3_EDGE_HIGH (Bit 15) */
#define IO_BANK0_INTR0_GPIO3_EDGE_HIGH_Msk (0x8000UL) /*!< GPIO3_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_INTR0_GPIO3_EDGE_LOW_Pos (14UL) /*!< GPIO3_EDGE_LOW (Bit 14) */
#define IO_BANK0_INTR0_GPIO3_EDGE_LOW_Msk (0x4000UL) /*!< GPIO3_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_INTR0_GPIO3_LEVEL_HIGH_Pos (13UL) /*!< GPIO3_LEVEL_HIGH (Bit 13) */
#define IO_BANK0_INTR0_GPIO3_LEVEL_HIGH_Msk (0x2000UL) /*!< GPIO3_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_INTR0_GPIO3_LEVEL_LOW_Pos (12UL) /*!< GPIO3_LEVEL_LOW (Bit 12) */
#define IO_BANK0_INTR0_GPIO3_LEVEL_LOW_Msk (0x1000UL) /*!< GPIO3_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_INTR0_GPIO2_EDGE_HIGH_Pos (11UL) /*!< GPIO2_EDGE_HIGH (Bit 11) */
#define IO_BANK0_INTR0_GPIO2_EDGE_HIGH_Msk (0x800UL) /*!< GPIO2_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_INTR0_GPIO2_EDGE_LOW_Pos (10UL) /*!< GPIO2_EDGE_LOW (Bit 10) */
#define IO_BANK0_INTR0_GPIO2_EDGE_LOW_Msk (0x400UL) /*!< GPIO2_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_INTR0_GPIO2_LEVEL_HIGH_Pos (9UL) /*!< GPIO2_LEVEL_HIGH (Bit 9) */
#define IO_BANK0_INTR0_GPIO2_LEVEL_HIGH_Msk (0x200UL) /*!< GPIO2_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_INTR0_GPIO2_LEVEL_LOW_Pos (8UL) /*!< GPIO2_LEVEL_LOW (Bit 8) */
#define IO_BANK0_INTR0_GPIO2_LEVEL_LOW_Msk (0x100UL) /*!< GPIO2_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_INTR0_GPIO1_EDGE_HIGH_Pos (7UL) /*!< GPIO1_EDGE_HIGH (Bit 7) */
#define IO_BANK0_INTR0_GPIO1_EDGE_HIGH_Msk (0x80UL) /*!< GPIO1_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_INTR0_GPIO1_EDGE_LOW_Pos (6UL) /*!< GPIO1_EDGE_LOW (Bit 6) */
#define IO_BANK0_INTR0_GPIO1_EDGE_LOW_Msk (0x40UL) /*!< GPIO1_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_INTR0_GPIO1_LEVEL_HIGH_Pos (5UL) /*!< GPIO1_LEVEL_HIGH (Bit 5) */
#define IO_BANK0_INTR0_GPIO1_LEVEL_HIGH_Msk (0x20UL) /*!< GPIO1_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_INTR0_GPIO1_LEVEL_LOW_Pos (4UL) /*!< GPIO1_LEVEL_LOW (Bit 4) */
#define IO_BANK0_INTR0_GPIO1_LEVEL_LOW_Msk (0x10UL) /*!< GPIO1_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_INTR0_GPIO0_EDGE_HIGH_Pos (3UL) /*!< GPIO0_EDGE_HIGH (Bit 3) */
#define IO_BANK0_INTR0_GPIO0_EDGE_HIGH_Msk (0x8UL) /*!< GPIO0_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_INTR0_GPIO0_EDGE_LOW_Pos (2UL) /*!< GPIO0_EDGE_LOW (Bit 2) */
#define IO_BANK0_INTR0_GPIO0_EDGE_LOW_Msk (0x4UL) /*!< GPIO0_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_INTR0_GPIO0_LEVEL_HIGH_Pos (1UL) /*!< GPIO0_LEVEL_HIGH (Bit 1) */
#define IO_BANK0_INTR0_GPIO0_LEVEL_HIGH_Msk (0x2UL) /*!< GPIO0_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_INTR0_GPIO0_LEVEL_LOW_Pos (0UL) /*!< GPIO0_LEVEL_LOW (Bit 0) */
#define IO_BANK0_INTR0_GPIO0_LEVEL_LOW_Msk (0x1UL) /*!< GPIO0_LEVEL_LOW (Bitfield-Mask: 0x01) */
/* ========================================================= INTR1 ========================================================= */
#define IO_BANK0_INTR1_GPIO15_EDGE_HIGH_Pos (31UL) /*!< GPIO15_EDGE_HIGH (Bit 31) */
#define IO_BANK0_INTR1_GPIO15_EDGE_HIGH_Msk (0x80000000UL) /*!< GPIO15_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_INTR1_GPIO15_EDGE_LOW_Pos (30UL) /*!< GPIO15_EDGE_LOW (Bit 30) */
#define IO_BANK0_INTR1_GPIO15_EDGE_LOW_Msk (0x40000000UL) /*!< GPIO15_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_INTR1_GPIO15_LEVEL_HIGH_Pos (29UL) /*!< GPIO15_LEVEL_HIGH (Bit 29) */
#define IO_BANK0_INTR1_GPIO15_LEVEL_HIGH_Msk (0x20000000UL) /*!< GPIO15_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_INTR1_GPIO15_LEVEL_LOW_Pos (28UL) /*!< GPIO15_LEVEL_LOW (Bit 28) */
#define IO_BANK0_INTR1_GPIO15_LEVEL_LOW_Msk (0x10000000UL) /*!< GPIO15_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_INTR1_GPIO14_EDGE_HIGH_Pos (27UL) /*!< GPIO14_EDGE_HIGH (Bit 27) */
#define IO_BANK0_INTR1_GPIO14_EDGE_HIGH_Msk (0x8000000UL) /*!< GPIO14_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_INTR1_GPIO14_EDGE_LOW_Pos (26UL) /*!< GPIO14_EDGE_LOW (Bit 26) */
#define IO_BANK0_INTR1_GPIO14_EDGE_LOW_Msk (0x4000000UL) /*!< GPIO14_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_INTR1_GPIO14_LEVEL_HIGH_Pos (25UL) /*!< GPIO14_LEVEL_HIGH (Bit 25) */
#define IO_BANK0_INTR1_GPIO14_LEVEL_HIGH_Msk (0x2000000UL) /*!< GPIO14_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_INTR1_GPIO14_LEVEL_LOW_Pos (24UL) /*!< GPIO14_LEVEL_LOW (Bit 24) */
#define IO_BANK0_INTR1_GPIO14_LEVEL_LOW_Msk (0x1000000UL) /*!< GPIO14_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_INTR1_GPIO13_EDGE_HIGH_Pos (23UL) /*!< GPIO13_EDGE_HIGH (Bit 23) */
#define IO_BANK0_INTR1_GPIO13_EDGE_HIGH_Msk (0x800000UL) /*!< GPIO13_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_INTR1_GPIO13_EDGE_LOW_Pos (22UL) /*!< GPIO13_EDGE_LOW (Bit 22) */
#define IO_BANK0_INTR1_GPIO13_EDGE_LOW_Msk (0x400000UL) /*!< GPIO13_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_INTR1_GPIO13_LEVEL_HIGH_Pos (21UL) /*!< GPIO13_LEVEL_HIGH (Bit 21) */
#define IO_BANK0_INTR1_GPIO13_LEVEL_HIGH_Msk (0x200000UL) /*!< GPIO13_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_INTR1_GPIO13_LEVEL_LOW_Pos (20UL) /*!< GPIO13_LEVEL_LOW (Bit 20) */
#define IO_BANK0_INTR1_GPIO13_LEVEL_LOW_Msk (0x100000UL) /*!< GPIO13_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_INTR1_GPIO12_EDGE_HIGH_Pos (19UL) /*!< GPIO12_EDGE_HIGH (Bit 19) */
#define IO_BANK0_INTR1_GPIO12_EDGE_HIGH_Msk (0x80000UL) /*!< GPIO12_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_INTR1_GPIO12_EDGE_LOW_Pos (18UL) /*!< GPIO12_EDGE_LOW (Bit 18) */
#define IO_BANK0_INTR1_GPIO12_EDGE_LOW_Msk (0x40000UL) /*!< GPIO12_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_INTR1_GPIO12_LEVEL_HIGH_Pos (17UL) /*!< GPIO12_LEVEL_HIGH (Bit 17) */
#define IO_BANK0_INTR1_GPIO12_LEVEL_HIGH_Msk (0x20000UL) /*!< GPIO12_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_INTR1_GPIO12_LEVEL_LOW_Pos (16UL) /*!< GPIO12_LEVEL_LOW (Bit 16) */
#define IO_BANK0_INTR1_GPIO12_LEVEL_LOW_Msk (0x10000UL) /*!< GPIO12_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_INTR1_GPIO11_EDGE_HIGH_Pos (15UL) /*!< GPIO11_EDGE_HIGH (Bit 15) */
#define IO_BANK0_INTR1_GPIO11_EDGE_HIGH_Msk (0x8000UL) /*!< GPIO11_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_INTR1_GPIO11_EDGE_LOW_Pos (14UL) /*!< GPIO11_EDGE_LOW (Bit 14) */
#define IO_BANK0_INTR1_GPIO11_EDGE_LOW_Msk (0x4000UL) /*!< GPIO11_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_INTR1_GPIO11_LEVEL_HIGH_Pos (13UL) /*!< GPIO11_LEVEL_HIGH (Bit 13) */
#define IO_BANK0_INTR1_GPIO11_LEVEL_HIGH_Msk (0x2000UL) /*!< GPIO11_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_INTR1_GPIO11_LEVEL_LOW_Pos (12UL) /*!< GPIO11_LEVEL_LOW (Bit 12) */
#define IO_BANK0_INTR1_GPIO11_LEVEL_LOW_Msk (0x1000UL) /*!< GPIO11_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_INTR1_GPIO10_EDGE_HIGH_Pos (11UL) /*!< GPIO10_EDGE_HIGH (Bit 11) */
#define IO_BANK0_INTR1_GPIO10_EDGE_HIGH_Msk (0x800UL) /*!< GPIO10_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_INTR1_GPIO10_EDGE_LOW_Pos (10UL) /*!< GPIO10_EDGE_LOW (Bit 10) */
#define IO_BANK0_INTR1_GPIO10_EDGE_LOW_Msk (0x400UL) /*!< GPIO10_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_INTR1_GPIO10_LEVEL_HIGH_Pos (9UL) /*!< GPIO10_LEVEL_HIGH (Bit 9) */
#define IO_BANK0_INTR1_GPIO10_LEVEL_HIGH_Msk (0x200UL) /*!< GPIO10_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_INTR1_GPIO10_LEVEL_LOW_Pos (8UL) /*!< GPIO10_LEVEL_LOW (Bit 8) */
#define IO_BANK0_INTR1_GPIO10_LEVEL_LOW_Msk (0x100UL) /*!< GPIO10_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_INTR1_GPIO9_EDGE_HIGH_Pos (7UL) /*!< GPIO9_EDGE_HIGH (Bit 7) */
#define IO_BANK0_INTR1_GPIO9_EDGE_HIGH_Msk (0x80UL) /*!< GPIO9_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_INTR1_GPIO9_EDGE_LOW_Pos (6UL) /*!< GPIO9_EDGE_LOW (Bit 6) */
#define IO_BANK0_INTR1_GPIO9_EDGE_LOW_Msk (0x40UL) /*!< GPIO9_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_INTR1_GPIO9_LEVEL_HIGH_Pos (5UL) /*!< GPIO9_LEVEL_HIGH (Bit 5) */
#define IO_BANK0_INTR1_GPIO9_LEVEL_HIGH_Msk (0x20UL) /*!< GPIO9_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_INTR1_GPIO9_LEVEL_LOW_Pos (4UL) /*!< GPIO9_LEVEL_LOW (Bit 4) */
#define IO_BANK0_INTR1_GPIO9_LEVEL_LOW_Msk (0x10UL) /*!< GPIO9_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_INTR1_GPIO8_EDGE_HIGH_Pos (3UL) /*!< GPIO8_EDGE_HIGH (Bit 3) */
#define IO_BANK0_INTR1_GPIO8_EDGE_HIGH_Msk (0x8UL) /*!< GPIO8_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_INTR1_GPIO8_EDGE_LOW_Pos (2UL) /*!< GPIO8_EDGE_LOW (Bit 2) */
#define IO_BANK0_INTR1_GPIO8_EDGE_LOW_Msk (0x4UL) /*!< GPIO8_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_INTR1_GPIO8_LEVEL_HIGH_Pos (1UL) /*!< GPIO8_LEVEL_HIGH (Bit 1) */
#define IO_BANK0_INTR1_GPIO8_LEVEL_HIGH_Msk (0x2UL) /*!< GPIO8_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_INTR1_GPIO8_LEVEL_LOW_Pos (0UL) /*!< GPIO8_LEVEL_LOW (Bit 0) */
#define IO_BANK0_INTR1_GPIO8_LEVEL_LOW_Msk (0x1UL) /*!< GPIO8_LEVEL_LOW (Bitfield-Mask: 0x01) */
/* ========================================================= INTR2 ========================================================= */
#define IO_BANK0_INTR2_GPIO23_EDGE_HIGH_Pos (31UL) /*!< GPIO23_EDGE_HIGH (Bit 31) */
#define IO_BANK0_INTR2_GPIO23_EDGE_HIGH_Msk (0x80000000UL) /*!< GPIO23_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_INTR2_GPIO23_EDGE_LOW_Pos (30UL) /*!< GPIO23_EDGE_LOW (Bit 30) */
#define IO_BANK0_INTR2_GPIO23_EDGE_LOW_Msk (0x40000000UL) /*!< GPIO23_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_INTR2_GPIO23_LEVEL_HIGH_Pos (29UL) /*!< GPIO23_LEVEL_HIGH (Bit 29) */
#define IO_BANK0_INTR2_GPIO23_LEVEL_HIGH_Msk (0x20000000UL) /*!< GPIO23_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_INTR2_GPIO23_LEVEL_LOW_Pos (28UL) /*!< GPIO23_LEVEL_LOW (Bit 28) */
#define IO_BANK0_INTR2_GPIO23_LEVEL_LOW_Msk (0x10000000UL) /*!< GPIO23_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_INTR2_GPIO22_EDGE_HIGH_Pos (27UL) /*!< GPIO22_EDGE_HIGH (Bit 27) */
#define IO_BANK0_INTR2_GPIO22_EDGE_HIGH_Msk (0x8000000UL) /*!< GPIO22_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_INTR2_GPIO22_EDGE_LOW_Pos (26UL) /*!< GPIO22_EDGE_LOW (Bit 26) */
#define IO_BANK0_INTR2_GPIO22_EDGE_LOW_Msk (0x4000000UL) /*!< GPIO22_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_INTR2_GPIO22_LEVEL_HIGH_Pos (25UL) /*!< GPIO22_LEVEL_HIGH (Bit 25) */
#define IO_BANK0_INTR2_GPIO22_LEVEL_HIGH_Msk (0x2000000UL) /*!< GPIO22_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_INTR2_GPIO22_LEVEL_LOW_Pos (24UL) /*!< GPIO22_LEVEL_LOW (Bit 24) */
#define IO_BANK0_INTR2_GPIO22_LEVEL_LOW_Msk (0x1000000UL) /*!< GPIO22_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_INTR2_GPIO21_EDGE_HIGH_Pos (23UL) /*!< GPIO21_EDGE_HIGH (Bit 23) */
#define IO_BANK0_INTR2_GPIO21_EDGE_HIGH_Msk (0x800000UL) /*!< GPIO21_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_INTR2_GPIO21_EDGE_LOW_Pos (22UL) /*!< GPIO21_EDGE_LOW (Bit 22) */
#define IO_BANK0_INTR2_GPIO21_EDGE_LOW_Msk (0x400000UL) /*!< GPIO21_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_INTR2_GPIO21_LEVEL_HIGH_Pos (21UL) /*!< GPIO21_LEVEL_HIGH (Bit 21) */
#define IO_BANK0_INTR2_GPIO21_LEVEL_HIGH_Msk (0x200000UL) /*!< GPIO21_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_INTR2_GPIO21_LEVEL_LOW_Pos (20UL) /*!< GPIO21_LEVEL_LOW (Bit 20) */
#define IO_BANK0_INTR2_GPIO21_LEVEL_LOW_Msk (0x100000UL) /*!< GPIO21_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_INTR2_GPIO20_EDGE_HIGH_Pos (19UL) /*!< GPIO20_EDGE_HIGH (Bit 19) */
#define IO_BANK0_INTR2_GPIO20_EDGE_HIGH_Msk (0x80000UL) /*!< GPIO20_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_INTR2_GPIO20_EDGE_LOW_Pos (18UL) /*!< GPIO20_EDGE_LOW (Bit 18) */
#define IO_BANK0_INTR2_GPIO20_EDGE_LOW_Msk (0x40000UL) /*!< GPIO20_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_INTR2_GPIO20_LEVEL_HIGH_Pos (17UL) /*!< GPIO20_LEVEL_HIGH (Bit 17) */
#define IO_BANK0_INTR2_GPIO20_LEVEL_HIGH_Msk (0x20000UL) /*!< GPIO20_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_INTR2_GPIO20_LEVEL_LOW_Pos (16UL) /*!< GPIO20_LEVEL_LOW (Bit 16) */
#define IO_BANK0_INTR2_GPIO20_LEVEL_LOW_Msk (0x10000UL) /*!< GPIO20_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_INTR2_GPIO19_EDGE_HIGH_Pos (15UL) /*!< GPIO19_EDGE_HIGH (Bit 15) */
#define IO_BANK0_INTR2_GPIO19_EDGE_HIGH_Msk (0x8000UL) /*!< GPIO19_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_INTR2_GPIO19_EDGE_LOW_Pos (14UL) /*!< GPIO19_EDGE_LOW (Bit 14) */
#define IO_BANK0_INTR2_GPIO19_EDGE_LOW_Msk (0x4000UL) /*!< GPIO19_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_INTR2_GPIO19_LEVEL_HIGH_Pos (13UL) /*!< GPIO19_LEVEL_HIGH (Bit 13) */
#define IO_BANK0_INTR2_GPIO19_LEVEL_HIGH_Msk (0x2000UL) /*!< GPIO19_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_INTR2_GPIO19_LEVEL_LOW_Pos (12UL) /*!< GPIO19_LEVEL_LOW (Bit 12) */
#define IO_BANK0_INTR2_GPIO19_LEVEL_LOW_Msk (0x1000UL) /*!< GPIO19_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_INTR2_GPIO18_EDGE_HIGH_Pos (11UL) /*!< GPIO18_EDGE_HIGH (Bit 11) */
#define IO_BANK0_INTR2_GPIO18_EDGE_HIGH_Msk (0x800UL) /*!< GPIO18_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_INTR2_GPIO18_EDGE_LOW_Pos (10UL) /*!< GPIO18_EDGE_LOW (Bit 10) */
#define IO_BANK0_INTR2_GPIO18_EDGE_LOW_Msk (0x400UL) /*!< GPIO18_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_INTR2_GPIO18_LEVEL_HIGH_Pos (9UL) /*!< GPIO18_LEVEL_HIGH (Bit 9) */
#define IO_BANK0_INTR2_GPIO18_LEVEL_HIGH_Msk (0x200UL) /*!< GPIO18_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_INTR2_GPIO18_LEVEL_LOW_Pos (8UL) /*!< GPIO18_LEVEL_LOW (Bit 8) */
#define IO_BANK0_INTR2_GPIO18_LEVEL_LOW_Msk (0x100UL) /*!< GPIO18_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_INTR2_GPIO17_EDGE_HIGH_Pos (7UL) /*!< GPIO17_EDGE_HIGH (Bit 7) */
#define IO_BANK0_INTR2_GPIO17_EDGE_HIGH_Msk (0x80UL) /*!< GPIO17_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_INTR2_GPIO17_EDGE_LOW_Pos (6UL) /*!< GPIO17_EDGE_LOW (Bit 6) */
#define IO_BANK0_INTR2_GPIO17_EDGE_LOW_Msk (0x40UL) /*!< GPIO17_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_INTR2_GPIO17_LEVEL_HIGH_Pos (5UL) /*!< GPIO17_LEVEL_HIGH (Bit 5) */
#define IO_BANK0_INTR2_GPIO17_LEVEL_HIGH_Msk (0x20UL) /*!< GPIO17_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_INTR2_GPIO17_LEVEL_LOW_Pos (4UL) /*!< GPIO17_LEVEL_LOW (Bit 4) */
#define IO_BANK0_INTR2_GPIO17_LEVEL_LOW_Msk (0x10UL) /*!< GPIO17_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_INTR2_GPIO16_EDGE_HIGH_Pos (3UL) /*!< GPIO16_EDGE_HIGH (Bit 3) */
#define IO_BANK0_INTR2_GPIO16_EDGE_HIGH_Msk (0x8UL) /*!< GPIO16_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_INTR2_GPIO16_EDGE_LOW_Pos (2UL) /*!< GPIO16_EDGE_LOW (Bit 2) */
#define IO_BANK0_INTR2_GPIO16_EDGE_LOW_Msk (0x4UL) /*!< GPIO16_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_INTR2_GPIO16_LEVEL_HIGH_Pos (1UL) /*!< GPIO16_LEVEL_HIGH (Bit 1) */
#define IO_BANK0_INTR2_GPIO16_LEVEL_HIGH_Msk (0x2UL) /*!< GPIO16_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_INTR2_GPIO16_LEVEL_LOW_Pos (0UL) /*!< GPIO16_LEVEL_LOW (Bit 0) */
#define IO_BANK0_INTR2_GPIO16_LEVEL_LOW_Msk (0x1UL) /*!< GPIO16_LEVEL_LOW (Bitfield-Mask: 0x01) */
/* ========================================================= INTR3 ========================================================= */
#define IO_BANK0_INTR3_GPIO29_EDGE_HIGH_Pos (23UL) /*!< GPIO29_EDGE_HIGH (Bit 23) */
#define IO_BANK0_INTR3_GPIO29_EDGE_HIGH_Msk (0x800000UL) /*!< GPIO29_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_INTR3_GPIO29_EDGE_LOW_Pos (22UL) /*!< GPIO29_EDGE_LOW (Bit 22) */
#define IO_BANK0_INTR3_GPIO29_EDGE_LOW_Msk (0x400000UL) /*!< GPIO29_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_INTR3_GPIO29_LEVEL_HIGH_Pos (21UL) /*!< GPIO29_LEVEL_HIGH (Bit 21) */
#define IO_BANK0_INTR3_GPIO29_LEVEL_HIGH_Msk (0x200000UL) /*!< GPIO29_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_INTR3_GPIO29_LEVEL_LOW_Pos (20UL) /*!< GPIO29_LEVEL_LOW (Bit 20) */
#define IO_BANK0_INTR3_GPIO29_LEVEL_LOW_Msk (0x100000UL) /*!< GPIO29_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_INTR3_GPIO28_EDGE_HIGH_Pos (19UL) /*!< GPIO28_EDGE_HIGH (Bit 19) */
#define IO_BANK0_INTR3_GPIO28_EDGE_HIGH_Msk (0x80000UL) /*!< GPIO28_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_INTR3_GPIO28_EDGE_LOW_Pos (18UL) /*!< GPIO28_EDGE_LOW (Bit 18) */
#define IO_BANK0_INTR3_GPIO28_EDGE_LOW_Msk (0x40000UL) /*!< GPIO28_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_INTR3_GPIO28_LEVEL_HIGH_Pos (17UL) /*!< GPIO28_LEVEL_HIGH (Bit 17) */
#define IO_BANK0_INTR3_GPIO28_LEVEL_HIGH_Msk (0x20000UL) /*!< GPIO28_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_INTR3_GPIO28_LEVEL_LOW_Pos (16UL) /*!< GPIO28_LEVEL_LOW (Bit 16) */
#define IO_BANK0_INTR3_GPIO28_LEVEL_LOW_Msk (0x10000UL) /*!< GPIO28_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_INTR3_GPIO27_EDGE_HIGH_Pos (15UL) /*!< GPIO27_EDGE_HIGH (Bit 15) */
#define IO_BANK0_INTR3_GPIO27_EDGE_HIGH_Msk (0x8000UL) /*!< GPIO27_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_INTR3_GPIO27_EDGE_LOW_Pos (14UL) /*!< GPIO27_EDGE_LOW (Bit 14) */
#define IO_BANK0_INTR3_GPIO27_EDGE_LOW_Msk (0x4000UL) /*!< GPIO27_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_INTR3_GPIO27_LEVEL_HIGH_Pos (13UL) /*!< GPIO27_LEVEL_HIGH (Bit 13) */
#define IO_BANK0_INTR3_GPIO27_LEVEL_HIGH_Msk (0x2000UL) /*!< GPIO27_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_INTR3_GPIO27_LEVEL_LOW_Pos (12UL) /*!< GPIO27_LEVEL_LOW (Bit 12) */
#define IO_BANK0_INTR3_GPIO27_LEVEL_LOW_Msk (0x1000UL) /*!< GPIO27_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_INTR3_GPIO26_EDGE_HIGH_Pos (11UL) /*!< GPIO26_EDGE_HIGH (Bit 11) */
#define IO_BANK0_INTR3_GPIO26_EDGE_HIGH_Msk (0x800UL) /*!< GPIO26_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_INTR3_GPIO26_EDGE_LOW_Pos (10UL) /*!< GPIO26_EDGE_LOW (Bit 10) */
#define IO_BANK0_INTR3_GPIO26_EDGE_LOW_Msk (0x400UL) /*!< GPIO26_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_INTR3_GPIO26_LEVEL_HIGH_Pos (9UL) /*!< GPIO26_LEVEL_HIGH (Bit 9) */
#define IO_BANK0_INTR3_GPIO26_LEVEL_HIGH_Msk (0x200UL) /*!< GPIO26_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_INTR3_GPIO26_LEVEL_LOW_Pos (8UL) /*!< GPIO26_LEVEL_LOW (Bit 8) */
#define IO_BANK0_INTR3_GPIO26_LEVEL_LOW_Msk (0x100UL) /*!< GPIO26_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_INTR3_GPIO25_EDGE_HIGH_Pos (7UL) /*!< GPIO25_EDGE_HIGH (Bit 7) */
#define IO_BANK0_INTR3_GPIO25_EDGE_HIGH_Msk (0x80UL) /*!< GPIO25_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_INTR3_GPIO25_EDGE_LOW_Pos (6UL) /*!< GPIO25_EDGE_LOW (Bit 6) */
#define IO_BANK0_INTR3_GPIO25_EDGE_LOW_Msk (0x40UL) /*!< GPIO25_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_INTR3_GPIO25_LEVEL_HIGH_Pos (5UL) /*!< GPIO25_LEVEL_HIGH (Bit 5) */
#define IO_BANK0_INTR3_GPIO25_LEVEL_HIGH_Msk (0x20UL) /*!< GPIO25_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_INTR3_GPIO25_LEVEL_LOW_Pos (4UL) /*!< GPIO25_LEVEL_LOW (Bit 4) */
#define IO_BANK0_INTR3_GPIO25_LEVEL_LOW_Msk (0x10UL) /*!< GPIO25_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_INTR3_GPIO24_EDGE_HIGH_Pos (3UL) /*!< GPIO24_EDGE_HIGH (Bit 3) */
#define IO_BANK0_INTR3_GPIO24_EDGE_HIGH_Msk (0x8UL) /*!< GPIO24_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_INTR3_GPIO24_EDGE_LOW_Pos (2UL) /*!< GPIO24_EDGE_LOW (Bit 2) */
#define IO_BANK0_INTR3_GPIO24_EDGE_LOW_Msk (0x4UL) /*!< GPIO24_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_INTR3_GPIO24_LEVEL_HIGH_Pos (1UL) /*!< GPIO24_LEVEL_HIGH (Bit 1) */
#define IO_BANK0_INTR3_GPIO24_LEVEL_HIGH_Msk (0x2UL) /*!< GPIO24_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_INTR3_GPIO24_LEVEL_LOW_Pos (0UL) /*!< GPIO24_LEVEL_LOW (Bit 0) */
#define IO_BANK0_INTR3_GPIO24_LEVEL_LOW_Msk (0x1UL) /*!< GPIO24_LEVEL_LOW (Bitfield-Mask: 0x01) */
/* ====================================================== PROC0_INTE0 ====================================================== */
#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_HIGH_Pos (31UL) /*!< GPIO7_EDGE_HIGH (Bit 31) */
#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_HIGH_Msk (0x80000000UL) /*!< GPIO7_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_LOW_Pos (30UL) /*!< GPIO7_EDGE_LOW (Bit 30) */
#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_LOW_Msk (0x40000000UL) /*!< GPIO7_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_HIGH_Pos (29UL) /*!< GPIO7_LEVEL_HIGH (Bit 29) */
#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_HIGH_Msk (0x20000000UL) /*!< GPIO7_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_LOW_Pos (28UL) /*!< GPIO7_LEVEL_LOW (Bit 28) */
#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_LOW_Msk (0x10000000UL) /*!< GPIO7_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_HIGH_Pos (27UL) /*!< GPIO6_EDGE_HIGH (Bit 27) */
#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_HIGH_Msk (0x8000000UL) /*!< GPIO6_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_LOW_Pos (26UL) /*!< GPIO6_EDGE_LOW (Bit 26) */
#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_LOW_Msk (0x4000000UL) /*!< GPIO6_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_HIGH_Pos (25UL) /*!< GPIO6_LEVEL_HIGH (Bit 25) */
#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_HIGH_Msk (0x2000000UL) /*!< GPIO6_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_LOW_Pos (24UL) /*!< GPIO6_LEVEL_LOW (Bit 24) */
#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_LOW_Msk (0x1000000UL) /*!< GPIO6_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_HIGH_Pos (23UL) /*!< GPIO5_EDGE_HIGH (Bit 23) */
#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_HIGH_Msk (0x800000UL) /*!< GPIO5_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_LOW_Pos (22UL) /*!< GPIO5_EDGE_LOW (Bit 22) */
#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_LOW_Msk (0x400000UL) /*!< GPIO5_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_HIGH_Pos (21UL) /*!< GPIO5_LEVEL_HIGH (Bit 21) */
#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_HIGH_Msk (0x200000UL) /*!< GPIO5_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_LOW_Pos (20UL) /*!< GPIO5_LEVEL_LOW (Bit 20) */
#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_LOW_Msk (0x100000UL) /*!< GPIO5_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_HIGH_Pos (19UL) /*!< GPIO4_EDGE_HIGH (Bit 19) */
#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_HIGH_Msk (0x80000UL) /*!< GPIO4_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_LOW_Pos (18UL) /*!< GPIO4_EDGE_LOW (Bit 18) */
#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_LOW_Msk (0x40000UL) /*!< GPIO4_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_HIGH_Pos (17UL) /*!< GPIO4_LEVEL_HIGH (Bit 17) */
#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_HIGH_Msk (0x20000UL) /*!< GPIO4_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_LOW_Pos (16UL) /*!< GPIO4_LEVEL_LOW (Bit 16) */
#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_LOW_Msk (0x10000UL) /*!< GPIO4_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_HIGH_Pos (15UL) /*!< GPIO3_EDGE_HIGH (Bit 15) */
#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_HIGH_Msk (0x8000UL) /*!< GPIO3_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_LOW_Pos (14UL) /*!< GPIO3_EDGE_LOW (Bit 14) */
#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_LOW_Msk (0x4000UL) /*!< GPIO3_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_HIGH_Pos (13UL) /*!< GPIO3_LEVEL_HIGH (Bit 13) */
#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_HIGH_Msk (0x2000UL) /*!< GPIO3_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_LOW_Pos (12UL) /*!< GPIO3_LEVEL_LOW (Bit 12) */
#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_LOW_Msk (0x1000UL) /*!< GPIO3_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_HIGH_Pos (11UL) /*!< GPIO2_EDGE_HIGH (Bit 11) */
#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_HIGH_Msk (0x800UL) /*!< GPIO2_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_LOW_Pos (10UL) /*!< GPIO2_EDGE_LOW (Bit 10) */
#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_LOW_Msk (0x400UL) /*!< GPIO2_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_HIGH_Pos (9UL) /*!< GPIO2_LEVEL_HIGH (Bit 9) */
#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_HIGH_Msk (0x200UL) /*!< GPIO2_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_LOW_Pos (8UL) /*!< GPIO2_LEVEL_LOW (Bit 8) */
#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_LOW_Msk (0x100UL) /*!< GPIO2_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_HIGH_Pos (7UL) /*!< GPIO1_EDGE_HIGH (Bit 7) */
#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_HIGH_Msk (0x80UL) /*!< GPIO1_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_LOW_Pos (6UL) /*!< GPIO1_EDGE_LOW (Bit 6) */
#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_LOW_Msk (0x40UL) /*!< GPIO1_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_HIGH_Pos (5UL) /*!< GPIO1_LEVEL_HIGH (Bit 5) */
#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_HIGH_Msk (0x20UL) /*!< GPIO1_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_LOW_Pos (4UL) /*!< GPIO1_LEVEL_LOW (Bit 4) */
#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_LOW_Msk (0x10UL) /*!< GPIO1_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_HIGH_Pos (3UL) /*!< GPIO0_EDGE_HIGH (Bit 3) */
#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_HIGH_Msk (0x8UL) /*!< GPIO0_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_LOW_Pos (2UL) /*!< GPIO0_EDGE_LOW (Bit 2) */
#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_LOW_Msk (0x4UL) /*!< GPIO0_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_HIGH_Pos (1UL) /*!< GPIO0_LEVEL_HIGH (Bit 1) */
#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_HIGH_Msk (0x2UL) /*!< GPIO0_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_LOW_Pos (0UL) /*!< GPIO0_LEVEL_LOW (Bit 0) */
#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_LOW_Msk (0x1UL) /*!< GPIO0_LEVEL_LOW (Bitfield-Mask: 0x01) */
/* ====================================================== PROC0_INTE1 ====================================================== */
#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_HIGH_Pos (31UL) /*!< GPIO15_EDGE_HIGH (Bit 31) */
#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_HIGH_Msk (0x80000000UL) /*!< GPIO15_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_LOW_Pos (30UL) /*!< GPIO15_EDGE_LOW (Bit 30) */
#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_LOW_Msk (0x40000000UL) /*!< GPIO15_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_HIGH_Pos (29UL) /*!< GPIO15_LEVEL_HIGH (Bit 29) */
#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_HIGH_Msk (0x20000000UL) /*!< GPIO15_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_LOW_Pos (28UL) /*!< GPIO15_LEVEL_LOW (Bit 28) */
#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_LOW_Msk (0x10000000UL) /*!< GPIO15_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_HIGH_Pos (27UL) /*!< GPIO14_EDGE_HIGH (Bit 27) */
#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_HIGH_Msk (0x8000000UL) /*!< GPIO14_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_LOW_Pos (26UL) /*!< GPIO14_EDGE_LOW (Bit 26) */
#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_LOW_Msk (0x4000000UL) /*!< GPIO14_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_HIGH_Pos (25UL) /*!< GPIO14_LEVEL_HIGH (Bit 25) */
#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_HIGH_Msk (0x2000000UL) /*!< GPIO14_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_LOW_Pos (24UL) /*!< GPIO14_LEVEL_LOW (Bit 24) */
#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_LOW_Msk (0x1000000UL) /*!< GPIO14_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_HIGH_Pos (23UL) /*!< GPIO13_EDGE_HIGH (Bit 23) */
#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_HIGH_Msk (0x800000UL) /*!< GPIO13_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_LOW_Pos (22UL) /*!< GPIO13_EDGE_LOW (Bit 22) */
#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_LOW_Msk (0x400000UL) /*!< GPIO13_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_HIGH_Pos (21UL) /*!< GPIO13_LEVEL_HIGH (Bit 21) */
#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_HIGH_Msk (0x200000UL) /*!< GPIO13_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_LOW_Pos (20UL) /*!< GPIO13_LEVEL_LOW (Bit 20) */
#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_LOW_Msk (0x100000UL) /*!< GPIO13_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_HIGH_Pos (19UL) /*!< GPIO12_EDGE_HIGH (Bit 19) */
#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_HIGH_Msk (0x80000UL) /*!< GPIO12_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_LOW_Pos (18UL) /*!< GPIO12_EDGE_LOW (Bit 18) */
#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_LOW_Msk (0x40000UL) /*!< GPIO12_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_HIGH_Pos (17UL) /*!< GPIO12_LEVEL_HIGH (Bit 17) */
#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_HIGH_Msk (0x20000UL) /*!< GPIO12_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_LOW_Pos (16UL) /*!< GPIO12_LEVEL_LOW (Bit 16) */
#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_LOW_Msk (0x10000UL) /*!< GPIO12_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_HIGH_Pos (15UL) /*!< GPIO11_EDGE_HIGH (Bit 15) */
#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_HIGH_Msk (0x8000UL) /*!< GPIO11_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_LOW_Pos (14UL) /*!< GPIO11_EDGE_LOW (Bit 14) */
#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_LOW_Msk (0x4000UL) /*!< GPIO11_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_HIGH_Pos (13UL) /*!< GPIO11_LEVEL_HIGH (Bit 13) */
#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_HIGH_Msk (0x2000UL) /*!< GPIO11_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_LOW_Pos (12UL) /*!< GPIO11_LEVEL_LOW (Bit 12) */
#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_LOW_Msk (0x1000UL) /*!< GPIO11_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_HIGH_Pos (11UL) /*!< GPIO10_EDGE_HIGH (Bit 11) */
#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_HIGH_Msk (0x800UL) /*!< GPIO10_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_LOW_Pos (10UL) /*!< GPIO10_EDGE_LOW (Bit 10) */
#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_LOW_Msk (0x400UL) /*!< GPIO10_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_HIGH_Pos (9UL) /*!< GPIO10_LEVEL_HIGH (Bit 9) */
#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_HIGH_Msk (0x200UL) /*!< GPIO10_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_LOW_Pos (8UL) /*!< GPIO10_LEVEL_LOW (Bit 8) */
#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_LOW_Msk (0x100UL) /*!< GPIO10_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_HIGH_Pos (7UL) /*!< GPIO9_EDGE_HIGH (Bit 7) */
#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_HIGH_Msk (0x80UL) /*!< GPIO9_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_LOW_Pos (6UL) /*!< GPIO9_EDGE_LOW (Bit 6) */
#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_LOW_Msk (0x40UL) /*!< GPIO9_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_HIGH_Pos (5UL) /*!< GPIO9_LEVEL_HIGH (Bit 5) */
#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_HIGH_Msk (0x20UL) /*!< GPIO9_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_LOW_Pos (4UL) /*!< GPIO9_LEVEL_LOW (Bit 4) */
#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_LOW_Msk (0x10UL) /*!< GPIO9_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_HIGH_Pos (3UL) /*!< GPIO8_EDGE_HIGH (Bit 3) */
#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_HIGH_Msk (0x8UL) /*!< GPIO8_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_LOW_Pos (2UL) /*!< GPIO8_EDGE_LOW (Bit 2) */
#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_LOW_Msk (0x4UL) /*!< GPIO8_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_HIGH_Pos (1UL) /*!< GPIO8_LEVEL_HIGH (Bit 1) */
#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_HIGH_Msk (0x2UL) /*!< GPIO8_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_LOW_Pos (0UL) /*!< GPIO8_LEVEL_LOW (Bit 0) */
#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_LOW_Msk (0x1UL) /*!< GPIO8_LEVEL_LOW (Bitfield-Mask: 0x01) */
/* ====================================================== PROC0_INTE2 ====================================================== */
#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_HIGH_Pos (31UL) /*!< GPIO23_EDGE_HIGH (Bit 31) */
#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_HIGH_Msk (0x80000000UL) /*!< GPIO23_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_LOW_Pos (30UL) /*!< GPIO23_EDGE_LOW (Bit 30) */
#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_LOW_Msk (0x40000000UL) /*!< GPIO23_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_HIGH_Pos (29UL) /*!< GPIO23_LEVEL_HIGH (Bit 29) */
#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_HIGH_Msk (0x20000000UL) /*!< GPIO23_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_LOW_Pos (28UL) /*!< GPIO23_LEVEL_LOW (Bit 28) */
#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_LOW_Msk (0x10000000UL) /*!< GPIO23_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_HIGH_Pos (27UL) /*!< GPIO22_EDGE_HIGH (Bit 27) */
#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_HIGH_Msk (0x8000000UL) /*!< GPIO22_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_LOW_Pos (26UL) /*!< GPIO22_EDGE_LOW (Bit 26) */
#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_LOW_Msk (0x4000000UL) /*!< GPIO22_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_HIGH_Pos (25UL) /*!< GPIO22_LEVEL_HIGH (Bit 25) */
#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_HIGH_Msk (0x2000000UL) /*!< GPIO22_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_LOW_Pos (24UL) /*!< GPIO22_LEVEL_LOW (Bit 24) */
#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_LOW_Msk (0x1000000UL) /*!< GPIO22_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_HIGH_Pos (23UL) /*!< GPIO21_EDGE_HIGH (Bit 23) */
#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_HIGH_Msk (0x800000UL) /*!< GPIO21_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_LOW_Pos (22UL) /*!< GPIO21_EDGE_LOW (Bit 22) */
#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_LOW_Msk (0x400000UL) /*!< GPIO21_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_HIGH_Pos (21UL) /*!< GPIO21_LEVEL_HIGH (Bit 21) */
#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_HIGH_Msk (0x200000UL) /*!< GPIO21_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_LOW_Pos (20UL) /*!< GPIO21_LEVEL_LOW (Bit 20) */
#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_LOW_Msk (0x100000UL) /*!< GPIO21_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_HIGH_Pos (19UL) /*!< GPIO20_EDGE_HIGH (Bit 19) */
#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_HIGH_Msk (0x80000UL) /*!< GPIO20_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_LOW_Pos (18UL) /*!< GPIO20_EDGE_LOW (Bit 18) */
#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_LOW_Msk (0x40000UL) /*!< GPIO20_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_HIGH_Pos (17UL) /*!< GPIO20_LEVEL_HIGH (Bit 17) */
#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_HIGH_Msk (0x20000UL) /*!< GPIO20_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_LOW_Pos (16UL) /*!< GPIO20_LEVEL_LOW (Bit 16) */
#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_LOW_Msk (0x10000UL) /*!< GPIO20_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_HIGH_Pos (15UL) /*!< GPIO19_EDGE_HIGH (Bit 15) */
#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_HIGH_Msk (0x8000UL) /*!< GPIO19_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_LOW_Pos (14UL) /*!< GPIO19_EDGE_LOW (Bit 14) */
#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_LOW_Msk (0x4000UL) /*!< GPIO19_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_HIGH_Pos (13UL) /*!< GPIO19_LEVEL_HIGH (Bit 13) */
#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_HIGH_Msk (0x2000UL) /*!< GPIO19_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_LOW_Pos (12UL) /*!< GPIO19_LEVEL_LOW (Bit 12) */
#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_LOW_Msk (0x1000UL) /*!< GPIO19_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_HIGH_Pos (11UL) /*!< GPIO18_EDGE_HIGH (Bit 11) */
#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_HIGH_Msk (0x800UL) /*!< GPIO18_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_LOW_Pos (10UL) /*!< GPIO18_EDGE_LOW (Bit 10) */
#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_LOW_Msk (0x400UL) /*!< GPIO18_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_HIGH_Pos (9UL) /*!< GPIO18_LEVEL_HIGH (Bit 9) */
#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_HIGH_Msk (0x200UL) /*!< GPIO18_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_LOW_Pos (8UL) /*!< GPIO18_LEVEL_LOW (Bit 8) */
#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_LOW_Msk (0x100UL) /*!< GPIO18_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_HIGH_Pos (7UL) /*!< GPIO17_EDGE_HIGH (Bit 7) */
#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_HIGH_Msk (0x80UL) /*!< GPIO17_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_LOW_Pos (6UL) /*!< GPIO17_EDGE_LOW (Bit 6) */
#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_LOW_Msk (0x40UL) /*!< GPIO17_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_HIGH_Pos (5UL) /*!< GPIO17_LEVEL_HIGH (Bit 5) */
#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_HIGH_Msk (0x20UL) /*!< GPIO17_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_LOW_Pos (4UL) /*!< GPIO17_LEVEL_LOW (Bit 4) */
#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_LOW_Msk (0x10UL) /*!< GPIO17_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_HIGH_Pos (3UL) /*!< GPIO16_EDGE_HIGH (Bit 3) */
#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_HIGH_Msk (0x8UL) /*!< GPIO16_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_LOW_Pos (2UL) /*!< GPIO16_EDGE_LOW (Bit 2) */
#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_LOW_Msk (0x4UL) /*!< GPIO16_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_HIGH_Pos (1UL) /*!< GPIO16_LEVEL_HIGH (Bit 1) */
#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_HIGH_Msk (0x2UL) /*!< GPIO16_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_LOW_Pos (0UL) /*!< GPIO16_LEVEL_LOW (Bit 0) */
#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_LOW_Msk (0x1UL) /*!< GPIO16_LEVEL_LOW (Bitfield-Mask: 0x01) */
/* ====================================================== PROC0_INTE3 ====================================================== */
#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_HIGH_Pos (23UL) /*!< GPIO29_EDGE_HIGH (Bit 23) */
#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_HIGH_Msk (0x800000UL) /*!< GPIO29_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_LOW_Pos (22UL) /*!< GPIO29_EDGE_LOW (Bit 22) */
#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_LOW_Msk (0x400000UL) /*!< GPIO29_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_HIGH_Pos (21UL) /*!< GPIO29_LEVEL_HIGH (Bit 21) */
#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_HIGH_Msk (0x200000UL) /*!< GPIO29_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_LOW_Pos (20UL) /*!< GPIO29_LEVEL_LOW (Bit 20) */
#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_LOW_Msk (0x100000UL) /*!< GPIO29_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_HIGH_Pos (19UL) /*!< GPIO28_EDGE_HIGH (Bit 19) */
#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_HIGH_Msk (0x80000UL) /*!< GPIO28_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_LOW_Pos (18UL) /*!< GPIO28_EDGE_LOW (Bit 18) */
#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_LOW_Msk (0x40000UL) /*!< GPIO28_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_HIGH_Pos (17UL) /*!< GPIO28_LEVEL_HIGH (Bit 17) */
#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_HIGH_Msk (0x20000UL) /*!< GPIO28_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_LOW_Pos (16UL) /*!< GPIO28_LEVEL_LOW (Bit 16) */
#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_LOW_Msk (0x10000UL) /*!< GPIO28_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_HIGH_Pos (15UL) /*!< GPIO27_EDGE_HIGH (Bit 15) */
#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_HIGH_Msk (0x8000UL) /*!< GPIO27_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_LOW_Pos (14UL) /*!< GPIO27_EDGE_LOW (Bit 14) */
#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_LOW_Msk (0x4000UL) /*!< GPIO27_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_HIGH_Pos (13UL) /*!< GPIO27_LEVEL_HIGH (Bit 13) */
#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_HIGH_Msk (0x2000UL) /*!< GPIO27_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_LOW_Pos (12UL) /*!< GPIO27_LEVEL_LOW (Bit 12) */
#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_LOW_Msk (0x1000UL) /*!< GPIO27_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_HIGH_Pos (11UL) /*!< GPIO26_EDGE_HIGH (Bit 11) */
#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_HIGH_Msk (0x800UL) /*!< GPIO26_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_LOW_Pos (10UL) /*!< GPIO26_EDGE_LOW (Bit 10) */
#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_LOW_Msk (0x400UL) /*!< GPIO26_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_HIGH_Pos (9UL) /*!< GPIO26_LEVEL_HIGH (Bit 9) */
#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_HIGH_Msk (0x200UL) /*!< GPIO26_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_LOW_Pos (8UL) /*!< GPIO26_LEVEL_LOW (Bit 8) */
#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_LOW_Msk (0x100UL) /*!< GPIO26_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_HIGH_Pos (7UL) /*!< GPIO25_EDGE_HIGH (Bit 7) */
#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_HIGH_Msk (0x80UL) /*!< GPIO25_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_LOW_Pos (6UL) /*!< GPIO25_EDGE_LOW (Bit 6) */
#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_LOW_Msk (0x40UL) /*!< GPIO25_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_HIGH_Pos (5UL) /*!< GPIO25_LEVEL_HIGH (Bit 5) */
#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_HIGH_Msk (0x20UL) /*!< GPIO25_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_LOW_Pos (4UL) /*!< GPIO25_LEVEL_LOW (Bit 4) */
#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_LOW_Msk (0x10UL) /*!< GPIO25_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_HIGH_Pos (3UL) /*!< GPIO24_EDGE_HIGH (Bit 3) */
#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_HIGH_Msk (0x8UL) /*!< GPIO24_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_LOW_Pos (2UL) /*!< GPIO24_EDGE_LOW (Bit 2) */
#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_LOW_Msk (0x4UL) /*!< GPIO24_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_HIGH_Pos (1UL) /*!< GPIO24_LEVEL_HIGH (Bit 1) */
#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_HIGH_Msk (0x2UL) /*!< GPIO24_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_LOW_Pos (0UL) /*!< GPIO24_LEVEL_LOW (Bit 0) */
#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_LOW_Msk (0x1UL) /*!< GPIO24_LEVEL_LOW (Bitfield-Mask: 0x01) */
/* ====================================================== PROC0_INTF0 ====================================================== */
#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_HIGH_Pos (31UL) /*!< GPIO7_EDGE_HIGH (Bit 31) */
#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_HIGH_Msk (0x80000000UL) /*!< GPIO7_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_LOW_Pos (30UL) /*!< GPIO7_EDGE_LOW (Bit 30) */
#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_LOW_Msk (0x40000000UL) /*!< GPIO7_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_HIGH_Pos (29UL) /*!< GPIO7_LEVEL_HIGH (Bit 29) */
#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_HIGH_Msk (0x20000000UL) /*!< GPIO7_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_LOW_Pos (28UL) /*!< GPIO7_LEVEL_LOW (Bit 28) */
#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_LOW_Msk (0x10000000UL) /*!< GPIO7_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_HIGH_Pos (27UL) /*!< GPIO6_EDGE_HIGH (Bit 27) */
#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_HIGH_Msk (0x8000000UL) /*!< GPIO6_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_LOW_Pos (26UL) /*!< GPIO6_EDGE_LOW (Bit 26) */
#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_LOW_Msk (0x4000000UL) /*!< GPIO6_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_HIGH_Pos (25UL) /*!< GPIO6_LEVEL_HIGH (Bit 25) */
#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_HIGH_Msk (0x2000000UL) /*!< GPIO6_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_LOW_Pos (24UL) /*!< GPIO6_LEVEL_LOW (Bit 24) */
#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_LOW_Msk (0x1000000UL) /*!< GPIO6_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_HIGH_Pos (23UL) /*!< GPIO5_EDGE_HIGH (Bit 23) */
#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_HIGH_Msk (0x800000UL) /*!< GPIO5_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_LOW_Pos (22UL) /*!< GPIO5_EDGE_LOW (Bit 22) */
#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_LOW_Msk (0x400000UL) /*!< GPIO5_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_HIGH_Pos (21UL) /*!< GPIO5_LEVEL_HIGH (Bit 21) */
#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_HIGH_Msk (0x200000UL) /*!< GPIO5_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_LOW_Pos (20UL) /*!< GPIO5_LEVEL_LOW (Bit 20) */
#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_LOW_Msk (0x100000UL) /*!< GPIO5_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_HIGH_Pos (19UL) /*!< GPIO4_EDGE_HIGH (Bit 19) */
#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_HIGH_Msk (0x80000UL) /*!< GPIO4_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_LOW_Pos (18UL) /*!< GPIO4_EDGE_LOW (Bit 18) */
#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_LOW_Msk (0x40000UL) /*!< GPIO4_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_HIGH_Pos (17UL) /*!< GPIO4_LEVEL_HIGH (Bit 17) */
#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_HIGH_Msk (0x20000UL) /*!< GPIO4_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_LOW_Pos (16UL) /*!< GPIO4_LEVEL_LOW (Bit 16) */
#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_LOW_Msk (0x10000UL) /*!< GPIO4_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_HIGH_Pos (15UL) /*!< GPIO3_EDGE_HIGH (Bit 15) */
#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_HIGH_Msk (0x8000UL) /*!< GPIO3_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_LOW_Pos (14UL) /*!< GPIO3_EDGE_LOW (Bit 14) */
#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_LOW_Msk (0x4000UL) /*!< GPIO3_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_HIGH_Pos (13UL) /*!< GPIO3_LEVEL_HIGH (Bit 13) */
#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_HIGH_Msk (0x2000UL) /*!< GPIO3_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_LOW_Pos (12UL) /*!< GPIO3_LEVEL_LOW (Bit 12) */
#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_LOW_Msk (0x1000UL) /*!< GPIO3_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_HIGH_Pos (11UL) /*!< GPIO2_EDGE_HIGH (Bit 11) */
#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_HIGH_Msk (0x800UL) /*!< GPIO2_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_LOW_Pos (10UL) /*!< GPIO2_EDGE_LOW (Bit 10) */
#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_LOW_Msk (0x400UL) /*!< GPIO2_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_HIGH_Pos (9UL) /*!< GPIO2_LEVEL_HIGH (Bit 9) */
#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_HIGH_Msk (0x200UL) /*!< GPIO2_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_LOW_Pos (8UL) /*!< GPIO2_LEVEL_LOW (Bit 8) */
#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_LOW_Msk (0x100UL) /*!< GPIO2_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_HIGH_Pos (7UL) /*!< GPIO1_EDGE_HIGH (Bit 7) */
#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_HIGH_Msk (0x80UL) /*!< GPIO1_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_LOW_Pos (6UL) /*!< GPIO1_EDGE_LOW (Bit 6) */
#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_LOW_Msk (0x40UL) /*!< GPIO1_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_HIGH_Pos (5UL) /*!< GPIO1_LEVEL_HIGH (Bit 5) */
#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_HIGH_Msk (0x20UL) /*!< GPIO1_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_LOW_Pos (4UL) /*!< GPIO1_LEVEL_LOW (Bit 4) */
#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_LOW_Msk (0x10UL) /*!< GPIO1_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_HIGH_Pos (3UL) /*!< GPIO0_EDGE_HIGH (Bit 3) */
#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_HIGH_Msk (0x8UL) /*!< GPIO0_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_LOW_Pos (2UL) /*!< GPIO0_EDGE_LOW (Bit 2) */
#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_LOW_Msk (0x4UL) /*!< GPIO0_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_HIGH_Pos (1UL) /*!< GPIO0_LEVEL_HIGH (Bit 1) */
#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_HIGH_Msk (0x2UL) /*!< GPIO0_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_LOW_Pos (0UL) /*!< GPIO0_LEVEL_LOW (Bit 0) */
#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_LOW_Msk (0x1UL) /*!< GPIO0_LEVEL_LOW (Bitfield-Mask: 0x01) */
/* ====================================================== PROC0_INTF1 ====================================================== */
#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_HIGH_Pos (31UL) /*!< GPIO15_EDGE_HIGH (Bit 31) */
#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_HIGH_Msk (0x80000000UL) /*!< GPIO15_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_LOW_Pos (30UL) /*!< GPIO15_EDGE_LOW (Bit 30) */
#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_LOW_Msk (0x40000000UL) /*!< GPIO15_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_HIGH_Pos (29UL) /*!< GPIO15_LEVEL_HIGH (Bit 29) */
#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_HIGH_Msk (0x20000000UL) /*!< GPIO15_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_LOW_Pos (28UL) /*!< GPIO15_LEVEL_LOW (Bit 28) */
#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_LOW_Msk (0x10000000UL) /*!< GPIO15_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_HIGH_Pos (27UL) /*!< GPIO14_EDGE_HIGH (Bit 27) */
#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_HIGH_Msk (0x8000000UL) /*!< GPIO14_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_LOW_Pos (26UL) /*!< GPIO14_EDGE_LOW (Bit 26) */
#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_LOW_Msk (0x4000000UL) /*!< GPIO14_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_HIGH_Pos (25UL) /*!< GPIO14_LEVEL_HIGH (Bit 25) */
#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_HIGH_Msk (0x2000000UL) /*!< GPIO14_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_LOW_Pos (24UL) /*!< GPIO14_LEVEL_LOW (Bit 24) */
#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_LOW_Msk (0x1000000UL) /*!< GPIO14_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_HIGH_Pos (23UL) /*!< GPIO13_EDGE_HIGH (Bit 23) */
#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_HIGH_Msk (0x800000UL) /*!< GPIO13_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_LOW_Pos (22UL) /*!< GPIO13_EDGE_LOW (Bit 22) */
#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_LOW_Msk (0x400000UL) /*!< GPIO13_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_HIGH_Pos (21UL) /*!< GPIO13_LEVEL_HIGH (Bit 21) */
#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_HIGH_Msk (0x200000UL) /*!< GPIO13_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_LOW_Pos (20UL) /*!< GPIO13_LEVEL_LOW (Bit 20) */
#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_LOW_Msk (0x100000UL) /*!< GPIO13_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_HIGH_Pos (19UL) /*!< GPIO12_EDGE_HIGH (Bit 19) */
#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_HIGH_Msk (0x80000UL) /*!< GPIO12_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_LOW_Pos (18UL) /*!< GPIO12_EDGE_LOW (Bit 18) */
#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_LOW_Msk (0x40000UL) /*!< GPIO12_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_HIGH_Pos (17UL) /*!< GPIO12_LEVEL_HIGH (Bit 17) */
#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_HIGH_Msk (0x20000UL) /*!< GPIO12_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_LOW_Pos (16UL) /*!< GPIO12_LEVEL_LOW (Bit 16) */
#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_LOW_Msk (0x10000UL) /*!< GPIO12_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_HIGH_Pos (15UL) /*!< GPIO11_EDGE_HIGH (Bit 15) */
#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_HIGH_Msk (0x8000UL) /*!< GPIO11_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_LOW_Pos (14UL) /*!< GPIO11_EDGE_LOW (Bit 14) */
#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_LOW_Msk (0x4000UL) /*!< GPIO11_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_HIGH_Pos (13UL) /*!< GPIO11_LEVEL_HIGH (Bit 13) */
#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_HIGH_Msk (0x2000UL) /*!< GPIO11_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_LOW_Pos (12UL) /*!< GPIO11_LEVEL_LOW (Bit 12) */
#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_LOW_Msk (0x1000UL) /*!< GPIO11_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_HIGH_Pos (11UL) /*!< GPIO10_EDGE_HIGH (Bit 11) */
#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_HIGH_Msk (0x800UL) /*!< GPIO10_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_LOW_Pos (10UL) /*!< GPIO10_EDGE_LOW (Bit 10) */
#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_LOW_Msk (0x400UL) /*!< GPIO10_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_HIGH_Pos (9UL) /*!< GPIO10_LEVEL_HIGH (Bit 9) */
#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_HIGH_Msk (0x200UL) /*!< GPIO10_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_LOW_Pos (8UL) /*!< GPIO10_LEVEL_LOW (Bit 8) */
#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_LOW_Msk (0x100UL) /*!< GPIO10_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_HIGH_Pos (7UL) /*!< GPIO9_EDGE_HIGH (Bit 7) */
#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_HIGH_Msk (0x80UL) /*!< GPIO9_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_LOW_Pos (6UL) /*!< GPIO9_EDGE_LOW (Bit 6) */
#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_LOW_Msk (0x40UL) /*!< GPIO9_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_HIGH_Pos (5UL) /*!< GPIO9_LEVEL_HIGH (Bit 5) */
#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_HIGH_Msk (0x20UL) /*!< GPIO9_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_LOW_Pos (4UL) /*!< GPIO9_LEVEL_LOW (Bit 4) */
#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_LOW_Msk (0x10UL) /*!< GPIO9_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_HIGH_Pos (3UL) /*!< GPIO8_EDGE_HIGH (Bit 3) */
#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_HIGH_Msk (0x8UL) /*!< GPIO8_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_LOW_Pos (2UL) /*!< GPIO8_EDGE_LOW (Bit 2) */
#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_LOW_Msk (0x4UL) /*!< GPIO8_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_HIGH_Pos (1UL) /*!< GPIO8_LEVEL_HIGH (Bit 1) */
#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_HIGH_Msk (0x2UL) /*!< GPIO8_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_LOW_Pos (0UL) /*!< GPIO8_LEVEL_LOW (Bit 0) */
#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_LOW_Msk (0x1UL) /*!< GPIO8_LEVEL_LOW (Bitfield-Mask: 0x01) */
/* ====================================================== PROC0_INTF2 ====================================================== */
#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_HIGH_Pos (31UL) /*!< GPIO23_EDGE_HIGH (Bit 31) */
#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_HIGH_Msk (0x80000000UL) /*!< GPIO23_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_LOW_Pos (30UL) /*!< GPIO23_EDGE_LOW (Bit 30) */
#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_LOW_Msk (0x40000000UL) /*!< GPIO23_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_HIGH_Pos (29UL) /*!< GPIO23_LEVEL_HIGH (Bit 29) */
#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_HIGH_Msk (0x20000000UL) /*!< GPIO23_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_LOW_Pos (28UL) /*!< GPIO23_LEVEL_LOW (Bit 28) */
#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_LOW_Msk (0x10000000UL) /*!< GPIO23_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_HIGH_Pos (27UL) /*!< GPIO22_EDGE_HIGH (Bit 27) */
#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_HIGH_Msk (0x8000000UL) /*!< GPIO22_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_LOW_Pos (26UL) /*!< GPIO22_EDGE_LOW (Bit 26) */
#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_LOW_Msk (0x4000000UL) /*!< GPIO22_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_HIGH_Pos (25UL) /*!< GPIO22_LEVEL_HIGH (Bit 25) */
#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_HIGH_Msk (0x2000000UL) /*!< GPIO22_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_LOW_Pos (24UL) /*!< GPIO22_LEVEL_LOW (Bit 24) */
#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_LOW_Msk (0x1000000UL) /*!< GPIO22_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_HIGH_Pos (23UL) /*!< GPIO21_EDGE_HIGH (Bit 23) */
#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_HIGH_Msk (0x800000UL) /*!< GPIO21_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_LOW_Pos (22UL) /*!< GPIO21_EDGE_LOW (Bit 22) */
#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_LOW_Msk (0x400000UL) /*!< GPIO21_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_HIGH_Pos (21UL) /*!< GPIO21_LEVEL_HIGH (Bit 21) */
#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_HIGH_Msk (0x200000UL) /*!< GPIO21_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_LOW_Pos (20UL) /*!< GPIO21_LEVEL_LOW (Bit 20) */
#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_LOW_Msk (0x100000UL) /*!< GPIO21_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_HIGH_Pos (19UL) /*!< GPIO20_EDGE_HIGH (Bit 19) */
#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_HIGH_Msk (0x80000UL) /*!< GPIO20_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_LOW_Pos (18UL) /*!< GPIO20_EDGE_LOW (Bit 18) */
#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_LOW_Msk (0x40000UL) /*!< GPIO20_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_HIGH_Pos (17UL) /*!< GPIO20_LEVEL_HIGH (Bit 17) */
#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_HIGH_Msk (0x20000UL) /*!< GPIO20_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_LOW_Pos (16UL) /*!< GPIO20_LEVEL_LOW (Bit 16) */
#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_LOW_Msk (0x10000UL) /*!< GPIO20_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_HIGH_Pos (15UL) /*!< GPIO19_EDGE_HIGH (Bit 15) */
#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_HIGH_Msk (0x8000UL) /*!< GPIO19_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_LOW_Pos (14UL) /*!< GPIO19_EDGE_LOW (Bit 14) */
#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_LOW_Msk (0x4000UL) /*!< GPIO19_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_HIGH_Pos (13UL) /*!< GPIO19_LEVEL_HIGH (Bit 13) */
#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_HIGH_Msk (0x2000UL) /*!< GPIO19_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_LOW_Pos (12UL) /*!< GPIO19_LEVEL_LOW (Bit 12) */
#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_LOW_Msk (0x1000UL) /*!< GPIO19_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_HIGH_Pos (11UL) /*!< GPIO18_EDGE_HIGH (Bit 11) */
#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_HIGH_Msk (0x800UL) /*!< GPIO18_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_LOW_Pos (10UL) /*!< GPIO18_EDGE_LOW (Bit 10) */
#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_LOW_Msk (0x400UL) /*!< GPIO18_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_HIGH_Pos (9UL) /*!< GPIO18_LEVEL_HIGH (Bit 9) */
#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_HIGH_Msk (0x200UL) /*!< GPIO18_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_LOW_Pos (8UL) /*!< GPIO18_LEVEL_LOW (Bit 8) */
#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_LOW_Msk (0x100UL) /*!< GPIO18_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_HIGH_Pos (7UL) /*!< GPIO17_EDGE_HIGH (Bit 7) */
#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_HIGH_Msk (0x80UL) /*!< GPIO17_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_LOW_Pos (6UL) /*!< GPIO17_EDGE_LOW (Bit 6) */
#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_LOW_Msk (0x40UL) /*!< GPIO17_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_HIGH_Pos (5UL) /*!< GPIO17_LEVEL_HIGH (Bit 5) */
#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_HIGH_Msk (0x20UL) /*!< GPIO17_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_LOW_Pos (4UL) /*!< GPIO17_LEVEL_LOW (Bit 4) */
#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_LOW_Msk (0x10UL) /*!< GPIO17_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_HIGH_Pos (3UL) /*!< GPIO16_EDGE_HIGH (Bit 3) */
#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_HIGH_Msk (0x8UL) /*!< GPIO16_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_LOW_Pos (2UL) /*!< GPIO16_EDGE_LOW (Bit 2) */
#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_LOW_Msk (0x4UL) /*!< GPIO16_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_HIGH_Pos (1UL) /*!< GPIO16_LEVEL_HIGH (Bit 1) */
#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_HIGH_Msk (0x2UL) /*!< GPIO16_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_LOW_Pos (0UL) /*!< GPIO16_LEVEL_LOW (Bit 0) */
#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_LOW_Msk (0x1UL) /*!< GPIO16_LEVEL_LOW (Bitfield-Mask: 0x01) */
/* ====================================================== PROC0_INTF3 ====================================================== */
#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_HIGH_Pos (23UL) /*!< GPIO29_EDGE_HIGH (Bit 23) */
#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_HIGH_Msk (0x800000UL) /*!< GPIO29_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_LOW_Pos (22UL) /*!< GPIO29_EDGE_LOW (Bit 22) */
#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_LOW_Msk (0x400000UL) /*!< GPIO29_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_HIGH_Pos (21UL) /*!< GPIO29_LEVEL_HIGH (Bit 21) */
#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_HIGH_Msk (0x200000UL) /*!< GPIO29_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_LOW_Pos (20UL) /*!< GPIO29_LEVEL_LOW (Bit 20) */
#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_LOW_Msk (0x100000UL) /*!< GPIO29_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_HIGH_Pos (19UL) /*!< GPIO28_EDGE_HIGH (Bit 19) */
#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_HIGH_Msk (0x80000UL) /*!< GPIO28_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_LOW_Pos (18UL) /*!< GPIO28_EDGE_LOW (Bit 18) */
#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_LOW_Msk (0x40000UL) /*!< GPIO28_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_HIGH_Pos (17UL) /*!< GPIO28_LEVEL_HIGH (Bit 17) */
#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_HIGH_Msk (0x20000UL) /*!< GPIO28_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_LOW_Pos (16UL) /*!< GPIO28_LEVEL_LOW (Bit 16) */
#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_LOW_Msk (0x10000UL) /*!< GPIO28_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_HIGH_Pos (15UL) /*!< GPIO27_EDGE_HIGH (Bit 15) */
#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_HIGH_Msk (0x8000UL) /*!< GPIO27_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_LOW_Pos (14UL) /*!< GPIO27_EDGE_LOW (Bit 14) */
#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_LOW_Msk (0x4000UL) /*!< GPIO27_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_HIGH_Pos (13UL) /*!< GPIO27_LEVEL_HIGH (Bit 13) */
#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_HIGH_Msk (0x2000UL) /*!< GPIO27_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_LOW_Pos (12UL) /*!< GPIO27_LEVEL_LOW (Bit 12) */
#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_LOW_Msk (0x1000UL) /*!< GPIO27_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_HIGH_Pos (11UL) /*!< GPIO26_EDGE_HIGH (Bit 11) */
#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_HIGH_Msk (0x800UL) /*!< GPIO26_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_LOW_Pos (10UL) /*!< GPIO26_EDGE_LOW (Bit 10) */
#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_LOW_Msk (0x400UL) /*!< GPIO26_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_HIGH_Pos (9UL) /*!< GPIO26_LEVEL_HIGH (Bit 9) */
#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_HIGH_Msk (0x200UL) /*!< GPIO26_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_LOW_Pos (8UL) /*!< GPIO26_LEVEL_LOW (Bit 8) */
#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_LOW_Msk (0x100UL) /*!< GPIO26_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_HIGH_Pos (7UL) /*!< GPIO25_EDGE_HIGH (Bit 7) */
#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_HIGH_Msk (0x80UL) /*!< GPIO25_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_LOW_Pos (6UL) /*!< GPIO25_EDGE_LOW (Bit 6) */
#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_LOW_Msk (0x40UL) /*!< GPIO25_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_HIGH_Pos (5UL) /*!< GPIO25_LEVEL_HIGH (Bit 5) */
#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_HIGH_Msk (0x20UL) /*!< GPIO25_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_LOW_Pos (4UL) /*!< GPIO25_LEVEL_LOW (Bit 4) */
#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_LOW_Msk (0x10UL) /*!< GPIO25_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_HIGH_Pos (3UL) /*!< GPIO24_EDGE_HIGH (Bit 3) */
#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_HIGH_Msk (0x8UL) /*!< GPIO24_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_LOW_Pos (2UL) /*!< GPIO24_EDGE_LOW (Bit 2) */
#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_LOW_Msk (0x4UL) /*!< GPIO24_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_HIGH_Pos (1UL) /*!< GPIO24_LEVEL_HIGH (Bit 1) */
#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_HIGH_Msk (0x2UL) /*!< GPIO24_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_LOW_Pos (0UL) /*!< GPIO24_LEVEL_LOW (Bit 0) */
#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_LOW_Msk (0x1UL) /*!< GPIO24_LEVEL_LOW (Bitfield-Mask: 0x01) */
/* ====================================================== PROC0_INTS0 ====================================================== */
#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_HIGH_Pos (31UL) /*!< GPIO7_EDGE_HIGH (Bit 31) */
#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_HIGH_Msk (0x80000000UL) /*!< GPIO7_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_LOW_Pos (30UL) /*!< GPIO7_EDGE_LOW (Bit 30) */
#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_LOW_Msk (0x40000000UL) /*!< GPIO7_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_HIGH_Pos (29UL) /*!< GPIO7_LEVEL_HIGH (Bit 29) */
#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_HIGH_Msk (0x20000000UL) /*!< GPIO7_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_LOW_Pos (28UL) /*!< GPIO7_LEVEL_LOW (Bit 28) */
#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_LOW_Msk (0x10000000UL) /*!< GPIO7_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_HIGH_Pos (27UL) /*!< GPIO6_EDGE_HIGH (Bit 27) */
#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_HIGH_Msk (0x8000000UL) /*!< GPIO6_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_LOW_Pos (26UL) /*!< GPIO6_EDGE_LOW (Bit 26) */
#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_LOW_Msk (0x4000000UL) /*!< GPIO6_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_HIGH_Pos (25UL) /*!< GPIO6_LEVEL_HIGH (Bit 25) */
#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_HIGH_Msk (0x2000000UL) /*!< GPIO6_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_LOW_Pos (24UL) /*!< GPIO6_LEVEL_LOW (Bit 24) */
#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_LOW_Msk (0x1000000UL) /*!< GPIO6_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_HIGH_Pos (23UL) /*!< GPIO5_EDGE_HIGH (Bit 23) */
#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_HIGH_Msk (0x800000UL) /*!< GPIO5_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_LOW_Pos (22UL) /*!< GPIO5_EDGE_LOW (Bit 22) */
#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_LOW_Msk (0x400000UL) /*!< GPIO5_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_HIGH_Pos (21UL) /*!< GPIO5_LEVEL_HIGH (Bit 21) */
#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_HIGH_Msk (0x200000UL) /*!< GPIO5_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_LOW_Pos (20UL) /*!< GPIO5_LEVEL_LOW (Bit 20) */
#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_LOW_Msk (0x100000UL) /*!< GPIO5_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_HIGH_Pos (19UL) /*!< GPIO4_EDGE_HIGH (Bit 19) */
#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_HIGH_Msk (0x80000UL) /*!< GPIO4_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_LOW_Pos (18UL) /*!< GPIO4_EDGE_LOW (Bit 18) */
#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_LOW_Msk (0x40000UL) /*!< GPIO4_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_HIGH_Pos (17UL) /*!< GPIO4_LEVEL_HIGH (Bit 17) */
#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_HIGH_Msk (0x20000UL) /*!< GPIO4_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_LOW_Pos (16UL) /*!< GPIO4_LEVEL_LOW (Bit 16) */
#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_LOW_Msk (0x10000UL) /*!< GPIO4_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_HIGH_Pos (15UL) /*!< GPIO3_EDGE_HIGH (Bit 15) */
#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_HIGH_Msk (0x8000UL) /*!< GPIO3_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_LOW_Pos (14UL) /*!< GPIO3_EDGE_LOW (Bit 14) */
#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_LOW_Msk (0x4000UL) /*!< GPIO3_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_HIGH_Pos (13UL) /*!< GPIO3_LEVEL_HIGH (Bit 13) */
#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_HIGH_Msk (0x2000UL) /*!< GPIO3_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_LOW_Pos (12UL) /*!< GPIO3_LEVEL_LOW (Bit 12) */
#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_LOW_Msk (0x1000UL) /*!< GPIO3_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_HIGH_Pos (11UL) /*!< GPIO2_EDGE_HIGH (Bit 11) */
#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_HIGH_Msk (0x800UL) /*!< GPIO2_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_LOW_Pos (10UL) /*!< GPIO2_EDGE_LOW (Bit 10) */
#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_LOW_Msk (0x400UL) /*!< GPIO2_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_HIGH_Pos (9UL) /*!< GPIO2_LEVEL_HIGH (Bit 9) */
#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_HIGH_Msk (0x200UL) /*!< GPIO2_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_LOW_Pos (8UL) /*!< GPIO2_LEVEL_LOW (Bit 8) */
#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_LOW_Msk (0x100UL) /*!< GPIO2_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_HIGH_Pos (7UL) /*!< GPIO1_EDGE_HIGH (Bit 7) */
#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_HIGH_Msk (0x80UL) /*!< GPIO1_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_LOW_Pos (6UL) /*!< GPIO1_EDGE_LOW (Bit 6) */
#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_LOW_Msk (0x40UL) /*!< GPIO1_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_HIGH_Pos (5UL) /*!< GPIO1_LEVEL_HIGH (Bit 5) */
#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_HIGH_Msk (0x20UL) /*!< GPIO1_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_LOW_Pos (4UL) /*!< GPIO1_LEVEL_LOW (Bit 4) */
#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_LOW_Msk (0x10UL) /*!< GPIO1_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_HIGH_Pos (3UL) /*!< GPIO0_EDGE_HIGH (Bit 3) */
#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_HIGH_Msk (0x8UL) /*!< GPIO0_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_LOW_Pos (2UL) /*!< GPIO0_EDGE_LOW (Bit 2) */
#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_LOW_Msk (0x4UL) /*!< GPIO0_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_HIGH_Pos (1UL) /*!< GPIO0_LEVEL_HIGH (Bit 1) */
#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_HIGH_Msk (0x2UL) /*!< GPIO0_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_LOW_Pos (0UL) /*!< GPIO0_LEVEL_LOW (Bit 0) */
#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_LOW_Msk (0x1UL) /*!< GPIO0_LEVEL_LOW (Bitfield-Mask: 0x01) */
/* ====================================================== PROC0_INTS1 ====================================================== */
#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_HIGH_Pos (31UL) /*!< GPIO15_EDGE_HIGH (Bit 31) */
#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_HIGH_Msk (0x80000000UL) /*!< GPIO15_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_LOW_Pos (30UL) /*!< GPIO15_EDGE_LOW (Bit 30) */
#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_LOW_Msk (0x40000000UL) /*!< GPIO15_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_HIGH_Pos (29UL) /*!< GPIO15_LEVEL_HIGH (Bit 29) */
#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_HIGH_Msk (0x20000000UL) /*!< GPIO15_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_LOW_Pos (28UL) /*!< GPIO15_LEVEL_LOW (Bit 28) */
#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_LOW_Msk (0x10000000UL) /*!< GPIO15_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_HIGH_Pos (27UL) /*!< GPIO14_EDGE_HIGH (Bit 27) */
#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_HIGH_Msk (0x8000000UL) /*!< GPIO14_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_LOW_Pos (26UL) /*!< GPIO14_EDGE_LOW (Bit 26) */
#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_LOW_Msk (0x4000000UL) /*!< GPIO14_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_HIGH_Pos (25UL) /*!< GPIO14_LEVEL_HIGH (Bit 25) */
#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_HIGH_Msk (0x2000000UL) /*!< GPIO14_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_LOW_Pos (24UL) /*!< GPIO14_LEVEL_LOW (Bit 24) */
#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_LOW_Msk (0x1000000UL) /*!< GPIO14_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_HIGH_Pos (23UL) /*!< GPIO13_EDGE_HIGH (Bit 23) */
#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_HIGH_Msk (0x800000UL) /*!< GPIO13_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_LOW_Pos (22UL) /*!< GPIO13_EDGE_LOW (Bit 22) */
#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_LOW_Msk (0x400000UL) /*!< GPIO13_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_HIGH_Pos (21UL) /*!< GPIO13_LEVEL_HIGH (Bit 21) */
#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_HIGH_Msk (0x200000UL) /*!< GPIO13_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_LOW_Pos (20UL) /*!< GPIO13_LEVEL_LOW (Bit 20) */
#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_LOW_Msk (0x100000UL) /*!< GPIO13_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_HIGH_Pos (19UL) /*!< GPIO12_EDGE_HIGH (Bit 19) */
#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_HIGH_Msk (0x80000UL) /*!< GPIO12_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_LOW_Pos (18UL) /*!< GPIO12_EDGE_LOW (Bit 18) */
#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_LOW_Msk (0x40000UL) /*!< GPIO12_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_HIGH_Pos (17UL) /*!< GPIO12_LEVEL_HIGH (Bit 17) */
#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_HIGH_Msk (0x20000UL) /*!< GPIO12_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_LOW_Pos (16UL) /*!< GPIO12_LEVEL_LOW (Bit 16) */
#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_LOW_Msk (0x10000UL) /*!< GPIO12_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_HIGH_Pos (15UL) /*!< GPIO11_EDGE_HIGH (Bit 15) */
#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_HIGH_Msk (0x8000UL) /*!< GPIO11_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_LOW_Pos (14UL) /*!< GPIO11_EDGE_LOW (Bit 14) */
#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_LOW_Msk (0x4000UL) /*!< GPIO11_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_HIGH_Pos (13UL) /*!< GPIO11_LEVEL_HIGH (Bit 13) */
#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_HIGH_Msk (0x2000UL) /*!< GPIO11_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_LOW_Pos (12UL) /*!< GPIO11_LEVEL_LOW (Bit 12) */
#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_LOW_Msk (0x1000UL) /*!< GPIO11_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_HIGH_Pos (11UL) /*!< GPIO10_EDGE_HIGH (Bit 11) */
#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_HIGH_Msk (0x800UL) /*!< GPIO10_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_LOW_Pos (10UL) /*!< GPIO10_EDGE_LOW (Bit 10) */
#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_LOW_Msk (0x400UL) /*!< GPIO10_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_HIGH_Pos (9UL) /*!< GPIO10_LEVEL_HIGH (Bit 9) */
#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_HIGH_Msk (0x200UL) /*!< GPIO10_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_LOW_Pos (8UL) /*!< GPIO10_LEVEL_LOW (Bit 8) */
#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_LOW_Msk (0x100UL) /*!< GPIO10_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_HIGH_Pos (7UL) /*!< GPIO9_EDGE_HIGH (Bit 7) */
#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_HIGH_Msk (0x80UL) /*!< GPIO9_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_LOW_Pos (6UL) /*!< GPIO9_EDGE_LOW (Bit 6) */
#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_LOW_Msk (0x40UL) /*!< GPIO9_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_HIGH_Pos (5UL) /*!< GPIO9_LEVEL_HIGH (Bit 5) */
#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_HIGH_Msk (0x20UL) /*!< GPIO9_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_LOW_Pos (4UL) /*!< GPIO9_LEVEL_LOW (Bit 4) */
#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_LOW_Msk (0x10UL) /*!< GPIO9_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_HIGH_Pos (3UL) /*!< GPIO8_EDGE_HIGH (Bit 3) */
#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_HIGH_Msk (0x8UL) /*!< GPIO8_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_LOW_Pos (2UL) /*!< GPIO8_EDGE_LOW (Bit 2) */
#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_LOW_Msk (0x4UL) /*!< GPIO8_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_HIGH_Pos (1UL) /*!< GPIO8_LEVEL_HIGH (Bit 1) */
#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_HIGH_Msk (0x2UL) /*!< GPIO8_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_LOW_Pos (0UL) /*!< GPIO8_LEVEL_LOW (Bit 0) */
#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_LOW_Msk (0x1UL) /*!< GPIO8_LEVEL_LOW (Bitfield-Mask: 0x01) */
/* ====================================================== PROC0_INTS2 ====================================================== */
#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_HIGH_Pos (31UL) /*!< GPIO23_EDGE_HIGH (Bit 31) */
#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_HIGH_Msk (0x80000000UL) /*!< GPIO23_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_LOW_Pos (30UL) /*!< GPIO23_EDGE_LOW (Bit 30) */
#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_LOW_Msk (0x40000000UL) /*!< GPIO23_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_HIGH_Pos (29UL) /*!< GPIO23_LEVEL_HIGH (Bit 29) */
#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_HIGH_Msk (0x20000000UL) /*!< GPIO23_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_LOW_Pos (28UL) /*!< GPIO23_LEVEL_LOW (Bit 28) */
#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_LOW_Msk (0x10000000UL) /*!< GPIO23_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_HIGH_Pos (27UL) /*!< GPIO22_EDGE_HIGH (Bit 27) */
#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_HIGH_Msk (0x8000000UL) /*!< GPIO22_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_LOW_Pos (26UL) /*!< GPIO22_EDGE_LOW (Bit 26) */
#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_LOW_Msk (0x4000000UL) /*!< GPIO22_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_HIGH_Pos (25UL) /*!< GPIO22_LEVEL_HIGH (Bit 25) */
#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_HIGH_Msk (0x2000000UL) /*!< GPIO22_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_LOW_Pos (24UL) /*!< GPIO22_LEVEL_LOW (Bit 24) */
#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_LOW_Msk (0x1000000UL) /*!< GPIO22_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_HIGH_Pos (23UL) /*!< GPIO21_EDGE_HIGH (Bit 23) */
#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_HIGH_Msk (0x800000UL) /*!< GPIO21_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_LOW_Pos (22UL) /*!< GPIO21_EDGE_LOW (Bit 22) */
#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_LOW_Msk (0x400000UL) /*!< GPIO21_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_HIGH_Pos (21UL) /*!< GPIO21_LEVEL_HIGH (Bit 21) */
#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_HIGH_Msk (0x200000UL) /*!< GPIO21_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_LOW_Pos (20UL) /*!< GPIO21_LEVEL_LOW (Bit 20) */
#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_LOW_Msk (0x100000UL) /*!< GPIO21_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_HIGH_Pos (19UL) /*!< GPIO20_EDGE_HIGH (Bit 19) */
#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_HIGH_Msk (0x80000UL) /*!< GPIO20_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_LOW_Pos (18UL) /*!< GPIO20_EDGE_LOW (Bit 18) */
#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_LOW_Msk (0x40000UL) /*!< GPIO20_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_HIGH_Pos (17UL) /*!< GPIO20_LEVEL_HIGH (Bit 17) */
#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_HIGH_Msk (0x20000UL) /*!< GPIO20_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_LOW_Pos (16UL) /*!< GPIO20_LEVEL_LOW (Bit 16) */
#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_LOW_Msk (0x10000UL) /*!< GPIO20_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_HIGH_Pos (15UL) /*!< GPIO19_EDGE_HIGH (Bit 15) */
#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_HIGH_Msk (0x8000UL) /*!< GPIO19_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_LOW_Pos (14UL) /*!< GPIO19_EDGE_LOW (Bit 14) */
#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_LOW_Msk (0x4000UL) /*!< GPIO19_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_HIGH_Pos (13UL) /*!< GPIO19_LEVEL_HIGH (Bit 13) */
#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_HIGH_Msk (0x2000UL) /*!< GPIO19_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_LOW_Pos (12UL) /*!< GPIO19_LEVEL_LOW (Bit 12) */
#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_LOW_Msk (0x1000UL) /*!< GPIO19_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_HIGH_Pos (11UL) /*!< GPIO18_EDGE_HIGH (Bit 11) */
#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_HIGH_Msk (0x800UL) /*!< GPIO18_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_LOW_Pos (10UL) /*!< GPIO18_EDGE_LOW (Bit 10) */
#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_LOW_Msk (0x400UL) /*!< GPIO18_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_HIGH_Pos (9UL) /*!< GPIO18_LEVEL_HIGH (Bit 9) */
#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_HIGH_Msk (0x200UL) /*!< GPIO18_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_LOW_Pos (8UL) /*!< GPIO18_LEVEL_LOW (Bit 8) */
#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_LOW_Msk (0x100UL) /*!< GPIO18_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_HIGH_Pos (7UL) /*!< GPIO17_EDGE_HIGH (Bit 7) */
#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_HIGH_Msk (0x80UL) /*!< GPIO17_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_LOW_Pos (6UL) /*!< GPIO17_EDGE_LOW (Bit 6) */
#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_LOW_Msk (0x40UL) /*!< GPIO17_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_HIGH_Pos (5UL) /*!< GPIO17_LEVEL_HIGH (Bit 5) */
#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_HIGH_Msk (0x20UL) /*!< GPIO17_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_LOW_Pos (4UL) /*!< GPIO17_LEVEL_LOW (Bit 4) */
#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_LOW_Msk (0x10UL) /*!< GPIO17_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_HIGH_Pos (3UL) /*!< GPIO16_EDGE_HIGH (Bit 3) */
#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_HIGH_Msk (0x8UL) /*!< GPIO16_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_LOW_Pos (2UL) /*!< GPIO16_EDGE_LOW (Bit 2) */
#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_LOW_Msk (0x4UL) /*!< GPIO16_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_HIGH_Pos (1UL) /*!< GPIO16_LEVEL_HIGH (Bit 1) */
#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_HIGH_Msk (0x2UL) /*!< GPIO16_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_LOW_Pos (0UL) /*!< GPIO16_LEVEL_LOW (Bit 0) */
#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_LOW_Msk (0x1UL) /*!< GPIO16_LEVEL_LOW (Bitfield-Mask: 0x01) */
/* ====================================================== PROC0_INTS3 ====================================================== */
#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_HIGH_Pos (23UL) /*!< GPIO29_EDGE_HIGH (Bit 23) */
#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_HIGH_Msk (0x800000UL) /*!< GPIO29_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_LOW_Pos (22UL) /*!< GPIO29_EDGE_LOW (Bit 22) */
#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_LOW_Msk (0x400000UL) /*!< GPIO29_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_HIGH_Pos (21UL) /*!< GPIO29_LEVEL_HIGH (Bit 21) */
#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_HIGH_Msk (0x200000UL) /*!< GPIO29_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_LOW_Pos (20UL) /*!< GPIO29_LEVEL_LOW (Bit 20) */
#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_LOW_Msk (0x100000UL) /*!< GPIO29_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_HIGH_Pos (19UL) /*!< GPIO28_EDGE_HIGH (Bit 19) */
#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_HIGH_Msk (0x80000UL) /*!< GPIO28_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_LOW_Pos (18UL) /*!< GPIO28_EDGE_LOW (Bit 18) */
#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_LOW_Msk (0x40000UL) /*!< GPIO28_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_HIGH_Pos (17UL) /*!< GPIO28_LEVEL_HIGH (Bit 17) */
#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_HIGH_Msk (0x20000UL) /*!< GPIO28_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_LOW_Pos (16UL) /*!< GPIO28_LEVEL_LOW (Bit 16) */
#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_LOW_Msk (0x10000UL) /*!< GPIO28_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_HIGH_Pos (15UL) /*!< GPIO27_EDGE_HIGH (Bit 15) */
#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_HIGH_Msk (0x8000UL) /*!< GPIO27_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_LOW_Pos (14UL) /*!< GPIO27_EDGE_LOW (Bit 14) */
#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_LOW_Msk (0x4000UL) /*!< GPIO27_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_HIGH_Pos (13UL) /*!< GPIO27_LEVEL_HIGH (Bit 13) */
#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_HIGH_Msk (0x2000UL) /*!< GPIO27_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_LOW_Pos (12UL) /*!< GPIO27_LEVEL_LOW (Bit 12) */
#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_LOW_Msk (0x1000UL) /*!< GPIO27_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_HIGH_Pos (11UL) /*!< GPIO26_EDGE_HIGH (Bit 11) */
#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_HIGH_Msk (0x800UL) /*!< GPIO26_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_LOW_Pos (10UL) /*!< GPIO26_EDGE_LOW (Bit 10) */
#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_LOW_Msk (0x400UL) /*!< GPIO26_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_HIGH_Pos (9UL) /*!< GPIO26_LEVEL_HIGH (Bit 9) */
#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_HIGH_Msk (0x200UL) /*!< GPIO26_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_LOW_Pos (8UL) /*!< GPIO26_LEVEL_LOW (Bit 8) */
#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_LOW_Msk (0x100UL) /*!< GPIO26_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_HIGH_Pos (7UL) /*!< GPIO25_EDGE_HIGH (Bit 7) */
#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_HIGH_Msk (0x80UL) /*!< GPIO25_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_LOW_Pos (6UL) /*!< GPIO25_EDGE_LOW (Bit 6) */
#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_LOW_Msk (0x40UL) /*!< GPIO25_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_HIGH_Pos (5UL) /*!< GPIO25_LEVEL_HIGH (Bit 5) */
#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_HIGH_Msk (0x20UL) /*!< GPIO25_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_LOW_Pos (4UL) /*!< GPIO25_LEVEL_LOW (Bit 4) */
#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_LOW_Msk (0x10UL) /*!< GPIO25_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_HIGH_Pos (3UL) /*!< GPIO24_EDGE_HIGH (Bit 3) */
#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_HIGH_Msk (0x8UL) /*!< GPIO24_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_LOW_Pos (2UL) /*!< GPIO24_EDGE_LOW (Bit 2) */
#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_LOW_Msk (0x4UL) /*!< GPIO24_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_HIGH_Pos (1UL) /*!< GPIO24_LEVEL_HIGH (Bit 1) */
#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_HIGH_Msk (0x2UL) /*!< GPIO24_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_LOW_Pos (0UL) /*!< GPIO24_LEVEL_LOW (Bit 0) */
#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_LOW_Msk (0x1UL) /*!< GPIO24_LEVEL_LOW (Bitfield-Mask: 0x01) */
/* ====================================================== PROC1_INTE0 ====================================================== */
#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_HIGH_Pos (31UL) /*!< GPIO7_EDGE_HIGH (Bit 31) */
#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_HIGH_Msk (0x80000000UL) /*!< GPIO7_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_LOW_Pos (30UL) /*!< GPIO7_EDGE_LOW (Bit 30) */
#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_LOW_Msk (0x40000000UL) /*!< GPIO7_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_HIGH_Pos (29UL) /*!< GPIO7_LEVEL_HIGH (Bit 29) */
#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_HIGH_Msk (0x20000000UL) /*!< GPIO7_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_LOW_Pos (28UL) /*!< GPIO7_LEVEL_LOW (Bit 28) */
#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_LOW_Msk (0x10000000UL) /*!< GPIO7_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_HIGH_Pos (27UL) /*!< GPIO6_EDGE_HIGH (Bit 27) */
#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_HIGH_Msk (0x8000000UL) /*!< GPIO6_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_LOW_Pos (26UL) /*!< GPIO6_EDGE_LOW (Bit 26) */
#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_LOW_Msk (0x4000000UL) /*!< GPIO6_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_HIGH_Pos (25UL) /*!< GPIO6_LEVEL_HIGH (Bit 25) */
#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_HIGH_Msk (0x2000000UL) /*!< GPIO6_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_LOW_Pos (24UL) /*!< GPIO6_LEVEL_LOW (Bit 24) */
#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_LOW_Msk (0x1000000UL) /*!< GPIO6_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_HIGH_Pos (23UL) /*!< GPIO5_EDGE_HIGH (Bit 23) */
#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_HIGH_Msk (0x800000UL) /*!< GPIO5_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_LOW_Pos (22UL) /*!< GPIO5_EDGE_LOW (Bit 22) */
#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_LOW_Msk (0x400000UL) /*!< GPIO5_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_HIGH_Pos (21UL) /*!< GPIO5_LEVEL_HIGH (Bit 21) */
#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_HIGH_Msk (0x200000UL) /*!< GPIO5_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_LOW_Pos (20UL) /*!< GPIO5_LEVEL_LOW (Bit 20) */
#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_LOW_Msk (0x100000UL) /*!< GPIO5_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_HIGH_Pos (19UL) /*!< GPIO4_EDGE_HIGH (Bit 19) */
#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_HIGH_Msk (0x80000UL) /*!< GPIO4_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_LOW_Pos (18UL) /*!< GPIO4_EDGE_LOW (Bit 18) */
#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_LOW_Msk (0x40000UL) /*!< GPIO4_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_HIGH_Pos (17UL) /*!< GPIO4_LEVEL_HIGH (Bit 17) */
#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_HIGH_Msk (0x20000UL) /*!< GPIO4_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_LOW_Pos (16UL) /*!< GPIO4_LEVEL_LOW (Bit 16) */
#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_LOW_Msk (0x10000UL) /*!< GPIO4_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_HIGH_Pos (15UL) /*!< GPIO3_EDGE_HIGH (Bit 15) */
#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_HIGH_Msk (0x8000UL) /*!< GPIO3_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_LOW_Pos (14UL) /*!< GPIO3_EDGE_LOW (Bit 14) */
#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_LOW_Msk (0x4000UL) /*!< GPIO3_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_HIGH_Pos (13UL) /*!< GPIO3_LEVEL_HIGH (Bit 13) */
#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_HIGH_Msk (0x2000UL) /*!< GPIO3_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_LOW_Pos (12UL) /*!< GPIO3_LEVEL_LOW (Bit 12) */
#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_LOW_Msk (0x1000UL) /*!< GPIO3_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_HIGH_Pos (11UL) /*!< GPIO2_EDGE_HIGH (Bit 11) */
#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_HIGH_Msk (0x800UL) /*!< GPIO2_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_LOW_Pos (10UL) /*!< GPIO2_EDGE_LOW (Bit 10) */
#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_LOW_Msk (0x400UL) /*!< GPIO2_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_HIGH_Pos (9UL) /*!< GPIO2_LEVEL_HIGH (Bit 9) */
#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_HIGH_Msk (0x200UL) /*!< GPIO2_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_LOW_Pos (8UL) /*!< GPIO2_LEVEL_LOW (Bit 8) */
#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_LOW_Msk (0x100UL) /*!< GPIO2_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_HIGH_Pos (7UL) /*!< GPIO1_EDGE_HIGH (Bit 7) */
#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_HIGH_Msk (0x80UL) /*!< GPIO1_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_LOW_Pos (6UL) /*!< GPIO1_EDGE_LOW (Bit 6) */
#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_LOW_Msk (0x40UL) /*!< GPIO1_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_HIGH_Pos (5UL) /*!< GPIO1_LEVEL_HIGH (Bit 5) */
#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_HIGH_Msk (0x20UL) /*!< GPIO1_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_LOW_Pos (4UL) /*!< GPIO1_LEVEL_LOW (Bit 4) */
#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_LOW_Msk (0x10UL) /*!< GPIO1_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_HIGH_Pos (3UL) /*!< GPIO0_EDGE_HIGH (Bit 3) */
#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_HIGH_Msk (0x8UL) /*!< GPIO0_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_LOW_Pos (2UL) /*!< GPIO0_EDGE_LOW (Bit 2) */
#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_LOW_Msk (0x4UL) /*!< GPIO0_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_HIGH_Pos (1UL) /*!< GPIO0_LEVEL_HIGH (Bit 1) */
#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_HIGH_Msk (0x2UL) /*!< GPIO0_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_LOW_Pos (0UL) /*!< GPIO0_LEVEL_LOW (Bit 0) */
#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_LOW_Msk (0x1UL) /*!< GPIO0_LEVEL_LOW (Bitfield-Mask: 0x01) */
/* ====================================================== PROC1_INTE1 ====================================================== */
#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_HIGH_Pos (31UL) /*!< GPIO15_EDGE_HIGH (Bit 31) */
#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_HIGH_Msk (0x80000000UL) /*!< GPIO15_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_LOW_Pos (30UL) /*!< GPIO15_EDGE_LOW (Bit 30) */
#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_LOW_Msk (0x40000000UL) /*!< GPIO15_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_HIGH_Pos (29UL) /*!< GPIO15_LEVEL_HIGH (Bit 29) */
#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_HIGH_Msk (0x20000000UL) /*!< GPIO15_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_LOW_Pos (28UL) /*!< GPIO15_LEVEL_LOW (Bit 28) */
#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_LOW_Msk (0x10000000UL) /*!< GPIO15_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_HIGH_Pos (27UL) /*!< GPIO14_EDGE_HIGH (Bit 27) */
#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_HIGH_Msk (0x8000000UL) /*!< GPIO14_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_LOW_Pos (26UL) /*!< GPIO14_EDGE_LOW (Bit 26) */
#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_LOW_Msk (0x4000000UL) /*!< GPIO14_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_HIGH_Pos (25UL) /*!< GPIO14_LEVEL_HIGH (Bit 25) */
#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_HIGH_Msk (0x2000000UL) /*!< GPIO14_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_LOW_Pos (24UL) /*!< GPIO14_LEVEL_LOW (Bit 24) */
#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_LOW_Msk (0x1000000UL) /*!< GPIO14_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_HIGH_Pos (23UL) /*!< GPIO13_EDGE_HIGH (Bit 23) */
#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_HIGH_Msk (0x800000UL) /*!< GPIO13_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_LOW_Pos (22UL) /*!< GPIO13_EDGE_LOW (Bit 22) */
#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_LOW_Msk (0x400000UL) /*!< GPIO13_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_HIGH_Pos (21UL) /*!< GPIO13_LEVEL_HIGH (Bit 21) */
#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_HIGH_Msk (0x200000UL) /*!< GPIO13_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_LOW_Pos (20UL) /*!< GPIO13_LEVEL_LOW (Bit 20) */
#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_LOW_Msk (0x100000UL) /*!< GPIO13_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_HIGH_Pos (19UL) /*!< GPIO12_EDGE_HIGH (Bit 19) */
#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_HIGH_Msk (0x80000UL) /*!< GPIO12_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_LOW_Pos (18UL) /*!< GPIO12_EDGE_LOW (Bit 18) */
#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_LOW_Msk (0x40000UL) /*!< GPIO12_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_HIGH_Pos (17UL) /*!< GPIO12_LEVEL_HIGH (Bit 17) */
#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_HIGH_Msk (0x20000UL) /*!< GPIO12_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_LOW_Pos (16UL) /*!< GPIO12_LEVEL_LOW (Bit 16) */
#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_LOW_Msk (0x10000UL) /*!< GPIO12_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_HIGH_Pos (15UL) /*!< GPIO11_EDGE_HIGH (Bit 15) */
#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_HIGH_Msk (0x8000UL) /*!< GPIO11_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_LOW_Pos (14UL) /*!< GPIO11_EDGE_LOW (Bit 14) */
#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_LOW_Msk (0x4000UL) /*!< GPIO11_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_HIGH_Pos (13UL) /*!< GPIO11_LEVEL_HIGH (Bit 13) */
#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_HIGH_Msk (0x2000UL) /*!< GPIO11_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_LOW_Pos (12UL) /*!< GPIO11_LEVEL_LOW (Bit 12) */
#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_LOW_Msk (0x1000UL) /*!< GPIO11_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_HIGH_Pos (11UL) /*!< GPIO10_EDGE_HIGH (Bit 11) */
#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_HIGH_Msk (0x800UL) /*!< GPIO10_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_LOW_Pos (10UL) /*!< GPIO10_EDGE_LOW (Bit 10) */
#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_LOW_Msk (0x400UL) /*!< GPIO10_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_HIGH_Pos (9UL) /*!< GPIO10_LEVEL_HIGH (Bit 9) */
#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_HIGH_Msk (0x200UL) /*!< GPIO10_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_LOW_Pos (8UL) /*!< GPIO10_LEVEL_LOW (Bit 8) */
#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_LOW_Msk (0x100UL) /*!< GPIO10_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_HIGH_Pos (7UL) /*!< GPIO9_EDGE_HIGH (Bit 7) */
#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_HIGH_Msk (0x80UL) /*!< GPIO9_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_LOW_Pos (6UL) /*!< GPIO9_EDGE_LOW (Bit 6) */
#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_LOW_Msk (0x40UL) /*!< GPIO9_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_HIGH_Pos (5UL) /*!< GPIO9_LEVEL_HIGH (Bit 5) */
#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_HIGH_Msk (0x20UL) /*!< GPIO9_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_LOW_Pos (4UL) /*!< GPIO9_LEVEL_LOW (Bit 4) */
#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_LOW_Msk (0x10UL) /*!< GPIO9_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_HIGH_Pos (3UL) /*!< GPIO8_EDGE_HIGH (Bit 3) */
#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_HIGH_Msk (0x8UL) /*!< GPIO8_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_LOW_Pos (2UL) /*!< GPIO8_EDGE_LOW (Bit 2) */
#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_LOW_Msk (0x4UL) /*!< GPIO8_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_HIGH_Pos (1UL) /*!< GPIO8_LEVEL_HIGH (Bit 1) */
#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_HIGH_Msk (0x2UL) /*!< GPIO8_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_LOW_Pos (0UL) /*!< GPIO8_LEVEL_LOW (Bit 0) */
#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_LOW_Msk (0x1UL) /*!< GPIO8_LEVEL_LOW (Bitfield-Mask: 0x01) */
/* ====================================================== PROC1_INTE2 ====================================================== */
#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_HIGH_Pos (31UL) /*!< GPIO23_EDGE_HIGH (Bit 31) */
#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_HIGH_Msk (0x80000000UL) /*!< GPIO23_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_LOW_Pos (30UL) /*!< GPIO23_EDGE_LOW (Bit 30) */
#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_LOW_Msk (0x40000000UL) /*!< GPIO23_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_HIGH_Pos (29UL) /*!< GPIO23_LEVEL_HIGH (Bit 29) */
#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_HIGH_Msk (0x20000000UL) /*!< GPIO23_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_LOW_Pos (28UL) /*!< GPIO23_LEVEL_LOW (Bit 28) */
#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_LOW_Msk (0x10000000UL) /*!< GPIO23_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_HIGH_Pos (27UL) /*!< GPIO22_EDGE_HIGH (Bit 27) */
#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_HIGH_Msk (0x8000000UL) /*!< GPIO22_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_LOW_Pos (26UL) /*!< GPIO22_EDGE_LOW (Bit 26) */
#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_LOW_Msk (0x4000000UL) /*!< GPIO22_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_HIGH_Pos (25UL) /*!< GPIO22_LEVEL_HIGH (Bit 25) */
#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_HIGH_Msk (0x2000000UL) /*!< GPIO22_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_LOW_Pos (24UL) /*!< GPIO22_LEVEL_LOW (Bit 24) */
#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_LOW_Msk (0x1000000UL) /*!< GPIO22_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_HIGH_Pos (23UL) /*!< GPIO21_EDGE_HIGH (Bit 23) */
#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_HIGH_Msk (0x800000UL) /*!< GPIO21_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_LOW_Pos (22UL) /*!< GPIO21_EDGE_LOW (Bit 22) */
#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_LOW_Msk (0x400000UL) /*!< GPIO21_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_HIGH_Pos (21UL) /*!< GPIO21_LEVEL_HIGH (Bit 21) */
#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_HIGH_Msk (0x200000UL) /*!< GPIO21_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_LOW_Pos (20UL) /*!< GPIO21_LEVEL_LOW (Bit 20) */
#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_LOW_Msk (0x100000UL) /*!< GPIO21_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_HIGH_Pos (19UL) /*!< GPIO20_EDGE_HIGH (Bit 19) */
#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_HIGH_Msk (0x80000UL) /*!< GPIO20_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_LOW_Pos (18UL) /*!< GPIO20_EDGE_LOW (Bit 18) */
#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_LOW_Msk (0x40000UL) /*!< GPIO20_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_HIGH_Pos (17UL) /*!< GPIO20_LEVEL_HIGH (Bit 17) */
#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_HIGH_Msk (0x20000UL) /*!< GPIO20_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_LOW_Pos (16UL) /*!< GPIO20_LEVEL_LOW (Bit 16) */
#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_LOW_Msk (0x10000UL) /*!< GPIO20_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_HIGH_Pos (15UL) /*!< GPIO19_EDGE_HIGH (Bit 15) */
#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_HIGH_Msk (0x8000UL) /*!< GPIO19_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_LOW_Pos (14UL) /*!< GPIO19_EDGE_LOW (Bit 14) */
#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_LOW_Msk (0x4000UL) /*!< GPIO19_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_HIGH_Pos (13UL) /*!< GPIO19_LEVEL_HIGH (Bit 13) */
#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_HIGH_Msk (0x2000UL) /*!< GPIO19_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_LOW_Pos (12UL) /*!< GPIO19_LEVEL_LOW (Bit 12) */
#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_LOW_Msk (0x1000UL) /*!< GPIO19_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_HIGH_Pos (11UL) /*!< GPIO18_EDGE_HIGH (Bit 11) */
#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_HIGH_Msk (0x800UL) /*!< GPIO18_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_LOW_Pos (10UL) /*!< GPIO18_EDGE_LOW (Bit 10) */
#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_LOW_Msk (0x400UL) /*!< GPIO18_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_HIGH_Pos (9UL) /*!< GPIO18_LEVEL_HIGH (Bit 9) */
#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_HIGH_Msk (0x200UL) /*!< GPIO18_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_LOW_Pos (8UL) /*!< GPIO18_LEVEL_LOW (Bit 8) */
#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_LOW_Msk (0x100UL) /*!< GPIO18_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_HIGH_Pos (7UL) /*!< GPIO17_EDGE_HIGH (Bit 7) */
#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_HIGH_Msk (0x80UL) /*!< GPIO17_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_LOW_Pos (6UL) /*!< GPIO17_EDGE_LOW (Bit 6) */
#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_LOW_Msk (0x40UL) /*!< GPIO17_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_HIGH_Pos (5UL) /*!< GPIO17_LEVEL_HIGH (Bit 5) */
#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_HIGH_Msk (0x20UL) /*!< GPIO17_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_LOW_Pos (4UL) /*!< GPIO17_LEVEL_LOW (Bit 4) */
#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_LOW_Msk (0x10UL) /*!< GPIO17_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_HIGH_Pos (3UL) /*!< GPIO16_EDGE_HIGH (Bit 3) */
#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_HIGH_Msk (0x8UL) /*!< GPIO16_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_LOW_Pos (2UL) /*!< GPIO16_EDGE_LOW (Bit 2) */
#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_LOW_Msk (0x4UL) /*!< GPIO16_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_HIGH_Pos (1UL) /*!< GPIO16_LEVEL_HIGH (Bit 1) */
#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_HIGH_Msk (0x2UL) /*!< GPIO16_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_LOW_Pos (0UL) /*!< GPIO16_LEVEL_LOW (Bit 0) */
#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_LOW_Msk (0x1UL) /*!< GPIO16_LEVEL_LOW (Bitfield-Mask: 0x01) */
/* ====================================================== PROC1_INTE3 ====================================================== */
#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_HIGH_Pos (23UL) /*!< GPIO29_EDGE_HIGH (Bit 23) */
#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_HIGH_Msk (0x800000UL) /*!< GPIO29_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_LOW_Pos (22UL) /*!< GPIO29_EDGE_LOW (Bit 22) */
#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_LOW_Msk (0x400000UL) /*!< GPIO29_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_HIGH_Pos (21UL) /*!< GPIO29_LEVEL_HIGH (Bit 21) */
#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_HIGH_Msk (0x200000UL) /*!< GPIO29_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_LOW_Pos (20UL) /*!< GPIO29_LEVEL_LOW (Bit 20) */
#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_LOW_Msk (0x100000UL) /*!< GPIO29_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_HIGH_Pos (19UL) /*!< GPIO28_EDGE_HIGH (Bit 19) */
#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_HIGH_Msk (0x80000UL) /*!< GPIO28_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_LOW_Pos (18UL) /*!< GPIO28_EDGE_LOW (Bit 18) */
#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_LOW_Msk (0x40000UL) /*!< GPIO28_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_HIGH_Pos (17UL) /*!< GPIO28_LEVEL_HIGH (Bit 17) */
#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_HIGH_Msk (0x20000UL) /*!< GPIO28_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_LOW_Pos (16UL) /*!< GPIO28_LEVEL_LOW (Bit 16) */
#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_LOW_Msk (0x10000UL) /*!< GPIO28_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_HIGH_Pos (15UL) /*!< GPIO27_EDGE_HIGH (Bit 15) */
#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_HIGH_Msk (0x8000UL) /*!< GPIO27_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_LOW_Pos (14UL) /*!< GPIO27_EDGE_LOW (Bit 14) */
#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_LOW_Msk (0x4000UL) /*!< GPIO27_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_HIGH_Pos (13UL) /*!< GPIO27_LEVEL_HIGH (Bit 13) */
#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_HIGH_Msk (0x2000UL) /*!< GPIO27_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_LOW_Pos (12UL) /*!< GPIO27_LEVEL_LOW (Bit 12) */
#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_LOW_Msk (0x1000UL) /*!< GPIO27_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_HIGH_Pos (11UL) /*!< GPIO26_EDGE_HIGH (Bit 11) */
#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_HIGH_Msk (0x800UL) /*!< GPIO26_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_LOW_Pos (10UL) /*!< GPIO26_EDGE_LOW (Bit 10) */
#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_LOW_Msk (0x400UL) /*!< GPIO26_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_HIGH_Pos (9UL) /*!< GPIO26_LEVEL_HIGH (Bit 9) */
#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_HIGH_Msk (0x200UL) /*!< GPIO26_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_LOW_Pos (8UL) /*!< GPIO26_LEVEL_LOW (Bit 8) */
#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_LOW_Msk (0x100UL) /*!< GPIO26_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_HIGH_Pos (7UL) /*!< GPIO25_EDGE_HIGH (Bit 7) */
#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_HIGH_Msk (0x80UL) /*!< GPIO25_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_LOW_Pos (6UL) /*!< GPIO25_EDGE_LOW (Bit 6) */
#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_LOW_Msk (0x40UL) /*!< GPIO25_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_HIGH_Pos (5UL) /*!< GPIO25_LEVEL_HIGH (Bit 5) */
#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_HIGH_Msk (0x20UL) /*!< GPIO25_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_LOW_Pos (4UL) /*!< GPIO25_LEVEL_LOW (Bit 4) */
#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_LOW_Msk (0x10UL) /*!< GPIO25_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_HIGH_Pos (3UL) /*!< GPIO24_EDGE_HIGH (Bit 3) */
#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_HIGH_Msk (0x8UL) /*!< GPIO24_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_LOW_Pos (2UL) /*!< GPIO24_EDGE_LOW (Bit 2) */
#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_LOW_Msk (0x4UL) /*!< GPIO24_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_HIGH_Pos (1UL) /*!< GPIO24_LEVEL_HIGH (Bit 1) */
#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_HIGH_Msk (0x2UL) /*!< GPIO24_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_LOW_Pos (0UL) /*!< GPIO24_LEVEL_LOW (Bit 0) */
#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_LOW_Msk (0x1UL) /*!< GPIO24_LEVEL_LOW (Bitfield-Mask: 0x01) */
/* ====================================================== PROC1_INTF0 ====================================================== */
#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_HIGH_Pos (31UL) /*!< GPIO7_EDGE_HIGH (Bit 31) */
#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_HIGH_Msk (0x80000000UL) /*!< GPIO7_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_LOW_Pos (30UL) /*!< GPIO7_EDGE_LOW (Bit 30) */
#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_LOW_Msk (0x40000000UL) /*!< GPIO7_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_HIGH_Pos (29UL) /*!< GPIO7_LEVEL_HIGH (Bit 29) */
#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_HIGH_Msk (0x20000000UL) /*!< GPIO7_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_LOW_Pos (28UL) /*!< GPIO7_LEVEL_LOW (Bit 28) */
#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_LOW_Msk (0x10000000UL) /*!< GPIO7_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_HIGH_Pos (27UL) /*!< GPIO6_EDGE_HIGH (Bit 27) */
#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_HIGH_Msk (0x8000000UL) /*!< GPIO6_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_LOW_Pos (26UL) /*!< GPIO6_EDGE_LOW (Bit 26) */
#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_LOW_Msk (0x4000000UL) /*!< GPIO6_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_HIGH_Pos (25UL) /*!< GPIO6_LEVEL_HIGH (Bit 25) */
#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_HIGH_Msk (0x2000000UL) /*!< GPIO6_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_LOW_Pos (24UL) /*!< GPIO6_LEVEL_LOW (Bit 24) */
#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_LOW_Msk (0x1000000UL) /*!< GPIO6_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_HIGH_Pos (23UL) /*!< GPIO5_EDGE_HIGH (Bit 23) */
#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_HIGH_Msk (0x800000UL) /*!< GPIO5_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_LOW_Pos (22UL) /*!< GPIO5_EDGE_LOW (Bit 22) */
#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_LOW_Msk (0x400000UL) /*!< GPIO5_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_HIGH_Pos (21UL) /*!< GPIO5_LEVEL_HIGH (Bit 21) */
#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_HIGH_Msk (0x200000UL) /*!< GPIO5_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_LOW_Pos (20UL) /*!< GPIO5_LEVEL_LOW (Bit 20) */
#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_LOW_Msk (0x100000UL) /*!< GPIO5_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_HIGH_Pos (19UL) /*!< GPIO4_EDGE_HIGH (Bit 19) */
#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_HIGH_Msk (0x80000UL) /*!< GPIO4_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_LOW_Pos (18UL) /*!< GPIO4_EDGE_LOW (Bit 18) */
#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_LOW_Msk (0x40000UL) /*!< GPIO4_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_HIGH_Pos (17UL) /*!< GPIO4_LEVEL_HIGH (Bit 17) */
#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_HIGH_Msk (0x20000UL) /*!< GPIO4_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_LOW_Pos (16UL) /*!< GPIO4_LEVEL_LOW (Bit 16) */
#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_LOW_Msk (0x10000UL) /*!< GPIO4_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_HIGH_Pos (15UL) /*!< GPIO3_EDGE_HIGH (Bit 15) */
#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_HIGH_Msk (0x8000UL) /*!< GPIO3_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_LOW_Pos (14UL) /*!< GPIO3_EDGE_LOW (Bit 14) */
#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_LOW_Msk (0x4000UL) /*!< GPIO3_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_HIGH_Pos (13UL) /*!< GPIO3_LEVEL_HIGH (Bit 13) */
#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_HIGH_Msk (0x2000UL) /*!< GPIO3_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_LOW_Pos (12UL) /*!< GPIO3_LEVEL_LOW (Bit 12) */
#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_LOW_Msk (0x1000UL) /*!< GPIO3_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_HIGH_Pos (11UL) /*!< GPIO2_EDGE_HIGH (Bit 11) */
#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_HIGH_Msk (0x800UL) /*!< GPIO2_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_LOW_Pos (10UL) /*!< GPIO2_EDGE_LOW (Bit 10) */
#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_LOW_Msk (0x400UL) /*!< GPIO2_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_HIGH_Pos (9UL) /*!< GPIO2_LEVEL_HIGH (Bit 9) */
#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_HIGH_Msk (0x200UL) /*!< GPIO2_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_LOW_Pos (8UL) /*!< GPIO2_LEVEL_LOW (Bit 8) */
#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_LOW_Msk (0x100UL) /*!< GPIO2_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_HIGH_Pos (7UL) /*!< GPIO1_EDGE_HIGH (Bit 7) */
#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_HIGH_Msk (0x80UL) /*!< GPIO1_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_LOW_Pos (6UL) /*!< GPIO1_EDGE_LOW (Bit 6) */
#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_LOW_Msk (0x40UL) /*!< GPIO1_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_HIGH_Pos (5UL) /*!< GPIO1_LEVEL_HIGH (Bit 5) */
#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_HIGH_Msk (0x20UL) /*!< GPIO1_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_LOW_Pos (4UL) /*!< GPIO1_LEVEL_LOW (Bit 4) */
#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_LOW_Msk (0x10UL) /*!< GPIO1_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_HIGH_Pos (3UL) /*!< GPIO0_EDGE_HIGH (Bit 3) */
#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_HIGH_Msk (0x8UL) /*!< GPIO0_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_LOW_Pos (2UL) /*!< GPIO0_EDGE_LOW (Bit 2) */
#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_LOW_Msk (0x4UL) /*!< GPIO0_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_HIGH_Pos (1UL) /*!< GPIO0_LEVEL_HIGH (Bit 1) */
#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_HIGH_Msk (0x2UL) /*!< GPIO0_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_LOW_Pos (0UL) /*!< GPIO0_LEVEL_LOW (Bit 0) */
#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_LOW_Msk (0x1UL) /*!< GPIO0_LEVEL_LOW (Bitfield-Mask: 0x01) */
/* ====================================================== PROC1_INTF1 ====================================================== */
#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_HIGH_Pos (31UL) /*!< GPIO15_EDGE_HIGH (Bit 31) */
#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_HIGH_Msk (0x80000000UL) /*!< GPIO15_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_LOW_Pos (30UL) /*!< GPIO15_EDGE_LOW (Bit 30) */
#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_LOW_Msk (0x40000000UL) /*!< GPIO15_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_HIGH_Pos (29UL) /*!< GPIO15_LEVEL_HIGH (Bit 29) */
#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_HIGH_Msk (0x20000000UL) /*!< GPIO15_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_LOW_Pos (28UL) /*!< GPIO15_LEVEL_LOW (Bit 28) */
#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_LOW_Msk (0x10000000UL) /*!< GPIO15_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_HIGH_Pos (27UL) /*!< GPIO14_EDGE_HIGH (Bit 27) */
#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_HIGH_Msk (0x8000000UL) /*!< GPIO14_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_LOW_Pos (26UL) /*!< GPIO14_EDGE_LOW (Bit 26) */
#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_LOW_Msk (0x4000000UL) /*!< GPIO14_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_HIGH_Pos (25UL) /*!< GPIO14_LEVEL_HIGH (Bit 25) */
#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_HIGH_Msk (0x2000000UL) /*!< GPIO14_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_LOW_Pos (24UL) /*!< GPIO14_LEVEL_LOW (Bit 24) */
#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_LOW_Msk (0x1000000UL) /*!< GPIO14_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_HIGH_Pos (23UL) /*!< GPIO13_EDGE_HIGH (Bit 23) */
#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_HIGH_Msk (0x800000UL) /*!< GPIO13_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_LOW_Pos (22UL) /*!< GPIO13_EDGE_LOW (Bit 22) */
#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_LOW_Msk (0x400000UL) /*!< GPIO13_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_HIGH_Pos (21UL) /*!< GPIO13_LEVEL_HIGH (Bit 21) */
#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_HIGH_Msk (0x200000UL) /*!< GPIO13_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_LOW_Pos (20UL) /*!< GPIO13_LEVEL_LOW (Bit 20) */
#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_LOW_Msk (0x100000UL) /*!< GPIO13_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_HIGH_Pos (19UL) /*!< GPIO12_EDGE_HIGH (Bit 19) */
#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_HIGH_Msk (0x80000UL) /*!< GPIO12_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_LOW_Pos (18UL) /*!< GPIO12_EDGE_LOW (Bit 18) */
#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_LOW_Msk (0x40000UL) /*!< GPIO12_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_HIGH_Pos (17UL) /*!< GPIO12_LEVEL_HIGH (Bit 17) */
#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_HIGH_Msk (0x20000UL) /*!< GPIO12_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_LOW_Pos (16UL) /*!< GPIO12_LEVEL_LOW (Bit 16) */
#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_LOW_Msk (0x10000UL) /*!< GPIO12_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_HIGH_Pos (15UL) /*!< GPIO11_EDGE_HIGH (Bit 15) */
#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_HIGH_Msk (0x8000UL) /*!< GPIO11_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_LOW_Pos (14UL) /*!< GPIO11_EDGE_LOW (Bit 14) */
#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_LOW_Msk (0x4000UL) /*!< GPIO11_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_HIGH_Pos (13UL) /*!< GPIO11_LEVEL_HIGH (Bit 13) */
#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_HIGH_Msk (0x2000UL) /*!< GPIO11_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_LOW_Pos (12UL) /*!< GPIO11_LEVEL_LOW (Bit 12) */
#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_LOW_Msk (0x1000UL) /*!< GPIO11_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_HIGH_Pos (11UL) /*!< GPIO10_EDGE_HIGH (Bit 11) */
#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_HIGH_Msk (0x800UL) /*!< GPIO10_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_LOW_Pos (10UL) /*!< GPIO10_EDGE_LOW (Bit 10) */
#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_LOW_Msk (0x400UL) /*!< GPIO10_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_HIGH_Pos (9UL) /*!< GPIO10_LEVEL_HIGH (Bit 9) */
#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_HIGH_Msk (0x200UL) /*!< GPIO10_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_LOW_Pos (8UL) /*!< GPIO10_LEVEL_LOW (Bit 8) */
#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_LOW_Msk (0x100UL) /*!< GPIO10_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_HIGH_Pos (7UL) /*!< GPIO9_EDGE_HIGH (Bit 7) */
#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_HIGH_Msk (0x80UL) /*!< GPIO9_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_LOW_Pos (6UL) /*!< GPIO9_EDGE_LOW (Bit 6) */
#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_LOW_Msk (0x40UL) /*!< GPIO9_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_HIGH_Pos (5UL) /*!< GPIO9_LEVEL_HIGH (Bit 5) */
#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_HIGH_Msk (0x20UL) /*!< GPIO9_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_LOW_Pos (4UL) /*!< GPIO9_LEVEL_LOW (Bit 4) */
#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_LOW_Msk (0x10UL) /*!< GPIO9_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_HIGH_Pos (3UL) /*!< GPIO8_EDGE_HIGH (Bit 3) */
#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_HIGH_Msk (0x8UL) /*!< GPIO8_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_LOW_Pos (2UL) /*!< GPIO8_EDGE_LOW (Bit 2) */
#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_LOW_Msk (0x4UL) /*!< GPIO8_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_HIGH_Pos (1UL) /*!< GPIO8_LEVEL_HIGH (Bit 1) */
#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_HIGH_Msk (0x2UL) /*!< GPIO8_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_LOW_Pos (0UL) /*!< GPIO8_LEVEL_LOW (Bit 0) */
#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_LOW_Msk (0x1UL) /*!< GPIO8_LEVEL_LOW (Bitfield-Mask: 0x01) */
/* ====================================================== PROC1_INTF2 ====================================================== */
#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_HIGH_Pos (31UL) /*!< GPIO23_EDGE_HIGH (Bit 31) */
#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_HIGH_Msk (0x80000000UL) /*!< GPIO23_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_LOW_Pos (30UL) /*!< GPIO23_EDGE_LOW (Bit 30) */
#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_LOW_Msk (0x40000000UL) /*!< GPIO23_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_HIGH_Pos (29UL) /*!< GPIO23_LEVEL_HIGH (Bit 29) */
#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_HIGH_Msk (0x20000000UL) /*!< GPIO23_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_LOW_Pos (28UL) /*!< GPIO23_LEVEL_LOW (Bit 28) */
#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_LOW_Msk (0x10000000UL) /*!< GPIO23_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_HIGH_Pos (27UL) /*!< GPIO22_EDGE_HIGH (Bit 27) */
#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_HIGH_Msk (0x8000000UL) /*!< GPIO22_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_LOW_Pos (26UL) /*!< GPIO22_EDGE_LOW (Bit 26) */
#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_LOW_Msk (0x4000000UL) /*!< GPIO22_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_HIGH_Pos (25UL) /*!< GPIO22_LEVEL_HIGH (Bit 25) */
#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_HIGH_Msk (0x2000000UL) /*!< GPIO22_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_LOW_Pos (24UL) /*!< GPIO22_LEVEL_LOW (Bit 24) */
#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_LOW_Msk (0x1000000UL) /*!< GPIO22_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_HIGH_Pos (23UL) /*!< GPIO21_EDGE_HIGH (Bit 23) */
#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_HIGH_Msk (0x800000UL) /*!< GPIO21_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_LOW_Pos (22UL) /*!< GPIO21_EDGE_LOW (Bit 22) */
#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_LOW_Msk (0x400000UL) /*!< GPIO21_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_HIGH_Pos (21UL) /*!< GPIO21_LEVEL_HIGH (Bit 21) */
#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_HIGH_Msk (0x200000UL) /*!< GPIO21_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_LOW_Pos (20UL) /*!< GPIO21_LEVEL_LOW (Bit 20) */
#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_LOW_Msk (0x100000UL) /*!< GPIO21_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_HIGH_Pos (19UL) /*!< GPIO20_EDGE_HIGH (Bit 19) */
#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_HIGH_Msk (0x80000UL) /*!< GPIO20_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_LOW_Pos (18UL) /*!< GPIO20_EDGE_LOW (Bit 18) */
#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_LOW_Msk (0x40000UL) /*!< GPIO20_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_HIGH_Pos (17UL) /*!< GPIO20_LEVEL_HIGH (Bit 17) */
#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_HIGH_Msk (0x20000UL) /*!< GPIO20_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_LOW_Pos (16UL) /*!< GPIO20_LEVEL_LOW (Bit 16) */
#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_LOW_Msk (0x10000UL) /*!< GPIO20_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_HIGH_Pos (15UL) /*!< GPIO19_EDGE_HIGH (Bit 15) */
#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_HIGH_Msk (0x8000UL) /*!< GPIO19_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_LOW_Pos (14UL) /*!< GPIO19_EDGE_LOW (Bit 14) */
#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_LOW_Msk (0x4000UL) /*!< GPIO19_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_HIGH_Pos (13UL) /*!< GPIO19_LEVEL_HIGH (Bit 13) */
#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_HIGH_Msk (0x2000UL) /*!< GPIO19_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_LOW_Pos (12UL) /*!< GPIO19_LEVEL_LOW (Bit 12) */
#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_LOW_Msk (0x1000UL) /*!< GPIO19_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_HIGH_Pos (11UL) /*!< GPIO18_EDGE_HIGH (Bit 11) */
#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_HIGH_Msk (0x800UL) /*!< GPIO18_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_LOW_Pos (10UL) /*!< GPIO18_EDGE_LOW (Bit 10) */
#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_LOW_Msk (0x400UL) /*!< GPIO18_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_HIGH_Pos (9UL) /*!< GPIO18_LEVEL_HIGH (Bit 9) */
#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_HIGH_Msk (0x200UL) /*!< GPIO18_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_LOW_Pos (8UL) /*!< GPIO18_LEVEL_LOW (Bit 8) */
#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_LOW_Msk (0x100UL) /*!< GPIO18_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_HIGH_Pos (7UL) /*!< GPIO17_EDGE_HIGH (Bit 7) */
#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_HIGH_Msk (0x80UL) /*!< GPIO17_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_LOW_Pos (6UL) /*!< GPIO17_EDGE_LOW (Bit 6) */
#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_LOW_Msk (0x40UL) /*!< GPIO17_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_HIGH_Pos (5UL) /*!< GPIO17_LEVEL_HIGH (Bit 5) */
#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_HIGH_Msk (0x20UL) /*!< GPIO17_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_LOW_Pos (4UL) /*!< GPIO17_LEVEL_LOW (Bit 4) */
#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_LOW_Msk (0x10UL) /*!< GPIO17_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_HIGH_Pos (3UL) /*!< GPIO16_EDGE_HIGH (Bit 3) */
#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_HIGH_Msk (0x8UL) /*!< GPIO16_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_LOW_Pos (2UL) /*!< GPIO16_EDGE_LOW (Bit 2) */
#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_LOW_Msk (0x4UL) /*!< GPIO16_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_HIGH_Pos (1UL) /*!< GPIO16_LEVEL_HIGH (Bit 1) */
#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_HIGH_Msk (0x2UL) /*!< GPIO16_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_LOW_Pos (0UL) /*!< GPIO16_LEVEL_LOW (Bit 0) */
#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_LOW_Msk (0x1UL) /*!< GPIO16_LEVEL_LOW (Bitfield-Mask: 0x01) */
/* ====================================================== PROC1_INTF3 ====================================================== */
#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_HIGH_Pos (23UL) /*!< GPIO29_EDGE_HIGH (Bit 23) */
#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_HIGH_Msk (0x800000UL) /*!< GPIO29_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_LOW_Pos (22UL) /*!< GPIO29_EDGE_LOW (Bit 22) */
#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_LOW_Msk (0x400000UL) /*!< GPIO29_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_HIGH_Pos (21UL) /*!< GPIO29_LEVEL_HIGH (Bit 21) */
#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_HIGH_Msk (0x200000UL) /*!< GPIO29_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_LOW_Pos (20UL) /*!< GPIO29_LEVEL_LOW (Bit 20) */
#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_LOW_Msk (0x100000UL) /*!< GPIO29_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_HIGH_Pos (19UL) /*!< GPIO28_EDGE_HIGH (Bit 19) */
#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_HIGH_Msk (0x80000UL) /*!< GPIO28_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_LOW_Pos (18UL) /*!< GPIO28_EDGE_LOW (Bit 18) */
#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_LOW_Msk (0x40000UL) /*!< GPIO28_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_HIGH_Pos (17UL) /*!< GPIO28_LEVEL_HIGH (Bit 17) */
#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_HIGH_Msk (0x20000UL) /*!< GPIO28_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_LOW_Pos (16UL) /*!< GPIO28_LEVEL_LOW (Bit 16) */
#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_LOW_Msk (0x10000UL) /*!< GPIO28_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_HIGH_Pos (15UL) /*!< GPIO27_EDGE_HIGH (Bit 15) */
#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_HIGH_Msk (0x8000UL) /*!< GPIO27_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_LOW_Pos (14UL) /*!< GPIO27_EDGE_LOW (Bit 14) */
#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_LOW_Msk (0x4000UL) /*!< GPIO27_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_HIGH_Pos (13UL) /*!< GPIO27_LEVEL_HIGH (Bit 13) */
#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_HIGH_Msk (0x2000UL) /*!< GPIO27_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_LOW_Pos (12UL) /*!< GPIO27_LEVEL_LOW (Bit 12) */
#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_LOW_Msk (0x1000UL) /*!< GPIO27_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_HIGH_Pos (11UL) /*!< GPIO26_EDGE_HIGH (Bit 11) */
#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_HIGH_Msk (0x800UL) /*!< GPIO26_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_LOW_Pos (10UL) /*!< GPIO26_EDGE_LOW (Bit 10) */
#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_LOW_Msk (0x400UL) /*!< GPIO26_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_HIGH_Pos (9UL) /*!< GPIO26_LEVEL_HIGH (Bit 9) */
#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_HIGH_Msk (0x200UL) /*!< GPIO26_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_LOW_Pos (8UL) /*!< GPIO26_LEVEL_LOW (Bit 8) */
#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_LOW_Msk (0x100UL) /*!< GPIO26_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_HIGH_Pos (7UL) /*!< GPIO25_EDGE_HIGH (Bit 7) */
#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_HIGH_Msk (0x80UL) /*!< GPIO25_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_LOW_Pos (6UL) /*!< GPIO25_EDGE_LOW (Bit 6) */
#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_LOW_Msk (0x40UL) /*!< GPIO25_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_HIGH_Pos (5UL) /*!< GPIO25_LEVEL_HIGH (Bit 5) */
#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_HIGH_Msk (0x20UL) /*!< GPIO25_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_LOW_Pos (4UL) /*!< GPIO25_LEVEL_LOW (Bit 4) */
#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_LOW_Msk (0x10UL) /*!< GPIO25_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_HIGH_Pos (3UL) /*!< GPIO24_EDGE_HIGH (Bit 3) */
#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_HIGH_Msk (0x8UL) /*!< GPIO24_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_LOW_Pos (2UL) /*!< GPIO24_EDGE_LOW (Bit 2) */
#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_LOW_Msk (0x4UL) /*!< GPIO24_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_HIGH_Pos (1UL) /*!< GPIO24_LEVEL_HIGH (Bit 1) */
#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_HIGH_Msk (0x2UL) /*!< GPIO24_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_LOW_Pos (0UL) /*!< GPIO24_LEVEL_LOW (Bit 0) */
#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_LOW_Msk (0x1UL) /*!< GPIO24_LEVEL_LOW (Bitfield-Mask: 0x01) */
/* ====================================================== PROC1_INTS0 ====================================================== */
#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_HIGH_Pos (31UL) /*!< GPIO7_EDGE_HIGH (Bit 31) */
#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_HIGH_Msk (0x80000000UL) /*!< GPIO7_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_LOW_Pos (30UL) /*!< GPIO7_EDGE_LOW (Bit 30) */
#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_LOW_Msk (0x40000000UL) /*!< GPIO7_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_HIGH_Pos (29UL) /*!< GPIO7_LEVEL_HIGH (Bit 29) */
#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_HIGH_Msk (0x20000000UL) /*!< GPIO7_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_LOW_Pos (28UL) /*!< GPIO7_LEVEL_LOW (Bit 28) */
#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_LOW_Msk (0x10000000UL) /*!< GPIO7_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_HIGH_Pos (27UL) /*!< GPIO6_EDGE_HIGH (Bit 27) */
#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_HIGH_Msk (0x8000000UL) /*!< GPIO6_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_LOW_Pos (26UL) /*!< GPIO6_EDGE_LOW (Bit 26) */
#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_LOW_Msk (0x4000000UL) /*!< GPIO6_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_HIGH_Pos (25UL) /*!< GPIO6_LEVEL_HIGH (Bit 25) */
#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_HIGH_Msk (0x2000000UL) /*!< GPIO6_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_LOW_Pos (24UL) /*!< GPIO6_LEVEL_LOW (Bit 24) */
#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_LOW_Msk (0x1000000UL) /*!< GPIO6_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_HIGH_Pos (23UL) /*!< GPIO5_EDGE_HIGH (Bit 23) */
#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_HIGH_Msk (0x800000UL) /*!< GPIO5_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_LOW_Pos (22UL) /*!< GPIO5_EDGE_LOW (Bit 22) */
#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_LOW_Msk (0x400000UL) /*!< GPIO5_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_HIGH_Pos (21UL) /*!< GPIO5_LEVEL_HIGH (Bit 21) */
#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_HIGH_Msk (0x200000UL) /*!< GPIO5_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_LOW_Pos (20UL) /*!< GPIO5_LEVEL_LOW (Bit 20) */
#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_LOW_Msk (0x100000UL) /*!< GPIO5_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_HIGH_Pos (19UL) /*!< GPIO4_EDGE_HIGH (Bit 19) */
#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_HIGH_Msk (0x80000UL) /*!< GPIO4_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_LOW_Pos (18UL) /*!< GPIO4_EDGE_LOW (Bit 18) */
#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_LOW_Msk (0x40000UL) /*!< GPIO4_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_HIGH_Pos (17UL) /*!< GPIO4_LEVEL_HIGH (Bit 17) */
#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_HIGH_Msk (0x20000UL) /*!< GPIO4_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_LOW_Pos (16UL) /*!< GPIO4_LEVEL_LOW (Bit 16) */
#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_LOW_Msk (0x10000UL) /*!< GPIO4_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_HIGH_Pos (15UL) /*!< GPIO3_EDGE_HIGH (Bit 15) */
#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_HIGH_Msk (0x8000UL) /*!< GPIO3_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_LOW_Pos (14UL) /*!< GPIO3_EDGE_LOW (Bit 14) */
#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_LOW_Msk (0x4000UL) /*!< GPIO3_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_HIGH_Pos (13UL) /*!< GPIO3_LEVEL_HIGH (Bit 13) */
#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_HIGH_Msk (0x2000UL) /*!< GPIO3_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_LOW_Pos (12UL) /*!< GPIO3_LEVEL_LOW (Bit 12) */
#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_LOW_Msk (0x1000UL) /*!< GPIO3_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_HIGH_Pos (11UL) /*!< GPIO2_EDGE_HIGH (Bit 11) */
#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_HIGH_Msk (0x800UL) /*!< GPIO2_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_LOW_Pos (10UL) /*!< GPIO2_EDGE_LOW (Bit 10) */
#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_LOW_Msk (0x400UL) /*!< GPIO2_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_HIGH_Pos (9UL) /*!< GPIO2_LEVEL_HIGH (Bit 9) */
#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_HIGH_Msk (0x200UL) /*!< GPIO2_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_LOW_Pos (8UL) /*!< GPIO2_LEVEL_LOW (Bit 8) */
#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_LOW_Msk (0x100UL) /*!< GPIO2_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_HIGH_Pos (7UL) /*!< GPIO1_EDGE_HIGH (Bit 7) */
#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_HIGH_Msk (0x80UL) /*!< GPIO1_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_LOW_Pos (6UL) /*!< GPIO1_EDGE_LOW (Bit 6) */
#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_LOW_Msk (0x40UL) /*!< GPIO1_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_HIGH_Pos (5UL) /*!< GPIO1_LEVEL_HIGH (Bit 5) */
#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_HIGH_Msk (0x20UL) /*!< GPIO1_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_LOW_Pos (4UL) /*!< GPIO1_LEVEL_LOW (Bit 4) */
#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_LOW_Msk (0x10UL) /*!< GPIO1_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_HIGH_Pos (3UL) /*!< GPIO0_EDGE_HIGH (Bit 3) */
#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_HIGH_Msk (0x8UL) /*!< GPIO0_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_LOW_Pos (2UL) /*!< GPIO0_EDGE_LOW (Bit 2) */
#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_LOW_Msk (0x4UL) /*!< GPIO0_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_HIGH_Pos (1UL) /*!< GPIO0_LEVEL_HIGH (Bit 1) */
#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_HIGH_Msk (0x2UL) /*!< GPIO0_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_LOW_Pos (0UL) /*!< GPIO0_LEVEL_LOW (Bit 0) */
#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_LOW_Msk (0x1UL) /*!< GPIO0_LEVEL_LOW (Bitfield-Mask: 0x01) */
/* ====================================================== PROC1_INTS1 ====================================================== */
#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_HIGH_Pos (31UL) /*!< GPIO15_EDGE_HIGH (Bit 31) */
#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_HIGH_Msk (0x80000000UL) /*!< GPIO15_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_LOW_Pos (30UL) /*!< GPIO15_EDGE_LOW (Bit 30) */
#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_LOW_Msk (0x40000000UL) /*!< GPIO15_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_HIGH_Pos (29UL) /*!< GPIO15_LEVEL_HIGH (Bit 29) */
#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_HIGH_Msk (0x20000000UL) /*!< GPIO15_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_LOW_Pos (28UL) /*!< GPIO15_LEVEL_LOW (Bit 28) */
#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_LOW_Msk (0x10000000UL) /*!< GPIO15_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_HIGH_Pos (27UL) /*!< GPIO14_EDGE_HIGH (Bit 27) */
#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_HIGH_Msk (0x8000000UL) /*!< GPIO14_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_LOW_Pos (26UL) /*!< GPIO14_EDGE_LOW (Bit 26) */
#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_LOW_Msk (0x4000000UL) /*!< GPIO14_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_HIGH_Pos (25UL) /*!< GPIO14_LEVEL_HIGH (Bit 25) */
#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_HIGH_Msk (0x2000000UL) /*!< GPIO14_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_LOW_Pos (24UL) /*!< GPIO14_LEVEL_LOW (Bit 24) */
#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_LOW_Msk (0x1000000UL) /*!< GPIO14_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_HIGH_Pos (23UL) /*!< GPIO13_EDGE_HIGH (Bit 23) */
#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_HIGH_Msk (0x800000UL) /*!< GPIO13_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_LOW_Pos (22UL) /*!< GPIO13_EDGE_LOW (Bit 22) */
#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_LOW_Msk (0x400000UL) /*!< GPIO13_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_HIGH_Pos (21UL) /*!< GPIO13_LEVEL_HIGH (Bit 21) */
#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_HIGH_Msk (0x200000UL) /*!< GPIO13_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_LOW_Pos (20UL) /*!< GPIO13_LEVEL_LOW (Bit 20) */
#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_LOW_Msk (0x100000UL) /*!< GPIO13_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_HIGH_Pos (19UL) /*!< GPIO12_EDGE_HIGH (Bit 19) */
#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_HIGH_Msk (0x80000UL) /*!< GPIO12_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_LOW_Pos (18UL) /*!< GPIO12_EDGE_LOW (Bit 18) */
#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_LOW_Msk (0x40000UL) /*!< GPIO12_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_HIGH_Pos (17UL) /*!< GPIO12_LEVEL_HIGH (Bit 17) */
#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_HIGH_Msk (0x20000UL) /*!< GPIO12_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_LOW_Pos (16UL) /*!< GPIO12_LEVEL_LOW (Bit 16) */
#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_LOW_Msk (0x10000UL) /*!< GPIO12_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_HIGH_Pos (15UL) /*!< GPIO11_EDGE_HIGH (Bit 15) */
#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_HIGH_Msk (0x8000UL) /*!< GPIO11_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_LOW_Pos (14UL) /*!< GPIO11_EDGE_LOW (Bit 14) */
#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_LOW_Msk (0x4000UL) /*!< GPIO11_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_HIGH_Pos (13UL) /*!< GPIO11_LEVEL_HIGH (Bit 13) */
#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_HIGH_Msk (0x2000UL) /*!< GPIO11_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_LOW_Pos (12UL) /*!< GPIO11_LEVEL_LOW (Bit 12) */
#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_LOW_Msk (0x1000UL) /*!< GPIO11_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_HIGH_Pos (11UL) /*!< GPIO10_EDGE_HIGH (Bit 11) */
#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_HIGH_Msk (0x800UL) /*!< GPIO10_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_LOW_Pos (10UL) /*!< GPIO10_EDGE_LOW (Bit 10) */
#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_LOW_Msk (0x400UL) /*!< GPIO10_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_HIGH_Pos (9UL) /*!< GPIO10_LEVEL_HIGH (Bit 9) */
#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_HIGH_Msk (0x200UL) /*!< GPIO10_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_LOW_Pos (8UL) /*!< GPIO10_LEVEL_LOW (Bit 8) */
#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_LOW_Msk (0x100UL) /*!< GPIO10_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_HIGH_Pos (7UL) /*!< GPIO9_EDGE_HIGH (Bit 7) */
#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_HIGH_Msk (0x80UL) /*!< GPIO9_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_LOW_Pos (6UL) /*!< GPIO9_EDGE_LOW (Bit 6) */
#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_LOW_Msk (0x40UL) /*!< GPIO9_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_HIGH_Pos (5UL) /*!< GPIO9_LEVEL_HIGH (Bit 5) */
#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_HIGH_Msk (0x20UL) /*!< GPIO9_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_LOW_Pos (4UL) /*!< GPIO9_LEVEL_LOW (Bit 4) */
#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_LOW_Msk (0x10UL) /*!< GPIO9_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_HIGH_Pos (3UL) /*!< GPIO8_EDGE_HIGH (Bit 3) */
#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_HIGH_Msk (0x8UL) /*!< GPIO8_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_LOW_Pos (2UL) /*!< GPIO8_EDGE_LOW (Bit 2) */
#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_LOW_Msk (0x4UL) /*!< GPIO8_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_HIGH_Pos (1UL) /*!< GPIO8_LEVEL_HIGH (Bit 1) */
#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_HIGH_Msk (0x2UL) /*!< GPIO8_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_LOW_Pos (0UL) /*!< GPIO8_LEVEL_LOW (Bit 0) */
#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_LOW_Msk (0x1UL) /*!< GPIO8_LEVEL_LOW (Bitfield-Mask: 0x01) */
/* ====================================================== PROC1_INTS2 ====================================================== */
#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_HIGH_Pos (31UL) /*!< GPIO23_EDGE_HIGH (Bit 31) */
#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_HIGH_Msk (0x80000000UL) /*!< GPIO23_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_LOW_Pos (30UL) /*!< GPIO23_EDGE_LOW (Bit 30) */
#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_LOW_Msk (0x40000000UL) /*!< GPIO23_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_HIGH_Pos (29UL) /*!< GPIO23_LEVEL_HIGH (Bit 29) */
#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_HIGH_Msk (0x20000000UL) /*!< GPIO23_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_LOW_Pos (28UL) /*!< GPIO23_LEVEL_LOW (Bit 28) */
#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_LOW_Msk (0x10000000UL) /*!< GPIO23_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_HIGH_Pos (27UL) /*!< GPIO22_EDGE_HIGH (Bit 27) */
#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_HIGH_Msk (0x8000000UL) /*!< GPIO22_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_LOW_Pos (26UL) /*!< GPIO22_EDGE_LOW (Bit 26) */
#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_LOW_Msk (0x4000000UL) /*!< GPIO22_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_HIGH_Pos (25UL) /*!< GPIO22_LEVEL_HIGH (Bit 25) */
#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_HIGH_Msk (0x2000000UL) /*!< GPIO22_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_LOW_Pos (24UL) /*!< GPIO22_LEVEL_LOW (Bit 24) */
#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_LOW_Msk (0x1000000UL) /*!< GPIO22_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_HIGH_Pos (23UL) /*!< GPIO21_EDGE_HIGH (Bit 23) */
#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_HIGH_Msk (0x800000UL) /*!< GPIO21_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_LOW_Pos (22UL) /*!< GPIO21_EDGE_LOW (Bit 22) */
#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_LOW_Msk (0x400000UL) /*!< GPIO21_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_HIGH_Pos (21UL) /*!< GPIO21_LEVEL_HIGH (Bit 21) */
#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_HIGH_Msk (0x200000UL) /*!< GPIO21_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_LOW_Pos (20UL) /*!< GPIO21_LEVEL_LOW (Bit 20) */
#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_LOW_Msk (0x100000UL) /*!< GPIO21_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_HIGH_Pos (19UL) /*!< GPIO20_EDGE_HIGH (Bit 19) */
#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_HIGH_Msk (0x80000UL) /*!< GPIO20_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_LOW_Pos (18UL) /*!< GPIO20_EDGE_LOW (Bit 18) */
#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_LOW_Msk (0x40000UL) /*!< GPIO20_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_HIGH_Pos (17UL) /*!< GPIO20_LEVEL_HIGH (Bit 17) */
#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_HIGH_Msk (0x20000UL) /*!< GPIO20_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_LOW_Pos (16UL) /*!< GPIO20_LEVEL_LOW (Bit 16) */
#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_LOW_Msk (0x10000UL) /*!< GPIO20_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_HIGH_Pos (15UL) /*!< GPIO19_EDGE_HIGH (Bit 15) */
#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_HIGH_Msk (0x8000UL) /*!< GPIO19_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_LOW_Pos (14UL) /*!< GPIO19_EDGE_LOW (Bit 14) */
#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_LOW_Msk (0x4000UL) /*!< GPIO19_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_HIGH_Pos (13UL) /*!< GPIO19_LEVEL_HIGH (Bit 13) */
#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_HIGH_Msk (0x2000UL) /*!< GPIO19_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_LOW_Pos (12UL) /*!< GPIO19_LEVEL_LOW (Bit 12) */
#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_LOW_Msk (0x1000UL) /*!< GPIO19_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_HIGH_Pos (11UL) /*!< GPIO18_EDGE_HIGH (Bit 11) */
#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_HIGH_Msk (0x800UL) /*!< GPIO18_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_LOW_Pos (10UL) /*!< GPIO18_EDGE_LOW (Bit 10) */
#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_LOW_Msk (0x400UL) /*!< GPIO18_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_HIGH_Pos (9UL) /*!< GPIO18_LEVEL_HIGH (Bit 9) */
#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_HIGH_Msk (0x200UL) /*!< GPIO18_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_LOW_Pos (8UL) /*!< GPIO18_LEVEL_LOW (Bit 8) */
#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_LOW_Msk (0x100UL) /*!< GPIO18_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_HIGH_Pos (7UL) /*!< GPIO17_EDGE_HIGH (Bit 7) */
#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_HIGH_Msk (0x80UL) /*!< GPIO17_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_LOW_Pos (6UL) /*!< GPIO17_EDGE_LOW (Bit 6) */
#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_LOW_Msk (0x40UL) /*!< GPIO17_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_HIGH_Pos (5UL) /*!< GPIO17_LEVEL_HIGH (Bit 5) */
#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_HIGH_Msk (0x20UL) /*!< GPIO17_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_LOW_Pos (4UL) /*!< GPIO17_LEVEL_LOW (Bit 4) */
#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_LOW_Msk (0x10UL) /*!< GPIO17_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_HIGH_Pos (3UL) /*!< GPIO16_EDGE_HIGH (Bit 3) */
#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_HIGH_Msk (0x8UL) /*!< GPIO16_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_LOW_Pos (2UL) /*!< GPIO16_EDGE_LOW (Bit 2) */
#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_LOW_Msk (0x4UL) /*!< GPIO16_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_HIGH_Pos (1UL) /*!< GPIO16_LEVEL_HIGH (Bit 1) */
#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_HIGH_Msk (0x2UL) /*!< GPIO16_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_LOW_Pos (0UL) /*!< GPIO16_LEVEL_LOW (Bit 0) */
#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_LOW_Msk (0x1UL) /*!< GPIO16_LEVEL_LOW (Bitfield-Mask: 0x01) */
/* ====================================================== PROC1_INTS3 ====================================================== */
#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_HIGH_Pos (23UL) /*!< GPIO29_EDGE_HIGH (Bit 23) */
#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_HIGH_Msk (0x800000UL) /*!< GPIO29_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_LOW_Pos (22UL) /*!< GPIO29_EDGE_LOW (Bit 22) */
#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_LOW_Msk (0x400000UL) /*!< GPIO29_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_HIGH_Pos (21UL) /*!< GPIO29_LEVEL_HIGH (Bit 21) */
#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_HIGH_Msk (0x200000UL) /*!< GPIO29_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_LOW_Pos (20UL) /*!< GPIO29_LEVEL_LOW (Bit 20) */
#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_LOW_Msk (0x100000UL) /*!< GPIO29_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_HIGH_Pos (19UL) /*!< GPIO28_EDGE_HIGH (Bit 19) */
#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_HIGH_Msk (0x80000UL) /*!< GPIO28_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_LOW_Pos (18UL) /*!< GPIO28_EDGE_LOW (Bit 18) */
#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_LOW_Msk (0x40000UL) /*!< GPIO28_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_HIGH_Pos (17UL) /*!< GPIO28_LEVEL_HIGH (Bit 17) */
#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_HIGH_Msk (0x20000UL) /*!< GPIO28_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_LOW_Pos (16UL) /*!< GPIO28_LEVEL_LOW (Bit 16) */
#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_LOW_Msk (0x10000UL) /*!< GPIO28_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_HIGH_Pos (15UL) /*!< GPIO27_EDGE_HIGH (Bit 15) */
#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_HIGH_Msk (0x8000UL) /*!< GPIO27_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_LOW_Pos (14UL) /*!< GPIO27_EDGE_LOW (Bit 14) */
#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_LOW_Msk (0x4000UL) /*!< GPIO27_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_HIGH_Pos (13UL) /*!< GPIO27_LEVEL_HIGH (Bit 13) */
#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_HIGH_Msk (0x2000UL) /*!< GPIO27_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_LOW_Pos (12UL) /*!< GPIO27_LEVEL_LOW (Bit 12) */
#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_LOW_Msk (0x1000UL) /*!< GPIO27_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_HIGH_Pos (11UL) /*!< GPIO26_EDGE_HIGH (Bit 11) */
#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_HIGH_Msk (0x800UL) /*!< GPIO26_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_LOW_Pos (10UL) /*!< GPIO26_EDGE_LOW (Bit 10) */
#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_LOW_Msk (0x400UL) /*!< GPIO26_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_HIGH_Pos (9UL) /*!< GPIO26_LEVEL_HIGH (Bit 9) */
#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_HIGH_Msk (0x200UL) /*!< GPIO26_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_LOW_Pos (8UL) /*!< GPIO26_LEVEL_LOW (Bit 8) */
#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_LOW_Msk (0x100UL) /*!< GPIO26_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_HIGH_Pos (7UL) /*!< GPIO25_EDGE_HIGH (Bit 7) */
#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_HIGH_Msk (0x80UL) /*!< GPIO25_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_LOW_Pos (6UL) /*!< GPIO25_EDGE_LOW (Bit 6) */
#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_LOW_Msk (0x40UL) /*!< GPIO25_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_HIGH_Pos (5UL) /*!< GPIO25_LEVEL_HIGH (Bit 5) */
#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_HIGH_Msk (0x20UL) /*!< GPIO25_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_LOW_Pos (4UL) /*!< GPIO25_LEVEL_LOW (Bit 4) */
#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_LOW_Msk (0x10UL) /*!< GPIO25_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_HIGH_Pos (3UL) /*!< GPIO24_EDGE_HIGH (Bit 3) */
#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_HIGH_Msk (0x8UL) /*!< GPIO24_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_LOW_Pos (2UL) /*!< GPIO24_EDGE_LOW (Bit 2) */
#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_LOW_Msk (0x4UL) /*!< GPIO24_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_HIGH_Pos (1UL) /*!< GPIO24_LEVEL_HIGH (Bit 1) */
#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_HIGH_Msk (0x2UL) /*!< GPIO24_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_LOW_Pos (0UL) /*!< GPIO24_LEVEL_LOW (Bit 0) */
#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_LOW_Msk (0x1UL) /*!< GPIO24_LEVEL_LOW (Bitfield-Mask: 0x01) */
/* ================================================== DORMANT_WAKE_INTE0 =================================================== */
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_HIGH_Pos (31UL) /*!< GPIO7_EDGE_HIGH (Bit 31) */
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_HIGH_Msk (0x80000000UL) /*!< GPIO7_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_LOW_Pos (30UL) /*!< GPIO7_EDGE_LOW (Bit 30) */
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_LOW_Msk (0x40000000UL) /*!< GPIO7_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_HIGH_Pos (29UL) /*!< GPIO7_LEVEL_HIGH (Bit 29) */
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_HIGH_Msk (0x20000000UL) /*!< GPIO7_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_LOW_Pos (28UL) /*!< GPIO7_LEVEL_LOW (Bit 28) */
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_LOW_Msk (0x10000000UL) /*!< GPIO7_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_HIGH_Pos (27UL) /*!< GPIO6_EDGE_HIGH (Bit 27) */
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_HIGH_Msk (0x8000000UL) /*!< GPIO6_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_LOW_Pos (26UL) /*!< GPIO6_EDGE_LOW (Bit 26) */
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_LOW_Msk (0x4000000UL) /*!< GPIO6_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_HIGH_Pos (25UL) /*!< GPIO6_LEVEL_HIGH (Bit 25) */
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_HIGH_Msk (0x2000000UL) /*!< GPIO6_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_LOW_Pos (24UL) /*!< GPIO6_LEVEL_LOW (Bit 24) */
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_LOW_Msk (0x1000000UL) /*!< GPIO6_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_HIGH_Pos (23UL) /*!< GPIO5_EDGE_HIGH (Bit 23) */
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_HIGH_Msk (0x800000UL) /*!< GPIO5_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_LOW_Pos (22UL) /*!< GPIO5_EDGE_LOW (Bit 22) */
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_LOW_Msk (0x400000UL) /*!< GPIO5_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_HIGH_Pos (21UL) /*!< GPIO5_LEVEL_HIGH (Bit 21) */
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_HIGH_Msk (0x200000UL) /*!< GPIO5_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_LOW_Pos (20UL) /*!< GPIO5_LEVEL_LOW (Bit 20) */
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_LOW_Msk (0x100000UL) /*!< GPIO5_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_HIGH_Pos (19UL) /*!< GPIO4_EDGE_HIGH (Bit 19) */
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_HIGH_Msk (0x80000UL) /*!< GPIO4_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_LOW_Pos (18UL) /*!< GPIO4_EDGE_LOW (Bit 18) */
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_LOW_Msk (0x40000UL) /*!< GPIO4_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_HIGH_Pos (17UL) /*!< GPIO4_LEVEL_HIGH (Bit 17) */
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_HIGH_Msk (0x20000UL) /*!< GPIO4_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_LOW_Pos (16UL) /*!< GPIO4_LEVEL_LOW (Bit 16) */
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_LOW_Msk (0x10000UL) /*!< GPIO4_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_HIGH_Pos (15UL) /*!< GPIO3_EDGE_HIGH (Bit 15) */
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_HIGH_Msk (0x8000UL) /*!< GPIO3_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_LOW_Pos (14UL) /*!< GPIO3_EDGE_LOW (Bit 14) */
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_LOW_Msk (0x4000UL) /*!< GPIO3_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_HIGH_Pos (13UL) /*!< GPIO3_LEVEL_HIGH (Bit 13) */
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_HIGH_Msk (0x2000UL) /*!< GPIO3_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_LOW_Pos (12UL) /*!< GPIO3_LEVEL_LOW (Bit 12) */
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_LOW_Msk (0x1000UL) /*!< GPIO3_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_HIGH_Pos (11UL) /*!< GPIO2_EDGE_HIGH (Bit 11) */
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_HIGH_Msk (0x800UL) /*!< GPIO2_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_LOW_Pos (10UL) /*!< GPIO2_EDGE_LOW (Bit 10) */
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_LOW_Msk (0x400UL) /*!< GPIO2_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_HIGH_Pos (9UL) /*!< GPIO2_LEVEL_HIGH (Bit 9) */
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_HIGH_Msk (0x200UL) /*!< GPIO2_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_LOW_Pos (8UL) /*!< GPIO2_LEVEL_LOW (Bit 8) */
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_LOW_Msk (0x100UL) /*!< GPIO2_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_HIGH_Pos (7UL) /*!< GPIO1_EDGE_HIGH (Bit 7) */
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_HIGH_Msk (0x80UL) /*!< GPIO1_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_LOW_Pos (6UL) /*!< GPIO1_EDGE_LOW (Bit 6) */
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_LOW_Msk (0x40UL) /*!< GPIO1_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_HIGH_Pos (5UL) /*!< GPIO1_LEVEL_HIGH (Bit 5) */
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_HIGH_Msk (0x20UL) /*!< GPIO1_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_LOW_Pos (4UL) /*!< GPIO1_LEVEL_LOW (Bit 4) */
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_LOW_Msk (0x10UL) /*!< GPIO1_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_HIGH_Pos (3UL) /*!< GPIO0_EDGE_HIGH (Bit 3) */
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_HIGH_Msk (0x8UL) /*!< GPIO0_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_LOW_Pos (2UL) /*!< GPIO0_EDGE_LOW (Bit 2) */
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_LOW_Msk (0x4UL) /*!< GPIO0_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_HIGH_Pos (1UL) /*!< GPIO0_LEVEL_HIGH (Bit 1) */
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_HIGH_Msk (0x2UL) /*!< GPIO0_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_LOW_Pos (0UL) /*!< GPIO0_LEVEL_LOW (Bit 0) */
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_LOW_Msk (0x1UL) /*!< GPIO0_LEVEL_LOW (Bitfield-Mask: 0x01) */
/* ================================================== DORMANT_WAKE_INTE1 =================================================== */
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_HIGH_Pos (31UL) /*!< GPIO15_EDGE_HIGH (Bit 31) */
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_HIGH_Msk (0x80000000UL) /*!< GPIO15_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_LOW_Pos (30UL) /*!< GPIO15_EDGE_LOW (Bit 30) */
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_LOW_Msk (0x40000000UL) /*!< GPIO15_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_HIGH_Pos (29UL) /*!< GPIO15_LEVEL_HIGH (Bit 29) */
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_HIGH_Msk (0x20000000UL) /*!< GPIO15_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_LOW_Pos (28UL) /*!< GPIO15_LEVEL_LOW (Bit 28) */
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_LOW_Msk (0x10000000UL) /*!< GPIO15_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_HIGH_Pos (27UL) /*!< GPIO14_EDGE_HIGH (Bit 27) */
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_HIGH_Msk (0x8000000UL) /*!< GPIO14_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_LOW_Pos (26UL) /*!< GPIO14_EDGE_LOW (Bit 26) */
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_LOW_Msk (0x4000000UL) /*!< GPIO14_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_HIGH_Pos (25UL) /*!< GPIO14_LEVEL_HIGH (Bit 25) */
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_HIGH_Msk (0x2000000UL) /*!< GPIO14_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_LOW_Pos (24UL) /*!< GPIO14_LEVEL_LOW (Bit 24) */
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_LOW_Msk (0x1000000UL) /*!< GPIO14_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_HIGH_Pos (23UL) /*!< GPIO13_EDGE_HIGH (Bit 23) */
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_HIGH_Msk (0x800000UL) /*!< GPIO13_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_LOW_Pos (22UL) /*!< GPIO13_EDGE_LOW (Bit 22) */
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_LOW_Msk (0x400000UL) /*!< GPIO13_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_HIGH_Pos (21UL) /*!< GPIO13_LEVEL_HIGH (Bit 21) */
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_HIGH_Msk (0x200000UL) /*!< GPIO13_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_LOW_Pos (20UL) /*!< GPIO13_LEVEL_LOW (Bit 20) */
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_LOW_Msk (0x100000UL) /*!< GPIO13_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_HIGH_Pos (19UL) /*!< GPIO12_EDGE_HIGH (Bit 19) */
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_HIGH_Msk (0x80000UL) /*!< GPIO12_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_LOW_Pos (18UL) /*!< GPIO12_EDGE_LOW (Bit 18) */
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_LOW_Msk (0x40000UL) /*!< GPIO12_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_HIGH_Pos (17UL) /*!< GPIO12_LEVEL_HIGH (Bit 17) */
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_HIGH_Msk (0x20000UL) /*!< GPIO12_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_LOW_Pos (16UL) /*!< GPIO12_LEVEL_LOW (Bit 16) */
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_LOW_Msk (0x10000UL) /*!< GPIO12_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_HIGH_Pos (15UL) /*!< GPIO11_EDGE_HIGH (Bit 15) */
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_HIGH_Msk (0x8000UL) /*!< GPIO11_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_LOW_Pos (14UL) /*!< GPIO11_EDGE_LOW (Bit 14) */
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_LOW_Msk (0x4000UL) /*!< GPIO11_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_HIGH_Pos (13UL) /*!< GPIO11_LEVEL_HIGH (Bit 13) */
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_HIGH_Msk (0x2000UL) /*!< GPIO11_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_LOW_Pos (12UL) /*!< GPIO11_LEVEL_LOW (Bit 12) */
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_LOW_Msk (0x1000UL) /*!< GPIO11_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_HIGH_Pos (11UL) /*!< GPIO10_EDGE_HIGH (Bit 11) */
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_HIGH_Msk (0x800UL) /*!< GPIO10_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_LOW_Pos (10UL) /*!< GPIO10_EDGE_LOW (Bit 10) */
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_LOW_Msk (0x400UL) /*!< GPIO10_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_HIGH_Pos (9UL) /*!< GPIO10_LEVEL_HIGH (Bit 9) */
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_HIGH_Msk (0x200UL) /*!< GPIO10_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_LOW_Pos (8UL) /*!< GPIO10_LEVEL_LOW (Bit 8) */
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_LOW_Msk (0x100UL) /*!< GPIO10_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_HIGH_Pos (7UL) /*!< GPIO9_EDGE_HIGH (Bit 7) */
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_HIGH_Msk (0x80UL) /*!< GPIO9_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_LOW_Pos (6UL) /*!< GPIO9_EDGE_LOW (Bit 6) */
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_LOW_Msk (0x40UL) /*!< GPIO9_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_HIGH_Pos (5UL) /*!< GPIO9_LEVEL_HIGH (Bit 5) */
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_HIGH_Msk (0x20UL) /*!< GPIO9_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_LOW_Pos (4UL) /*!< GPIO9_LEVEL_LOW (Bit 4) */
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_LOW_Msk (0x10UL) /*!< GPIO9_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_HIGH_Pos (3UL) /*!< GPIO8_EDGE_HIGH (Bit 3) */
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_HIGH_Msk (0x8UL) /*!< GPIO8_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_LOW_Pos (2UL) /*!< GPIO8_EDGE_LOW (Bit 2) */
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_LOW_Msk (0x4UL) /*!< GPIO8_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_HIGH_Pos (1UL) /*!< GPIO8_LEVEL_HIGH (Bit 1) */
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_HIGH_Msk (0x2UL) /*!< GPIO8_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_LOW_Pos (0UL) /*!< GPIO8_LEVEL_LOW (Bit 0) */
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_LOW_Msk (0x1UL) /*!< GPIO8_LEVEL_LOW (Bitfield-Mask: 0x01) */
/* ================================================== DORMANT_WAKE_INTE2 =================================================== */
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_HIGH_Pos (31UL) /*!< GPIO23_EDGE_HIGH (Bit 31) */
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_HIGH_Msk (0x80000000UL) /*!< GPIO23_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_LOW_Pos (30UL) /*!< GPIO23_EDGE_LOW (Bit 30) */
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_LOW_Msk (0x40000000UL) /*!< GPIO23_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_HIGH_Pos (29UL) /*!< GPIO23_LEVEL_HIGH (Bit 29) */
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_HIGH_Msk (0x20000000UL) /*!< GPIO23_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_LOW_Pos (28UL) /*!< GPIO23_LEVEL_LOW (Bit 28) */
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_LOW_Msk (0x10000000UL) /*!< GPIO23_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_HIGH_Pos (27UL) /*!< GPIO22_EDGE_HIGH (Bit 27) */
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_HIGH_Msk (0x8000000UL) /*!< GPIO22_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_LOW_Pos (26UL) /*!< GPIO22_EDGE_LOW (Bit 26) */
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_LOW_Msk (0x4000000UL) /*!< GPIO22_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_HIGH_Pos (25UL) /*!< GPIO22_LEVEL_HIGH (Bit 25) */
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_HIGH_Msk (0x2000000UL) /*!< GPIO22_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_LOW_Pos (24UL) /*!< GPIO22_LEVEL_LOW (Bit 24) */
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_LOW_Msk (0x1000000UL) /*!< GPIO22_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_HIGH_Pos (23UL) /*!< GPIO21_EDGE_HIGH (Bit 23) */
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_HIGH_Msk (0x800000UL) /*!< GPIO21_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_LOW_Pos (22UL) /*!< GPIO21_EDGE_LOW (Bit 22) */
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_LOW_Msk (0x400000UL) /*!< GPIO21_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_HIGH_Pos (21UL) /*!< GPIO21_LEVEL_HIGH (Bit 21) */
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_HIGH_Msk (0x200000UL) /*!< GPIO21_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_LOW_Pos (20UL) /*!< GPIO21_LEVEL_LOW (Bit 20) */
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_LOW_Msk (0x100000UL) /*!< GPIO21_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_HIGH_Pos (19UL) /*!< GPIO20_EDGE_HIGH (Bit 19) */
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_HIGH_Msk (0x80000UL) /*!< GPIO20_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_LOW_Pos (18UL) /*!< GPIO20_EDGE_LOW (Bit 18) */
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_LOW_Msk (0x40000UL) /*!< GPIO20_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_HIGH_Pos (17UL) /*!< GPIO20_LEVEL_HIGH (Bit 17) */
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_HIGH_Msk (0x20000UL) /*!< GPIO20_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_LOW_Pos (16UL) /*!< GPIO20_LEVEL_LOW (Bit 16) */
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_LOW_Msk (0x10000UL) /*!< GPIO20_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_HIGH_Pos (15UL) /*!< GPIO19_EDGE_HIGH (Bit 15) */
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_HIGH_Msk (0x8000UL) /*!< GPIO19_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_LOW_Pos (14UL) /*!< GPIO19_EDGE_LOW (Bit 14) */
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_LOW_Msk (0x4000UL) /*!< GPIO19_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_HIGH_Pos (13UL) /*!< GPIO19_LEVEL_HIGH (Bit 13) */
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_HIGH_Msk (0x2000UL) /*!< GPIO19_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_LOW_Pos (12UL) /*!< GPIO19_LEVEL_LOW (Bit 12) */
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_LOW_Msk (0x1000UL) /*!< GPIO19_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_HIGH_Pos (11UL) /*!< GPIO18_EDGE_HIGH (Bit 11) */
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_HIGH_Msk (0x800UL) /*!< GPIO18_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_LOW_Pos (10UL) /*!< GPIO18_EDGE_LOW (Bit 10) */
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_LOW_Msk (0x400UL) /*!< GPIO18_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_HIGH_Pos (9UL) /*!< GPIO18_LEVEL_HIGH (Bit 9) */
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_HIGH_Msk (0x200UL) /*!< GPIO18_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_LOW_Pos (8UL) /*!< GPIO18_LEVEL_LOW (Bit 8) */
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_LOW_Msk (0x100UL) /*!< GPIO18_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_HIGH_Pos (7UL) /*!< GPIO17_EDGE_HIGH (Bit 7) */
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_HIGH_Msk (0x80UL) /*!< GPIO17_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_LOW_Pos (6UL) /*!< GPIO17_EDGE_LOW (Bit 6) */
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_LOW_Msk (0x40UL) /*!< GPIO17_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_HIGH_Pos (5UL) /*!< GPIO17_LEVEL_HIGH (Bit 5) */
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_HIGH_Msk (0x20UL) /*!< GPIO17_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_LOW_Pos (4UL) /*!< GPIO17_LEVEL_LOW (Bit 4) */
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_LOW_Msk (0x10UL) /*!< GPIO17_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_HIGH_Pos (3UL) /*!< GPIO16_EDGE_HIGH (Bit 3) */
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_HIGH_Msk (0x8UL) /*!< GPIO16_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_LOW_Pos (2UL) /*!< GPIO16_EDGE_LOW (Bit 2) */
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_LOW_Msk (0x4UL) /*!< GPIO16_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_HIGH_Pos (1UL) /*!< GPIO16_LEVEL_HIGH (Bit 1) */
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_HIGH_Msk (0x2UL) /*!< GPIO16_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_LOW_Pos (0UL) /*!< GPIO16_LEVEL_LOW (Bit 0) */
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_LOW_Msk (0x1UL) /*!< GPIO16_LEVEL_LOW (Bitfield-Mask: 0x01) */
/* ================================================== DORMANT_WAKE_INTE3 =================================================== */
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_HIGH_Pos (23UL) /*!< GPIO29_EDGE_HIGH (Bit 23) */
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_HIGH_Msk (0x800000UL) /*!< GPIO29_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_LOW_Pos (22UL) /*!< GPIO29_EDGE_LOW (Bit 22) */
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_LOW_Msk (0x400000UL) /*!< GPIO29_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_HIGH_Pos (21UL) /*!< GPIO29_LEVEL_HIGH (Bit 21) */
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_HIGH_Msk (0x200000UL) /*!< GPIO29_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_LOW_Pos (20UL) /*!< GPIO29_LEVEL_LOW (Bit 20) */
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_LOW_Msk (0x100000UL) /*!< GPIO29_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_HIGH_Pos (19UL) /*!< GPIO28_EDGE_HIGH (Bit 19) */
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_HIGH_Msk (0x80000UL) /*!< GPIO28_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_LOW_Pos (18UL) /*!< GPIO28_EDGE_LOW (Bit 18) */
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_LOW_Msk (0x40000UL) /*!< GPIO28_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_HIGH_Pos (17UL) /*!< GPIO28_LEVEL_HIGH (Bit 17) */
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_HIGH_Msk (0x20000UL) /*!< GPIO28_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_LOW_Pos (16UL) /*!< GPIO28_LEVEL_LOW (Bit 16) */
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_LOW_Msk (0x10000UL) /*!< GPIO28_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_HIGH_Pos (15UL) /*!< GPIO27_EDGE_HIGH (Bit 15) */
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_HIGH_Msk (0x8000UL) /*!< GPIO27_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_LOW_Pos (14UL) /*!< GPIO27_EDGE_LOW (Bit 14) */
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_LOW_Msk (0x4000UL) /*!< GPIO27_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_HIGH_Pos (13UL) /*!< GPIO27_LEVEL_HIGH (Bit 13) */
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_HIGH_Msk (0x2000UL) /*!< GPIO27_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_LOW_Pos (12UL) /*!< GPIO27_LEVEL_LOW (Bit 12) */
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_LOW_Msk (0x1000UL) /*!< GPIO27_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_HIGH_Pos (11UL) /*!< GPIO26_EDGE_HIGH (Bit 11) */
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_HIGH_Msk (0x800UL) /*!< GPIO26_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_LOW_Pos (10UL) /*!< GPIO26_EDGE_LOW (Bit 10) */
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_LOW_Msk (0x400UL) /*!< GPIO26_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_HIGH_Pos (9UL) /*!< GPIO26_LEVEL_HIGH (Bit 9) */
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_HIGH_Msk (0x200UL) /*!< GPIO26_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_LOW_Pos (8UL) /*!< GPIO26_LEVEL_LOW (Bit 8) */
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_LOW_Msk (0x100UL) /*!< GPIO26_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_HIGH_Pos (7UL) /*!< GPIO25_EDGE_HIGH (Bit 7) */
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_HIGH_Msk (0x80UL) /*!< GPIO25_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_LOW_Pos (6UL) /*!< GPIO25_EDGE_LOW (Bit 6) */
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_LOW_Msk (0x40UL) /*!< GPIO25_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_HIGH_Pos (5UL) /*!< GPIO25_LEVEL_HIGH (Bit 5) */
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_HIGH_Msk (0x20UL) /*!< GPIO25_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_LOW_Pos (4UL) /*!< GPIO25_LEVEL_LOW (Bit 4) */
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_LOW_Msk (0x10UL) /*!< GPIO25_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_HIGH_Pos (3UL) /*!< GPIO24_EDGE_HIGH (Bit 3) */
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_HIGH_Msk (0x8UL) /*!< GPIO24_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_LOW_Pos (2UL) /*!< GPIO24_EDGE_LOW (Bit 2) */
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_LOW_Msk (0x4UL) /*!< GPIO24_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_HIGH_Pos (1UL) /*!< GPIO24_LEVEL_HIGH (Bit 1) */
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_HIGH_Msk (0x2UL) /*!< GPIO24_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_LOW_Pos (0UL) /*!< GPIO24_LEVEL_LOW (Bit 0) */
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_LOW_Msk (0x1UL) /*!< GPIO24_LEVEL_LOW (Bitfield-Mask: 0x01) */
/* ================================================== DORMANT_WAKE_INTF0 =================================================== */
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_HIGH_Pos (31UL) /*!< GPIO7_EDGE_HIGH (Bit 31) */
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_HIGH_Msk (0x80000000UL) /*!< GPIO7_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_LOW_Pos (30UL) /*!< GPIO7_EDGE_LOW (Bit 30) */
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_LOW_Msk (0x40000000UL) /*!< GPIO7_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_HIGH_Pos (29UL) /*!< GPIO7_LEVEL_HIGH (Bit 29) */
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_HIGH_Msk (0x20000000UL) /*!< GPIO7_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_LOW_Pos (28UL) /*!< GPIO7_LEVEL_LOW (Bit 28) */
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_LOW_Msk (0x10000000UL) /*!< GPIO7_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_HIGH_Pos (27UL) /*!< GPIO6_EDGE_HIGH (Bit 27) */
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_HIGH_Msk (0x8000000UL) /*!< GPIO6_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_LOW_Pos (26UL) /*!< GPIO6_EDGE_LOW (Bit 26) */
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_LOW_Msk (0x4000000UL) /*!< GPIO6_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_HIGH_Pos (25UL) /*!< GPIO6_LEVEL_HIGH (Bit 25) */
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_HIGH_Msk (0x2000000UL) /*!< GPIO6_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_LOW_Pos (24UL) /*!< GPIO6_LEVEL_LOW (Bit 24) */
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_LOW_Msk (0x1000000UL) /*!< GPIO6_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_HIGH_Pos (23UL) /*!< GPIO5_EDGE_HIGH (Bit 23) */
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_HIGH_Msk (0x800000UL) /*!< GPIO5_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_LOW_Pos (22UL) /*!< GPIO5_EDGE_LOW (Bit 22) */
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_LOW_Msk (0x400000UL) /*!< GPIO5_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_HIGH_Pos (21UL) /*!< GPIO5_LEVEL_HIGH (Bit 21) */
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_HIGH_Msk (0x200000UL) /*!< GPIO5_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_LOW_Pos (20UL) /*!< GPIO5_LEVEL_LOW (Bit 20) */
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_LOW_Msk (0x100000UL) /*!< GPIO5_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_HIGH_Pos (19UL) /*!< GPIO4_EDGE_HIGH (Bit 19) */
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_HIGH_Msk (0x80000UL) /*!< GPIO4_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_LOW_Pos (18UL) /*!< GPIO4_EDGE_LOW (Bit 18) */
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_LOW_Msk (0x40000UL) /*!< GPIO4_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_HIGH_Pos (17UL) /*!< GPIO4_LEVEL_HIGH (Bit 17) */
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_HIGH_Msk (0x20000UL) /*!< GPIO4_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_LOW_Pos (16UL) /*!< GPIO4_LEVEL_LOW (Bit 16) */
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_LOW_Msk (0x10000UL) /*!< GPIO4_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_HIGH_Pos (15UL) /*!< GPIO3_EDGE_HIGH (Bit 15) */
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_HIGH_Msk (0x8000UL) /*!< GPIO3_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_LOW_Pos (14UL) /*!< GPIO3_EDGE_LOW (Bit 14) */
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_LOW_Msk (0x4000UL) /*!< GPIO3_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_HIGH_Pos (13UL) /*!< GPIO3_LEVEL_HIGH (Bit 13) */
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_HIGH_Msk (0x2000UL) /*!< GPIO3_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_LOW_Pos (12UL) /*!< GPIO3_LEVEL_LOW (Bit 12) */
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_LOW_Msk (0x1000UL) /*!< GPIO3_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_HIGH_Pos (11UL) /*!< GPIO2_EDGE_HIGH (Bit 11) */
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_HIGH_Msk (0x800UL) /*!< GPIO2_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_LOW_Pos (10UL) /*!< GPIO2_EDGE_LOW (Bit 10) */
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_LOW_Msk (0x400UL) /*!< GPIO2_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_HIGH_Pos (9UL) /*!< GPIO2_LEVEL_HIGH (Bit 9) */
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_HIGH_Msk (0x200UL) /*!< GPIO2_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_LOW_Pos (8UL) /*!< GPIO2_LEVEL_LOW (Bit 8) */
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_LOW_Msk (0x100UL) /*!< GPIO2_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_HIGH_Pos (7UL) /*!< GPIO1_EDGE_HIGH (Bit 7) */
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_HIGH_Msk (0x80UL) /*!< GPIO1_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_LOW_Pos (6UL) /*!< GPIO1_EDGE_LOW (Bit 6) */
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_LOW_Msk (0x40UL) /*!< GPIO1_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_HIGH_Pos (5UL) /*!< GPIO1_LEVEL_HIGH (Bit 5) */
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_HIGH_Msk (0x20UL) /*!< GPIO1_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_LOW_Pos (4UL) /*!< GPIO1_LEVEL_LOW (Bit 4) */
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_LOW_Msk (0x10UL) /*!< GPIO1_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_HIGH_Pos (3UL) /*!< GPIO0_EDGE_HIGH (Bit 3) */
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_HIGH_Msk (0x8UL) /*!< GPIO0_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_LOW_Pos (2UL) /*!< GPIO0_EDGE_LOW (Bit 2) */
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_LOW_Msk (0x4UL) /*!< GPIO0_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_HIGH_Pos (1UL) /*!< GPIO0_LEVEL_HIGH (Bit 1) */
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_HIGH_Msk (0x2UL) /*!< GPIO0_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_LOW_Pos (0UL) /*!< GPIO0_LEVEL_LOW (Bit 0) */
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_LOW_Msk (0x1UL) /*!< GPIO0_LEVEL_LOW (Bitfield-Mask: 0x01) */
/* ================================================== DORMANT_WAKE_INTF1 =================================================== */
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_HIGH_Pos (31UL) /*!< GPIO15_EDGE_HIGH (Bit 31) */
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_HIGH_Msk (0x80000000UL) /*!< GPIO15_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_LOW_Pos (30UL) /*!< GPIO15_EDGE_LOW (Bit 30) */
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_LOW_Msk (0x40000000UL) /*!< GPIO15_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_HIGH_Pos (29UL) /*!< GPIO15_LEVEL_HIGH (Bit 29) */
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_HIGH_Msk (0x20000000UL) /*!< GPIO15_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_LOW_Pos (28UL) /*!< GPIO15_LEVEL_LOW (Bit 28) */
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_LOW_Msk (0x10000000UL) /*!< GPIO15_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_HIGH_Pos (27UL) /*!< GPIO14_EDGE_HIGH (Bit 27) */
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_HIGH_Msk (0x8000000UL) /*!< GPIO14_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_LOW_Pos (26UL) /*!< GPIO14_EDGE_LOW (Bit 26) */
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_LOW_Msk (0x4000000UL) /*!< GPIO14_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_HIGH_Pos (25UL) /*!< GPIO14_LEVEL_HIGH (Bit 25) */
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_HIGH_Msk (0x2000000UL) /*!< GPIO14_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_LOW_Pos (24UL) /*!< GPIO14_LEVEL_LOW (Bit 24) */
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_LOW_Msk (0x1000000UL) /*!< GPIO14_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_HIGH_Pos (23UL) /*!< GPIO13_EDGE_HIGH (Bit 23) */
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_HIGH_Msk (0x800000UL) /*!< GPIO13_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_LOW_Pos (22UL) /*!< GPIO13_EDGE_LOW (Bit 22) */
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_LOW_Msk (0x400000UL) /*!< GPIO13_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_HIGH_Pos (21UL) /*!< GPIO13_LEVEL_HIGH (Bit 21) */
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_HIGH_Msk (0x200000UL) /*!< GPIO13_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_LOW_Pos (20UL) /*!< GPIO13_LEVEL_LOW (Bit 20) */
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_LOW_Msk (0x100000UL) /*!< GPIO13_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_HIGH_Pos (19UL) /*!< GPIO12_EDGE_HIGH (Bit 19) */
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_HIGH_Msk (0x80000UL) /*!< GPIO12_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_LOW_Pos (18UL) /*!< GPIO12_EDGE_LOW (Bit 18) */
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_LOW_Msk (0x40000UL) /*!< GPIO12_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_HIGH_Pos (17UL) /*!< GPIO12_LEVEL_HIGH (Bit 17) */
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_HIGH_Msk (0x20000UL) /*!< GPIO12_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_LOW_Pos (16UL) /*!< GPIO12_LEVEL_LOW (Bit 16) */
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_LOW_Msk (0x10000UL) /*!< GPIO12_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_HIGH_Pos (15UL) /*!< GPIO11_EDGE_HIGH (Bit 15) */
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_HIGH_Msk (0x8000UL) /*!< GPIO11_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_LOW_Pos (14UL) /*!< GPIO11_EDGE_LOW (Bit 14) */
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_LOW_Msk (0x4000UL) /*!< GPIO11_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_HIGH_Pos (13UL) /*!< GPIO11_LEVEL_HIGH (Bit 13) */
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_HIGH_Msk (0x2000UL) /*!< GPIO11_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_LOW_Pos (12UL) /*!< GPIO11_LEVEL_LOW (Bit 12) */
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_LOW_Msk (0x1000UL) /*!< GPIO11_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_HIGH_Pos (11UL) /*!< GPIO10_EDGE_HIGH (Bit 11) */
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_HIGH_Msk (0x800UL) /*!< GPIO10_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_LOW_Pos (10UL) /*!< GPIO10_EDGE_LOW (Bit 10) */
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_LOW_Msk (0x400UL) /*!< GPIO10_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_HIGH_Pos (9UL) /*!< GPIO10_LEVEL_HIGH (Bit 9) */
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_HIGH_Msk (0x200UL) /*!< GPIO10_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_LOW_Pos (8UL) /*!< GPIO10_LEVEL_LOW (Bit 8) */
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_LOW_Msk (0x100UL) /*!< GPIO10_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_HIGH_Pos (7UL) /*!< GPIO9_EDGE_HIGH (Bit 7) */
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_HIGH_Msk (0x80UL) /*!< GPIO9_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_LOW_Pos (6UL) /*!< GPIO9_EDGE_LOW (Bit 6) */
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_LOW_Msk (0x40UL) /*!< GPIO9_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_HIGH_Pos (5UL) /*!< GPIO9_LEVEL_HIGH (Bit 5) */
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_HIGH_Msk (0x20UL) /*!< GPIO9_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_LOW_Pos (4UL) /*!< GPIO9_LEVEL_LOW (Bit 4) */
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_LOW_Msk (0x10UL) /*!< GPIO9_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_HIGH_Pos (3UL) /*!< GPIO8_EDGE_HIGH (Bit 3) */
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_HIGH_Msk (0x8UL) /*!< GPIO8_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_LOW_Pos (2UL) /*!< GPIO8_EDGE_LOW (Bit 2) */
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_LOW_Msk (0x4UL) /*!< GPIO8_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_HIGH_Pos (1UL) /*!< GPIO8_LEVEL_HIGH (Bit 1) */
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_HIGH_Msk (0x2UL) /*!< GPIO8_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_LOW_Pos (0UL) /*!< GPIO8_LEVEL_LOW (Bit 0) */
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_LOW_Msk (0x1UL) /*!< GPIO8_LEVEL_LOW (Bitfield-Mask: 0x01) */
/* ================================================== DORMANT_WAKE_INTF2 =================================================== */
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_HIGH_Pos (31UL) /*!< GPIO23_EDGE_HIGH (Bit 31) */
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_HIGH_Msk (0x80000000UL) /*!< GPIO23_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_LOW_Pos (30UL) /*!< GPIO23_EDGE_LOW (Bit 30) */
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_LOW_Msk (0x40000000UL) /*!< GPIO23_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_HIGH_Pos (29UL) /*!< GPIO23_LEVEL_HIGH (Bit 29) */
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_HIGH_Msk (0x20000000UL) /*!< GPIO23_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_LOW_Pos (28UL) /*!< GPIO23_LEVEL_LOW (Bit 28) */
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_LOW_Msk (0x10000000UL) /*!< GPIO23_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_HIGH_Pos (27UL) /*!< GPIO22_EDGE_HIGH (Bit 27) */
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_HIGH_Msk (0x8000000UL) /*!< GPIO22_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_LOW_Pos (26UL) /*!< GPIO22_EDGE_LOW (Bit 26) */
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_LOW_Msk (0x4000000UL) /*!< GPIO22_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_HIGH_Pos (25UL) /*!< GPIO22_LEVEL_HIGH (Bit 25) */
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_HIGH_Msk (0x2000000UL) /*!< GPIO22_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_LOW_Pos (24UL) /*!< GPIO22_LEVEL_LOW (Bit 24) */
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_LOW_Msk (0x1000000UL) /*!< GPIO22_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_HIGH_Pos (23UL) /*!< GPIO21_EDGE_HIGH (Bit 23) */
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_HIGH_Msk (0x800000UL) /*!< GPIO21_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_LOW_Pos (22UL) /*!< GPIO21_EDGE_LOW (Bit 22) */
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_LOW_Msk (0x400000UL) /*!< GPIO21_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_HIGH_Pos (21UL) /*!< GPIO21_LEVEL_HIGH (Bit 21) */
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_HIGH_Msk (0x200000UL) /*!< GPIO21_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_LOW_Pos (20UL) /*!< GPIO21_LEVEL_LOW (Bit 20) */
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_LOW_Msk (0x100000UL) /*!< GPIO21_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_HIGH_Pos (19UL) /*!< GPIO20_EDGE_HIGH (Bit 19) */
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_HIGH_Msk (0x80000UL) /*!< GPIO20_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_LOW_Pos (18UL) /*!< GPIO20_EDGE_LOW (Bit 18) */
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_LOW_Msk (0x40000UL) /*!< GPIO20_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_HIGH_Pos (17UL) /*!< GPIO20_LEVEL_HIGH (Bit 17) */
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_HIGH_Msk (0x20000UL) /*!< GPIO20_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_LOW_Pos (16UL) /*!< GPIO20_LEVEL_LOW (Bit 16) */
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_LOW_Msk (0x10000UL) /*!< GPIO20_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_HIGH_Pos (15UL) /*!< GPIO19_EDGE_HIGH (Bit 15) */
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_HIGH_Msk (0x8000UL) /*!< GPIO19_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_LOW_Pos (14UL) /*!< GPIO19_EDGE_LOW (Bit 14) */
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_LOW_Msk (0x4000UL) /*!< GPIO19_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_HIGH_Pos (13UL) /*!< GPIO19_LEVEL_HIGH (Bit 13) */
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_HIGH_Msk (0x2000UL) /*!< GPIO19_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_LOW_Pos (12UL) /*!< GPIO19_LEVEL_LOW (Bit 12) */
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_LOW_Msk (0x1000UL) /*!< GPIO19_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_HIGH_Pos (11UL) /*!< GPIO18_EDGE_HIGH (Bit 11) */
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_HIGH_Msk (0x800UL) /*!< GPIO18_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_LOW_Pos (10UL) /*!< GPIO18_EDGE_LOW (Bit 10) */
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_LOW_Msk (0x400UL) /*!< GPIO18_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_HIGH_Pos (9UL) /*!< GPIO18_LEVEL_HIGH (Bit 9) */
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_HIGH_Msk (0x200UL) /*!< GPIO18_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_LOW_Pos (8UL) /*!< GPIO18_LEVEL_LOW (Bit 8) */
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_LOW_Msk (0x100UL) /*!< GPIO18_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_HIGH_Pos (7UL) /*!< GPIO17_EDGE_HIGH (Bit 7) */
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_HIGH_Msk (0x80UL) /*!< GPIO17_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_LOW_Pos (6UL) /*!< GPIO17_EDGE_LOW (Bit 6) */
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_LOW_Msk (0x40UL) /*!< GPIO17_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_HIGH_Pos (5UL) /*!< GPIO17_LEVEL_HIGH (Bit 5) */
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_HIGH_Msk (0x20UL) /*!< GPIO17_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_LOW_Pos (4UL) /*!< GPIO17_LEVEL_LOW (Bit 4) */
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_LOW_Msk (0x10UL) /*!< GPIO17_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_HIGH_Pos (3UL) /*!< GPIO16_EDGE_HIGH (Bit 3) */
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_HIGH_Msk (0x8UL) /*!< GPIO16_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_LOW_Pos (2UL) /*!< GPIO16_EDGE_LOW (Bit 2) */
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_LOW_Msk (0x4UL) /*!< GPIO16_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_HIGH_Pos (1UL) /*!< GPIO16_LEVEL_HIGH (Bit 1) */
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_HIGH_Msk (0x2UL) /*!< GPIO16_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_LOW_Pos (0UL) /*!< GPIO16_LEVEL_LOW (Bit 0) */
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_LOW_Msk (0x1UL) /*!< GPIO16_LEVEL_LOW (Bitfield-Mask: 0x01) */
/* ================================================== DORMANT_WAKE_INTF3 =================================================== */
#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_HIGH_Pos (23UL) /*!< GPIO29_EDGE_HIGH (Bit 23) */
#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_HIGH_Msk (0x800000UL) /*!< GPIO29_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_LOW_Pos (22UL) /*!< GPIO29_EDGE_LOW (Bit 22) */
#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_LOW_Msk (0x400000UL) /*!< GPIO29_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_HIGH_Pos (21UL) /*!< GPIO29_LEVEL_HIGH (Bit 21) */
#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_HIGH_Msk (0x200000UL) /*!< GPIO29_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_LOW_Pos (20UL) /*!< GPIO29_LEVEL_LOW (Bit 20) */
#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_LOW_Msk (0x100000UL) /*!< GPIO29_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_HIGH_Pos (19UL) /*!< GPIO28_EDGE_HIGH (Bit 19) */
#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_HIGH_Msk (0x80000UL) /*!< GPIO28_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_LOW_Pos (18UL) /*!< GPIO28_EDGE_LOW (Bit 18) */
#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_LOW_Msk (0x40000UL) /*!< GPIO28_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_HIGH_Pos (17UL) /*!< GPIO28_LEVEL_HIGH (Bit 17) */
#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_HIGH_Msk (0x20000UL) /*!< GPIO28_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_LOW_Pos (16UL) /*!< GPIO28_LEVEL_LOW (Bit 16) */
#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_LOW_Msk (0x10000UL) /*!< GPIO28_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_HIGH_Pos (15UL) /*!< GPIO27_EDGE_HIGH (Bit 15) */
#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_HIGH_Msk (0x8000UL) /*!< GPIO27_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_LOW_Pos (14UL) /*!< GPIO27_EDGE_LOW (Bit 14) */
#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_LOW_Msk (0x4000UL) /*!< GPIO27_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_HIGH_Pos (13UL) /*!< GPIO27_LEVEL_HIGH (Bit 13) */
#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_HIGH_Msk (0x2000UL) /*!< GPIO27_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_LOW_Pos (12UL) /*!< GPIO27_LEVEL_LOW (Bit 12) */
#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_LOW_Msk (0x1000UL) /*!< GPIO27_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_HIGH_Pos (11UL) /*!< GPIO26_EDGE_HIGH (Bit 11) */
#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_HIGH_Msk (0x800UL) /*!< GPIO26_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_LOW_Pos (10UL) /*!< GPIO26_EDGE_LOW (Bit 10) */
#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_LOW_Msk (0x400UL) /*!< GPIO26_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_HIGH_Pos (9UL) /*!< GPIO26_LEVEL_HIGH (Bit 9) */
#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_HIGH_Msk (0x200UL) /*!< GPIO26_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_LOW_Pos (8UL) /*!< GPIO26_LEVEL_LOW (Bit 8) */
#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_LOW_Msk (0x100UL) /*!< GPIO26_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_HIGH_Pos (7UL) /*!< GPIO25_EDGE_HIGH (Bit 7) */
#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_HIGH_Msk (0x80UL) /*!< GPIO25_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_LOW_Pos (6UL) /*!< GPIO25_EDGE_LOW (Bit 6) */
#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_LOW_Msk (0x40UL) /*!< GPIO25_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_HIGH_Pos (5UL) /*!< GPIO25_LEVEL_HIGH (Bit 5) */
#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_HIGH_Msk (0x20UL) /*!< GPIO25_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_LOW_Pos (4UL) /*!< GPIO25_LEVEL_LOW (Bit 4) */
#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_LOW_Msk (0x10UL) /*!< GPIO25_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_HIGH_Pos (3UL) /*!< GPIO24_EDGE_HIGH (Bit 3) */
#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_HIGH_Msk (0x8UL) /*!< GPIO24_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_LOW_Pos (2UL) /*!< GPIO24_EDGE_LOW (Bit 2) */
#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_LOW_Msk (0x4UL) /*!< GPIO24_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_HIGH_Pos (1UL) /*!< GPIO24_LEVEL_HIGH (Bit 1) */
#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_HIGH_Msk (0x2UL) /*!< GPIO24_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_LOW_Pos (0UL) /*!< GPIO24_LEVEL_LOW (Bit 0) */
#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_LOW_Msk (0x1UL) /*!< GPIO24_LEVEL_LOW (Bitfield-Mask: 0x01) */
/* ================================================== DORMANT_WAKE_INTS0 =================================================== */
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_HIGH_Pos (31UL) /*!< GPIO7_EDGE_HIGH (Bit 31) */
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_HIGH_Msk (0x80000000UL) /*!< GPIO7_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_LOW_Pos (30UL) /*!< GPIO7_EDGE_LOW (Bit 30) */
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_LOW_Msk (0x40000000UL) /*!< GPIO7_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_HIGH_Pos (29UL) /*!< GPIO7_LEVEL_HIGH (Bit 29) */
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_HIGH_Msk (0x20000000UL) /*!< GPIO7_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_LOW_Pos (28UL) /*!< GPIO7_LEVEL_LOW (Bit 28) */
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_LOW_Msk (0x10000000UL) /*!< GPIO7_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_HIGH_Pos (27UL) /*!< GPIO6_EDGE_HIGH (Bit 27) */
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_HIGH_Msk (0x8000000UL) /*!< GPIO6_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_LOW_Pos (26UL) /*!< GPIO6_EDGE_LOW (Bit 26) */
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_LOW_Msk (0x4000000UL) /*!< GPIO6_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_HIGH_Pos (25UL) /*!< GPIO6_LEVEL_HIGH (Bit 25) */
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_HIGH_Msk (0x2000000UL) /*!< GPIO6_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_LOW_Pos (24UL) /*!< GPIO6_LEVEL_LOW (Bit 24) */
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_LOW_Msk (0x1000000UL) /*!< GPIO6_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_HIGH_Pos (23UL) /*!< GPIO5_EDGE_HIGH (Bit 23) */
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_HIGH_Msk (0x800000UL) /*!< GPIO5_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_LOW_Pos (22UL) /*!< GPIO5_EDGE_LOW (Bit 22) */
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_LOW_Msk (0x400000UL) /*!< GPIO5_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_HIGH_Pos (21UL) /*!< GPIO5_LEVEL_HIGH (Bit 21) */
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_HIGH_Msk (0x200000UL) /*!< GPIO5_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_LOW_Pos (20UL) /*!< GPIO5_LEVEL_LOW (Bit 20) */
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_LOW_Msk (0x100000UL) /*!< GPIO5_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_HIGH_Pos (19UL) /*!< GPIO4_EDGE_HIGH (Bit 19) */
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_HIGH_Msk (0x80000UL) /*!< GPIO4_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_LOW_Pos (18UL) /*!< GPIO4_EDGE_LOW (Bit 18) */
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_LOW_Msk (0x40000UL) /*!< GPIO4_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_HIGH_Pos (17UL) /*!< GPIO4_LEVEL_HIGH (Bit 17) */
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_HIGH_Msk (0x20000UL) /*!< GPIO4_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_LOW_Pos (16UL) /*!< GPIO4_LEVEL_LOW (Bit 16) */
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_LOW_Msk (0x10000UL) /*!< GPIO4_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_HIGH_Pos (15UL) /*!< GPIO3_EDGE_HIGH (Bit 15) */
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_HIGH_Msk (0x8000UL) /*!< GPIO3_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_LOW_Pos (14UL) /*!< GPIO3_EDGE_LOW (Bit 14) */
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_LOW_Msk (0x4000UL) /*!< GPIO3_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_HIGH_Pos (13UL) /*!< GPIO3_LEVEL_HIGH (Bit 13) */
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_HIGH_Msk (0x2000UL) /*!< GPIO3_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_LOW_Pos (12UL) /*!< GPIO3_LEVEL_LOW (Bit 12) */
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_LOW_Msk (0x1000UL) /*!< GPIO3_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_HIGH_Pos (11UL) /*!< GPIO2_EDGE_HIGH (Bit 11) */
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_HIGH_Msk (0x800UL) /*!< GPIO2_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_LOW_Pos (10UL) /*!< GPIO2_EDGE_LOW (Bit 10) */
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_LOW_Msk (0x400UL) /*!< GPIO2_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_HIGH_Pos (9UL) /*!< GPIO2_LEVEL_HIGH (Bit 9) */
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_HIGH_Msk (0x200UL) /*!< GPIO2_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_LOW_Pos (8UL) /*!< GPIO2_LEVEL_LOW (Bit 8) */
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_LOW_Msk (0x100UL) /*!< GPIO2_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_HIGH_Pos (7UL) /*!< GPIO1_EDGE_HIGH (Bit 7) */
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_HIGH_Msk (0x80UL) /*!< GPIO1_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_LOW_Pos (6UL) /*!< GPIO1_EDGE_LOW (Bit 6) */
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_LOW_Msk (0x40UL) /*!< GPIO1_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_HIGH_Pos (5UL) /*!< GPIO1_LEVEL_HIGH (Bit 5) */
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_HIGH_Msk (0x20UL) /*!< GPIO1_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_LOW_Pos (4UL) /*!< GPIO1_LEVEL_LOW (Bit 4) */
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_LOW_Msk (0x10UL) /*!< GPIO1_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_HIGH_Pos (3UL) /*!< GPIO0_EDGE_HIGH (Bit 3) */
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_HIGH_Msk (0x8UL) /*!< GPIO0_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_LOW_Pos (2UL) /*!< GPIO0_EDGE_LOW (Bit 2) */
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_LOW_Msk (0x4UL) /*!< GPIO0_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_HIGH_Pos (1UL) /*!< GPIO0_LEVEL_HIGH (Bit 1) */
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_HIGH_Msk (0x2UL) /*!< GPIO0_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_LOW_Pos (0UL) /*!< GPIO0_LEVEL_LOW (Bit 0) */
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_LOW_Msk (0x1UL) /*!< GPIO0_LEVEL_LOW (Bitfield-Mask: 0x01) */
/* ================================================== DORMANT_WAKE_INTS1 =================================================== */
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_HIGH_Pos (31UL) /*!< GPIO15_EDGE_HIGH (Bit 31) */
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_HIGH_Msk (0x80000000UL) /*!< GPIO15_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_LOW_Pos (30UL) /*!< GPIO15_EDGE_LOW (Bit 30) */
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_LOW_Msk (0x40000000UL) /*!< GPIO15_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_HIGH_Pos (29UL) /*!< GPIO15_LEVEL_HIGH (Bit 29) */
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_HIGH_Msk (0x20000000UL) /*!< GPIO15_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_LOW_Pos (28UL) /*!< GPIO15_LEVEL_LOW (Bit 28) */
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_LOW_Msk (0x10000000UL) /*!< GPIO15_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_HIGH_Pos (27UL) /*!< GPIO14_EDGE_HIGH (Bit 27) */
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_HIGH_Msk (0x8000000UL) /*!< GPIO14_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_LOW_Pos (26UL) /*!< GPIO14_EDGE_LOW (Bit 26) */
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_LOW_Msk (0x4000000UL) /*!< GPIO14_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_HIGH_Pos (25UL) /*!< GPIO14_LEVEL_HIGH (Bit 25) */
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_HIGH_Msk (0x2000000UL) /*!< GPIO14_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_LOW_Pos (24UL) /*!< GPIO14_LEVEL_LOW (Bit 24) */
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_LOW_Msk (0x1000000UL) /*!< GPIO14_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_HIGH_Pos (23UL) /*!< GPIO13_EDGE_HIGH (Bit 23) */
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_HIGH_Msk (0x800000UL) /*!< GPIO13_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_LOW_Pos (22UL) /*!< GPIO13_EDGE_LOW (Bit 22) */
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_LOW_Msk (0x400000UL) /*!< GPIO13_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_HIGH_Pos (21UL) /*!< GPIO13_LEVEL_HIGH (Bit 21) */
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_HIGH_Msk (0x200000UL) /*!< GPIO13_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_LOW_Pos (20UL) /*!< GPIO13_LEVEL_LOW (Bit 20) */
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_LOW_Msk (0x100000UL) /*!< GPIO13_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_HIGH_Pos (19UL) /*!< GPIO12_EDGE_HIGH (Bit 19) */
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_HIGH_Msk (0x80000UL) /*!< GPIO12_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_LOW_Pos (18UL) /*!< GPIO12_EDGE_LOW (Bit 18) */
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_LOW_Msk (0x40000UL) /*!< GPIO12_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_HIGH_Pos (17UL) /*!< GPIO12_LEVEL_HIGH (Bit 17) */
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_HIGH_Msk (0x20000UL) /*!< GPIO12_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_LOW_Pos (16UL) /*!< GPIO12_LEVEL_LOW (Bit 16) */
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_LOW_Msk (0x10000UL) /*!< GPIO12_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_HIGH_Pos (15UL) /*!< GPIO11_EDGE_HIGH (Bit 15) */
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_HIGH_Msk (0x8000UL) /*!< GPIO11_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_LOW_Pos (14UL) /*!< GPIO11_EDGE_LOW (Bit 14) */
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_LOW_Msk (0x4000UL) /*!< GPIO11_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_HIGH_Pos (13UL) /*!< GPIO11_LEVEL_HIGH (Bit 13) */
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_HIGH_Msk (0x2000UL) /*!< GPIO11_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_LOW_Pos (12UL) /*!< GPIO11_LEVEL_LOW (Bit 12) */
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_LOW_Msk (0x1000UL) /*!< GPIO11_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_HIGH_Pos (11UL) /*!< GPIO10_EDGE_HIGH (Bit 11) */
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_HIGH_Msk (0x800UL) /*!< GPIO10_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_LOW_Pos (10UL) /*!< GPIO10_EDGE_LOW (Bit 10) */
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_LOW_Msk (0x400UL) /*!< GPIO10_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_HIGH_Pos (9UL) /*!< GPIO10_LEVEL_HIGH (Bit 9) */
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_HIGH_Msk (0x200UL) /*!< GPIO10_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_LOW_Pos (8UL) /*!< GPIO10_LEVEL_LOW (Bit 8) */
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_LOW_Msk (0x100UL) /*!< GPIO10_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_HIGH_Pos (7UL) /*!< GPIO9_EDGE_HIGH (Bit 7) */
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_HIGH_Msk (0x80UL) /*!< GPIO9_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_LOW_Pos (6UL) /*!< GPIO9_EDGE_LOW (Bit 6) */
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_LOW_Msk (0x40UL) /*!< GPIO9_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_HIGH_Pos (5UL) /*!< GPIO9_LEVEL_HIGH (Bit 5) */
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_HIGH_Msk (0x20UL) /*!< GPIO9_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_LOW_Pos (4UL) /*!< GPIO9_LEVEL_LOW (Bit 4) */
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_LOW_Msk (0x10UL) /*!< GPIO9_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_HIGH_Pos (3UL) /*!< GPIO8_EDGE_HIGH (Bit 3) */
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_HIGH_Msk (0x8UL) /*!< GPIO8_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_LOW_Pos (2UL) /*!< GPIO8_EDGE_LOW (Bit 2) */
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_LOW_Msk (0x4UL) /*!< GPIO8_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_HIGH_Pos (1UL) /*!< GPIO8_LEVEL_HIGH (Bit 1) */
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_HIGH_Msk (0x2UL) /*!< GPIO8_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_LOW_Pos (0UL) /*!< GPIO8_LEVEL_LOW (Bit 0) */
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_LOW_Msk (0x1UL) /*!< GPIO8_LEVEL_LOW (Bitfield-Mask: 0x01) */
/* ================================================== DORMANT_WAKE_INTS2 =================================================== */
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_HIGH_Pos (31UL) /*!< GPIO23_EDGE_HIGH (Bit 31) */
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_HIGH_Msk (0x80000000UL) /*!< GPIO23_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_LOW_Pos (30UL) /*!< GPIO23_EDGE_LOW (Bit 30) */
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_LOW_Msk (0x40000000UL) /*!< GPIO23_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_HIGH_Pos (29UL) /*!< GPIO23_LEVEL_HIGH (Bit 29) */
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_HIGH_Msk (0x20000000UL) /*!< GPIO23_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_LOW_Pos (28UL) /*!< GPIO23_LEVEL_LOW (Bit 28) */
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_LOW_Msk (0x10000000UL) /*!< GPIO23_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_HIGH_Pos (27UL) /*!< GPIO22_EDGE_HIGH (Bit 27) */
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_HIGH_Msk (0x8000000UL) /*!< GPIO22_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_LOW_Pos (26UL) /*!< GPIO22_EDGE_LOW (Bit 26) */
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_LOW_Msk (0x4000000UL) /*!< GPIO22_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_HIGH_Pos (25UL) /*!< GPIO22_LEVEL_HIGH (Bit 25) */
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_HIGH_Msk (0x2000000UL) /*!< GPIO22_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_LOW_Pos (24UL) /*!< GPIO22_LEVEL_LOW (Bit 24) */
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_LOW_Msk (0x1000000UL) /*!< GPIO22_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_HIGH_Pos (23UL) /*!< GPIO21_EDGE_HIGH (Bit 23) */
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_HIGH_Msk (0x800000UL) /*!< GPIO21_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_LOW_Pos (22UL) /*!< GPIO21_EDGE_LOW (Bit 22) */
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_LOW_Msk (0x400000UL) /*!< GPIO21_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_HIGH_Pos (21UL) /*!< GPIO21_LEVEL_HIGH (Bit 21) */
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_HIGH_Msk (0x200000UL) /*!< GPIO21_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_LOW_Pos (20UL) /*!< GPIO21_LEVEL_LOW (Bit 20) */
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_LOW_Msk (0x100000UL) /*!< GPIO21_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_HIGH_Pos (19UL) /*!< GPIO20_EDGE_HIGH (Bit 19) */
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_HIGH_Msk (0x80000UL) /*!< GPIO20_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_LOW_Pos (18UL) /*!< GPIO20_EDGE_LOW (Bit 18) */
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_LOW_Msk (0x40000UL) /*!< GPIO20_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_HIGH_Pos (17UL) /*!< GPIO20_LEVEL_HIGH (Bit 17) */
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_HIGH_Msk (0x20000UL) /*!< GPIO20_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_LOW_Pos (16UL) /*!< GPIO20_LEVEL_LOW (Bit 16) */
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_LOW_Msk (0x10000UL) /*!< GPIO20_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_HIGH_Pos (15UL) /*!< GPIO19_EDGE_HIGH (Bit 15) */
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_HIGH_Msk (0x8000UL) /*!< GPIO19_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_LOW_Pos (14UL) /*!< GPIO19_EDGE_LOW (Bit 14) */
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_LOW_Msk (0x4000UL) /*!< GPIO19_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_HIGH_Pos (13UL) /*!< GPIO19_LEVEL_HIGH (Bit 13) */
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_HIGH_Msk (0x2000UL) /*!< GPIO19_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_LOW_Pos (12UL) /*!< GPIO19_LEVEL_LOW (Bit 12) */
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_LOW_Msk (0x1000UL) /*!< GPIO19_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_HIGH_Pos (11UL) /*!< GPIO18_EDGE_HIGH (Bit 11) */
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_HIGH_Msk (0x800UL) /*!< GPIO18_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_LOW_Pos (10UL) /*!< GPIO18_EDGE_LOW (Bit 10) */
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_LOW_Msk (0x400UL) /*!< GPIO18_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_HIGH_Pos (9UL) /*!< GPIO18_LEVEL_HIGH (Bit 9) */
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_HIGH_Msk (0x200UL) /*!< GPIO18_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_LOW_Pos (8UL) /*!< GPIO18_LEVEL_LOW (Bit 8) */
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_LOW_Msk (0x100UL) /*!< GPIO18_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_HIGH_Pos (7UL) /*!< GPIO17_EDGE_HIGH (Bit 7) */
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_HIGH_Msk (0x80UL) /*!< GPIO17_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_LOW_Pos (6UL) /*!< GPIO17_EDGE_LOW (Bit 6) */
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_LOW_Msk (0x40UL) /*!< GPIO17_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_HIGH_Pos (5UL) /*!< GPIO17_LEVEL_HIGH (Bit 5) */
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_HIGH_Msk (0x20UL) /*!< GPIO17_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_LOW_Pos (4UL) /*!< GPIO17_LEVEL_LOW (Bit 4) */
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_LOW_Msk (0x10UL) /*!< GPIO17_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_HIGH_Pos (3UL) /*!< GPIO16_EDGE_HIGH (Bit 3) */
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_HIGH_Msk (0x8UL) /*!< GPIO16_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_LOW_Pos (2UL) /*!< GPIO16_EDGE_LOW (Bit 2) */
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_LOW_Msk (0x4UL) /*!< GPIO16_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_HIGH_Pos (1UL) /*!< GPIO16_LEVEL_HIGH (Bit 1) */
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_HIGH_Msk (0x2UL) /*!< GPIO16_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_LOW_Pos (0UL) /*!< GPIO16_LEVEL_LOW (Bit 0) */
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_LOW_Msk (0x1UL) /*!< GPIO16_LEVEL_LOW (Bitfield-Mask: 0x01) */
/* ================================================== DORMANT_WAKE_INTS3 =================================================== */
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_HIGH_Pos (23UL) /*!< GPIO29_EDGE_HIGH (Bit 23) */
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_HIGH_Msk (0x800000UL) /*!< GPIO29_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_LOW_Pos (22UL) /*!< GPIO29_EDGE_LOW (Bit 22) */
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_LOW_Msk (0x400000UL) /*!< GPIO29_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_HIGH_Pos (21UL) /*!< GPIO29_LEVEL_HIGH (Bit 21) */
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_HIGH_Msk (0x200000UL) /*!< GPIO29_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_LOW_Pos (20UL) /*!< GPIO29_LEVEL_LOW (Bit 20) */
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_LOW_Msk (0x100000UL) /*!< GPIO29_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_HIGH_Pos (19UL) /*!< GPIO28_EDGE_HIGH (Bit 19) */
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_HIGH_Msk (0x80000UL) /*!< GPIO28_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_LOW_Pos (18UL) /*!< GPIO28_EDGE_LOW (Bit 18) */
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_LOW_Msk (0x40000UL) /*!< GPIO28_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_HIGH_Pos (17UL) /*!< GPIO28_LEVEL_HIGH (Bit 17) */
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_HIGH_Msk (0x20000UL) /*!< GPIO28_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_LOW_Pos (16UL) /*!< GPIO28_LEVEL_LOW (Bit 16) */
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_LOW_Msk (0x10000UL) /*!< GPIO28_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_HIGH_Pos (15UL) /*!< GPIO27_EDGE_HIGH (Bit 15) */
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_HIGH_Msk (0x8000UL) /*!< GPIO27_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_LOW_Pos (14UL) /*!< GPIO27_EDGE_LOW (Bit 14) */
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_LOW_Msk (0x4000UL) /*!< GPIO27_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_HIGH_Pos (13UL) /*!< GPIO27_LEVEL_HIGH (Bit 13) */
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_HIGH_Msk (0x2000UL) /*!< GPIO27_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_LOW_Pos (12UL) /*!< GPIO27_LEVEL_LOW (Bit 12) */
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_LOW_Msk (0x1000UL) /*!< GPIO27_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_HIGH_Pos (11UL) /*!< GPIO26_EDGE_HIGH (Bit 11) */
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_HIGH_Msk (0x800UL) /*!< GPIO26_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_LOW_Pos (10UL) /*!< GPIO26_EDGE_LOW (Bit 10) */
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_LOW_Msk (0x400UL) /*!< GPIO26_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_HIGH_Pos (9UL) /*!< GPIO26_LEVEL_HIGH (Bit 9) */
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_HIGH_Msk (0x200UL) /*!< GPIO26_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_LOW_Pos (8UL) /*!< GPIO26_LEVEL_LOW (Bit 8) */
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_LOW_Msk (0x100UL) /*!< GPIO26_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_HIGH_Pos (7UL) /*!< GPIO25_EDGE_HIGH (Bit 7) */
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_HIGH_Msk (0x80UL) /*!< GPIO25_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_LOW_Pos (6UL) /*!< GPIO25_EDGE_LOW (Bit 6) */
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_LOW_Msk (0x40UL) /*!< GPIO25_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_HIGH_Pos (5UL) /*!< GPIO25_LEVEL_HIGH (Bit 5) */
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_HIGH_Msk (0x20UL) /*!< GPIO25_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_LOW_Pos (4UL) /*!< GPIO25_LEVEL_LOW (Bit 4) */
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_LOW_Msk (0x10UL) /*!< GPIO25_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_HIGH_Pos (3UL) /*!< GPIO24_EDGE_HIGH (Bit 3) */
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_HIGH_Msk (0x8UL) /*!< GPIO24_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_LOW_Pos (2UL) /*!< GPIO24_EDGE_LOW (Bit 2) */
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_LOW_Msk (0x4UL) /*!< GPIO24_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_HIGH_Pos (1UL) /*!< GPIO24_LEVEL_HIGH (Bit 1) */
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_HIGH_Msk (0x2UL) /*!< GPIO24_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_LOW_Pos (0UL) /*!< GPIO24_LEVEL_LOW (Bit 0) */
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_LOW_Msk (0x1UL) /*!< GPIO24_LEVEL_LOW (Bitfield-Mask: 0x01) */
/* =========================================================================================================================== */
/* ================ IO_QSPI ================ */
/* =========================================================================================================================== */
/* ================================================= GPIO_QSPI_SCLK_STATUS ================================================= */
#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQTOPROC_Pos (26UL) /*!< IRQTOPROC (Bit 26) */
#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQTOPROC_Msk (0x4000000UL) /*!< IRQTOPROC (Bitfield-Mask: 0x01) */
#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQFROMPAD_Pos (24UL) /*!< IRQFROMPAD (Bit 24) */
#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQFROMPAD_Msk (0x1000000UL) /*!< IRQFROMPAD (Bitfield-Mask: 0x01) */
#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INTOPERI_Pos (19UL) /*!< INTOPERI (Bit 19) */
#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INTOPERI_Msk (0x80000UL) /*!< INTOPERI (Bitfield-Mask: 0x01) */
#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INFROMPAD_Pos (17UL) /*!< INFROMPAD (Bit 17) */
#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INFROMPAD_Msk (0x20000UL) /*!< INFROMPAD (Bitfield-Mask: 0x01) */
#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OETOPAD_Pos (13UL) /*!< OETOPAD (Bit 13) */
#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OETOPAD_Msk (0x2000UL) /*!< OETOPAD (Bitfield-Mask: 0x01) */
#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OEFROMPERI_Pos (12UL) /*!< OEFROMPERI (Bit 12) */
#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OEFROMPERI_Msk (0x1000UL) /*!< OEFROMPERI (Bitfield-Mask: 0x01) */
#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTTOPAD_Pos (9UL) /*!< OUTTOPAD (Bit 9) */
#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTTOPAD_Msk (0x200UL) /*!< OUTTOPAD (Bitfield-Mask: 0x01) */
#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTFROMPERI_Pos (8UL) /*!< OUTFROMPERI (Bit 8) */
#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTFROMPERI_Msk (0x100UL) /*!< OUTFROMPERI (Bitfield-Mask: 0x01) */
/* ================================================== GPIO_QSPI_SCLK_CTRL ================================================== */
#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_Pos (28UL) /*!< IRQOVER (Bit 28) */
#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_Msk (0x30000000UL) /*!< IRQOVER (Bitfield-Mask: 0x03) */
#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_Pos (16UL) /*!< INOVER (Bit 16) */
#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_Msk (0x30000UL) /*!< INOVER (Bitfield-Mask: 0x03) */
#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_Pos (12UL) /*!< OEOVER (Bit 12) */
#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_Msk (0x3000UL) /*!< OEOVER (Bitfield-Mask: 0x03) */
#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_Pos (8UL) /*!< OUTOVER (Bit 8) */
#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_Msk (0x300UL) /*!< OUTOVER (Bitfield-Mask: 0x03) */
#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_Pos (0UL) /*!< FUNCSEL (Bit 0) */
#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_Msk (0x1fUL) /*!< FUNCSEL (Bitfield-Mask: 0x1f) */
/* ================================================== GPIO_QSPI_SS_STATUS ================================================== */
#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQTOPROC_Pos (26UL) /*!< IRQTOPROC (Bit 26) */
#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQTOPROC_Msk (0x4000000UL) /*!< IRQTOPROC (Bitfield-Mask: 0x01) */
#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQFROMPAD_Pos (24UL) /*!< IRQFROMPAD (Bit 24) */
#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQFROMPAD_Msk (0x1000000UL) /*!< IRQFROMPAD (Bitfield-Mask: 0x01) */
#define IO_QSPI_GPIO_QSPI_SS_STATUS_INTOPERI_Pos (19UL) /*!< INTOPERI (Bit 19) */
#define IO_QSPI_GPIO_QSPI_SS_STATUS_INTOPERI_Msk (0x80000UL) /*!< INTOPERI (Bitfield-Mask: 0x01) */
#define IO_QSPI_GPIO_QSPI_SS_STATUS_INFROMPAD_Pos (17UL) /*!< INFROMPAD (Bit 17) */
#define IO_QSPI_GPIO_QSPI_SS_STATUS_INFROMPAD_Msk (0x20000UL) /*!< INFROMPAD (Bitfield-Mask: 0x01) */
#define IO_QSPI_GPIO_QSPI_SS_STATUS_OETOPAD_Pos (13UL) /*!< OETOPAD (Bit 13) */
#define IO_QSPI_GPIO_QSPI_SS_STATUS_OETOPAD_Msk (0x2000UL) /*!< OETOPAD (Bitfield-Mask: 0x01) */
#define IO_QSPI_GPIO_QSPI_SS_STATUS_OEFROMPERI_Pos (12UL) /*!< OEFROMPERI (Bit 12) */
#define IO_QSPI_GPIO_QSPI_SS_STATUS_OEFROMPERI_Msk (0x1000UL) /*!< OEFROMPERI (Bitfield-Mask: 0x01) */
#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTTOPAD_Pos (9UL) /*!< OUTTOPAD (Bit 9) */
#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTTOPAD_Msk (0x200UL) /*!< OUTTOPAD (Bitfield-Mask: 0x01) */
#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTFROMPERI_Pos (8UL) /*!< OUTFROMPERI (Bit 8) */
#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTFROMPERI_Msk (0x100UL) /*!< OUTFROMPERI (Bitfield-Mask: 0x01) */
/* =================================================== GPIO_QSPI_SS_CTRL =================================================== */
#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_Pos (28UL) /*!< IRQOVER (Bit 28) */
#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_Msk (0x30000000UL) /*!< IRQOVER (Bitfield-Mask: 0x03) */
#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_Pos (16UL) /*!< INOVER (Bit 16) */
#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_Msk (0x30000UL) /*!< INOVER (Bitfield-Mask: 0x03) */
#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_Pos (12UL) /*!< OEOVER (Bit 12) */
#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_Msk (0x3000UL) /*!< OEOVER (Bitfield-Mask: 0x03) */
#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_Pos (8UL) /*!< OUTOVER (Bit 8) */
#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_Msk (0x300UL) /*!< OUTOVER (Bitfield-Mask: 0x03) */
#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_Pos (0UL) /*!< FUNCSEL (Bit 0) */
#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_Msk (0x1fUL) /*!< FUNCSEL (Bitfield-Mask: 0x1f) */
/* ================================================= GPIO_QSPI_SD0_STATUS ================================================== */
#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQTOPROC_Pos (26UL) /*!< IRQTOPROC (Bit 26) */
#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQTOPROC_Msk (0x4000000UL) /*!< IRQTOPROC (Bitfield-Mask: 0x01) */
#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQFROMPAD_Pos (24UL) /*!< IRQFROMPAD (Bit 24) */
#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQFROMPAD_Msk (0x1000000UL) /*!< IRQFROMPAD (Bitfield-Mask: 0x01) */
#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INTOPERI_Pos (19UL) /*!< INTOPERI (Bit 19) */
#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INTOPERI_Msk (0x80000UL) /*!< INTOPERI (Bitfield-Mask: 0x01) */
#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INFROMPAD_Pos (17UL) /*!< INFROMPAD (Bit 17) */
#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INFROMPAD_Msk (0x20000UL) /*!< INFROMPAD (Bitfield-Mask: 0x01) */
#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OETOPAD_Pos (13UL) /*!< OETOPAD (Bit 13) */
#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OETOPAD_Msk (0x2000UL) /*!< OETOPAD (Bitfield-Mask: 0x01) */
#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OEFROMPERI_Pos (12UL) /*!< OEFROMPERI (Bit 12) */
#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OEFROMPERI_Msk (0x1000UL) /*!< OEFROMPERI (Bitfield-Mask: 0x01) */
#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTTOPAD_Pos (9UL) /*!< OUTTOPAD (Bit 9) */
#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTTOPAD_Msk (0x200UL) /*!< OUTTOPAD (Bitfield-Mask: 0x01) */
#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTFROMPERI_Pos (8UL) /*!< OUTFROMPERI (Bit 8) */
#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTFROMPERI_Msk (0x100UL) /*!< OUTFROMPERI (Bitfield-Mask: 0x01) */
/* ================================================== GPIO_QSPI_SD0_CTRL =================================================== */
#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_Pos (28UL) /*!< IRQOVER (Bit 28) */
#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_Msk (0x30000000UL) /*!< IRQOVER (Bitfield-Mask: 0x03) */
#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_Pos (16UL) /*!< INOVER (Bit 16) */
#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_Msk (0x30000UL) /*!< INOVER (Bitfield-Mask: 0x03) */
#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_Pos (12UL) /*!< OEOVER (Bit 12) */
#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_Msk (0x3000UL) /*!< OEOVER (Bitfield-Mask: 0x03) */
#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_Pos (8UL) /*!< OUTOVER (Bit 8) */
#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_Msk (0x300UL) /*!< OUTOVER (Bitfield-Mask: 0x03) */
#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_Pos (0UL) /*!< FUNCSEL (Bit 0) */
#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_Msk (0x1fUL) /*!< FUNCSEL (Bitfield-Mask: 0x1f) */
/* ================================================= GPIO_QSPI_SD1_STATUS ================================================== */
#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQTOPROC_Pos (26UL) /*!< IRQTOPROC (Bit 26) */
#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQTOPROC_Msk (0x4000000UL) /*!< IRQTOPROC (Bitfield-Mask: 0x01) */
#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQFROMPAD_Pos (24UL) /*!< IRQFROMPAD (Bit 24) */
#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQFROMPAD_Msk (0x1000000UL) /*!< IRQFROMPAD (Bitfield-Mask: 0x01) */
#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INTOPERI_Pos (19UL) /*!< INTOPERI (Bit 19) */
#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INTOPERI_Msk (0x80000UL) /*!< INTOPERI (Bitfield-Mask: 0x01) */
#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INFROMPAD_Pos (17UL) /*!< INFROMPAD (Bit 17) */
#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INFROMPAD_Msk (0x20000UL) /*!< INFROMPAD (Bitfield-Mask: 0x01) */
#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OETOPAD_Pos (13UL) /*!< OETOPAD (Bit 13) */
#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OETOPAD_Msk (0x2000UL) /*!< OETOPAD (Bitfield-Mask: 0x01) */
#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OEFROMPERI_Pos (12UL) /*!< OEFROMPERI (Bit 12) */
#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OEFROMPERI_Msk (0x1000UL) /*!< OEFROMPERI (Bitfield-Mask: 0x01) */
#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTTOPAD_Pos (9UL) /*!< OUTTOPAD (Bit 9) */
#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTTOPAD_Msk (0x200UL) /*!< OUTTOPAD (Bitfield-Mask: 0x01) */
#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTFROMPERI_Pos (8UL) /*!< OUTFROMPERI (Bit 8) */
#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTFROMPERI_Msk (0x100UL) /*!< OUTFROMPERI (Bitfield-Mask: 0x01) */
/* ================================================== GPIO_QSPI_SD1_CTRL =================================================== */
#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_Pos (28UL) /*!< IRQOVER (Bit 28) */
#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_Msk (0x30000000UL) /*!< IRQOVER (Bitfield-Mask: 0x03) */
#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_Pos (16UL) /*!< INOVER (Bit 16) */
#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_Msk (0x30000UL) /*!< INOVER (Bitfield-Mask: 0x03) */
#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_Pos (12UL) /*!< OEOVER (Bit 12) */
#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_Msk (0x3000UL) /*!< OEOVER (Bitfield-Mask: 0x03) */
#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_Pos (8UL) /*!< OUTOVER (Bit 8) */
#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_Msk (0x300UL) /*!< OUTOVER (Bitfield-Mask: 0x03) */
#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_Pos (0UL) /*!< FUNCSEL (Bit 0) */
#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_Msk (0x1fUL) /*!< FUNCSEL (Bitfield-Mask: 0x1f) */
/* ================================================= GPIO_QSPI_SD2_STATUS ================================================== */
#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQTOPROC_Pos (26UL) /*!< IRQTOPROC (Bit 26) */
#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQTOPROC_Msk (0x4000000UL) /*!< IRQTOPROC (Bitfield-Mask: 0x01) */
#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQFROMPAD_Pos (24UL) /*!< IRQFROMPAD (Bit 24) */
#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQFROMPAD_Msk (0x1000000UL) /*!< IRQFROMPAD (Bitfield-Mask: 0x01) */
#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INTOPERI_Pos (19UL) /*!< INTOPERI (Bit 19) */
#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INTOPERI_Msk (0x80000UL) /*!< INTOPERI (Bitfield-Mask: 0x01) */
#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INFROMPAD_Pos (17UL) /*!< INFROMPAD (Bit 17) */
#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INFROMPAD_Msk (0x20000UL) /*!< INFROMPAD (Bitfield-Mask: 0x01) */
#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OETOPAD_Pos (13UL) /*!< OETOPAD (Bit 13) */
#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OETOPAD_Msk (0x2000UL) /*!< OETOPAD (Bitfield-Mask: 0x01) */
#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OEFROMPERI_Pos (12UL) /*!< OEFROMPERI (Bit 12) */
#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OEFROMPERI_Msk (0x1000UL) /*!< OEFROMPERI (Bitfield-Mask: 0x01) */
#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTTOPAD_Pos (9UL) /*!< OUTTOPAD (Bit 9) */
#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTTOPAD_Msk (0x200UL) /*!< OUTTOPAD (Bitfield-Mask: 0x01) */
#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTFROMPERI_Pos (8UL) /*!< OUTFROMPERI (Bit 8) */
#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTFROMPERI_Msk (0x100UL) /*!< OUTFROMPERI (Bitfield-Mask: 0x01) */
/* ================================================== GPIO_QSPI_SD2_CTRL =================================================== */
#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_Pos (28UL) /*!< IRQOVER (Bit 28) */
#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_Msk (0x30000000UL) /*!< IRQOVER (Bitfield-Mask: 0x03) */
#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_Pos (16UL) /*!< INOVER (Bit 16) */
#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_Msk (0x30000UL) /*!< INOVER (Bitfield-Mask: 0x03) */
#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_Pos (12UL) /*!< OEOVER (Bit 12) */
#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_Msk (0x3000UL) /*!< OEOVER (Bitfield-Mask: 0x03) */
#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_Pos (8UL) /*!< OUTOVER (Bit 8) */
#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_Msk (0x300UL) /*!< OUTOVER (Bitfield-Mask: 0x03) */
#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_Pos (0UL) /*!< FUNCSEL (Bit 0) */
#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_Msk (0x1fUL) /*!< FUNCSEL (Bitfield-Mask: 0x1f) */
/* ================================================= GPIO_QSPI_SD3_STATUS ================================================== */
#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQTOPROC_Pos (26UL) /*!< IRQTOPROC (Bit 26) */
#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQTOPROC_Msk (0x4000000UL) /*!< IRQTOPROC (Bitfield-Mask: 0x01) */
#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQFROMPAD_Pos (24UL) /*!< IRQFROMPAD (Bit 24) */
#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQFROMPAD_Msk (0x1000000UL) /*!< IRQFROMPAD (Bitfield-Mask: 0x01) */
#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INTOPERI_Pos (19UL) /*!< INTOPERI (Bit 19) */
#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INTOPERI_Msk (0x80000UL) /*!< INTOPERI (Bitfield-Mask: 0x01) */
#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INFROMPAD_Pos (17UL) /*!< INFROMPAD (Bit 17) */
#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INFROMPAD_Msk (0x20000UL) /*!< INFROMPAD (Bitfield-Mask: 0x01) */
#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OETOPAD_Pos (13UL) /*!< OETOPAD (Bit 13) */
#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OETOPAD_Msk (0x2000UL) /*!< OETOPAD (Bitfield-Mask: 0x01) */
#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OEFROMPERI_Pos (12UL) /*!< OEFROMPERI (Bit 12) */
#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OEFROMPERI_Msk (0x1000UL) /*!< OEFROMPERI (Bitfield-Mask: 0x01) */
#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTTOPAD_Pos (9UL) /*!< OUTTOPAD (Bit 9) */
#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTTOPAD_Msk (0x200UL) /*!< OUTTOPAD (Bitfield-Mask: 0x01) */
#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTFROMPERI_Pos (8UL) /*!< OUTFROMPERI (Bit 8) */
#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTFROMPERI_Msk (0x100UL) /*!< OUTFROMPERI (Bitfield-Mask: 0x01) */
/* ================================================== GPIO_QSPI_SD3_CTRL =================================================== */
#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_Pos (28UL) /*!< IRQOVER (Bit 28) */
#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_Msk (0x30000000UL) /*!< IRQOVER (Bitfield-Mask: 0x03) */
#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_Pos (16UL) /*!< INOVER (Bit 16) */
#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_Msk (0x30000UL) /*!< INOVER (Bitfield-Mask: 0x03) */
#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_Pos (12UL) /*!< OEOVER (Bit 12) */
#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_Msk (0x3000UL) /*!< OEOVER (Bitfield-Mask: 0x03) */
#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_Pos (8UL) /*!< OUTOVER (Bit 8) */
#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_Msk (0x300UL) /*!< OUTOVER (Bitfield-Mask: 0x03) */
#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_Pos (0UL) /*!< FUNCSEL (Bit 0) */
#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_Msk (0x1fUL) /*!< FUNCSEL (Bitfield-Mask: 0x1f) */
/* ========================================================= INTR ========================================================== */
#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_HIGH_Pos (23UL) /*!< GPIO_QSPI_SD3_EDGE_HIGH (Bit 23) */
#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_HIGH_Msk (0x800000UL) /*!< GPIO_QSPI_SD3_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_LOW_Pos (22UL) /*!< GPIO_QSPI_SD3_EDGE_LOW (Bit 22) */
#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_LOW_Msk (0x400000UL) /*!< GPIO_QSPI_SD3_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_HIGH_Pos (21UL) /*!< GPIO_QSPI_SD3_LEVEL_HIGH (Bit 21) */
#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_HIGH_Msk (0x200000UL) /*!< GPIO_QSPI_SD3_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_LOW_Pos (20UL) /*!< GPIO_QSPI_SD3_LEVEL_LOW (Bit 20) */
#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_LOW_Msk (0x100000UL) /*!< GPIO_QSPI_SD3_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_HIGH_Pos (19UL) /*!< GPIO_QSPI_SD2_EDGE_HIGH (Bit 19) */
#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_HIGH_Msk (0x80000UL) /*!< GPIO_QSPI_SD2_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_LOW_Pos (18UL) /*!< GPIO_QSPI_SD2_EDGE_LOW (Bit 18) */
#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_LOW_Msk (0x40000UL) /*!< GPIO_QSPI_SD2_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_HIGH_Pos (17UL) /*!< GPIO_QSPI_SD2_LEVEL_HIGH (Bit 17) */
#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_HIGH_Msk (0x20000UL) /*!< GPIO_QSPI_SD2_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_LOW_Pos (16UL) /*!< GPIO_QSPI_SD2_LEVEL_LOW (Bit 16) */
#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_LOW_Msk (0x10000UL) /*!< GPIO_QSPI_SD2_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_HIGH_Pos (15UL) /*!< GPIO_QSPI_SD1_EDGE_HIGH (Bit 15) */
#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_HIGH_Msk (0x8000UL) /*!< GPIO_QSPI_SD1_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_LOW_Pos (14UL) /*!< GPIO_QSPI_SD1_EDGE_LOW (Bit 14) */
#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_LOW_Msk (0x4000UL) /*!< GPIO_QSPI_SD1_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_HIGH_Pos (13UL) /*!< GPIO_QSPI_SD1_LEVEL_HIGH (Bit 13) */
#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_HIGH_Msk (0x2000UL) /*!< GPIO_QSPI_SD1_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_LOW_Pos (12UL) /*!< GPIO_QSPI_SD1_LEVEL_LOW (Bit 12) */
#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_LOW_Msk (0x1000UL) /*!< GPIO_QSPI_SD1_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_HIGH_Pos (11UL) /*!< GPIO_QSPI_SD0_EDGE_HIGH (Bit 11) */
#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_HIGH_Msk (0x800UL) /*!< GPIO_QSPI_SD0_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_LOW_Pos (10UL) /*!< GPIO_QSPI_SD0_EDGE_LOW (Bit 10) */
#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_LOW_Msk (0x400UL) /*!< GPIO_QSPI_SD0_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_HIGH_Pos (9UL) /*!< GPIO_QSPI_SD0_LEVEL_HIGH (Bit 9) */
#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_HIGH_Msk (0x200UL) /*!< GPIO_QSPI_SD0_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_LOW_Pos (8UL) /*!< GPIO_QSPI_SD0_LEVEL_LOW (Bit 8) */
#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_LOW_Msk (0x100UL) /*!< GPIO_QSPI_SD0_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_HIGH_Pos (7UL) /*!< GPIO_QSPI_SS_EDGE_HIGH (Bit 7) */
#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_HIGH_Msk (0x80UL) /*!< GPIO_QSPI_SS_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_LOW_Pos (6UL) /*!< GPIO_QSPI_SS_EDGE_LOW (Bit 6) */
#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_LOW_Msk (0x40UL) /*!< GPIO_QSPI_SS_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_HIGH_Pos (5UL) /*!< GPIO_QSPI_SS_LEVEL_HIGH (Bit 5) */
#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_HIGH_Msk (0x20UL) /*!< GPIO_QSPI_SS_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_LOW_Pos (4UL) /*!< GPIO_QSPI_SS_LEVEL_LOW (Bit 4) */
#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_LOW_Msk (0x10UL) /*!< GPIO_QSPI_SS_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_HIGH_Pos (3UL) /*!< GPIO_QSPI_SCLK_EDGE_HIGH (Bit 3) */
#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_HIGH_Msk (0x8UL) /*!< GPIO_QSPI_SCLK_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_LOW_Pos (2UL) /*!< GPIO_QSPI_SCLK_EDGE_LOW (Bit 2) */
#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_LOW_Msk (0x4UL) /*!< GPIO_QSPI_SCLK_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_HIGH_Pos (1UL) /*!< GPIO_QSPI_SCLK_LEVEL_HIGH (Bit 1) */
#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_HIGH_Msk (0x2UL) /*!< GPIO_QSPI_SCLK_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_LOW_Pos (0UL) /*!< GPIO_QSPI_SCLK_LEVEL_LOW (Bit 0) */
#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_LOW_Msk (0x1UL) /*!< GPIO_QSPI_SCLK_LEVEL_LOW (Bitfield-Mask: 0x01) */
/* ====================================================== PROC0_INTE ======================================================= */
#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_HIGH_Pos (23UL) /*!< GPIO_QSPI_SD3_EDGE_HIGH (Bit 23) */
#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_HIGH_Msk (0x800000UL) /*!< GPIO_QSPI_SD3_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_LOW_Pos (22UL) /*!< GPIO_QSPI_SD3_EDGE_LOW (Bit 22) */
#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_LOW_Msk (0x400000UL) /*!< GPIO_QSPI_SD3_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_Pos (21UL) /*!< GPIO_QSPI_SD3_LEVEL_HIGH (Bit 21) */
#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_Msk (0x200000UL) /*!< GPIO_QSPI_SD3_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_LOW_Pos (20UL) /*!< GPIO_QSPI_SD3_LEVEL_LOW (Bit 20) */
#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_LOW_Msk (0x100000UL) /*!< GPIO_QSPI_SD3_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_HIGH_Pos (19UL) /*!< GPIO_QSPI_SD2_EDGE_HIGH (Bit 19) */
#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_HIGH_Msk (0x80000UL) /*!< GPIO_QSPI_SD2_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_LOW_Pos (18UL) /*!< GPIO_QSPI_SD2_EDGE_LOW (Bit 18) */
#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_LOW_Msk (0x40000UL) /*!< GPIO_QSPI_SD2_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_Pos (17UL) /*!< GPIO_QSPI_SD2_LEVEL_HIGH (Bit 17) */
#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_Msk (0x20000UL) /*!< GPIO_QSPI_SD2_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_LOW_Pos (16UL) /*!< GPIO_QSPI_SD2_LEVEL_LOW (Bit 16) */
#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_LOW_Msk (0x10000UL) /*!< GPIO_QSPI_SD2_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_HIGH_Pos (15UL) /*!< GPIO_QSPI_SD1_EDGE_HIGH (Bit 15) */
#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_HIGH_Msk (0x8000UL) /*!< GPIO_QSPI_SD1_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_LOW_Pos (14UL) /*!< GPIO_QSPI_SD1_EDGE_LOW (Bit 14) */
#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_LOW_Msk (0x4000UL) /*!< GPIO_QSPI_SD1_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_Pos (13UL) /*!< GPIO_QSPI_SD1_LEVEL_HIGH (Bit 13) */
#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_Msk (0x2000UL) /*!< GPIO_QSPI_SD1_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_LOW_Pos (12UL) /*!< GPIO_QSPI_SD1_LEVEL_LOW (Bit 12) */
#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_LOW_Msk (0x1000UL) /*!< GPIO_QSPI_SD1_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_HIGH_Pos (11UL) /*!< GPIO_QSPI_SD0_EDGE_HIGH (Bit 11) */
#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_HIGH_Msk (0x800UL) /*!< GPIO_QSPI_SD0_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_LOW_Pos (10UL) /*!< GPIO_QSPI_SD0_EDGE_LOW (Bit 10) */
#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_LOW_Msk (0x400UL) /*!< GPIO_QSPI_SD0_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_Pos (9UL) /*!< GPIO_QSPI_SD0_LEVEL_HIGH (Bit 9) */
#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_Msk (0x200UL) /*!< GPIO_QSPI_SD0_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_LOW_Pos (8UL) /*!< GPIO_QSPI_SD0_LEVEL_LOW (Bit 8) */
#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_LOW_Msk (0x100UL) /*!< GPIO_QSPI_SD0_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_HIGH_Pos (7UL) /*!< GPIO_QSPI_SS_EDGE_HIGH (Bit 7) */
#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_HIGH_Msk (0x80UL) /*!< GPIO_QSPI_SS_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_LOW_Pos (6UL) /*!< GPIO_QSPI_SS_EDGE_LOW (Bit 6) */
#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_LOW_Msk (0x40UL) /*!< GPIO_QSPI_SS_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_HIGH_Pos (5UL) /*!< GPIO_QSPI_SS_LEVEL_HIGH (Bit 5) */
#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_HIGH_Msk (0x20UL) /*!< GPIO_QSPI_SS_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_LOW_Pos (4UL) /*!< GPIO_QSPI_SS_LEVEL_LOW (Bit 4) */
#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_LOW_Msk (0x10UL) /*!< GPIO_QSPI_SS_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_Pos (3UL) /*!< GPIO_QSPI_SCLK_EDGE_HIGH (Bit 3) */
#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_Msk (0x8UL) /*!< GPIO_QSPI_SCLK_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_LOW_Pos (2UL) /*!< GPIO_QSPI_SCLK_EDGE_LOW (Bit 2) */
#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_LOW_Msk (0x4UL) /*!< GPIO_QSPI_SCLK_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_Pos (1UL) /*!< GPIO_QSPI_SCLK_LEVEL_HIGH (Bit 1) */
#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_Msk (0x2UL) /*!< GPIO_QSPI_SCLK_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_Pos (0UL) /*!< GPIO_QSPI_SCLK_LEVEL_LOW (Bit 0) */
#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_Msk (0x1UL) /*!< GPIO_QSPI_SCLK_LEVEL_LOW (Bitfield-Mask: 0x01) */
/* ====================================================== PROC0_INTF ======================================================= */
#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_HIGH_Pos (23UL) /*!< GPIO_QSPI_SD3_EDGE_HIGH (Bit 23) */
#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_HIGH_Msk (0x800000UL) /*!< GPIO_QSPI_SD3_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_LOW_Pos (22UL) /*!< GPIO_QSPI_SD3_EDGE_LOW (Bit 22) */
#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_LOW_Msk (0x400000UL) /*!< GPIO_QSPI_SD3_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_Pos (21UL) /*!< GPIO_QSPI_SD3_LEVEL_HIGH (Bit 21) */
#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_Msk (0x200000UL) /*!< GPIO_QSPI_SD3_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_LOW_Pos (20UL) /*!< GPIO_QSPI_SD3_LEVEL_LOW (Bit 20) */
#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_LOW_Msk (0x100000UL) /*!< GPIO_QSPI_SD3_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_HIGH_Pos (19UL) /*!< GPIO_QSPI_SD2_EDGE_HIGH (Bit 19) */
#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_HIGH_Msk (0x80000UL) /*!< GPIO_QSPI_SD2_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_LOW_Pos (18UL) /*!< GPIO_QSPI_SD2_EDGE_LOW (Bit 18) */
#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_LOW_Msk (0x40000UL) /*!< GPIO_QSPI_SD2_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_Pos (17UL) /*!< GPIO_QSPI_SD2_LEVEL_HIGH (Bit 17) */
#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_Msk (0x20000UL) /*!< GPIO_QSPI_SD2_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_LOW_Pos (16UL) /*!< GPIO_QSPI_SD2_LEVEL_LOW (Bit 16) */
#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_LOW_Msk (0x10000UL) /*!< GPIO_QSPI_SD2_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_HIGH_Pos (15UL) /*!< GPIO_QSPI_SD1_EDGE_HIGH (Bit 15) */
#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_HIGH_Msk (0x8000UL) /*!< GPIO_QSPI_SD1_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_LOW_Pos (14UL) /*!< GPIO_QSPI_SD1_EDGE_LOW (Bit 14) */
#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_LOW_Msk (0x4000UL) /*!< GPIO_QSPI_SD1_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_Pos (13UL) /*!< GPIO_QSPI_SD1_LEVEL_HIGH (Bit 13) */
#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_Msk (0x2000UL) /*!< GPIO_QSPI_SD1_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_LOW_Pos (12UL) /*!< GPIO_QSPI_SD1_LEVEL_LOW (Bit 12) */
#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_LOW_Msk (0x1000UL) /*!< GPIO_QSPI_SD1_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_HIGH_Pos (11UL) /*!< GPIO_QSPI_SD0_EDGE_HIGH (Bit 11) */
#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_HIGH_Msk (0x800UL) /*!< GPIO_QSPI_SD0_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_LOW_Pos (10UL) /*!< GPIO_QSPI_SD0_EDGE_LOW (Bit 10) */
#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_LOW_Msk (0x400UL) /*!< GPIO_QSPI_SD0_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_Pos (9UL) /*!< GPIO_QSPI_SD0_LEVEL_HIGH (Bit 9) */
#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_Msk (0x200UL) /*!< GPIO_QSPI_SD0_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_LOW_Pos (8UL) /*!< GPIO_QSPI_SD0_LEVEL_LOW (Bit 8) */
#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_LOW_Msk (0x100UL) /*!< GPIO_QSPI_SD0_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_HIGH_Pos (7UL) /*!< GPIO_QSPI_SS_EDGE_HIGH (Bit 7) */
#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_HIGH_Msk (0x80UL) /*!< GPIO_QSPI_SS_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_LOW_Pos (6UL) /*!< GPIO_QSPI_SS_EDGE_LOW (Bit 6) */
#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_LOW_Msk (0x40UL) /*!< GPIO_QSPI_SS_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_HIGH_Pos (5UL) /*!< GPIO_QSPI_SS_LEVEL_HIGH (Bit 5) */
#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_HIGH_Msk (0x20UL) /*!< GPIO_QSPI_SS_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_LOW_Pos (4UL) /*!< GPIO_QSPI_SS_LEVEL_LOW (Bit 4) */
#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_LOW_Msk (0x10UL) /*!< GPIO_QSPI_SS_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_Pos (3UL) /*!< GPIO_QSPI_SCLK_EDGE_HIGH (Bit 3) */
#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_Msk (0x8UL) /*!< GPIO_QSPI_SCLK_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_LOW_Pos (2UL) /*!< GPIO_QSPI_SCLK_EDGE_LOW (Bit 2) */
#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_LOW_Msk (0x4UL) /*!< GPIO_QSPI_SCLK_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_Pos (1UL) /*!< GPIO_QSPI_SCLK_LEVEL_HIGH (Bit 1) */
#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_Msk (0x2UL) /*!< GPIO_QSPI_SCLK_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_Pos (0UL) /*!< GPIO_QSPI_SCLK_LEVEL_LOW (Bit 0) */
#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_Msk (0x1UL) /*!< GPIO_QSPI_SCLK_LEVEL_LOW (Bitfield-Mask: 0x01) */
/* ====================================================== PROC0_INTS ======================================================= */
#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_HIGH_Pos (23UL) /*!< GPIO_QSPI_SD3_EDGE_HIGH (Bit 23) */
#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_HIGH_Msk (0x800000UL) /*!< GPIO_QSPI_SD3_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_LOW_Pos (22UL) /*!< GPIO_QSPI_SD3_EDGE_LOW (Bit 22) */
#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_LOW_Msk (0x400000UL) /*!< GPIO_QSPI_SD3_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_Pos (21UL) /*!< GPIO_QSPI_SD3_LEVEL_HIGH (Bit 21) */
#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_Msk (0x200000UL) /*!< GPIO_QSPI_SD3_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_LOW_Pos (20UL) /*!< GPIO_QSPI_SD3_LEVEL_LOW (Bit 20) */
#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_LOW_Msk (0x100000UL) /*!< GPIO_QSPI_SD3_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_HIGH_Pos (19UL) /*!< GPIO_QSPI_SD2_EDGE_HIGH (Bit 19) */
#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_HIGH_Msk (0x80000UL) /*!< GPIO_QSPI_SD2_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_LOW_Pos (18UL) /*!< GPIO_QSPI_SD2_EDGE_LOW (Bit 18) */
#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_LOW_Msk (0x40000UL) /*!< GPIO_QSPI_SD2_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_Pos (17UL) /*!< GPIO_QSPI_SD2_LEVEL_HIGH (Bit 17) */
#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_Msk (0x20000UL) /*!< GPIO_QSPI_SD2_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_LOW_Pos (16UL) /*!< GPIO_QSPI_SD2_LEVEL_LOW (Bit 16) */
#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_LOW_Msk (0x10000UL) /*!< GPIO_QSPI_SD2_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_HIGH_Pos (15UL) /*!< GPIO_QSPI_SD1_EDGE_HIGH (Bit 15) */
#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_HIGH_Msk (0x8000UL) /*!< GPIO_QSPI_SD1_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_LOW_Pos (14UL) /*!< GPIO_QSPI_SD1_EDGE_LOW (Bit 14) */
#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_LOW_Msk (0x4000UL) /*!< GPIO_QSPI_SD1_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_Pos (13UL) /*!< GPIO_QSPI_SD1_LEVEL_HIGH (Bit 13) */
#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_Msk (0x2000UL) /*!< GPIO_QSPI_SD1_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_LOW_Pos (12UL) /*!< GPIO_QSPI_SD1_LEVEL_LOW (Bit 12) */
#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_LOW_Msk (0x1000UL) /*!< GPIO_QSPI_SD1_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_HIGH_Pos (11UL) /*!< GPIO_QSPI_SD0_EDGE_HIGH (Bit 11) */
#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_HIGH_Msk (0x800UL) /*!< GPIO_QSPI_SD0_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_LOW_Pos (10UL) /*!< GPIO_QSPI_SD0_EDGE_LOW (Bit 10) */
#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_LOW_Msk (0x400UL) /*!< GPIO_QSPI_SD0_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_Pos (9UL) /*!< GPIO_QSPI_SD0_LEVEL_HIGH (Bit 9) */
#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_Msk (0x200UL) /*!< GPIO_QSPI_SD0_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_LOW_Pos (8UL) /*!< GPIO_QSPI_SD0_LEVEL_LOW (Bit 8) */
#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_LOW_Msk (0x100UL) /*!< GPIO_QSPI_SD0_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_HIGH_Pos (7UL) /*!< GPIO_QSPI_SS_EDGE_HIGH (Bit 7) */
#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_HIGH_Msk (0x80UL) /*!< GPIO_QSPI_SS_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_LOW_Pos (6UL) /*!< GPIO_QSPI_SS_EDGE_LOW (Bit 6) */
#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_LOW_Msk (0x40UL) /*!< GPIO_QSPI_SS_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_HIGH_Pos (5UL) /*!< GPIO_QSPI_SS_LEVEL_HIGH (Bit 5) */
#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_HIGH_Msk (0x20UL) /*!< GPIO_QSPI_SS_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_LOW_Pos (4UL) /*!< GPIO_QSPI_SS_LEVEL_LOW (Bit 4) */
#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_LOW_Msk (0x10UL) /*!< GPIO_QSPI_SS_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_Pos (3UL) /*!< GPIO_QSPI_SCLK_EDGE_HIGH (Bit 3) */
#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_Msk (0x8UL) /*!< GPIO_QSPI_SCLK_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_LOW_Pos (2UL) /*!< GPIO_QSPI_SCLK_EDGE_LOW (Bit 2) */
#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_LOW_Msk (0x4UL) /*!< GPIO_QSPI_SCLK_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_Pos (1UL) /*!< GPIO_QSPI_SCLK_LEVEL_HIGH (Bit 1) */
#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_Msk (0x2UL) /*!< GPIO_QSPI_SCLK_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_Pos (0UL) /*!< GPIO_QSPI_SCLK_LEVEL_LOW (Bit 0) */
#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_Msk (0x1UL) /*!< GPIO_QSPI_SCLK_LEVEL_LOW (Bitfield-Mask: 0x01) */
/* ====================================================== PROC1_INTE ======================================================= */
#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_HIGH_Pos (23UL) /*!< GPIO_QSPI_SD3_EDGE_HIGH (Bit 23) */
#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_HIGH_Msk (0x800000UL) /*!< GPIO_QSPI_SD3_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_LOW_Pos (22UL) /*!< GPIO_QSPI_SD3_EDGE_LOW (Bit 22) */
#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_LOW_Msk (0x400000UL) /*!< GPIO_QSPI_SD3_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_Pos (21UL) /*!< GPIO_QSPI_SD3_LEVEL_HIGH (Bit 21) */
#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_Msk (0x200000UL) /*!< GPIO_QSPI_SD3_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_LOW_Pos (20UL) /*!< GPIO_QSPI_SD3_LEVEL_LOW (Bit 20) */
#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_LOW_Msk (0x100000UL) /*!< GPIO_QSPI_SD3_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_HIGH_Pos (19UL) /*!< GPIO_QSPI_SD2_EDGE_HIGH (Bit 19) */
#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_HIGH_Msk (0x80000UL) /*!< GPIO_QSPI_SD2_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_LOW_Pos (18UL) /*!< GPIO_QSPI_SD2_EDGE_LOW (Bit 18) */
#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_LOW_Msk (0x40000UL) /*!< GPIO_QSPI_SD2_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_Pos (17UL) /*!< GPIO_QSPI_SD2_LEVEL_HIGH (Bit 17) */
#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_Msk (0x20000UL) /*!< GPIO_QSPI_SD2_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_LOW_Pos (16UL) /*!< GPIO_QSPI_SD2_LEVEL_LOW (Bit 16) */
#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_LOW_Msk (0x10000UL) /*!< GPIO_QSPI_SD2_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_HIGH_Pos (15UL) /*!< GPIO_QSPI_SD1_EDGE_HIGH (Bit 15) */
#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_HIGH_Msk (0x8000UL) /*!< GPIO_QSPI_SD1_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_LOW_Pos (14UL) /*!< GPIO_QSPI_SD1_EDGE_LOW (Bit 14) */
#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_LOW_Msk (0x4000UL) /*!< GPIO_QSPI_SD1_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_Pos (13UL) /*!< GPIO_QSPI_SD1_LEVEL_HIGH (Bit 13) */
#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_Msk (0x2000UL) /*!< GPIO_QSPI_SD1_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_LOW_Pos (12UL) /*!< GPIO_QSPI_SD1_LEVEL_LOW (Bit 12) */
#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_LOW_Msk (0x1000UL) /*!< GPIO_QSPI_SD1_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_HIGH_Pos (11UL) /*!< GPIO_QSPI_SD0_EDGE_HIGH (Bit 11) */
#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_HIGH_Msk (0x800UL) /*!< GPIO_QSPI_SD0_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_LOW_Pos (10UL) /*!< GPIO_QSPI_SD0_EDGE_LOW (Bit 10) */
#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_LOW_Msk (0x400UL) /*!< GPIO_QSPI_SD0_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_Pos (9UL) /*!< GPIO_QSPI_SD0_LEVEL_HIGH (Bit 9) */
#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_Msk (0x200UL) /*!< GPIO_QSPI_SD0_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_LOW_Pos (8UL) /*!< GPIO_QSPI_SD0_LEVEL_LOW (Bit 8) */
#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_LOW_Msk (0x100UL) /*!< GPIO_QSPI_SD0_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_HIGH_Pos (7UL) /*!< GPIO_QSPI_SS_EDGE_HIGH (Bit 7) */
#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_HIGH_Msk (0x80UL) /*!< GPIO_QSPI_SS_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_LOW_Pos (6UL) /*!< GPIO_QSPI_SS_EDGE_LOW (Bit 6) */
#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_LOW_Msk (0x40UL) /*!< GPIO_QSPI_SS_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_HIGH_Pos (5UL) /*!< GPIO_QSPI_SS_LEVEL_HIGH (Bit 5) */
#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_HIGH_Msk (0x20UL) /*!< GPIO_QSPI_SS_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_LOW_Pos (4UL) /*!< GPIO_QSPI_SS_LEVEL_LOW (Bit 4) */
#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_LOW_Msk (0x10UL) /*!< GPIO_QSPI_SS_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_Pos (3UL) /*!< GPIO_QSPI_SCLK_EDGE_HIGH (Bit 3) */
#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_Msk (0x8UL) /*!< GPIO_QSPI_SCLK_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_LOW_Pos (2UL) /*!< GPIO_QSPI_SCLK_EDGE_LOW (Bit 2) */
#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_LOW_Msk (0x4UL) /*!< GPIO_QSPI_SCLK_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_Pos (1UL) /*!< GPIO_QSPI_SCLK_LEVEL_HIGH (Bit 1) */
#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_Msk (0x2UL) /*!< GPIO_QSPI_SCLK_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_Pos (0UL) /*!< GPIO_QSPI_SCLK_LEVEL_LOW (Bit 0) */
#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_Msk (0x1UL) /*!< GPIO_QSPI_SCLK_LEVEL_LOW (Bitfield-Mask: 0x01) */
/* ====================================================== PROC1_INTF ======================================================= */
#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_HIGH_Pos (23UL) /*!< GPIO_QSPI_SD3_EDGE_HIGH (Bit 23) */
#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_HIGH_Msk (0x800000UL) /*!< GPIO_QSPI_SD3_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_LOW_Pos (22UL) /*!< GPIO_QSPI_SD3_EDGE_LOW (Bit 22) */
#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_LOW_Msk (0x400000UL) /*!< GPIO_QSPI_SD3_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_Pos (21UL) /*!< GPIO_QSPI_SD3_LEVEL_HIGH (Bit 21) */
#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_Msk (0x200000UL) /*!< GPIO_QSPI_SD3_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_LOW_Pos (20UL) /*!< GPIO_QSPI_SD3_LEVEL_LOW (Bit 20) */
#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_LOW_Msk (0x100000UL) /*!< GPIO_QSPI_SD3_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_HIGH_Pos (19UL) /*!< GPIO_QSPI_SD2_EDGE_HIGH (Bit 19) */
#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_HIGH_Msk (0x80000UL) /*!< GPIO_QSPI_SD2_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_LOW_Pos (18UL) /*!< GPIO_QSPI_SD2_EDGE_LOW (Bit 18) */
#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_LOW_Msk (0x40000UL) /*!< GPIO_QSPI_SD2_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_Pos (17UL) /*!< GPIO_QSPI_SD2_LEVEL_HIGH (Bit 17) */
#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_Msk (0x20000UL) /*!< GPIO_QSPI_SD2_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_LOW_Pos (16UL) /*!< GPIO_QSPI_SD2_LEVEL_LOW (Bit 16) */
#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_LOW_Msk (0x10000UL) /*!< GPIO_QSPI_SD2_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_HIGH_Pos (15UL) /*!< GPIO_QSPI_SD1_EDGE_HIGH (Bit 15) */
#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_HIGH_Msk (0x8000UL) /*!< GPIO_QSPI_SD1_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_LOW_Pos (14UL) /*!< GPIO_QSPI_SD1_EDGE_LOW (Bit 14) */
#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_LOW_Msk (0x4000UL) /*!< GPIO_QSPI_SD1_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_Pos (13UL) /*!< GPIO_QSPI_SD1_LEVEL_HIGH (Bit 13) */
#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_Msk (0x2000UL) /*!< GPIO_QSPI_SD1_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_LOW_Pos (12UL) /*!< GPIO_QSPI_SD1_LEVEL_LOW (Bit 12) */
#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_LOW_Msk (0x1000UL) /*!< GPIO_QSPI_SD1_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_HIGH_Pos (11UL) /*!< GPIO_QSPI_SD0_EDGE_HIGH (Bit 11) */
#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_HIGH_Msk (0x800UL) /*!< GPIO_QSPI_SD0_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_LOW_Pos (10UL) /*!< GPIO_QSPI_SD0_EDGE_LOW (Bit 10) */
#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_LOW_Msk (0x400UL) /*!< GPIO_QSPI_SD0_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_Pos (9UL) /*!< GPIO_QSPI_SD0_LEVEL_HIGH (Bit 9) */
#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_Msk (0x200UL) /*!< GPIO_QSPI_SD0_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_LOW_Pos (8UL) /*!< GPIO_QSPI_SD0_LEVEL_LOW (Bit 8) */
#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_LOW_Msk (0x100UL) /*!< GPIO_QSPI_SD0_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_HIGH_Pos (7UL) /*!< GPIO_QSPI_SS_EDGE_HIGH (Bit 7) */
#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_HIGH_Msk (0x80UL) /*!< GPIO_QSPI_SS_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_LOW_Pos (6UL) /*!< GPIO_QSPI_SS_EDGE_LOW (Bit 6) */
#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_LOW_Msk (0x40UL) /*!< GPIO_QSPI_SS_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_HIGH_Pos (5UL) /*!< GPIO_QSPI_SS_LEVEL_HIGH (Bit 5) */
#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_HIGH_Msk (0x20UL) /*!< GPIO_QSPI_SS_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_LOW_Pos (4UL) /*!< GPIO_QSPI_SS_LEVEL_LOW (Bit 4) */
#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_LOW_Msk (0x10UL) /*!< GPIO_QSPI_SS_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_Pos (3UL) /*!< GPIO_QSPI_SCLK_EDGE_HIGH (Bit 3) */
#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_Msk (0x8UL) /*!< GPIO_QSPI_SCLK_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_LOW_Pos (2UL) /*!< GPIO_QSPI_SCLK_EDGE_LOW (Bit 2) */
#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_LOW_Msk (0x4UL) /*!< GPIO_QSPI_SCLK_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_Pos (1UL) /*!< GPIO_QSPI_SCLK_LEVEL_HIGH (Bit 1) */
#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_Msk (0x2UL) /*!< GPIO_QSPI_SCLK_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_Pos (0UL) /*!< GPIO_QSPI_SCLK_LEVEL_LOW (Bit 0) */
#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_Msk (0x1UL) /*!< GPIO_QSPI_SCLK_LEVEL_LOW (Bitfield-Mask: 0x01) */
/* ====================================================== PROC1_INTS ======================================================= */
#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_HIGH_Pos (23UL) /*!< GPIO_QSPI_SD3_EDGE_HIGH (Bit 23) */
#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_HIGH_Msk (0x800000UL) /*!< GPIO_QSPI_SD3_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_LOW_Pos (22UL) /*!< GPIO_QSPI_SD3_EDGE_LOW (Bit 22) */
#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_LOW_Msk (0x400000UL) /*!< GPIO_QSPI_SD3_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_Pos (21UL) /*!< GPIO_QSPI_SD3_LEVEL_HIGH (Bit 21) */
#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_Msk (0x200000UL) /*!< GPIO_QSPI_SD3_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_LOW_Pos (20UL) /*!< GPIO_QSPI_SD3_LEVEL_LOW (Bit 20) */
#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_LOW_Msk (0x100000UL) /*!< GPIO_QSPI_SD3_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_HIGH_Pos (19UL) /*!< GPIO_QSPI_SD2_EDGE_HIGH (Bit 19) */
#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_HIGH_Msk (0x80000UL) /*!< GPIO_QSPI_SD2_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_LOW_Pos (18UL) /*!< GPIO_QSPI_SD2_EDGE_LOW (Bit 18) */
#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_LOW_Msk (0x40000UL) /*!< GPIO_QSPI_SD2_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_Pos (17UL) /*!< GPIO_QSPI_SD2_LEVEL_HIGH (Bit 17) */
#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_Msk (0x20000UL) /*!< GPIO_QSPI_SD2_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_LOW_Pos (16UL) /*!< GPIO_QSPI_SD2_LEVEL_LOW (Bit 16) */
#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_LOW_Msk (0x10000UL) /*!< GPIO_QSPI_SD2_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_HIGH_Pos (15UL) /*!< GPIO_QSPI_SD1_EDGE_HIGH (Bit 15) */
#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_HIGH_Msk (0x8000UL) /*!< GPIO_QSPI_SD1_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_LOW_Pos (14UL) /*!< GPIO_QSPI_SD1_EDGE_LOW (Bit 14) */
#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_LOW_Msk (0x4000UL) /*!< GPIO_QSPI_SD1_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_Pos (13UL) /*!< GPIO_QSPI_SD1_LEVEL_HIGH (Bit 13) */
#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_Msk (0x2000UL) /*!< GPIO_QSPI_SD1_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_LOW_Pos (12UL) /*!< GPIO_QSPI_SD1_LEVEL_LOW (Bit 12) */
#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_LOW_Msk (0x1000UL) /*!< GPIO_QSPI_SD1_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_HIGH_Pos (11UL) /*!< GPIO_QSPI_SD0_EDGE_HIGH (Bit 11) */
#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_HIGH_Msk (0x800UL) /*!< GPIO_QSPI_SD0_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_LOW_Pos (10UL) /*!< GPIO_QSPI_SD0_EDGE_LOW (Bit 10) */
#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_LOW_Msk (0x400UL) /*!< GPIO_QSPI_SD0_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_Pos (9UL) /*!< GPIO_QSPI_SD0_LEVEL_HIGH (Bit 9) */
#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_Msk (0x200UL) /*!< GPIO_QSPI_SD0_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_LOW_Pos (8UL) /*!< GPIO_QSPI_SD0_LEVEL_LOW (Bit 8) */
#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_LOW_Msk (0x100UL) /*!< GPIO_QSPI_SD0_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_HIGH_Pos (7UL) /*!< GPIO_QSPI_SS_EDGE_HIGH (Bit 7) */
#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_HIGH_Msk (0x80UL) /*!< GPIO_QSPI_SS_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_LOW_Pos (6UL) /*!< GPIO_QSPI_SS_EDGE_LOW (Bit 6) */
#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_LOW_Msk (0x40UL) /*!< GPIO_QSPI_SS_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_HIGH_Pos (5UL) /*!< GPIO_QSPI_SS_LEVEL_HIGH (Bit 5) */
#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_HIGH_Msk (0x20UL) /*!< GPIO_QSPI_SS_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_LOW_Pos (4UL) /*!< GPIO_QSPI_SS_LEVEL_LOW (Bit 4) */
#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_LOW_Msk (0x10UL) /*!< GPIO_QSPI_SS_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_Pos (3UL) /*!< GPIO_QSPI_SCLK_EDGE_HIGH (Bit 3) */
#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_Msk (0x8UL) /*!< GPIO_QSPI_SCLK_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_LOW_Pos (2UL) /*!< GPIO_QSPI_SCLK_EDGE_LOW (Bit 2) */
#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_LOW_Msk (0x4UL) /*!< GPIO_QSPI_SCLK_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_Pos (1UL) /*!< GPIO_QSPI_SCLK_LEVEL_HIGH (Bit 1) */
#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_Msk (0x2UL) /*!< GPIO_QSPI_SCLK_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_Pos (0UL) /*!< GPIO_QSPI_SCLK_LEVEL_LOW (Bit 0) */
#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_Msk (0x1UL) /*!< GPIO_QSPI_SCLK_LEVEL_LOW (Bitfield-Mask: 0x01) */
/* =================================================== DORMANT_WAKE_INTE =================================================== */
#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_HIGH_Pos (23UL) /*!< GPIO_QSPI_SD3_EDGE_HIGH (Bit 23) */
#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_HIGH_Msk (0x800000UL) /*!< GPIO_QSPI_SD3_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_LOW_Pos (22UL) /*!< GPIO_QSPI_SD3_EDGE_LOW (Bit 22) */
#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_LOW_Msk (0x400000UL) /*!< GPIO_QSPI_SD3_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_Pos (21UL) /*!< GPIO_QSPI_SD3_LEVEL_HIGH (Bit 21) */
#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_Msk (0x200000UL) /*!< GPIO_QSPI_SD3_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_LOW_Pos (20UL) /*!< GPIO_QSPI_SD3_LEVEL_LOW (Bit 20) */
#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_LOW_Msk (0x100000UL) /*!< GPIO_QSPI_SD3_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_HIGH_Pos (19UL) /*!< GPIO_QSPI_SD2_EDGE_HIGH (Bit 19) */
#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_HIGH_Msk (0x80000UL) /*!< GPIO_QSPI_SD2_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_LOW_Pos (18UL) /*!< GPIO_QSPI_SD2_EDGE_LOW (Bit 18) */
#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_LOW_Msk (0x40000UL) /*!< GPIO_QSPI_SD2_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_Pos (17UL) /*!< GPIO_QSPI_SD2_LEVEL_HIGH (Bit 17) */
#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_Msk (0x20000UL) /*!< GPIO_QSPI_SD2_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_LOW_Pos (16UL) /*!< GPIO_QSPI_SD2_LEVEL_LOW (Bit 16) */
#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_LOW_Msk (0x10000UL) /*!< GPIO_QSPI_SD2_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_HIGH_Pos (15UL) /*!< GPIO_QSPI_SD1_EDGE_HIGH (Bit 15) */
#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_HIGH_Msk (0x8000UL) /*!< GPIO_QSPI_SD1_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_LOW_Pos (14UL) /*!< GPIO_QSPI_SD1_EDGE_LOW (Bit 14) */
#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_LOW_Msk (0x4000UL) /*!< GPIO_QSPI_SD1_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_Pos (13UL) /*!< GPIO_QSPI_SD1_LEVEL_HIGH (Bit 13) */
#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_Msk (0x2000UL) /*!< GPIO_QSPI_SD1_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_LOW_Pos (12UL) /*!< GPIO_QSPI_SD1_LEVEL_LOW (Bit 12) */
#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_LOW_Msk (0x1000UL) /*!< GPIO_QSPI_SD1_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_HIGH_Pos (11UL) /*!< GPIO_QSPI_SD0_EDGE_HIGH (Bit 11) */
#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_HIGH_Msk (0x800UL) /*!< GPIO_QSPI_SD0_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_LOW_Pos (10UL) /*!< GPIO_QSPI_SD0_EDGE_LOW (Bit 10) */
#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_LOW_Msk (0x400UL) /*!< GPIO_QSPI_SD0_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_Pos (9UL) /*!< GPIO_QSPI_SD0_LEVEL_HIGH (Bit 9) */
#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_Msk (0x200UL) /*!< GPIO_QSPI_SD0_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_LOW_Pos (8UL) /*!< GPIO_QSPI_SD0_LEVEL_LOW (Bit 8) */
#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_LOW_Msk (0x100UL) /*!< GPIO_QSPI_SD0_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_HIGH_Pos (7UL) /*!< GPIO_QSPI_SS_EDGE_HIGH (Bit 7) */
#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_HIGH_Msk (0x80UL) /*!< GPIO_QSPI_SS_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_LOW_Pos (6UL) /*!< GPIO_QSPI_SS_EDGE_LOW (Bit 6) */
#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_LOW_Msk (0x40UL) /*!< GPIO_QSPI_SS_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_HIGH_Pos (5UL) /*!< GPIO_QSPI_SS_LEVEL_HIGH (Bit 5) */
#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_HIGH_Msk (0x20UL) /*!< GPIO_QSPI_SS_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_LOW_Pos (4UL) /*!< GPIO_QSPI_SS_LEVEL_LOW (Bit 4) */
#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_LOW_Msk (0x10UL) /*!< GPIO_QSPI_SS_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_Pos (3UL) /*!< GPIO_QSPI_SCLK_EDGE_HIGH (Bit 3) */
#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_Msk (0x8UL) /*!< GPIO_QSPI_SCLK_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_LOW_Pos (2UL) /*!< GPIO_QSPI_SCLK_EDGE_LOW (Bit 2) */
#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_LOW_Msk (0x4UL) /*!< GPIO_QSPI_SCLK_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_Pos (1UL) /*!< GPIO_QSPI_SCLK_LEVEL_HIGH (Bit 1) */
#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_Msk (0x2UL) /*!< GPIO_QSPI_SCLK_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_Pos (0UL) /*!< GPIO_QSPI_SCLK_LEVEL_LOW (Bit 0) */
#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_Msk (0x1UL) /*!< GPIO_QSPI_SCLK_LEVEL_LOW (Bitfield-Mask: 0x01) */
/* =================================================== DORMANT_WAKE_INTF =================================================== */
#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_HIGH_Pos (23UL) /*!< GPIO_QSPI_SD3_EDGE_HIGH (Bit 23) */
#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_HIGH_Msk (0x800000UL) /*!< GPIO_QSPI_SD3_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_LOW_Pos (22UL) /*!< GPIO_QSPI_SD3_EDGE_LOW (Bit 22) */
#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_LOW_Msk (0x400000UL) /*!< GPIO_QSPI_SD3_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_Pos (21UL) /*!< GPIO_QSPI_SD3_LEVEL_HIGH (Bit 21) */
#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_Msk (0x200000UL) /*!< GPIO_QSPI_SD3_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_LOW_Pos (20UL) /*!< GPIO_QSPI_SD3_LEVEL_LOW (Bit 20) */
#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_LOW_Msk (0x100000UL) /*!< GPIO_QSPI_SD3_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_HIGH_Pos (19UL) /*!< GPIO_QSPI_SD2_EDGE_HIGH (Bit 19) */
#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_HIGH_Msk (0x80000UL) /*!< GPIO_QSPI_SD2_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_LOW_Pos (18UL) /*!< GPIO_QSPI_SD2_EDGE_LOW (Bit 18) */
#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_LOW_Msk (0x40000UL) /*!< GPIO_QSPI_SD2_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_Pos (17UL) /*!< GPIO_QSPI_SD2_LEVEL_HIGH (Bit 17) */
#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_Msk (0x20000UL) /*!< GPIO_QSPI_SD2_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_LOW_Pos (16UL) /*!< GPIO_QSPI_SD2_LEVEL_LOW (Bit 16) */
#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_LOW_Msk (0x10000UL) /*!< GPIO_QSPI_SD2_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_HIGH_Pos (15UL) /*!< GPIO_QSPI_SD1_EDGE_HIGH (Bit 15) */
#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_HIGH_Msk (0x8000UL) /*!< GPIO_QSPI_SD1_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_LOW_Pos (14UL) /*!< GPIO_QSPI_SD1_EDGE_LOW (Bit 14) */
#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_LOW_Msk (0x4000UL) /*!< GPIO_QSPI_SD1_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_Pos (13UL) /*!< GPIO_QSPI_SD1_LEVEL_HIGH (Bit 13) */
#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_Msk (0x2000UL) /*!< GPIO_QSPI_SD1_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_LOW_Pos (12UL) /*!< GPIO_QSPI_SD1_LEVEL_LOW (Bit 12) */
#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_LOW_Msk (0x1000UL) /*!< GPIO_QSPI_SD1_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_HIGH_Pos (11UL) /*!< GPIO_QSPI_SD0_EDGE_HIGH (Bit 11) */
#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_HIGH_Msk (0x800UL) /*!< GPIO_QSPI_SD0_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_LOW_Pos (10UL) /*!< GPIO_QSPI_SD0_EDGE_LOW (Bit 10) */
#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_LOW_Msk (0x400UL) /*!< GPIO_QSPI_SD0_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_Pos (9UL) /*!< GPIO_QSPI_SD0_LEVEL_HIGH (Bit 9) */
#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_Msk (0x200UL) /*!< GPIO_QSPI_SD0_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_LOW_Pos (8UL) /*!< GPIO_QSPI_SD0_LEVEL_LOW (Bit 8) */
#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_LOW_Msk (0x100UL) /*!< GPIO_QSPI_SD0_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_HIGH_Pos (7UL) /*!< GPIO_QSPI_SS_EDGE_HIGH (Bit 7) */
#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_HIGH_Msk (0x80UL) /*!< GPIO_QSPI_SS_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_LOW_Pos (6UL) /*!< GPIO_QSPI_SS_EDGE_LOW (Bit 6) */
#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_LOW_Msk (0x40UL) /*!< GPIO_QSPI_SS_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_HIGH_Pos (5UL) /*!< GPIO_QSPI_SS_LEVEL_HIGH (Bit 5) */
#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_HIGH_Msk (0x20UL) /*!< GPIO_QSPI_SS_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_LOW_Pos (4UL) /*!< GPIO_QSPI_SS_LEVEL_LOW (Bit 4) */
#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_LOW_Msk (0x10UL) /*!< GPIO_QSPI_SS_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_Pos (3UL) /*!< GPIO_QSPI_SCLK_EDGE_HIGH (Bit 3) */
#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_Msk (0x8UL) /*!< GPIO_QSPI_SCLK_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_LOW_Pos (2UL) /*!< GPIO_QSPI_SCLK_EDGE_LOW (Bit 2) */
#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_LOW_Msk (0x4UL) /*!< GPIO_QSPI_SCLK_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_Pos (1UL) /*!< GPIO_QSPI_SCLK_LEVEL_HIGH (Bit 1) */
#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_Msk (0x2UL) /*!< GPIO_QSPI_SCLK_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_Pos (0UL) /*!< GPIO_QSPI_SCLK_LEVEL_LOW (Bit 0) */
#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_Msk (0x1UL) /*!< GPIO_QSPI_SCLK_LEVEL_LOW (Bitfield-Mask: 0x01) */
/* =================================================== DORMANT_WAKE_INTS =================================================== */
#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_HIGH_Pos (23UL) /*!< GPIO_QSPI_SD3_EDGE_HIGH (Bit 23) */
#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_HIGH_Msk (0x800000UL) /*!< GPIO_QSPI_SD3_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_LOW_Pos (22UL) /*!< GPIO_QSPI_SD3_EDGE_LOW (Bit 22) */
#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_LOW_Msk (0x400000UL) /*!< GPIO_QSPI_SD3_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_Pos (21UL) /*!< GPIO_QSPI_SD3_LEVEL_HIGH (Bit 21) */
#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_Msk (0x200000UL) /*!< GPIO_QSPI_SD3_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_LOW_Pos (20UL) /*!< GPIO_QSPI_SD3_LEVEL_LOW (Bit 20) */
#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_LOW_Msk (0x100000UL) /*!< GPIO_QSPI_SD3_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_HIGH_Pos (19UL) /*!< GPIO_QSPI_SD2_EDGE_HIGH (Bit 19) */
#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_HIGH_Msk (0x80000UL) /*!< GPIO_QSPI_SD2_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_LOW_Pos (18UL) /*!< GPIO_QSPI_SD2_EDGE_LOW (Bit 18) */
#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_LOW_Msk (0x40000UL) /*!< GPIO_QSPI_SD2_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_Pos (17UL) /*!< GPIO_QSPI_SD2_LEVEL_HIGH (Bit 17) */
#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_Msk (0x20000UL) /*!< GPIO_QSPI_SD2_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_LOW_Pos (16UL) /*!< GPIO_QSPI_SD2_LEVEL_LOW (Bit 16) */
#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_LOW_Msk (0x10000UL) /*!< GPIO_QSPI_SD2_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_HIGH_Pos (15UL) /*!< GPIO_QSPI_SD1_EDGE_HIGH (Bit 15) */
#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_HIGH_Msk (0x8000UL) /*!< GPIO_QSPI_SD1_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_LOW_Pos (14UL) /*!< GPIO_QSPI_SD1_EDGE_LOW (Bit 14) */
#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_LOW_Msk (0x4000UL) /*!< GPIO_QSPI_SD1_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_Pos (13UL) /*!< GPIO_QSPI_SD1_LEVEL_HIGH (Bit 13) */
#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_Msk (0x2000UL) /*!< GPIO_QSPI_SD1_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_LOW_Pos (12UL) /*!< GPIO_QSPI_SD1_LEVEL_LOW (Bit 12) */
#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_LOW_Msk (0x1000UL) /*!< GPIO_QSPI_SD1_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_HIGH_Pos (11UL) /*!< GPIO_QSPI_SD0_EDGE_HIGH (Bit 11) */
#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_HIGH_Msk (0x800UL) /*!< GPIO_QSPI_SD0_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_LOW_Pos (10UL) /*!< GPIO_QSPI_SD0_EDGE_LOW (Bit 10) */
#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_LOW_Msk (0x400UL) /*!< GPIO_QSPI_SD0_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_Pos (9UL) /*!< GPIO_QSPI_SD0_LEVEL_HIGH (Bit 9) */
#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_Msk (0x200UL) /*!< GPIO_QSPI_SD0_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_LOW_Pos (8UL) /*!< GPIO_QSPI_SD0_LEVEL_LOW (Bit 8) */
#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_LOW_Msk (0x100UL) /*!< GPIO_QSPI_SD0_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_HIGH_Pos (7UL) /*!< GPIO_QSPI_SS_EDGE_HIGH (Bit 7) */
#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_HIGH_Msk (0x80UL) /*!< GPIO_QSPI_SS_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_LOW_Pos (6UL) /*!< GPIO_QSPI_SS_EDGE_LOW (Bit 6) */
#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_LOW_Msk (0x40UL) /*!< GPIO_QSPI_SS_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_HIGH_Pos (5UL) /*!< GPIO_QSPI_SS_LEVEL_HIGH (Bit 5) */
#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_HIGH_Msk (0x20UL) /*!< GPIO_QSPI_SS_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_LOW_Pos (4UL) /*!< GPIO_QSPI_SS_LEVEL_LOW (Bit 4) */
#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_LOW_Msk (0x10UL) /*!< GPIO_QSPI_SS_LEVEL_LOW (Bitfield-Mask: 0x01) */
#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_Pos (3UL) /*!< GPIO_QSPI_SCLK_EDGE_HIGH (Bit 3) */
#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_Msk (0x8UL) /*!< GPIO_QSPI_SCLK_EDGE_HIGH (Bitfield-Mask: 0x01) */
#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_LOW_Pos (2UL) /*!< GPIO_QSPI_SCLK_EDGE_LOW (Bit 2) */
#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_LOW_Msk (0x4UL) /*!< GPIO_QSPI_SCLK_EDGE_LOW (Bitfield-Mask: 0x01) */
#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_Pos (1UL) /*!< GPIO_QSPI_SCLK_LEVEL_HIGH (Bit 1) */
#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_Msk (0x2UL) /*!< GPIO_QSPI_SCLK_LEVEL_HIGH (Bitfield-Mask: 0x01) */
#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_Pos (0UL) /*!< GPIO_QSPI_SCLK_LEVEL_LOW (Bit 0) */
#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_Msk (0x1UL) /*!< GPIO_QSPI_SCLK_LEVEL_LOW (Bitfield-Mask: 0x01) */
/* =========================================================================================================================== */
/* ================ PADS_BANK0 ================ */
/* =========================================================================================================================== */
/* ==================================================== VOLTAGE_SELECT ===================================================== */
#define PADS_BANK0_VOLTAGE_SELECT_VOLTAGE_SELECT_Pos (0UL) /*!< VOLTAGE_SELECT (Bit 0) */
#define PADS_BANK0_VOLTAGE_SELECT_VOLTAGE_SELECT_Msk (0x1UL) /*!< VOLTAGE_SELECT (Bitfield-Mask: 0x01) */
/* ========================================================= GPIO0 ========================================================= */
#define PADS_BANK0_GPIO0_OD_Pos (7UL) /*!< OD (Bit 7) */
#define PADS_BANK0_GPIO0_OD_Msk (0x80UL) /*!< OD (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO0_IE_Pos (6UL) /*!< IE (Bit 6) */
#define PADS_BANK0_GPIO0_IE_Msk (0x40UL) /*!< IE (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO0_DRIVE_Pos (4UL) /*!< DRIVE (Bit 4) */
#define PADS_BANK0_GPIO0_DRIVE_Msk (0x30UL) /*!< DRIVE (Bitfield-Mask: 0x03) */
#define PADS_BANK0_GPIO0_PUE_Pos (3UL) /*!< PUE (Bit 3) */
#define PADS_BANK0_GPIO0_PUE_Msk (0x8UL) /*!< PUE (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO0_PDE_Pos (2UL) /*!< PDE (Bit 2) */
#define PADS_BANK0_GPIO0_PDE_Msk (0x4UL) /*!< PDE (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO0_SCHMITT_Pos (1UL) /*!< SCHMITT (Bit 1) */
#define PADS_BANK0_GPIO0_SCHMITT_Msk (0x2UL) /*!< SCHMITT (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO0_SLEWFAST_Pos (0UL) /*!< SLEWFAST (Bit 0) */
#define PADS_BANK0_GPIO0_SLEWFAST_Msk (0x1UL) /*!< SLEWFAST (Bitfield-Mask: 0x01) */
/* ========================================================= GPIO1 ========================================================= */
#define PADS_BANK0_GPIO1_OD_Pos (7UL) /*!< OD (Bit 7) */
#define PADS_BANK0_GPIO1_OD_Msk (0x80UL) /*!< OD (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO1_IE_Pos (6UL) /*!< IE (Bit 6) */
#define PADS_BANK0_GPIO1_IE_Msk (0x40UL) /*!< IE (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO1_DRIVE_Pos (4UL) /*!< DRIVE (Bit 4) */
#define PADS_BANK0_GPIO1_DRIVE_Msk (0x30UL) /*!< DRIVE (Bitfield-Mask: 0x03) */
#define PADS_BANK0_GPIO1_PUE_Pos (3UL) /*!< PUE (Bit 3) */
#define PADS_BANK0_GPIO1_PUE_Msk (0x8UL) /*!< PUE (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO1_PDE_Pos (2UL) /*!< PDE (Bit 2) */
#define PADS_BANK0_GPIO1_PDE_Msk (0x4UL) /*!< PDE (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO1_SCHMITT_Pos (1UL) /*!< SCHMITT (Bit 1) */
#define PADS_BANK0_GPIO1_SCHMITT_Msk (0x2UL) /*!< SCHMITT (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO1_SLEWFAST_Pos (0UL) /*!< SLEWFAST (Bit 0) */
#define PADS_BANK0_GPIO1_SLEWFAST_Msk (0x1UL) /*!< SLEWFAST (Bitfield-Mask: 0x01) */
/* ========================================================= GPIO2 ========================================================= */
#define PADS_BANK0_GPIO2_OD_Pos (7UL) /*!< OD (Bit 7) */
#define PADS_BANK0_GPIO2_OD_Msk (0x80UL) /*!< OD (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO2_IE_Pos (6UL) /*!< IE (Bit 6) */
#define PADS_BANK0_GPIO2_IE_Msk (0x40UL) /*!< IE (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO2_DRIVE_Pos (4UL) /*!< DRIVE (Bit 4) */
#define PADS_BANK0_GPIO2_DRIVE_Msk (0x30UL) /*!< DRIVE (Bitfield-Mask: 0x03) */
#define PADS_BANK0_GPIO2_PUE_Pos (3UL) /*!< PUE (Bit 3) */
#define PADS_BANK0_GPIO2_PUE_Msk (0x8UL) /*!< PUE (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO2_PDE_Pos (2UL) /*!< PDE (Bit 2) */
#define PADS_BANK0_GPIO2_PDE_Msk (0x4UL) /*!< PDE (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO2_SCHMITT_Pos (1UL) /*!< SCHMITT (Bit 1) */
#define PADS_BANK0_GPIO2_SCHMITT_Msk (0x2UL) /*!< SCHMITT (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO2_SLEWFAST_Pos (0UL) /*!< SLEWFAST (Bit 0) */
#define PADS_BANK0_GPIO2_SLEWFAST_Msk (0x1UL) /*!< SLEWFAST (Bitfield-Mask: 0x01) */
/* ========================================================= GPIO3 ========================================================= */
#define PADS_BANK0_GPIO3_OD_Pos (7UL) /*!< OD (Bit 7) */
#define PADS_BANK0_GPIO3_OD_Msk (0x80UL) /*!< OD (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO3_IE_Pos (6UL) /*!< IE (Bit 6) */
#define PADS_BANK0_GPIO3_IE_Msk (0x40UL) /*!< IE (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO3_DRIVE_Pos (4UL) /*!< DRIVE (Bit 4) */
#define PADS_BANK0_GPIO3_DRIVE_Msk (0x30UL) /*!< DRIVE (Bitfield-Mask: 0x03) */
#define PADS_BANK0_GPIO3_PUE_Pos (3UL) /*!< PUE (Bit 3) */
#define PADS_BANK0_GPIO3_PUE_Msk (0x8UL) /*!< PUE (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO3_PDE_Pos (2UL) /*!< PDE (Bit 2) */
#define PADS_BANK0_GPIO3_PDE_Msk (0x4UL) /*!< PDE (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO3_SCHMITT_Pos (1UL) /*!< SCHMITT (Bit 1) */
#define PADS_BANK0_GPIO3_SCHMITT_Msk (0x2UL) /*!< SCHMITT (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO3_SLEWFAST_Pos (0UL) /*!< SLEWFAST (Bit 0) */
#define PADS_BANK0_GPIO3_SLEWFAST_Msk (0x1UL) /*!< SLEWFAST (Bitfield-Mask: 0x01) */
/* ========================================================= GPIO4 ========================================================= */
#define PADS_BANK0_GPIO4_OD_Pos (7UL) /*!< OD (Bit 7) */
#define PADS_BANK0_GPIO4_OD_Msk (0x80UL) /*!< OD (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO4_IE_Pos (6UL) /*!< IE (Bit 6) */
#define PADS_BANK0_GPIO4_IE_Msk (0x40UL) /*!< IE (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO4_DRIVE_Pos (4UL) /*!< DRIVE (Bit 4) */
#define PADS_BANK0_GPIO4_DRIVE_Msk (0x30UL) /*!< DRIVE (Bitfield-Mask: 0x03) */
#define PADS_BANK0_GPIO4_PUE_Pos (3UL) /*!< PUE (Bit 3) */
#define PADS_BANK0_GPIO4_PUE_Msk (0x8UL) /*!< PUE (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO4_PDE_Pos (2UL) /*!< PDE (Bit 2) */
#define PADS_BANK0_GPIO4_PDE_Msk (0x4UL) /*!< PDE (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO4_SCHMITT_Pos (1UL) /*!< SCHMITT (Bit 1) */
#define PADS_BANK0_GPIO4_SCHMITT_Msk (0x2UL) /*!< SCHMITT (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO4_SLEWFAST_Pos (0UL) /*!< SLEWFAST (Bit 0) */
#define PADS_BANK0_GPIO4_SLEWFAST_Msk (0x1UL) /*!< SLEWFAST (Bitfield-Mask: 0x01) */
/* ========================================================= GPIO5 ========================================================= */
#define PADS_BANK0_GPIO5_OD_Pos (7UL) /*!< OD (Bit 7) */
#define PADS_BANK0_GPIO5_OD_Msk (0x80UL) /*!< OD (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO5_IE_Pos (6UL) /*!< IE (Bit 6) */
#define PADS_BANK0_GPIO5_IE_Msk (0x40UL) /*!< IE (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO5_DRIVE_Pos (4UL) /*!< DRIVE (Bit 4) */
#define PADS_BANK0_GPIO5_DRIVE_Msk (0x30UL) /*!< DRIVE (Bitfield-Mask: 0x03) */
#define PADS_BANK0_GPIO5_PUE_Pos (3UL) /*!< PUE (Bit 3) */
#define PADS_BANK0_GPIO5_PUE_Msk (0x8UL) /*!< PUE (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO5_PDE_Pos (2UL) /*!< PDE (Bit 2) */
#define PADS_BANK0_GPIO5_PDE_Msk (0x4UL) /*!< PDE (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO5_SCHMITT_Pos (1UL) /*!< SCHMITT (Bit 1) */
#define PADS_BANK0_GPIO5_SCHMITT_Msk (0x2UL) /*!< SCHMITT (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO5_SLEWFAST_Pos (0UL) /*!< SLEWFAST (Bit 0) */
#define PADS_BANK0_GPIO5_SLEWFAST_Msk (0x1UL) /*!< SLEWFAST (Bitfield-Mask: 0x01) */
/* ========================================================= GPIO6 ========================================================= */
#define PADS_BANK0_GPIO6_OD_Pos (7UL) /*!< OD (Bit 7) */
#define PADS_BANK0_GPIO6_OD_Msk (0x80UL) /*!< OD (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO6_IE_Pos (6UL) /*!< IE (Bit 6) */
#define PADS_BANK0_GPIO6_IE_Msk (0x40UL) /*!< IE (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO6_DRIVE_Pos (4UL) /*!< DRIVE (Bit 4) */
#define PADS_BANK0_GPIO6_DRIVE_Msk (0x30UL) /*!< DRIVE (Bitfield-Mask: 0x03) */
#define PADS_BANK0_GPIO6_PUE_Pos (3UL) /*!< PUE (Bit 3) */
#define PADS_BANK0_GPIO6_PUE_Msk (0x8UL) /*!< PUE (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO6_PDE_Pos (2UL) /*!< PDE (Bit 2) */
#define PADS_BANK0_GPIO6_PDE_Msk (0x4UL) /*!< PDE (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO6_SCHMITT_Pos (1UL) /*!< SCHMITT (Bit 1) */
#define PADS_BANK0_GPIO6_SCHMITT_Msk (0x2UL) /*!< SCHMITT (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO6_SLEWFAST_Pos (0UL) /*!< SLEWFAST (Bit 0) */
#define PADS_BANK0_GPIO6_SLEWFAST_Msk (0x1UL) /*!< SLEWFAST (Bitfield-Mask: 0x01) */
/* ========================================================= GPIO7 ========================================================= */
#define PADS_BANK0_GPIO7_OD_Pos (7UL) /*!< OD (Bit 7) */
#define PADS_BANK0_GPIO7_OD_Msk (0x80UL) /*!< OD (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO7_IE_Pos (6UL) /*!< IE (Bit 6) */
#define PADS_BANK0_GPIO7_IE_Msk (0x40UL) /*!< IE (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO7_DRIVE_Pos (4UL) /*!< DRIVE (Bit 4) */
#define PADS_BANK0_GPIO7_DRIVE_Msk (0x30UL) /*!< DRIVE (Bitfield-Mask: 0x03) */
#define PADS_BANK0_GPIO7_PUE_Pos (3UL) /*!< PUE (Bit 3) */
#define PADS_BANK0_GPIO7_PUE_Msk (0x8UL) /*!< PUE (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO7_PDE_Pos (2UL) /*!< PDE (Bit 2) */
#define PADS_BANK0_GPIO7_PDE_Msk (0x4UL) /*!< PDE (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO7_SCHMITT_Pos (1UL) /*!< SCHMITT (Bit 1) */
#define PADS_BANK0_GPIO7_SCHMITT_Msk (0x2UL) /*!< SCHMITT (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO7_SLEWFAST_Pos (0UL) /*!< SLEWFAST (Bit 0) */
#define PADS_BANK0_GPIO7_SLEWFAST_Msk (0x1UL) /*!< SLEWFAST (Bitfield-Mask: 0x01) */
/* ========================================================= GPIO8 ========================================================= */
#define PADS_BANK0_GPIO8_OD_Pos (7UL) /*!< OD (Bit 7) */
#define PADS_BANK0_GPIO8_OD_Msk (0x80UL) /*!< OD (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO8_IE_Pos (6UL) /*!< IE (Bit 6) */
#define PADS_BANK0_GPIO8_IE_Msk (0x40UL) /*!< IE (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO8_DRIVE_Pos (4UL) /*!< DRIVE (Bit 4) */
#define PADS_BANK0_GPIO8_DRIVE_Msk (0x30UL) /*!< DRIVE (Bitfield-Mask: 0x03) */
#define PADS_BANK0_GPIO8_PUE_Pos (3UL) /*!< PUE (Bit 3) */
#define PADS_BANK0_GPIO8_PUE_Msk (0x8UL) /*!< PUE (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO8_PDE_Pos (2UL) /*!< PDE (Bit 2) */
#define PADS_BANK0_GPIO8_PDE_Msk (0x4UL) /*!< PDE (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO8_SCHMITT_Pos (1UL) /*!< SCHMITT (Bit 1) */
#define PADS_BANK0_GPIO8_SCHMITT_Msk (0x2UL) /*!< SCHMITT (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO8_SLEWFAST_Pos (0UL) /*!< SLEWFAST (Bit 0) */
#define PADS_BANK0_GPIO8_SLEWFAST_Msk (0x1UL) /*!< SLEWFAST (Bitfield-Mask: 0x01) */
/* ========================================================= GPIO9 ========================================================= */
#define PADS_BANK0_GPIO9_OD_Pos (7UL) /*!< OD (Bit 7) */
#define PADS_BANK0_GPIO9_OD_Msk (0x80UL) /*!< OD (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO9_IE_Pos (6UL) /*!< IE (Bit 6) */
#define PADS_BANK0_GPIO9_IE_Msk (0x40UL) /*!< IE (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO9_DRIVE_Pos (4UL) /*!< DRIVE (Bit 4) */
#define PADS_BANK0_GPIO9_DRIVE_Msk (0x30UL) /*!< DRIVE (Bitfield-Mask: 0x03) */
#define PADS_BANK0_GPIO9_PUE_Pos (3UL) /*!< PUE (Bit 3) */
#define PADS_BANK0_GPIO9_PUE_Msk (0x8UL) /*!< PUE (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO9_PDE_Pos (2UL) /*!< PDE (Bit 2) */
#define PADS_BANK0_GPIO9_PDE_Msk (0x4UL) /*!< PDE (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO9_SCHMITT_Pos (1UL) /*!< SCHMITT (Bit 1) */
#define PADS_BANK0_GPIO9_SCHMITT_Msk (0x2UL) /*!< SCHMITT (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO9_SLEWFAST_Pos (0UL) /*!< SLEWFAST (Bit 0) */
#define PADS_BANK0_GPIO9_SLEWFAST_Msk (0x1UL) /*!< SLEWFAST (Bitfield-Mask: 0x01) */
/* ======================================================== GPIO10 ========================================================= */
#define PADS_BANK0_GPIO10_OD_Pos (7UL) /*!< OD (Bit 7) */
#define PADS_BANK0_GPIO10_OD_Msk (0x80UL) /*!< OD (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO10_IE_Pos (6UL) /*!< IE (Bit 6) */
#define PADS_BANK0_GPIO10_IE_Msk (0x40UL) /*!< IE (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO10_DRIVE_Pos (4UL) /*!< DRIVE (Bit 4) */
#define PADS_BANK0_GPIO10_DRIVE_Msk (0x30UL) /*!< DRIVE (Bitfield-Mask: 0x03) */
#define PADS_BANK0_GPIO10_PUE_Pos (3UL) /*!< PUE (Bit 3) */
#define PADS_BANK0_GPIO10_PUE_Msk (0x8UL) /*!< PUE (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO10_PDE_Pos (2UL) /*!< PDE (Bit 2) */
#define PADS_BANK0_GPIO10_PDE_Msk (0x4UL) /*!< PDE (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO10_SCHMITT_Pos (1UL) /*!< SCHMITT (Bit 1) */
#define PADS_BANK0_GPIO10_SCHMITT_Msk (0x2UL) /*!< SCHMITT (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO10_SLEWFAST_Pos (0UL) /*!< SLEWFAST (Bit 0) */
#define PADS_BANK0_GPIO10_SLEWFAST_Msk (0x1UL) /*!< SLEWFAST (Bitfield-Mask: 0x01) */
/* ======================================================== GPIO11 ========================================================= */
#define PADS_BANK0_GPIO11_OD_Pos (7UL) /*!< OD (Bit 7) */
#define PADS_BANK0_GPIO11_OD_Msk (0x80UL) /*!< OD (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO11_IE_Pos (6UL) /*!< IE (Bit 6) */
#define PADS_BANK0_GPIO11_IE_Msk (0x40UL) /*!< IE (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO11_DRIVE_Pos (4UL) /*!< DRIVE (Bit 4) */
#define PADS_BANK0_GPIO11_DRIVE_Msk (0x30UL) /*!< DRIVE (Bitfield-Mask: 0x03) */
#define PADS_BANK0_GPIO11_PUE_Pos (3UL) /*!< PUE (Bit 3) */
#define PADS_BANK0_GPIO11_PUE_Msk (0x8UL) /*!< PUE (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO11_PDE_Pos (2UL) /*!< PDE (Bit 2) */
#define PADS_BANK0_GPIO11_PDE_Msk (0x4UL) /*!< PDE (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO11_SCHMITT_Pos (1UL) /*!< SCHMITT (Bit 1) */
#define PADS_BANK0_GPIO11_SCHMITT_Msk (0x2UL) /*!< SCHMITT (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO11_SLEWFAST_Pos (0UL) /*!< SLEWFAST (Bit 0) */
#define PADS_BANK0_GPIO11_SLEWFAST_Msk (0x1UL) /*!< SLEWFAST (Bitfield-Mask: 0x01) */
/* ======================================================== GPIO12 ========================================================= */
#define PADS_BANK0_GPIO12_OD_Pos (7UL) /*!< OD (Bit 7) */
#define PADS_BANK0_GPIO12_OD_Msk (0x80UL) /*!< OD (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO12_IE_Pos (6UL) /*!< IE (Bit 6) */
#define PADS_BANK0_GPIO12_IE_Msk (0x40UL) /*!< IE (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO12_DRIVE_Pos (4UL) /*!< DRIVE (Bit 4) */
#define PADS_BANK0_GPIO12_DRIVE_Msk (0x30UL) /*!< DRIVE (Bitfield-Mask: 0x03) */
#define PADS_BANK0_GPIO12_PUE_Pos (3UL) /*!< PUE (Bit 3) */
#define PADS_BANK0_GPIO12_PUE_Msk (0x8UL) /*!< PUE (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO12_PDE_Pos (2UL) /*!< PDE (Bit 2) */
#define PADS_BANK0_GPIO12_PDE_Msk (0x4UL) /*!< PDE (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO12_SCHMITT_Pos (1UL) /*!< SCHMITT (Bit 1) */
#define PADS_BANK0_GPIO12_SCHMITT_Msk (0x2UL) /*!< SCHMITT (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO12_SLEWFAST_Pos (0UL) /*!< SLEWFAST (Bit 0) */
#define PADS_BANK0_GPIO12_SLEWFAST_Msk (0x1UL) /*!< SLEWFAST (Bitfield-Mask: 0x01) */
/* ======================================================== GPIO13 ========================================================= */
#define PADS_BANK0_GPIO13_OD_Pos (7UL) /*!< OD (Bit 7) */
#define PADS_BANK0_GPIO13_OD_Msk (0x80UL) /*!< OD (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO13_IE_Pos (6UL) /*!< IE (Bit 6) */
#define PADS_BANK0_GPIO13_IE_Msk (0x40UL) /*!< IE (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO13_DRIVE_Pos (4UL) /*!< DRIVE (Bit 4) */
#define PADS_BANK0_GPIO13_DRIVE_Msk (0x30UL) /*!< DRIVE (Bitfield-Mask: 0x03) */
#define PADS_BANK0_GPIO13_PUE_Pos (3UL) /*!< PUE (Bit 3) */
#define PADS_BANK0_GPIO13_PUE_Msk (0x8UL) /*!< PUE (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO13_PDE_Pos (2UL) /*!< PDE (Bit 2) */
#define PADS_BANK0_GPIO13_PDE_Msk (0x4UL) /*!< PDE (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO13_SCHMITT_Pos (1UL) /*!< SCHMITT (Bit 1) */
#define PADS_BANK0_GPIO13_SCHMITT_Msk (0x2UL) /*!< SCHMITT (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO13_SLEWFAST_Pos (0UL) /*!< SLEWFAST (Bit 0) */
#define PADS_BANK0_GPIO13_SLEWFAST_Msk (0x1UL) /*!< SLEWFAST (Bitfield-Mask: 0x01) */
/* ======================================================== GPIO14 ========================================================= */
#define PADS_BANK0_GPIO14_OD_Pos (7UL) /*!< OD (Bit 7) */
#define PADS_BANK0_GPIO14_OD_Msk (0x80UL) /*!< OD (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO14_IE_Pos (6UL) /*!< IE (Bit 6) */
#define PADS_BANK0_GPIO14_IE_Msk (0x40UL) /*!< IE (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO14_DRIVE_Pos (4UL) /*!< DRIVE (Bit 4) */
#define PADS_BANK0_GPIO14_DRIVE_Msk (0x30UL) /*!< DRIVE (Bitfield-Mask: 0x03) */
#define PADS_BANK0_GPIO14_PUE_Pos (3UL) /*!< PUE (Bit 3) */
#define PADS_BANK0_GPIO14_PUE_Msk (0x8UL) /*!< PUE (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO14_PDE_Pos (2UL) /*!< PDE (Bit 2) */
#define PADS_BANK0_GPIO14_PDE_Msk (0x4UL) /*!< PDE (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO14_SCHMITT_Pos (1UL) /*!< SCHMITT (Bit 1) */
#define PADS_BANK0_GPIO14_SCHMITT_Msk (0x2UL) /*!< SCHMITT (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO14_SLEWFAST_Pos (0UL) /*!< SLEWFAST (Bit 0) */
#define PADS_BANK0_GPIO14_SLEWFAST_Msk (0x1UL) /*!< SLEWFAST (Bitfield-Mask: 0x01) */
/* ======================================================== GPIO15 ========================================================= */
#define PADS_BANK0_GPIO15_OD_Pos (7UL) /*!< OD (Bit 7) */
#define PADS_BANK0_GPIO15_OD_Msk (0x80UL) /*!< OD (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO15_IE_Pos (6UL) /*!< IE (Bit 6) */
#define PADS_BANK0_GPIO15_IE_Msk (0x40UL) /*!< IE (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO15_DRIVE_Pos (4UL) /*!< DRIVE (Bit 4) */
#define PADS_BANK0_GPIO15_DRIVE_Msk (0x30UL) /*!< DRIVE (Bitfield-Mask: 0x03) */
#define PADS_BANK0_GPIO15_PUE_Pos (3UL) /*!< PUE (Bit 3) */
#define PADS_BANK0_GPIO15_PUE_Msk (0x8UL) /*!< PUE (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO15_PDE_Pos (2UL) /*!< PDE (Bit 2) */
#define PADS_BANK0_GPIO15_PDE_Msk (0x4UL) /*!< PDE (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO15_SCHMITT_Pos (1UL) /*!< SCHMITT (Bit 1) */
#define PADS_BANK0_GPIO15_SCHMITT_Msk (0x2UL) /*!< SCHMITT (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO15_SLEWFAST_Pos (0UL) /*!< SLEWFAST (Bit 0) */
#define PADS_BANK0_GPIO15_SLEWFAST_Msk (0x1UL) /*!< SLEWFAST (Bitfield-Mask: 0x01) */
/* ======================================================== GPIO16 ========================================================= */
#define PADS_BANK0_GPIO16_OD_Pos (7UL) /*!< OD (Bit 7) */
#define PADS_BANK0_GPIO16_OD_Msk (0x80UL) /*!< OD (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO16_IE_Pos (6UL) /*!< IE (Bit 6) */
#define PADS_BANK0_GPIO16_IE_Msk (0x40UL) /*!< IE (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO16_DRIVE_Pos (4UL) /*!< DRIVE (Bit 4) */
#define PADS_BANK0_GPIO16_DRIVE_Msk (0x30UL) /*!< DRIVE (Bitfield-Mask: 0x03) */
#define PADS_BANK0_GPIO16_PUE_Pos (3UL) /*!< PUE (Bit 3) */
#define PADS_BANK0_GPIO16_PUE_Msk (0x8UL) /*!< PUE (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO16_PDE_Pos (2UL) /*!< PDE (Bit 2) */
#define PADS_BANK0_GPIO16_PDE_Msk (0x4UL) /*!< PDE (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO16_SCHMITT_Pos (1UL) /*!< SCHMITT (Bit 1) */
#define PADS_BANK0_GPIO16_SCHMITT_Msk (0x2UL) /*!< SCHMITT (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO16_SLEWFAST_Pos (0UL) /*!< SLEWFAST (Bit 0) */
#define PADS_BANK0_GPIO16_SLEWFAST_Msk (0x1UL) /*!< SLEWFAST (Bitfield-Mask: 0x01) */
/* ======================================================== GPIO17 ========================================================= */
#define PADS_BANK0_GPIO17_OD_Pos (7UL) /*!< OD (Bit 7) */
#define PADS_BANK0_GPIO17_OD_Msk (0x80UL) /*!< OD (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO17_IE_Pos (6UL) /*!< IE (Bit 6) */
#define PADS_BANK0_GPIO17_IE_Msk (0x40UL) /*!< IE (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO17_DRIVE_Pos (4UL) /*!< DRIVE (Bit 4) */
#define PADS_BANK0_GPIO17_DRIVE_Msk (0x30UL) /*!< DRIVE (Bitfield-Mask: 0x03) */
#define PADS_BANK0_GPIO17_PUE_Pos (3UL) /*!< PUE (Bit 3) */
#define PADS_BANK0_GPIO17_PUE_Msk (0x8UL) /*!< PUE (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO17_PDE_Pos (2UL) /*!< PDE (Bit 2) */
#define PADS_BANK0_GPIO17_PDE_Msk (0x4UL) /*!< PDE (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO17_SCHMITT_Pos (1UL) /*!< SCHMITT (Bit 1) */
#define PADS_BANK0_GPIO17_SCHMITT_Msk (0x2UL) /*!< SCHMITT (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO17_SLEWFAST_Pos (0UL) /*!< SLEWFAST (Bit 0) */
#define PADS_BANK0_GPIO17_SLEWFAST_Msk (0x1UL) /*!< SLEWFAST (Bitfield-Mask: 0x01) */
/* ======================================================== GPIO18 ========================================================= */
#define PADS_BANK0_GPIO18_OD_Pos (7UL) /*!< OD (Bit 7) */
#define PADS_BANK0_GPIO18_OD_Msk (0x80UL) /*!< OD (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO18_IE_Pos (6UL) /*!< IE (Bit 6) */
#define PADS_BANK0_GPIO18_IE_Msk (0x40UL) /*!< IE (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO18_DRIVE_Pos (4UL) /*!< DRIVE (Bit 4) */
#define PADS_BANK0_GPIO18_DRIVE_Msk (0x30UL) /*!< DRIVE (Bitfield-Mask: 0x03) */
#define PADS_BANK0_GPIO18_PUE_Pos (3UL) /*!< PUE (Bit 3) */
#define PADS_BANK0_GPIO18_PUE_Msk (0x8UL) /*!< PUE (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO18_PDE_Pos (2UL) /*!< PDE (Bit 2) */
#define PADS_BANK0_GPIO18_PDE_Msk (0x4UL) /*!< PDE (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO18_SCHMITT_Pos (1UL) /*!< SCHMITT (Bit 1) */
#define PADS_BANK0_GPIO18_SCHMITT_Msk (0x2UL) /*!< SCHMITT (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO18_SLEWFAST_Pos (0UL) /*!< SLEWFAST (Bit 0) */
#define PADS_BANK0_GPIO18_SLEWFAST_Msk (0x1UL) /*!< SLEWFAST (Bitfield-Mask: 0x01) */
/* ======================================================== GPIO19 ========================================================= */
#define PADS_BANK0_GPIO19_OD_Pos (7UL) /*!< OD (Bit 7) */
#define PADS_BANK0_GPIO19_OD_Msk (0x80UL) /*!< OD (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO19_IE_Pos (6UL) /*!< IE (Bit 6) */
#define PADS_BANK0_GPIO19_IE_Msk (0x40UL) /*!< IE (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO19_DRIVE_Pos (4UL) /*!< DRIVE (Bit 4) */
#define PADS_BANK0_GPIO19_DRIVE_Msk (0x30UL) /*!< DRIVE (Bitfield-Mask: 0x03) */
#define PADS_BANK0_GPIO19_PUE_Pos (3UL) /*!< PUE (Bit 3) */
#define PADS_BANK0_GPIO19_PUE_Msk (0x8UL) /*!< PUE (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO19_PDE_Pos (2UL) /*!< PDE (Bit 2) */
#define PADS_BANK0_GPIO19_PDE_Msk (0x4UL) /*!< PDE (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO19_SCHMITT_Pos (1UL) /*!< SCHMITT (Bit 1) */
#define PADS_BANK0_GPIO19_SCHMITT_Msk (0x2UL) /*!< SCHMITT (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO19_SLEWFAST_Pos (0UL) /*!< SLEWFAST (Bit 0) */
#define PADS_BANK0_GPIO19_SLEWFAST_Msk (0x1UL) /*!< SLEWFAST (Bitfield-Mask: 0x01) */
/* ======================================================== GPIO20 ========================================================= */
#define PADS_BANK0_GPIO20_OD_Pos (7UL) /*!< OD (Bit 7) */
#define PADS_BANK0_GPIO20_OD_Msk (0x80UL) /*!< OD (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO20_IE_Pos (6UL) /*!< IE (Bit 6) */
#define PADS_BANK0_GPIO20_IE_Msk (0x40UL) /*!< IE (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO20_DRIVE_Pos (4UL) /*!< DRIVE (Bit 4) */
#define PADS_BANK0_GPIO20_DRIVE_Msk (0x30UL) /*!< DRIVE (Bitfield-Mask: 0x03) */
#define PADS_BANK0_GPIO20_PUE_Pos (3UL) /*!< PUE (Bit 3) */
#define PADS_BANK0_GPIO20_PUE_Msk (0x8UL) /*!< PUE (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO20_PDE_Pos (2UL) /*!< PDE (Bit 2) */
#define PADS_BANK0_GPIO20_PDE_Msk (0x4UL) /*!< PDE (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO20_SCHMITT_Pos (1UL) /*!< SCHMITT (Bit 1) */
#define PADS_BANK0_GPIO20_SCHMITT_Msk (0x2UL) /*!< SCHMITT (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO20_SLEWFAST_Pos (0UL) /*!< SLEWFAST (Bit 0) */
#define PADS_BANK0_GPIO20_SLEWFAST_Msk (0x1UL) /*!< SLEWFAST (Bitfield-Mask: 0x01) */
/* ======================================================== GPIO21 ========================================================= */
#define PADS_BANK0_GPIO21_OD_Pos (7UL) /*!< OD (Bit 7) */
#define PADS_BANK0_GPIO21_OD_Msk (0x80UL) /*!< OD (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO21_IE_Pos (6UL) /*!< IE (Bit 6) */
#define PADS_BANK0_GPIO21_IE_Msk (0x40UL) /*!< IE (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO21_DRIVE_Pos (4UL) /*!< DRIVE (Bit 4) */
#define PADS_BANK0_GPIO21_DRIVE_Msk (0x30UL) /*!< DRIVE (Bitfield-Mask: 0x03) */
#define PADS_BANK0_GPIO21_PUE_Pos (3UL) /*!< PUE (Bit 3) */
#define PADS_BANK0_GPIO21_PUE_Msk (0x8UL) /*!< PUE (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO21_PDE_Pos (2UL) /*!< PDE (Bit 2) */
#define PADS_BANK0_GPIO21_PDE_Msk (0x4UL) /*!< PDE (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO21_SCHMITT_Pos (1UL) /*!< SCHMITT (Bit 1) */
#define PADS_BANK0_GPIO21_SCHMITT_Msk (0x2UL) /*!< SCHMITT (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO21_SLEWFAST_Pos (0UL) /*!< SLEWFAST (Bit 0) */
#define PADS_BANK0_GPIO21_SLEWFAST_Msk (0x1UL) /*!< SLEWFAST (Bitfield-Mask: 0x01) */
/* ======================================================== GPIO22 ========================================================= */
#define PADS_BANK0_GPIO22_OD_Pos (7UL) /*!< OD (Bit 7) */
#define PADS_BANK0_GPIO22_OD_Msk (0x80UL) /*!< OD (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO22_IE_Pos (6UL) /*!< IE (Bit 6) */
#define PADS_BANK0_GPIO22_IE_Msk (0x40UL) /*!< IE (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO22_DRIVE_Pos (4UL) /*!< DRIVE (Bit 4) */
#define PADS_BANK0_GPIO22_DRIVE_Msk (0x30UL) /*!< DRIVE (Bitfield-Mask: 0x03) */
#define PADS_BANK0_GPIO22_PUE_Pos (3UL) /*!< PUE (Bit 3) */
#define PADS_BANK0_GPIO22_PUE_Msk (0x8UL) /*!< PUE (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO22_PDE_Pos (2UL) /*!< PDE (Bit 2) */
#define PADS_BANK0_GPIO22_PDE_Msk (0x4UL) /*!< PDE (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO22_SCHMITT_Pos (1UL) /*!< SCHMITT (Bit 1) */
#define PADS_BANK0_GPIO22_SCHMITT_Msk (0x2UL) /*!< SCHMITT (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO22_SLEWFAST_Pos (0UL) /*!< SLEWFAST (Bit 0) */
#define PADS_BANK0_GPIO22_SLEWFAST_Msk (0x1UL) /*!< SLEWFAST (Bitfield-Mask: 0x01) */
/* ======================================================== GPIO23 ========================================================= */
#define PADS_BANK0_GPIO23_OD_Pos (7UL) /*!< OD (Bit 7) */
#define PADS_BANK0_GPIO23_OD_Msk (0x80UL) /*!< OD (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO23_IE_Pos (6UL) /*!< IE (Bit 6) */
#define PADS_BANK0_GPIO23_IE_Msk (0x40UL) /*!< IE (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO23_DRIVE_Pos (4UL) /*!< DRIVE (Bit 4) */
#define PADS_BANK0_GPIO23_DRIVE_Msk (0x30UL) /*!< DRIVE (Bitfield-Mask: 0x03) */
#define PADS_BANK0_GPIO23_PUE_Pos (3UL) /*!< PUE (Bit 3) */
#define PADS_BANK0_GPIO23_PUE_Msk (0x8UL) /*!< PUE (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO23_PDE_Pos (2UL) /*!< PDE (Bit 2) */
#define PADS_BANK0_GPIO23_PDE_Msk (0x4UL) /*!< PDE (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO23_SCHMITT_Pos (1UL) /*!< SCHMITT (Bit 1) */
#define PADS_BANK0_GPIO23_SCHMITT_Msk (0x2UL) /*!< SCHMITT (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO23_SLEWFAST_Pos (0UL) /*!< SLEWFAST (Bit 0) */
#define PADS_BANK0_GPIO23_SLEWFAST_Msk (0x1UL) /*!< SLEWFAST (Bitfield-Mask: 0x01) */
/* ======================================================== GPIO24 ========================================================= */
#define PADS_BANK0_GPIO24_OD_Pos (7UL) /*!< OD (Bit 7) */
#define PADS_BANK0_GPIO24_OD_Msk (0x80UL) /*!< OD (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO24_IE_Pos (6UL) /*!< IE (Bit 6) */
#define PADS_BANK0_GPIO24_IE_Msk (0x40UL) /*!< IE (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO24_DRIVE_Pos (4UL) /*!< DRIVE (Bit 4) */
#define PADS_BANK0_GPIO24_DRIVE_Msk (0x30UL) /*!< DRIVE (Bitfield-Mask: 0x03) */
#define PADS_BANK0_GPIO24_PUE_Pos (3UL) /*!< PUE (Bit 3) */
#define PADS_BANK0_GPIO24_PUE_Msk (0x8UL) /*!< PUE (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO24_PDE_Pos (2UL) /*!< PDE (Bit 2) */
#define PADS_BANK0_GPIO24_PDE_Msk (0x4UL) /*!< PDE (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO24_SCHMITT_Pos (1UL) /*!< SCHMITT (Bit 1) */
#define PADS_BANK0_GPIO24_SCHMITT_Msk (0x2UL) /*!< SCHMITT (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO24_SLEWFAST_Pos (0UL) /*!< SLEWFAST (Bit 0) */
#define PADS_BANK0_GPIO24_SLEWFAST_Msk (0x1UL) /*!< SLEWFAST (Bitfield-Mask: 0x01) */
/* ======================================================== GPIO25 ========================================================= */
#define PADS_BANK0_GPIO25_OD_Pos (7UL) /*!< OD (Bit 7) */
#define PADS_BANK0_GPIO25_OD_Msk (0x80UL) /*!< OD (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO25_IE_Pos (6UL) /*!< IE (Bit 6) */
#define PADS_BANK0_GPIO25_IE_Msk (0x40UL) /*!< IE (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO25_DRIVE_Pos (4UL) /*!< DRIVE (Bit 4) */
#define PADS_BANK0_GPIO25_DRIVE_Msk (0x30UL) /*!< DRIVE (Bitfield-Mask: 0x03) */
#define PADS_BANK0_GPIO25_PUE_Pos (3UL) /*!< PUE (Bit 3) */
#define PADS_BANK0_GPIO25_PUE_Msk (0x8UL) /*!< PUE (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO25_PDE_Pos (2UL) /*!< PDE (Bit 2) */
#define PADS_BANK0_GPIO25_PDE_Msk (0x4UL) /*!< PDE (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO25_SCHMITT_Pos (1UL) /*!< SCHMITT (Bit 1) */
#define PADS_BANK0_GPIO25_SCHMITT_Msk (0x2UL) /*!< SCHMITT (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO25_SLEWFAST_Pos (0UL) /*!< SLEWFAST (Bit 0) */
#define PADS_BANK0_GPIO25_SLEWFAST_Msk (0x1UL) /*!< SLEWFAST (Bitfield-Mask: 0x01) */
/* ======================================================== GPIO26 ========================================================= */
#define PADS_BANK0_GPIO26_OD_Pos (7UL) /*!< OD (Bit 7) */
#define PADS_BANK0_GPIO26_OD_Msk (0x80UL) /*!< OD (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO26_IE_Pos (6UL) /*!< IE (Bit 6) */
#define PADS_BANK0_GPIO26_IE_Msk (0x40UL) /*!< IE (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO26_DRIVE_Pos (4UL) /*!< DRIVE (Bit 4) */
#define PADS_BANK0_GPIO26_DRIVE_Msk (0x30UL) /*!< DRIVE (Bitfield-Mask: 0x03) */
#define PADS_BANK0_GPIO26_PUE_Pos (3UL) /*!< PUE (Bit 3) */
#define PADS_BANK0_GPIO26_PUE_Msk (0x8UL) /*!< PUE (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO26_PDE_Pos (2UL) /*!< PDE (Bit 2) */
#define PADS_BANK0_GPIO26_PDE_Msk (0x4UL) /*!< PDE (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO26_SCHMITT_Pos (1UL) /*!< SCHMITT (Bit 1) */
#define PADS_BANK0_GPIO26_SCHMITT_Msk (0x2UL) /*!< SCHMITT (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO26_SLEWFAST_Pos (0UL) /*!< SLEWFAST (Bit 0) */
#define PADS_BANK0_GPIO26_SLEWFAST_Msk (0x1UL) /*!< SLEWFAST (Bitfield-Mask: 0x01) */
/* ======================================================== GPIO27 ========================================================= */
#define PADS_BANK0_GPIO27_OD_Pos (7UL) /*!< OD (Bit 7) */
#define PADS_BANK0_GPIO27_OD_Msk (0x80UL) /*!< OD (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO27_IE_Pos (6UL) /*!< IE (Bit 6) */
#define PADS_BANK0_GPIO27_IE_Msk (0x40UL) /*!< IE (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO27_DRIVE_Pos (4UL) /*!< DRIVE (Bit 4) */
#define PADS_BANK0_GPIO27_DRIVE_Msk (0x30UL) /*!< DRIVE (Bitfield-Mask: 0x03) */
#define PADS_BANK0_GPIO27_PUE_Pos (3UL) /*!< PUE (Bit 3) */
#define PADS_BANK0_GPIO27_PUE_Msk (0x8UL) /*!< PUE (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO27_PDE_Pos (2UL) /*!< PDE (Bit 2) */
#define PADS_BANK0_GPIO27_PDE_Msk (0x4UL) /*!< PDE (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO27_SCHMITT_Pos (1UL) /*!< SCHMITT (Bit 1) */
#define PADS_BANK0_GPIO27_SCHMITT_Msk (0x2UL) /*!< SCHMITT (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO27_SLEWFAST_Pos (0UL) /*!< SLEWFAST (Bit 0) */
#define PADS_BANK0_GPIO27_SLEWFAST_Msk (0x1UL) /*!< SLEWFAST (Bitfield-Mask: 0x01) */
/* ======================================================== GPIO28 ========================================================= */
#define PADS_BANK0_GPIO28_OD_Pos (7UL) /*!< OD (Bit 7) */
#define PADS_BANK0_GPIO28_OD_Msk (0x80UL) /*!< OD (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO28_IE_Pos (6UL) /*!< IE (Bit 6) */
#define PADS_BANK0_GPIO28_IE_Msk (0x40UL) /*!< IE (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO28_DRIVE_Pos (4UL) /*!< DRIVE (Bit 4) */
#define PADS_BANK0_GPIO28_DRIVE_Msk (0x30UL) /*!< DRIVE (Bitfield-Mask: 0x03) */
#define PADS_BANK0_GPIO28_PUE_Pos (3UL) /*!< PUE (Bit 3) */
#define PADS_BANK0_GPIO28_PUE_Msk (0x8UL) /*!< PUE (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO28_PDE_Pos (2UL) /*!< PDE (Bit 2) */
#define PADS_BANK0_GPIO28_PDE_Msk (0x4UL) /*!< PDE (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO28_SCHMITT_Pos (1UL) /*!< SCHMITT (Bit 1) */
#define PADS_BANK0_GPIO28_SCHMITT_Msk (0x2UL) /*!< SCHMITT (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO28_SLEWFAST_Pos (0UL) /*!< SLEWFAST (Bit 0) */
#define PADS_BANK0_GPIO28_SLEWFAST_Msk (0x1UL) /*!< SLEWFAST (Bitfield-Mask: 0x01) */
/* ======================================================== GPIO29 ========================================================= */
#define PADS_BANK0_GPIO29_OD_Pos (7UL) /*!< OD (Bit 7) */
#define PADS_BANK0_GPIO29_OD_Msk (0x80UL) /*!< OD (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO29_IE_Pos (6UL) /*!< IE (Bit 6) */
#define PADS_BANK0_GPIO29_IE_Msk (0x40UL) /*!< IE (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO29_DRIVE_Pos (4UL) /*!< DRIVE (Bit 4) */
#define PADS_BANK0_GPIO29_DRIVE_Msk (0x30UL) /*!< DRIVE (Bitfield-Mask: 0x03) */
#define PADS_BANK0_GPIO29_PUE_Pos (3UL) /*!< PUE (Bit 3) */
#define PADS_BANK0_GPIO29_PUE_Msk (0x8UL) /*!< PUE (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO29_PDE_Pos (2UL) /*!< PDE (Bit 2) */
#define PADS_BANK0_GPIO29_PDE_Msk (0x4UL) /*!< PDE (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO29_SCHMITT_Pos (1UL) /*!< SCHMITT (Bit 1) */
#define PADS_BANK0_GPIO29_SCHMITT_Msk (0x2UL) /*!< SCHMITT (Bitfield-Mask: 0x01) */
#define PADS_BANK0_GPIO29_SLEWFAST_Pos (0UL) /*!< SLEWFAST (Bit 0) */
#define PADS_BANK0_GPIO29_SLEWFAST_Msk (0x1UL) /*!< SLEWFAST (Bitfield-Mask: 0x01) */
/* ========================================================= SWCLK ========================================================= */
#define PADS_BANK0_SWCLK_OD_Pos (7UL) /*!< OD (Bit 7) */
#define PADS_BANK0_SWCLK_OD_Msk (0x80UL) /*!< OD (Bitfield-Mask: 0x01) */
#define PADS_BANK0_SWCLK_IE_Pos (6UL) /*!< IE (Bit 6) */
#define PADS_BANK0_SWCLK_IE_Msk (0x40UL) /*!< IE (Bitfield-Mask: 0x01) */
#define PADS_BANK0_SWCLK_DRIVE_Pos (4UL) /*!< DRIVE (Bit 4) */
#define PADS_BANK0_SWCLK_DRIVE_Msk (0x30UL) /*!< DRIVE (Bitfield-Mask: 0x03) */
#define PADS_BANK0_SWCLK_PUE_Pos (3UL) /*!< PUE (Bit 3) */
#define PADS_BANK0_SWCLK_PUE_Msk (0x8UL) /*!< PUE (Bitfield-Mask: 0x01) */
#define PADS_BANK0_SWCLK_PDE_Pos (2UL) /*!< PDE (Bit 2) */
#define PADS_BANK0_SWCLK_PDE_Msk (0x4UL) /*!< PDE (Bitfield-Mask: 0x01) */
#define PADS_BANK0_SWCLK_SCHMITT_Pos (1UL) /*!< SCHMITT (Bit 1) */
#define PADS_BANK0_SWCLK_SCHMITT_Msk (0x2UL) /*!< SCHMITT (Bitfield-Mask: 0x01) */
#define PADS_BANK0_SWCLK_SLEWFAST_Pos (0UL) /*!< SLEWFAST (Bit 0) */
#define PADS_BANK0_SWCLK_SLEWFAST_Msk (0x1UL) /*!< SLEWFAST (Bitfield-Mask: 0x01) */
/* ========================================================== SWD ========================================================== */
#define PADS_BANK0_SWD_OD_Pos (7UL) /*!< OD (Bit 7) */
#define PADS_BANK0_SWD_OD_Msk (0x80UL) /*!< OD (Bitfield-Mask: 0x01) */
#define PADS_BANK0_SWD_IE_Pos (6UL) /*!< IE (Bit 6) */
#define PADS_BANK0_SWD_IE_Msk (0x40UL) /*!< IE (Bitfield-Mask: 0x01) */
#define PADS_BANK0_SWD_DRIVE_Pos (4UL) /*!< DRIVE (Bit 4) */
#define PADS_BANK0_SWD_DRIVE_Msk (0x30UL) /*!< DRIVE (Bitfield-Mask: 0x03) */
#define PADS_BANK0_SWD_PUE_Pos (3UL) /*!< PUE (Bit 3) */
#define PADS_BANK0_SWD_PUE_Msk (0x8UL) /*!< PUE (Bitfield-Mask: 0x01) */
#define PADS_BANK0_SWD_PDE_Pos (2UL) /*!< PDE (Bit 2) */
#define PADS_BANK0_SWD_PDE_Msk (0x4UL) /*!< PDE (Bitfield-Mask: 0x01) */
#define PADS_BANK0_SWD_SCHMITT_Pos (1UL) /*!< SCHMITT (Bit 1) */
#define PADS_BANK0_SWD_SCHMITT_Msk (0x2UL) /*!< SCHMITT (Bitfield-Mask: 0x01) */
#define PADS_BANK0_SWD_SLEWFAST_Pos (0UL) /*!< SLEWFAST (Bit 0) */
#define PADS_BANK0_SWD_SLEWFAST_Msk (0x1UL) /*!< SLEWFAST (Bitfield-Mask: 0x01) */
/* =========================================================================================================================== */
/* ================ PADS_QSPI ================ */
/* =========================================================================================================================== */
/* ==================================================== VOLTAGE_SELECT ===================================================== */
#define PADS_QSPI_VOLTAGE_SELECT_VOLTAGE_SELECT_Pos (0UL) /*!< VOLTAGE_SELECT (Bit 0) */
#define PADS_QSPI_VOLTAGE_SELECT_VOLTAGE_SELECT_Msk (0x1UL) /*!< VOLTAGE_SELECT (Bitfield-Mask: 0x01) */
/* ==================================================== GPIO_QSPI_SCLK ===================================================== */
#define PADS_QSPI_GPIO_QSPI_SCLK_OD_Pos (7UL) /*!< OD (Bit 7) */
#define PADS_QSPI_GPIO_QSPI_SCLK_OD_Msk (0x80UL) /*!< OD (Bitfield-Mask: 0x01) */
#define PADS_QSPI_GPIO_QSPI_SCLK_IE_Pos (6UL) /*!< IE (Bit 6) */
#define PADS_QSPI_GPIO_QSPI_SCLK_IE_Msk (0x40UL) /*!< IE (Bitfield-Mask: 0x01) */
#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_Pos (4UL) /*!< DRIVE (Bit 4) */
#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_Msk (0x30UL) /*!< DRIVE (Bitfield-Mask: 0x03) */
#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_Pos (3UL) /*!< PUE (Bit 3) */
#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_Msk (0x8UL) /*!< PUE (Bitfield-Mask: 0x01) */
#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_Pos (2UL) /*!< PDE (Bit 2) */
#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_Msk (0x4UL) /*!< PDE (Bitfield-Mask: 0x01) */
#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_Pos (1UL) /*!< SCHMITT (Bit 1) */
#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_Msk (0x2UL) /*!< SCHMITT (Bitfield-Mask: 0x01) */
#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_Pos (0UL) /*!< SLEWFAST (Bit 0) */
#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_Msk (0x1UL) /*!< SLEWFAST (Bitfield-Mask: 0x01) */
/* ===================================================== GPIO_QSPI_SD0 ===================================================== */
#define PADS_QSPI_GPIO_QSPI_SD0_OD_Pos (7UL) /*!< OD (Bit 7) */
#define PADS_QSPI_GPIO_QSPI_SD0_OD_Msk (0x80UL) /*!< OD (Bitfield-Mask: 0x01) */
#define PADS_QSPI_GPIO_QSPI_SD0_IE_Pos (6UL) /*!< IE (Bit 6) */
#define PADS_QSPI_GPIO_QSPI_SD0_IE_Msk (0x40UL) /*!< IE (Bitfield-Mask: 0x01) */
#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_Pos (4UL) /*!< DRIVE (Bit 4) */
#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_Msk (0x30UL) /*!< DRIVE (Bitfield-Mask: 0x03) */
#define PADS_QSPI_GPIO_QSPI_SD0_PUE_Pos (3UL) /*!< PUE (Bit 3) */
#define PADS_QSPI_GPIO_QSPI_SD0_PUE_Msk (0x8UL) /*!< PUE (Bitfield-Mask: 0x01) */
#define PADS_QSPI_GPIO_QSPI_SD0_PDE_Pos (2UL) /*!< PDE (Bit 2) */
#define PADS_QSPI_GPIO_QSPI_SD0_PDE_Msk (0x4UL) /*!< PDE (Bitfield-Mask: 0x01) */
#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_Pos (1UL) /*!< SCHMITT (Bit 1) */
#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_Msk (0x2UL) /*!< SCHMITT (Bitfield-Mask: 0x01) */
#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_Pos (0UL) /*!< SLEWFAST (Bit 0) */
#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_Msk (0x1UL) /*!< SLEWFAST (Bitfield-Mask: 0x01) */
/* ===================================================== GPIO_QSPI_SD1 ===================================================== */
#define PADS_QSPI_GPIO_QSPI_SD1_OD_Pos (7UL) /*!< OD (Bit 7) */
#define PADS_QSPI_GPIO_QSPI_SD1_OD_Msk (0x80UL) /*!< OD (Bitfield-Mask: 0x01) */
#define PADS_QSPI_GPIO_QSPI_SD1_IE_Pos (6UL) /*!< IE (Bit 6) */
#define PADS_QSPI_GPIO_QSPI_SD1_IE_Msk (0x40UL) /*!< IE (Bitfield-Mask: 0x01) */
#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_Pos (4UL) /*!< DRIVE (Bit 4) */
#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_Msk (0x30UL) /*!< DRIVE (Bitfield-Mask: 0x03) */
#define PADS_QSPI_GPIO_QSPI_SD1_PUE_Pos (3UL) /*!< PUE (Bit 3) */
#define PADS_QSPI_GPIO_QSPI_SD1_PUE_Msk (0x8UL) /*!< PUE (Bitfield-Mask: 0x01) */
#define PADS_QSPI_GPIO_QSPI_SD1_PDE_Pos (2UL) /*!< PDE (Bit 2) */
#define PADS_QSPI_GPIO_QSPI_SD1_PDE_Msk (0x4UL) /*!< PDE (Bitfield-Mask: 0x01) */
#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_Pos (1UL) /*!< SCHMITT (Bit 1) */
#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_Msk (0x2UL) /*!< SCHMITT (Bitfield-Mask: 0x01) */
#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_Pos (0UL) /*!< SLEWFAST (Bit 0) */
#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_Msk (0x1UL) /*!< SLEWFAST (Bitfield-Mask: 0x01) */
/* ===================================================== GPIO_QSPI_SD2 ===================================================== */
#define PADS_QSPI_GPIO_QSPI_SD2_OD_Pos (7UL) /*!< OD (Bit 7) */
#define PADS_QSPI_GPIO_QSPI_SD2_OD_Msk (0x80UL) /*!< OD (Bitfield-Mask: 0x01) */
#define PADS_QSPI_GPIO_QSPI_SD2_IE_Pos (6UL) /*!< IE (Bit 6) */
#define PADS_QSPI_GPIO_QSPI_SD2_IE_Msk (0x40UL) /*!< IE (Bitfield-Mask: 0x01) */
#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_Pos (4UL) /*!< DRIVE (Bit 4) */
#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_Msk (0x30UL) /*!< DRIVE (Bitfield-Mask: 0x03) */
#define PADS_QSPI_GPIO_QSPI_SD2_PUE_Pos (3UL) /*!< PUE (Bit 3) */
#define PADS_QSPI_GPIO_QSPI_SD2_PUE_Msk (0x8UL) /*!< PUE (Bitfield-Mask: 0x01) */
#define PADS_QSPI_GPIO_QSPI_SD2_PDE_Pos (2UL) /*!< PDE (Bit 2) */
#define PADS_QSPI_GPIO_QSPI_SD2_PDE_Msk (0x4UL) /*!< PDE (Bitfield-Mask: 0x01) */
#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_Pos (1UL) /*!< SCHMITT (Bit 1) */
#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_Msk (0x2UL) /*!< SCHMITT (Bitfield-Mask: 0x01) */
#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_Pos (0UL) /*!< SLEWFAST (Bit 0) */
#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_Msk (0x1UL) /*!< SLEWFAST (Bitfield-Mask: 0x01) */
/* ===================================================== GPIO_QSPI_SD3 ===================================================== */
#define PADS_QSPI_GPIO_QSPI_SD3_OD_Pos (7UL) /*!< OD (Bit 7) */
#define PADS_QSPI_GPIO_QSPI_SD3_OD_Msk (0x80UL) /*!< OD (Bitfield-Mask: 0x01) */
#define PADS_QSPI_GPIO_QSPI_SD3_IE_Pos (6UL) /*!< IE (Bit 6) */
#define PADS_QSPI_GPIO_QSPI_SD3_IE_Msk (0x40UL) /*!< IE (Bitfield-Mask: 0x01) */
#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_Pos (4UL) /*!< DRIVE (Bit 4) */
#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_Msk (0x30UL) /*!< DRIVE (Bitfield-Mask: 0x03) */
#define PADS_QSPI_GPIO_QSPI_SD3_PUE_Pos (3UL) /*!< PUE (Bit 3) */
#define PADS_QSPI_GPIO_QSPI_SD3_PUE_Msk (0x8UL) /*!< PUE (Bitfield-Mask: 0x01) */
#define PADS_QSPI_GPIO_QSPI_SD3_PDE_Pos (2UL) /*!< PDE (Bit 2) */
#define PADS_QSPI_GPIO_QSPI_SD3_PDE_Msk (0x4UL) /*!< PDE (Bitfield-Mask: 0x01) */
#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_Pos (1UL) /*!< SCHMITT (Bit 1) */
#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_Msk (0x2UL) /*!< SCHMITT (Bitfield-Mask: 0x01) */
#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_Pos (0UL) /*!< SLEWFAST (Bit 0) */
#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_Msk (0x1UL) /*!< SLEWFAST (Bitfield-Mask: 0x01) */
/* ===================================================== GPIO_QSPI_SS ====================================================== */
#define PADS_QSPI_GPIO_QSPI_SS_OD_Pos (7UL) /*!< OD (Bit 7) */
#define PADS_QSPI_GPIO_QSPI_SS_OD_Msk (0x80UL) /*!< OD (Bitfield-Mask: 0x01) */
#define PADS_QSPI_GPIO_QSPI_SS_IE_Pos (6UL) /*!< IE (Bit 6) */
#define PADS_QSPI_GPIO_QSPI_SS_IE_Msk (0x40UL) /*!< IE (Bitfield-Mask: 0x01) */
#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_Pos (4UL) /*!< DRIVE (Bit 4) */
#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_Msk (0x30UL) /*!< DRIVE (Bitfield-Mask: 0x03) */
#define PADS_QSPI_GPIO_QSPI_SS_PUE_Pos (3UL) /*!< PUE (Bit 3) */
#define PADS_QSPI_GPIO_QSPI_SS_PUE_Msk (0x8UL) /*!< PUE (Bitfield-Mask: 0x01) */
#define PADS_QSPI_GPIO_QSPI_SS_PDE_Pos (2UL) /*!< PDE (Bit 2) */
#define PADS_QSPI_GPIO_QSPI_SS_PDE_Msk (0x4UL) /*!< PDE (Bitfield-Mask: 0x01) */
#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_Pos (1UL) /*!< SCHMITT (Bit 1) */
#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_Msk (0x2UL) /*!< SCHMITT (Bitfield-Mask: 0x01) */
#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_Pos (0UL) /*!< SLEWFAST (Bit 0) */
#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_Msk (0x1UL) /*!< SLEWFAST (Bitfield-Mask: 0x01) */
/* =========================================================================================================================== */
/* ================ XOSC ================ */
/* =========================================================================================================================== */
/* ========================================================= CTRL ========================================================== */
#define XOSC_CTRL_ENABLE_Pos (12UL) /*!< ENABLE (Bit 12) */
#define XOSC_CTRL_ENABLE_Msk (0xfff000UL) /*!< ENABLE (Bitfield-Mask: 0xfff) */
#define XOSC_CTRL_FREQ_RANGE_Pos (0UL) /*!< FREQ_RANGE (Bit 0) */
#define XOSC_CTRL_FREQ_RANGE_Msk (0xfffUL) /*!< FREQ_RANGE (Bitfield-Mask: 0xfff) */
/* ======================================================== STATUS ========================================================= */
#define XOSC_STATUS_STABLE_Pos (31UL) /*!< STABLE (Bit 31) */
#define XOSC_STATUS_STABLE_Msk (0x80000000UL) /*!< STABLE (Bitfield-Mask: 0x01) */
#define XOSC_STATUS_BADWRITE_Pos (24UL) /*!< BADWRITE (Bit 24) */
#define XOSC_STATUS_BADWRITE_Msk (0x1000000UL) /*!< BADWRITE (Bitfield-Mask: 0x01) */
#define XOSC_STATUS_ENABLED_Pos (12UL) /*!< ENABLED (Bit 12) */
#define XOSC_STATUS_ENABLED_Msk (0x1000UL) /*!< ENABLED (Bitfield-Mask: 0x01) */
#define XOSC_STATUS_FREQ_RANGE_Pos (0UL) /*!< FREQ_RANGE (Bit 0) */
#define XOSC_STATUS_FREQ_RANGE_Msk (0x3UL) /*!< FREQ_RANGE (Bitfield-Mask: 0x03) */
/* ======================================================== DORMANT ======================================================== */
/* ======================================================== STARTUP ======================================================== */
#define XOSC_STARTUP_X4_Pos (20UL) /*!< X4 (Bit 20) */
#define XOSC_STARTUP_X4_Msk (0x100000UL) /*!< X4 (Bitfield-Mask: 0x01) */
#define XOSC_STARTUP_DELAY_Pos (0UL) /*!< DELAY (Bit 0) */
#define XOSC_STARTUP_DELAY_Msk (0x3fffUL) /*!< DELAY (Bitfield-Mask: 0x3fff) */
/* ========================================================= COUNT ========================================================= */
#define XOSC_COUNT_COUNT_Pos (0UL) /*!< COUNT (Bit 0) */
#define XOSC_COUNT_COUNT_Msk (0xffUL) /*!< COUNT (Bitfield-Mask: 0xff) */
/* =========================================================================================================================== */
/* ================ PLL_SYS ================ */
/* =========================================================================================================================== */
/* ========================================================== CS =========================================================== */
#define PLL_SYS_CS_LOCK_Pos (31UL) /*!< LOCK (Bit 31) */
#define PLL_SYS_CS_LOCK_Msk (0x80000000UL) /*!< LOCK (Bitfield-Mask: 0x01) */
#define PLL_SYS_CS_BYPASS_Pos (8UL) /*!< BYPASS (Bit 8) */
#define PLL_SYS_CS_BYPASS_Msk (0x100UL) /*!< BYPASS (Bitfield-Mask: 0x01) */
#define PLL_SYS_CS_REFDIV_Pos (0UL) /*!< REFDIV (Bit 0) */
#define PLL_SYS_CS_REFDIV_Msk (0x3fUL) /*!< REFDIV (Bitfield-Mask: 0x3f) */
/* ========================================================== PWR ========================================================== */
#define PLL_SYS_PWR_VCOPD_Pos (5UL) /*!< VCOPD (Bit 5) */
#define PLL_SYS_PWR_VCOPD_Msk (0x20UL) /*!< VCOPD (Bitfield-Mask: 0x01) */
#define PLL_SYS_PWR_POSTDIVPD_Pos (3UL) /*!< POSTDIVPD (Bit 3) */
#define PLL_SYS_PWR_POSTDIVPD_Msk (0x8UL) /*!< POSTDIVPD (Bitfield-Mask: 0x01) */
#define PLL_SYS_PWR_DSMPD_Pos (2UL) /*!< DSMPD (Bit 2) */
#define PLL_SYS_PWR_DSMPD_Msk (0x4UL) /*!< DSMPD (Bitfield-Mask: 0x01) */
#define PLL_SYS_PWR_PD_Pos (0UL) /*!< PD (Bit 0) */
#define PLL_SYS_PWR_PD_Msk (0x1UL) /*!< PD (Bitfield-Mask: 0x01) */
/* ======================================================= FBDIV_INT ======================================================= */
#define PLL_SYS_FBDIV_INT_FBDIV_INT_Pos (0UL) /*!< FBDIV_INT (Bit 0) */
#define PLL_SYS_FBDIV_INT_FBDIV_INT_Msk (0xfffUL) /*!< FBDIV_INT (Bitfield-Mask: 0xfff) */
/* ========================================================= PRIM ========================================================== */
#define PLL_SYS_PRIM_POSTDIV1_Pos (16UL) /*!< POSTDIV1 (Bit 16) */
#define PLL_SYS_PRIM_POSTDIV1_Msk (0x70000UL) /*!< POSTDIV1 (Bitfield-Mask: 0x07) */
#define PLL_SYS_PRIM_POSTDIV2_Pos (12UL) /*!< POSTDIV2 (Bit 12) */
#define PLL_SYS_PRIM_POSTDIV2_Msk (0x7000UL) /*!< POSTDIV2 (Bitfield-Mask: 0x07) */
/* =========================================================================================================================== */
/* ================ BUSCTRL ================ */
/* =========================================================================================================================== */
/* ===================================================== BUS_PRIORITY ====================================================== */
#define BUSCTRL_BUS_PRIORITY_DMA_W_Pos (12UL) /*!< DMA_W (Bit 12) */
#define BUSCTRL_BUS_PRIORITY_DMA_W_Msk (0x1000UL) /*!< DMA_W (Bitfield-Mask: 0x01) */
#define BUSCTRL_BUS_PRIORITY_DMA_R_Pos (8UL) /*!< DMA_R (Bit 8) */
#define BUSCTRL_BUS_PRIORITY_DMA_R_Msk (0x100UL) /*!< DMA_R (Bitfield-Mask: 0x01) */
#define BUSCTRL_BUS_PRIORITY_PROC1_Pos (4UL) /*!< PROC1 (Bit 4) */
#define BUSCTRL_BUS_PRIORITY_PROC1_Msk (0x10UL) /*!< PROC1 (Bitfield-Mask: 0x01) */
#define BUSCTRL_BUS_PRIORITY_PROC0_Pos (0UL) /*!< PROC0 (Bit 0) */
#define BUSCTRL_BUS_PRIORITY_PROC0_Msk (0x1UL) /*!< PROC0 (Bitfield-Mask: 0x01) */
/* =================================================== BUS_PRIORITY_ACK ==================================================== */
#define BUSCTRL_BUS_PRIORITY_ACK_BUS_PRIORITY_ACK_Pos (0UL) /*!< BUS_PRIORITY_ACK (Bit 0) */
#define BUSCTRL_BUS_PRIORITY_ACK_BUS_PRIORITY_ACK_Msk (0x1UL) /*!< BUS_PRIORITY_ACK (Bitfield-Mask: 0x01) */
/* ======================================================= PERFCTR0 ======================================================== */
#define BUSCTRL_PERFCTR0_PERFCTR0_Pos (0UL) /*!< PERFCTR0 (Bit 0) */
#define BUSCTRL_PERFCTR0_PERFCTR0_Msk (0xffffffUL) /*!< PERFCTR0 (Bitfield-Mask: 0xffffff) */
/* ======================================================= PERFSEL0 ======================================================== */
#define BUSCTRL_PERFSEL0_PERFSEL0_Pos (0UL) /*!< PERFSEL0 (Bit 0) */
#define BUSCTRL_PERFSEL0_PERFSEL0_Msk (0x1fUL) /*!< PERFSEL0 (Bitfield-Mask: 0x1f) */
/* ======================================================= PERFCTR1 ======================================================== */
#define BUSCTRL_PERFCTR1_PERFCTR1_Pos (0UL) /*!< PERFCTR1 (Bit 0) */
#define BUSCTRL_PERFCTR1_PERFCTR1_Msk (0xffffffUL) /*!< PERFCTR1 (Bitfield-Mask: 0xffffff) */
/* ======================================================= PERFSEL1 ======================================================== */
#define BUSCTRL_PERFSEL1_PERFSEL1_Pos (0UL) /*!< PERFSEL1 (Bit 0) */
#define BUSCTRL_PERFSEL1_PERFSEL1_Msk (0x1fUL) /*!< PERFSEL1 (Bitfield-Mask: 0x1f) */
/* ======================================================= PERFCTR2 ======================================================== */
#define BUSCTRL_PERFCTR2_PERFCTR2_Pos (0UL) /*!< PERFCTR2 (Bit 0) */
#define BUSCTRL_PERFCTR2_PERFCTR2_Msk (0xffffffUL) /*!< PERFCTR2 (Bitfield-Mask: 0xffffff) */
/* ======================================================= PERFSEL2 ======================================================== */
#define BUSCTRL_PERFSEL2_PERFSEL2_Pos (0UL) /*!< PERFSEL2 (Bit 0) */
#define BUSCTRL_PERFSEL2_PERFSEL2_Msk (0x1fUL) /*!< PERFSEL2 (Bitfield-Mask: 0x1f) */
/* ======================================================= PERFCTR3 ======================================================== */
#define BUSCTRL_PERFCTR3_PERFCTR3_Pos (0UL) /*!< PERFCTR3 (Bit 0) */
#define BUSCTRL_PERFCTR3_PERFCTR3_Msk (0xffffffUL) /*!< PERFCTR3 (Bitfield-Mask: 0xffffff) */
/* ======================================================= PERFSEL3 ======================================================== */
#define BUSCTRL_PERFSEL3_PERFSEL3_Pos (0UL) /*!< PERFSEL3 (Bit 0) */
#define BUSCTRL_PERFSEL3_PERFSEL3_Msk (0x1fUL) /*!< PERFSEL3 (Bitfield-Mask: 0x1f) */
/* =========================================================================================================================== */
/* ================ UART0 ================ */
/* =========================================================================================================================== */
/* ======================================================== UARTDR ========================================================= */
#define UART0_UARTDR_OE_Pos (11UL) /*!< OE (Bit 11) */
#define UART0_UARTDR_OE_Msk (0x800UL) /*!< OE (Bitfield-Mask: 0x01) */
#define UART0_UARTDR_BE_Pos (10UL) /*!< BE (Bit 10) */
#define UART0_UARTDR_BE_Msk (0x400UL) /*!< BE (Bitfield-Mask: 0x01) */
#define UART0_UARTDR_PE_Pos (9UL) /*!< PE (Bit 9) */
#define UART0_UARTDR_PE_Msk (0x200UL) /*!< PE (Bitfield-Mask: 0x01) */
#define UART0_UARTDR_FE_Pos (8UL) /*!< FE (Bit 8) */
#define UART0_UARTDR_FE_Msk (0x100UL) /*!< FE (Bitfield-Mask: 0x01) */
#define UART0_UARTDR_DATA_Pos (0UL) /*!< DATA (Bit 0) */
#define UART0_UARTDR_DATA_Msk (0xffUL) /*!< DATA (Bitfield-Mask: 0xff) */
/* ======================================================== UARTRSR ======================================================== */
#define UART0_UARTRSR_OE_Pos (3UL) /*!< OE (Bit 3) */
#define UART0_UARTRSR_OE_Msk (0x8UL) /*!< OE (Bitfield-Mask: 0x01) */
#define UART0_UARTRSR_BE_Pos (2UL) /*!< BE (Bit 2) */
#define UART0_UARTRSR_BE_Msk (0x4UL) /*!< BE (Bitfield-Mask: 0x01) */
#define UART0_UARTRSR_PE_Pos (1UL) /*!< PE (Bit 1) */
#define UART0_UARTRSR_PE_Msk (0x2UL) /*!< PE (Bitfield-Mask: 0x01) */
#define UART0_UARTRSR_FE_Pos (0UL) /*!< FE (Bit 0) */
#define UART0_UARTRSR_FE_Msk (0x1UL) /*!< FE (Bitfield-Mask: 0x01) */
/* ======================================================== UARTFR ========================================================= */
#define UART0_UARTFR_RI_Pos (8UL) /*!< RI (Bit 8) */
#define UART0_UARTFR_RI_Msk (0x100UL) /*!< RI (Bitfield-Mask: 0x01) */
#define UART0_UARTFR_TXFE_Pos (7UL) /*!< TXFE (Bit 7) */
#define UART0_UARTFR_TXFE_Msk (0x80UL) /*!< TXFE (Bitfield-Mask: 0x01) */
#define UART0_UARTFR_RXFF_Pos (6UL) /*!< RXFF (Bit 6) */
#define UART0_UARTFR_RXFF_Msk (0x40UL) /*!< RXFF (Bitfield-Mask: 0x01) */
#define UART0_UARTFR_TXFF_Pos (5UL) /*!< TXFF (Bit 5) */
#define UART0_UARTFR_TXFF_Msk (0x20UL) /*!< TXFF (Bitfield-Mask: 0x01) */
#define UART0_UARTFR_RXFE_Pos (4UL) /*!< RXFE (Bit 4) */
#define UART0_UARTFR_RXFE_Msk (0x10UL) /*!< RXFE (Bitfield-Mask: 0x01) */
#define UART0_UARTFR_BUSY_Pos (3UL) /*!< BUSY (Bit 3) */
#define UART0_UARTFR_BUSY_Msk (0x8UL) /*!< BUSY (Bitfield-Mask: 0x01) */
#define UART0_UARTFR_DCD_Pos (2UL) /*!< DCD (Bit 2) */
#define UART0_UARTFR_DCD_Msk (0x4UL) /*!< DCD (Bitfield-Mask: 0x01) */
#define UART0_UARTFR_DSR_Pos (1UL) /*!< DSR (Bit 1) */
#define UART0_UARTFR_DSR_Msk (0x2UL) /*!< DSR (Bitfield-Mask: 0x01) */
#define UART0_UARTFR_CTS_Pos (0UL) /*!< CTS (Bit 0) */
#define UART0_UARTFR_CTS_Msk (0x1UL) /*!< CTS (Bitfield-Mask: 0x01) */
/* ======================================================= UARTILPR ======================================================== */
#define UART0_UARTILPR_ILPDVSR_Pos (0UL) /*!< ILPDVSR (Bit 0) */
#define UART0_UARTILPR_ILPDVSR_Msk (0xffUL) /*!< ILPDVSR (Bitfield-Mask: 0xff) */
/* ======================================================= UARTIBRD ======================================================== */
#define UART0_UARTIBRD_BAUD_DIVINT_Pos (0UL) /*!< BAUD_DIVINT (Bit 0) */
#define UART0_UARTIBRD_BAUD_DIVINT_Msk (0xffffUL) /*!< BAUD_DIVINT (Bitfield-Mask: 0xffff) */
/* ======================================================= UARTFBRD ======================================================== */
#define UART0_UARTFBRD_BAUD_DIVFRAC_Pos (0UL) /*!< BAUD_DIVFRAC (Bit 0) */
#define UART0_UARTFBRD_BAUD_DIVFRAC_Msk (0x3fUL) /*!< BAUD_DIVFRAC (Bitfield-Mask: 0x3f) */
/* ======================================================= UARTLCR_H ======================================================= */
#define UART0_UARTLCR_H_SPS_Pos (7UL) /*!< SPS (Bit 7) */
#define UART0_UARTLCR_H_SPS_Msk (0x80UL) /*!< SPS (Bitfield-Mask: 0x01) */
#define UART0_UARTLCR_H_WLEN_Pos (5UL) /*!< WLEN (Bit 5) */
#define UART0_UARTLCR_H_WLEN_Msk (0x60UL) /*!< WLEN (Bitfield-Mask: 0x03) */
#define UART0_UARTLCR_H_FEN_Pos (4UL) /*!< FEN (Bit 4) */
#define UART0_UARTLCR_H_FEN_Msk (0x10UL) /*!< FEN (Bitfield-Mask: 0x01) */
#define UART0_UARTLCR_H_STP2_Pos (3UL) /*!< STP2 (Bit 3) */
#define UART0_UARTLCR_H_STP2_Msk (0x8UL) /*!< STP2 (Bitfield-Mask: 0x01) */
#define UART0_UARTLCR_H_EPS_Pos (2UL) /*!< EPS (Bit 2) */
#define UART0_UARTLCR_H_EPS_Msk (0x4UL) /*!< EPS (Bitfield-Mask: 0x01) */
#define UART0_UARTLCR_H_PEN_Pos (1UL) /*!< PEN (Bit 1) */
#define UART0_UARTLCR_H_PEN_Msk (0x2UL) /*!< PEN (Bitfield-Mask: 0x01) */
#define UART0_UARTLCR_H_BRK_Pos (0UL) /*!< BRK (Bit 0) */
#define UART0_UARTLCR_H_BRK_Msk (0x1UL) /*!< BRK (Bitfield-Mask: 0x01) */
/* ======================================================== UARTCR ========================================================= */
#define UART0_UARTCR_CTSEN_Pos (15UL) /*!< CTSEN (Bit 15) */
#define UART0_UARTCR_CTSEN_Msk (0x8000UL) /*!< CTSEN (Bitfield-Mask: 0x01) */
#define UART0_UARTCR_RTSEN_Pos (14UL) /*!< RTSEN (Bit 14) */
#define UART0_UARTCR_RTSEN_Msk (0x4000UL) /*!< RTSEN (Bitfield-Mask: 0x01) */
#define UART0_UARTCR_OUT2_Pos (13UL) /*!< OUT2 (Bit 13) */
#define UART0_UARTCR_OUT2_Msk (0x2000UL) /*!< OUT2 (Bitfield-Mask: 0x01) */
#define UART0_UARTCR_OUT1_Pos (12UL) /*!< OUT1 (Bit 12) */
#define UART0_UARTCR_OUT1_Msk (0x1000UL) /*!< OUT1 (Bitfield-Mask: 0x01) */
#define UART0_UARTCR_RTS_Pos (11UL) /*!< RTS (Bit 11) */
#define UART0_UARTCR_RTS_Msk (0x800UL) /*!< RTS (Bitfield-Mask: 0x01) */
#define UART0_UARTCR_DTR_Pos (10UL) /*!< DTR (Bit 10) */
#define UART0_UARTCR_DTR_Msk (0x400UL) /*!< DTR (Bitfield-Mask: 0x01) */
#define UART0_UARTCR_RXE_Pos (9UL) /*!< RXE (Bit 9) */
#define UART0_UARTCR_RXE_Msk (0x200UL) /*!< RXE (Bitfield-Mask: 0x01) */
#define UART0_UARTCR_TXE_Pos (8UL) /*!< TXE (Bit 8) */
#define UART0_UARTCR_TXE_Msk (0x100UL) /*!< TXE (Bitfield-Mask: 0x01) */
#define UART0_UARTCR_LBE_Pos (7UL) /*!< LBE (Bit 7) */
#define UART0_UARTCR_LBE_Msk (0x80UL) /*!< LBE (Bitfield-Mask: 0x01) */
#define UART0_UARTCR_SIRLP_Pos (2UL) /*!< SIRLP (Bit 2) */
#define UART0_UARTCR_SIRLP_Msk (0x4UL) /*!< SIRLP (Bitfield-Mask: 0x01) */
#define UART0_UARTCR_SIREN_Pos (1UL) /*!< SIREN (Bit 1) */
#define UART0_UARTCR_SIREN_Msk (0x2UL) /*!< SIREN (Bitfield-Mask: 0x01) */
#define UART0_UARTCR_UARTEN_Pos (0UL) /*!< UARTEN (Bit 0) */
#define UART0_UARTCR_UARTEN_Msk (0x1UL) /*!< UARTEN (Bitfield-Mask: 0x01) */
/* ======================================================= UARTIFLS ======================================================== */
#define UART0_UARTIFLS_RXIFLSEL_Pos (3UL) /*!< RXIFLSEL (Bit 3) */
#define UART0_UARTIFLS_RXIFLSEL_Msk (0x38UL) /*!< RXIFLSEL (Bitfield-Mask: 0x07) */
#define UART0_UARTIFLS_TXIFLSEL_Pos (0UL) /*!< TXIFLSEL (Bit 0) */
#define UART0_UARTIFLS_TXIFLSEL_Msk (0x7UL) /*!< TXIFLSEL (Bitfield-Mask: 0x07) */
/* ======================================================= UARTIMSC ======================================================== */
#define UART0_UARTIMSC_OEIM_Pos (10UL) /*!< OEIM (Bit 10) */
#define UART0_UARTIMSC_OEIM_Msk (0x400UL) /*!< OEIM (Bitfield-Mask: 0x01) */
#define UART0_UARTIMSC_BEIM_Pos (9UL) /*!< BEIM (Bit 9) */
#define UART0_UARTIMSC_BEIM_Msk (0x200UL) /*!< BEIM (Bitfield-Mask: 0x01) */
#define UART0_UARTIMSC_PEIM_Pos (8UL) /*!< PEIM (Bit 8) */
#define UART0_UARTIMSC_PEIM_Msk (0x100UL) /*!< PEIM (Bitfield-Mask: 0x01) */
#define UART0_UARTIMSC_FEIM_Pos (7UL) /*!< FEIM (Bit 7) */
#define UART0_UARTIMSC_FEIM_Msk (0x80UL) /*!< FEIM (Bitfield-Mask: 0x01) */
#define UART0_UARTIMSC_RTIM_Pos (6UL) /*!< RTIM (Bit 6) */
#define UART0_UARTIMSC_RTIM_Msk (0x40UL) /*!< RTIM (Bitfield-Mask: 0x01) */
#define UART0_UARTIMSC_TXIM_Pos (5UL) /*!< TXIM (Bit 5) */
#define UART0_UARTIMSC_TXIM_Msk (0x20UL) /*!< TXIM (Bitfield-Mask: 0x01) */
#define UART0_UARTIMSC_RXIM_Pos (4UL) /*!< RXIM (Bit 4) */
#define UART0_UARTIMSC_RXIM_Msk (0x10UL) /*!< RXIM (Bitfield-Mask: 0x01) */
#define UART0_UARTIMSC_DSRMIM_Pos (3UL) /*!< DSRMIM (Bit 3) */
#define UART0_UARTIMSC_DSRMIM_Msk (0x8UL) /*!< DSRMIM (Bitfield-Mask: 0x01) */
#define UART0_UARTIMSC_DCDMIM_Pos (2UL) /*!< DCDMIM (Bit 2) */
#define UART0_UARTIMSC_DCDMIM_Msk (0x4UL) /*!< DCDMIM (Bitfield-Mask: 0x01) */
#define UART0_UARTIMSC_CTSMIM_Pos (1UL) /*!< CTSMIM (Bit 1) */
#define UART0_UARTIMSC_CTSMIM_Msk (0x2UL) /*!< CTSMIM (Bitfield-Mask: 0x01) */
#define UART0_UARTIMSC_RIMIM_Pos (0UL) /*!< RIMIM (Bit 0) */
#define UART0_UARTIMSC_RIMIM_Msk (0x1UL) /*!< RIMIM (Bitfield-Mask: 0x01) */
/* ======================================================== UARTRIS ======================================================== */
#define UART0_UARTRIS_OERIS_Pos (10UL) /*!< OERIS (Bit 10) */
#define UART0_UARTRIS_OERIS_Msk (0x400UL) /*!< OERIS (Bitfield-Mask: 0x01) */
#define UART0_UARTRIS_BERIS_Pos (9UL) /*!< BERIS (Bit 9) */
#define UART0_UARTRIS_BERIS_Msk (0x200UL) /*!< BERIS (Bitfield-Mask: 0x01) */
#define UART0_UARTRIS_PERIS_Pos (8UL) /*!< PERIS (Bit 8) */
#define UART0_UARTRIS_PERIS_Msk (0x100UL) /*!< PERIS (Bitfield-Mask: 0x01) */
#define UART0_UARTRIS_FERIS_Pos (7UL) /*!< FERIS (Bit 7) */
#define UART0_UARTRIS_FERIS_Msk (0x80UL) /*!< FERIS (Bitfield-Mask: 0x01) */
#define UART0_UARTRIS_RTRIS_Pos (6UL) /*!< RTRIS (Bit 6) */
#define UART0_UARTRIS_RTRIS_Msk (0x40UL) /*!< RTRIS (Bitfield-Mask: 0x01) */
#define UART0_UARTRIS_TXRIS_Pos (5UL) /*!< TXRIS (Bit 5) */
#define UART0_UARTRIS_TXRIS_Msk (0x20UL) /*!< TXRIS (Bitfield-Mask: 0x01) */
#define UART0_UARTRIS_RXRIS_Pos (4UL) /*!< RXRIS (Bit 4) */
#define UART0_UARTRIS_RXRIS_Msk (0x10UL) /*!< RXRIS (Bitfield-Mask: 0x01) */
#define UART0_UARTRIS_DSRRMIS_Pos (3UL) /*!< DSRRMIS (Bit 3) */
#define UART0_UARTRIS_DSRRMIS_Msk (0x8UL) /*!< DSRRMIS (Bitfield-Mask: 0x01) */
#define UART0_UARTRIS_DCDRMIS_Pos (2UL) /*!< DCDRMIS (Bit 2) */
#define UART0_UARTRIS_DCDRMIS_Msk (0x4UL) /*!< DCDRMIS (Bitfield-Mask: 0x01) */
#define UART0_UARTRIS_CTSRMIS_Pos (1UL) /*!< CTSRMIS (Bit 1) */
#define UART0_UARTRIS_CTSRMIS_Msk (0x2UL) /*!< CTSRMIS (Bitfield-Mask: 0x01) */
#define UART0_UARTRIS_RIRMIS_Pos (0UL) /*!< RIRMIS (Bit 0) */
#define UART0_UARTRIS_RIRMIS_Msk (0x1UL) /*!< RIRMIS (Bitfield-Mask: 0x01) */
/* ======================================================== UARTMIS ======================================================== */
#define UART0_UARTMIS_OEMIS_Pos (10UL) /*!< OEMIS (Bit 10) */
#define UART0_UARTMIS_OEMIS_Msk (0x400UL) /*!< OEMIS (Bitfield-Mask: 0x01) */
#define UART0_UARTMIS_BEMIS_Pos (9UL) /*!< BEMIS (Bit 9) */
#define UART0_UARTMIS_BEMIS_Msk (0x200UL) /*!< BEMIS (Bitfield-Mask: 0x01) */
#define UART0_UARTMIS_PEMIS_Pos (8UL) /*!< PEMIS (Bit 8) */
#define UART0_UARTMIS_PEMIS_Msk (0x100UL) /*!< PEMIS (Bitfield-Mask: 0x01) */
#define UART0_UARTMIS_FEMIS_Pos (7UL) /*!< FEMIS (Bit 7) */
#define UART0_UARTMIS_FEMIS_Msk (0x80UL) /*!< FEMIS (Bitfield-Mask: 0x01) */
#define UART0_UARTMIS_RTMIS_Pos (6UL) /*!< RTMIS (Bit 6) */
#define UART0_UARTMIS_RTMIS_Msk (0x40UL) /*!< RTMIS (Bitfield-Mask: 0x01) */
#define UART0_UARTMIS_TXMIS_Pos (5UL) /*!< TXMIS (Bit 5) */
#define UART0_UARTMIS_TXMIS_Msk (0x20UL) /*!< TXMIS (Bitfield-Mask: 0x01) */
#define UART0_UARTMIS_RXMIS_Pos (4UL) /*!< RXMIS (Bit 4) */
#define UART0_UARTMIS_RXMIS_Msk (0x10UL) /*!< RXMIS (Bitfield-Mask: 0x01) */
#define UART0_UARTMIS_DSRMMIS_Pos (3UL) /*!< DSRMMIS (Bit 3) */
#define UART0_UARTMIS_DSRMMIS_Msk (0x8UL) /*!< DSRMMIS (Bitfield-Mask: 0x01) */
#define UART0_UARTMIS_DCDMMIS_Pos (2UL) /*!< DCDMMIS (Bit 2) */
#define UART0_UARTMIS_DCDMMIS_Msk (0x4UL) /*!< DCDMMIS (Bitfield-Mask: 0x01) */
#define UART0_UARTMIS_CTSMMIS_Pos (1UL) /*!< CTSMMIS (Bit 1) */
#define UART0_UARTMIS_CTSMMIS_Msk (0x2UL) /*!< CTSMMIS (Bitfield-Mask: 0x01) */
#define UART0_UARTMIS_RIMMIS_Pos (0UL) /*!< RIMMIS (Bit 0) */
#define UART0_UARTMIS_RIMMIS_Msk (0x1UL) /*!< RIMMIS (Bitfield-Mask: 0x01) */
/* ======================================================== UARTICR ======================================================== */
#define UART0_UARTICR_OEIC_Pos (10UL) /*!< OEIC (Bit 10) */
#define UART0_UARTICR_OEIC_Msk (0x400UL) /*!< OEIC (Bitfield-Mask: 0x01) */
#define UART0_UARTICR_BEIC_Pos (9UL) /*!< BEIC (Bit 9) */
#define UART0_UARTICR_BEIC_Msk (0x200UL) /*!< BEIC (Bitfield-Mask: 0x01) */
#define UART0_UARTICR_PEIC_Pos (8UL) /*!< PEIC (Bit 8) */
#define UART0_UARTICR_PEIC_Msk (0x100UL) /*!< PEIC (Bitfield-Mask: 0x01) */
#define UART0_UARTICR_FEIC_Pos (7UL) /*!< FEIC (Bit 7) */
#define UART0_UARTICR_FEIC_Msk (0x80UL) /*!< FEIC (Bitfield-Mask: 0x01) */
#define UART0_UARTICR_RTIC_Pos (6UL) /*!< RTIC (Bit 6) */
#define UART0_UARTICR_RTIC_Msk (0x40UL) /*!< RTIC (Bitfield-Mask: 0x01) */
#define UART0_UARTICR_TXIC_Pos (5UL) /*!< TXIC (Bit 5) */
#define UART0_UARTICR_TXIC_Msk (0x20UL) /*!< TXIC (Bitfield-Mask: 0x01) */
#define UART0_UARTICR_RXIC_Pos (4UL) /*!< RXIC (Bit 4) */
#define UART0_UARTICR_RXIC_Msk (0x10UL) /*!< RXIC (Bitfield-Mask: 0x01) */
#define UART0_UARTICR_DSRMIC_Pos (3UL) /*!< DSRMIC (Bit 3) */
#define UART0_UARTICR_DSRMIC_Msk (0x8UL) /*!< DSRMIC (Bitfield-Mask: 0x01) */
#define UART0_UARTICR_DCDMIC_Pos (2UL) /*!< DCDMIC (Bit 2) */
#define UART0_UARTICR_DCDMIC_Msk (0x4UL) /*!< DCDMIC (Bitfield-Mask: 0x01) */
#define UART0_UARTICR_CTSMIC_Pos (1UL) /*!< CTSMIC (Bit 1) */
#define UART0_UARTICR_CTSMIC_Msk (0x2UL) /*!< CTSMIC (Bitfield-Mask: 0x01) */
#define UART0_UARTICR_RIMIC_Pos (0UL) /*!< RIMIC (Bit 0) */
#define UART0_UARTICR_RIMIC_Msk (0x1UL) /*!< RIMIC (Bitfield-Mask: 0x01) */
/* ======================================================= UARTDMACR ======================================================= */
#define UART0_UARTDMACR_DMAONERR_Pos (2UL) /*!< DMAONERR (Bit 2) */
#define UART0_UARTDMACR_DMAONERR_Msk (0x4UL) /*!< DMAONERR (Bitfield-Mask: 0x01) */
#define UART0_UARTDMACR_TXDMAE_Pos (1UL) /*!< TXDMAE (Bit 1) */
#define UART0_UARTDMACR_TXDMAE_Msk (0x2UL) /*!< TXDMAE (Bitfield-Mask: 0x01) */
#define UART0_UARTDMACR_RXDMAE_Pos (0UL) /*!< RXDMAE (Bit 0) */
#define UART0_UARTDMACR_RXDMAE_Msk (0x1UL) /*!< RXDMAE (Bitfield-Mask: 0x01) */
/* ===================================================== UARTPERIPHID0 ===================================================== */
#define UART0_UARTPERIPHID0_PARTNUMBER0_Pos (0UL) /*!< PARTNUMBER0 (Bit 0) */
#define UART0_UARTPERIPHID0_PARTNUMBER0_Msk (0xffUL) /*!< PARTNUMBER0 (Bitfield-Mask: 0xff) */
/* ===================================================== UARTPERIPHID1 ===================================================== */
#define UART0_UARTPERIPHID1_DESIGNER0_Pos (4UL) /*!< DESIGNER0 (Bit 4) */
#define UART0_UARTPERIPHID1_DESIGNER0_Msk (0xf0UL) /*!< DESIGNER0 (Bitfield-Mask: 0x0f) */
#define UART0_UARTPERIPHID1_PARTNUMBER1_Pos (0UL) /*!< PARTNUMBER1 (Bit 0) */
#define UART0_UARTPERIPHID1_PARTNUMBER1_Msk (0xfUL) /*!< PARTNUMBER1 (Bitfield-Mask: 0x0f) */
/* ===================================================== UARTPERIPHID2 ===================================================== */
#define UART0_UARTPERIPHID2_REVISION_Pos (4UL) /*!< REVISION (Bit 4) */
#define UART0_UARTPERIPHID2_REVISION_Msk (0xf0UL) /*!< REVISION (Bitfield-Mask: 0x0f) */
#define UART0_UARTPERIPHID2_DESIGNER1_Pos (0UL) /*!< DESIGNER1 (Bit 0) */
#define UART0_UARTPERIPHID2_DESIGNER1_Msk (0xfUL) /*!< DESIGNER1 (Bitfield-Mask: 0x0f) */
/* ===================================================== UARTPERIPHID3 ===================================================== */
#define UART0_UARTPERIPHID3_CONFIGURATION_Pos (0UL) /*!< CONFIGURATION (Bit 0) */
#define UART0_UARTPERIPHID3_CONFIGURATION_Msk (0xffUL) /*!< CONFIGURATION (Bitfield-Mask: 0xff) */
/* ===================================================== UARTPCELLID0 ====================================================== */
#define UART0_UARTPCELLID0_UARTPCELLID0_Pos (0UL) /*!< UARTPCELLID0 (Bit 0) */
#define UART0_UARTPCELLID0_UARTPCELLID0_Msk (0xffUL) /*!< UARTPCELLID0 (Bitfield-Mask: 0xff) */
/* ===================================================== UARTPCELLID1 ====================================================== */
#define UART0_UARTPCELLID1_UARTPCELLID1_Pos (0UL) /*!< UARTPCELLID1 (Bit 0) */
#define UART0_UARTPCELLID1_UARTPCELLID1_Msk (0xffUL) /*!< UARTPCELLID1 (Bitfield-Mask: 0xff) */
/* ===================================================== UARTPCELLID2 ====================================================== */
#define UART0_UARTPCELLID2_UARTPCELLID2_Pos (0UL) /*!< UARTPCELLID2 (Bit 0) */
#define UART0_UARTPCELLID2_UARTPCELLID2_Msk (0xffUL) /*!< UARTPCELLID2 (Bitfield-Mask: 0xff) */
/* ===================================================== UARTPCELLID3 ====================================================== */
#define UART0_UARTPCELLID3_UARTPCELLID3_Pos (0UL) /*!< UARTPCELLID3 (Bit 0) */
#define UART0_UARTPCELLID3_UARTPCELLID3_Msk (0xffUL) /*!< UARTPCELLID3 (Bitfield-Mask: 0xff) */
/* =========================================================================================================================== */
/* ================ SPI0 ================ */
/* =========================================================================================================================== */
/* ======================================================== SSPCR0 ========================================================= */
#define SPI0_SSPCR0_SCR_Pos (8UL) /*!< SCR (Bit 8) */
#define SPI0_SSPCR0_SCR_Msk (0xff00UL) /*!< SCR (Bitfield-Mask: 0xff) */
#define SPI0_SSPCR0_SPH_Pos (7UL) /*!< SPH (Bit 7) */
#define SPI0_SSPCR0_SPH_Msk (0x80UL) /*!< SPH (Bitfield-Mask: 0x01) */
#define SPI0_SSPCR0_SPO_Pos (6UL) /*!< SPO (Bit 6) */
#define SPI0_SSPCR0_SPO_Msk (0x40UL) /*!< SPO (Bitfield-Mask: 0x01) */
#define SPI0_SSPCR0_FRF_Pos (4UL) /*!< FRF (Bit 4) */
#define SPI0_SSPCR0_FRF_Msk (0x30UL) /*!< FRF (Bitfield-Mask: 0x03) */
#define SPI0_SSPCR0_DSS_Pos (0UL) /*!< DSS (Bit 0) */
#define SPI0_SSPCR0_DSS_Msk (0xfUL) /*!< DSS (Bitfield-Mask: 0x0f) */
/* ======================================================== SSPCR1 ========================================================= */
#define SPI0_SSPCR1_SOD_Pos (3UL) /*!< SOD (Bit 3) */
#define SPI0_SSPCR1_SOD_Msk (0x8UL) /*!< SOD (Bitfield-Mask: 0x01) */
#define SPI0_SSPCR1_MS_Pos (2UL) /*!< MS (Bit 2) */
#define SPI0_SSPCR1_MS_Msk (0x4UL) /*!< MS (Bitfield-Mask: 0x01) */
#define SPI0_SSPCR1_SSE_Pos (1UL) /*!< SSE (Bit 1) */
#define SPI0_SSPCR1_SSE_Msk (0x2UL) /*!< SSE (Bitfield-Mask: 0x01) */
#define SPI0_SSPCR1_LBM_Pos (0UL) /*!< LBM (Bit 0) */
#define SPI0_SSPCR1_LBM_Msk (0x1UL) /*!< LBM (Bitfield-Mask: 0x01) */
/* ========================================================= SSPDR ========================================================= */
#define SPI0_SSPDR_DATA_Pos (0UL) /*!< DATA (Bit 0) */
#define SPI0_SSPDR_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */
/* ========================================================= SSPSR ========================================================= */
#define SPI0_SSPSR_BSY_Pos (4UL) /*!< BSY (Bit 4) */
#define SPI0_SSPSR_BSY_Msk (0x10UL) /*!< BSY (Bitfield-Mask: 0x01) */
#define SPI0_SSPSR_RFF_Pos (3UL) /*!< RFF (Bit 3) */
#define SPI0_SSPSR_RFF_Msk (0x8UL) /*!< RFF (Bitfield-Mask: 0x01) */
#define SPI0_SSPSR_RNE_Pos (2UL) /*!< RNE (Bit 2) */
#define SPI0_SSPSR_RNE_Msk (0x4UL) /*!< RNE (Bitfield-Mask: 0x01) */
#define SPI0_SSPSR_TNF_Pos (1UL) /*!< TNF (Bit 1) */
#define SPI0_SSPSR_TNF_Msk (0x2UL) /*!< TNF (Bitfield-Mask: 0x01) */
#define SPI0_SSPSR_TFE_Pos (0UL) /*!< TFE (Bit 0) */
#define SPI0_SSPSR_TFE_Msk (0x1UL) /*!< TFE (Bitfield-Mask: 0x01) */
/* ======================================================== SSPCPSR ======================================================== */
#define SPI0_SSPCPSR_CPSDVSR_Pos (0UL) /*!< CPSDVSR (Bit 0) */
#define SPI0_SSPCPSR_CPSDVSR_Msk (0xffUL) /*!< CPSDVSR (Bitfield-Mask: 0xff) */
/* ======================================================== SSPIMSC ======================================================== */
#define SPI0_SSPIMSC_TXIM_Pos (3UL) /*!< TXIM (Bit 3) */
#define SPI0_SSPIMSC_TXIM_Msk (0x8UL) /*!< TXIM (Bitfield-Mask: 0x01) */
#define SPI0_SSPIMSC_RXIM_Pos (2UL) /*!< RXIM (Bit 2) */
#define SPI0_SSPIMSC_RXIM_Msk (0x4UL) /*!< RXIM (Bitfield-Mask: 0x01) */
#define SPI0_SSPIMSC_RTIM_Pos (1UL) /*!< RTIM (Bit 1) */
#define SPI0_SSPIMSC_RTIM_Msk (0x2UL) /*!< RTIM (Bitfield-Mask: 0x01) */
#define SPI0_SSPIMSC_RORIM_Pos (0UL) /*!< RORIM (Bit 0) */
#define SPI0_SSPIMSC_RORIM_Msk (0x1UL) /*!< RORIM (Bitfield-Mask: 0x01) */
/* ======================================================== SSPRIS ========================================================= */
#define SPI0_SSPRIS_TXRIS_Pos (3UL) /*!< TXRIS (Bit 3) */
#define SPI0_SSPRIS_TXRIS_Msk (0x8UL) /*!< TXRIS (Bitfield-Mask: 0x01) */
#define SPI0_SSPRIS_RXRIS_Pos (2UL) /*!< RXRIS (Bit 2) */
#define SPI0_SSPRIS_RXRIS_Msk (0x4UL) /*!< RXRIS (Bitfield-Mask: 0x01) */
#define SPI0_SSPRIS_RTRIS_Pos (1UL) /*!< RTRIS (Bit 1) */
#define SPI0_SSPRIS_RTRIS_Msk (0x2UL) /*!< RTRIS (Bitfield-Mask: 0x01) */
#define SPI0_SSPRIS_RORRIS_Pos (0UL) /*!< RORRIS (Bit 0) */
#define SPI0_SSPRIS_RORRIS_Msk (0x1UL) /*!< RORRIS (Bitfield-Mask: 0x01) */
/* ======================================================== SSPMIS ========================================================= */
#define SPI0_SSPMIS_TXMIS_Pos (3UL) /*!< TXMIS (Bit 3) */
#define SPI0_SSPMIS_TXMIS_Msk (0x8UL) /*!< TXMIS (Bitfield-Mask: 0x01) */
#define SPI0_SSPMIS_RXMIS_Pos (2UL) /*!< RXMIS (Bit 2) */
#define SPI0_SSPMIS_RXMIS_Msk (0x4UL) /*!< RXMIS (Bitfield-Mask: 0x01) */
#define SPI0_SSPMIS_RTMIS_Pos (1UL) /*!< RTMIS (Bit 1) */
#define SPI0_SSPMIS_RTMIS_Msk (0x2UL) /*!< RTMIS (Bitfield-Mask: 0x01) */
#define SPI0_SSPMIS_RORMIS_Pos (0UL) /*!< RORMIS (Bit 0) */
#define SPI0_SSPMIS_RORMIS_Msk (0x1UL) /*!< RORMIS (Bitfield-Mask: 0x01) */
/* ======================================================== SSPICR ========================================================= */
#define SPI0_SSPICR_RTIC_Pos (1UL) /*!< RTIC (Bit 1) */
#define SPI0_SSPICR_RTIC_Msk (0x2UL) /*!< RTIC (Bitfield-Mask: 0x01) */
#define SPI0_SSPICR_RORIC_Pos (0UL) /*!< RORIC (Bit 0) */
#define SPI0_SSPICR_RORIC_Msk (0x1UL) /*!< RORIC (Bitfield-Mask: 0x01) */
/* ======================================================= SSPDMACR ======================================================== */
#define SPI0_SSPDMACR_TXDMAE_Pos (1UL) /*!< TXDMAE (Bit 1) */
#define SPI0_SSPDMACR_TXDMAE_Msk (0x2UL) /*!< TXDMAE (Bitfield-Mask: 0x01) */
#define SPI0_SSPDMACR_RXDMAE_Pos (0UL) /*!< RXDMAE (Bit 0) */
#define SPI0_SSPDMACR_RXDMAE_Msk (0x1UL) /*!< RXDMAE (Bitfield-Mask: 0x01) */
/* ===================================================== SSPPERIPHID0 ====================================================== */
#define SPI0_SSPPERIPHID0_PARTNUMBER0_Pos (0UL) /*!< PARTNUMBER0 (Bit 0) */
#define SPI0_SSPPERIPHID0_PARTNUMBER0_Msk (0xffUL) /*!< PARTNUMBER0 (Bitfield-Mask: 0xff) */
/* ===================================================== SSPPERIPHID1 ====================================================== */
#define SPI0_SSPPERIPHID1_DESIGNER0_Pos (4UL) /*!< DESIGNER0 (Bit 4) */
#define SPI0_SSPPERIPHID1_DESIGNER0_Msk (0xf0UL) /*!< DESIGNER0 (Bitfield-Mask: 0x0f) */
#define SPI0_SSPPERIPHID1_PARTNUMBER1_Pos (0UL) /*!< PARTNUMBER1 (Bit 0) */
#define SPI0_SSPPERIPHID1_PARTNUMBER1_Msk (0xfUL) /*!< PARTNUMBER1 (Bitfield-Mask: 0x0f) */
/* ===================================================== SSPPERIPHID2 ====================================================== */
#define SPI0_SSPPERIPHID2_REVISION_Pos (4UL) /*!< REVISION (Bit 4) */
#define SPI0_SSPPERIPHID2_REVISION_Msk (0xf0UL) /*!< REVISION (Bitfield-Mask: 0x0f) */
#define SPI0_SSPPERIPHID2_DESIGNER1_Pos (0UL) /*!< DESIGNER1 (Bit 0) */
#define SPI0_SSPPERIPHID2_DESIGNER1_Msk (0xfUL) /*!< DESIGNER1 (Bitfield-Mask: 0x0f) */
/* ===================================================== SSPPERIPHID3 ====================================================== */
#define SPI0_SSPPERIPHID3_CONFIGURATION_Pos (0UL) /*!< CONFIGURATION (Bit 0) */
#define SPI0_SSPPERIPHID3_CONFIGURATION_Msk (0xffUL) /*!< CONFIGURATION (Bitfield-Mask: 0xff) */
/* ====================================================== SSPPCELLID0 ====================================================== */
#define SPI0_SSPPCELLID0_SSPPCELLID0_Pos (0UL) /*!< SSPPCELLID0 (Bit 0) */
#define SPI0_SSPPCELLID0_SSPPCELLID0_Msk (0xffUL) /*!< SSPPCELLID0 (Bitfield-Mask: 0xff) */
/* ====================================================== SSPPCELLID1 ====================================================== */
#define SPI0_SSPPCELLID1_SSPPCELLID1_Pos (0UL) /*!< SSPPCELLID1 (Bit 0) */
#define SPI0_SSPPCELLID1_SSPPCELLID1_Msk (0xffUL) /*!< SSPPCELLID1 (Bitfield-Mask: 0xff) */
/* ====================================================== SSPPCELLID2 ====================================================== */
#define SPI0_SSPPCELLID2_SSPPCELLID2_Pos (0UL) /*!< SSPPCELLID2 (Bit 0) */
#define SPI0_SSPPCELLID2_SSPPCELLID2_Msk (0xffUL) /*!< SSPPCELLID2 (Bitfield-Mask: 0xff) */
/* ====================================================== SSPPCELLID3 ====================================================== */
#define SPI0_SSPPCELLID3_SSPPCELLID3_Pos (0UL) /*!< SSPPCELLID3 (Bit 0) */
#define SPI0_SSPPCELLID3_SSPPCELLID3_Msk (0xffUL) /*!< SSPPCELLID3 (Bitfield-Mask: 0xff) */
/* =========================================================================================================================== */
/* ================ I2C0 ================ */
/* =========================================================================================================================== */
/* ======================================================== IC_CON ========================================================= */
#define I2C0_IC_CON_STOP_DET_IF_MASTER_ACTIVE_Pos (10UL) /*!< STOP_DET_IF_MASTER_ACTIVE (Bit 10) */
#define I2C0_IC_CON_STOP_DET_IF_MASTER_ACTIVE_Msk (0x400UL) /*!< STOP_DET_IF_MASTER_ACTIVE (Bitfield-Mask: 0x01) */
#define I2C0_IC_CON_RX_FIFO_FULL_HLD_CTRL_Pos (9UL) /*!< RX_FIFO_FULL_HLD_CTRL (Bit 9) */
#define I2C0_IC_CON_RX_FIFO_FULL_HLD_CTRL_Msk (0x200UL) /*!< RX_FIFO_FULL_HLD_CTRL (Bitfield-Mask: 0x01) */
#define I2C0_IC_CON_TX_EMPTY_CTRL_Pos (8UL) /*!< TX_EMPTY_CTRL (Bit 8) */
#define I2C0_IC_CON_TX_EMPTY_CTRL_Msk (0x100UL) /*!< TX_EMPTY_CTRL (Bitfield-Mask: 0x01) */
#define I2C0_IC_CON_STOP_DET_IFADDRESSED_Pos (7UL) /*!< STOP_DET_IFADDRESSED (Bit 7) */
#define I2C0_IC_CON_STOP_DET_IFADDRESSED_Msk (0x80UL) /*!< STOP_DET_IFADDRESSED (Bitfield-Mask: 0x01) */
#define I2C0_IC_CON_IC_SLAVE_DISABLE_Pos (6UL) /*!< IC_SLAVE_DISABLE (Bit 6) */
#define I2C0_IC_CON_IC_SLAVE_DISABLE_Msk (0x40UL) /*!< IC_SLAVE_DISABLE (Bitfield-Mask: 0x01) */
#define I2C0_IC_CON_IC_RESTART_EN_Pos (5UL) /*!< IC_RESTART_EN (Bit 5) */
#define I2C0_IC_CON_IC_RESTART_EN_Msk (0x20UL) /*!< IC_RESTART_EN (Bitfield-Mask: 0x01) */
#define I2C0_IC_CON_IC_10BITADDR_MASTER_Pos (4UL) /*!< IC_10BITADDR_MASTER (Bit 4) */
#define I2C0_IC_CON_IC_10BITADDR_MASTER_Msk (0x10UL) /*!< IC_10BITADDR_MASTER (Bitfield-Mask: 0x01) */
#define I2C0_IC_CON_IC_10BITADDR_SLAVE_Pos (3UL) /*!< IC_10BITADDR_SLAVE (Bit 3) */
#define I2C0_IC_CON_IC_10BITADDR_SLAVE_Msk (0x8UL) /*!< IC_10BITADDR_SLAVE (Bitfield-Mask: 0x01) */
#define I2C0_IC_CON_SPEED_Pos (1UL) /*!< SPEED (Bit 1) */
#define I2C0_IC_CON_SPEED_Msk (0x6UL) /*!< SPEED (Bitfield-Mask: 0x03) */
#define I2C0_IC_CON_MASTER_MODE_Pos (0UL) /*!< MASTER_MODE (Bit 0) */
#define I2C0_IC_CON_MASTER_MODE_Msk (0x1UL) /*!< MASTER_MODE (Bitfield-Mask: 0x01) */
/* ======================================================== IC_TAR ========================================================= */
#define I2C0_IC_TAR_SPECIAL_Pos (11UL) /*!< SPECIAL (Bit 11) */
#define I2C0_IC_TAR_SPECIAL_Msk (0x800UL) /*!< SPECIAL (Bitfield-Mask: 0x01) */
#define I2C0_IC_TAR_GC_OR_START_Pos (10UL) /*!< GC_OR_START (Bit 10) */
#define I2C0_IC_TAR_GC_OR_START_Msk (0x400UL) /*!< GC_OR_START (Bitfield-Mask: 0x01) */
#define I2C0_IC_TAR_IC_TAR_Pos (0UL) /*!< IC_TAR (Bit 0) */
#define I2C0_IC_TAR_IC_TAR_Msk (0x3ffUL) /*!< IC_TAR (Bitfield-Mask: 0x3ff) */
/* ======================================================== IC_SAR ========================================================= */
#define I2C0_IC_SAR_IC_SAR_Pos (0UL) /*!< IC_SAR (Bit 0) */
#define I2C0_IC_SAR_IC_SAR_Msk (0x3ffUL) /*!< IC_SAR (Bitfield-Mask: 0x3ff) */
/* ====================================================== IC_DATA_CMD ====================================================== */
#define I2C0_IC_DATA_CMD_FIRST_DATA_BYTE_Pos (11UL) /*!< FIRST_DATA_BYTE (Bit 11) */
#define I2C0_IC_DATA_CMD_FIRST_DATA_BYTE_Msk (0x800UL) /*!< FIRST_DATA_BYTE (Bitfield-Mask: 0x01) */
#define I2C0_IC_DATA_CMD_RESTART_Pos (10UL) /*!< RESTART (Bit 10) */
#define I2C0_IC_DATA_CMD_RESTART_Msk (0x400UL) /*!< RESTART (Bitfield-Mask: 0x01) */
#define I2C0_IC_DATA_CMD_STOP_Pos (9UL) /*!< STOP (Bit 9) */
#define I2C0_IC_DATA_CMD_STOP_Msk (0x200UL) /*!< STOP (Bitfield-Mask: 0x01) */
#define I2C0_IC_DATA_CMD_CMD_Pos (8UL) /*!< CMD (Bit 8) */
#define I2C0_IC_DATA_CMD_CMD_Msk (0x100UL) /*!< CMD (Bitfield-Mask: 0x01) */
#define I2C0_IC_DATA_CMD_DAT_Pos (0UL) /*!< DAT (Bit 0) */
#define I2C0_IC_DATA_CMD_DAT_Msk (0xffUL) /*!< DAT (Bitfield-Mask: 0xff) */
/* ==================================================== IC_SS_SCL_HCNT ===================================================== */
#define I2C0_IC_SS_SCL_HCNT_IC_SS_SCL_HCNT_Pos (0UL) /*!< IC_SS_SCL_HCNT (Bit 0) */
#define I2C0_IC_SS_SCL_HCNT_IC_SS_SCL_HCNT_Msk (0xffffUL) /*!< IC_SS_SCL_HCNT (Bitfield-Mask: 0xffff) */
/* ==================================================== IC_SS_SCL_LCNT ===================================================== */
#define I2C0_IC_SS_SCL_LCNT_IC_SS_SCL_LCNT_Pos (0UL) /*!< IC_SS_SCL_LCNT (Bit 0) */
#define I2C0_IC_SS_SCL_LCNT_IC_SS_SCL_LCNT_Msk (0xffffUL) /*!< IC_SS_SCL_LCNT (Bitfield-Mask: 0xffff) */
/* ==================================================== IC_FS_SCL_HCNT ===================================================== */
#define I2C0_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT_Pos (0UL) /*!< IC_FS_SCL_HCNT (Bit 0) */
#define I2C0_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT_Msk (0xffffUL) /*!< IC_FS_SCL_HCNT (Bitfield-Mask: 0xffff) */
/* ==================================================== IC_FS_SCL_LCNT ===================================================== */
#define I2C0_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT_Pos (0UL) /*!< IC_FS_SCL_LCNT (Bit 0) */
#define I2C0_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT_Msk (0xffffUL) /*!< IC_FS_SCL_LCNT (Bitfield-Mask: 0xffff) */
/* ===================================================== IC_INTR_STAT ====================================================== */
#define I2C0_IC_INTR_STAT_R_RESTART_DET_Pos (12UL) /*!< R_RESTART_DET (Bit 12) */
#define I2C0_IC_INTR_STAT_R_RESTART_DET_Msk (0x1000UL) /*!< R_RESTART_DET (Bitfield-Mask: 0x01) */
#define I2C0_IC_INTR_STAT_R_GEN_CALL_Pos (11UL) /*!< R_GEN_CALL (Bit 11) */
#define I2C0_IC_INTR_STAT_R_GEN_CALL_Msk (0x800UL) /*!< R_GEN_CALL (Bitfield-Mask: 0x01) */
#define I2C0_IC_INTR_STAT_R_START_DET_Pos (10UL) /*!< R_START_DET (Bit 10) */
#define I2C0_IC_INTR_STAT_R_START_DET_Msk (0x400UL) /*!< R_START_DET (Bitfield-Mask: 0x01) */
#define I2C0_IC_INTR_STAT_R_STOP_DET_Pos (9UL) /*!< R_STOP_DET (Bit 9) */
#define I2C0_IC_INTR_STAT_R_STOP_DET_Msk (0x200UL) /*!< R_STOP_DET (Bitfield-Mask: 0x01) */
#define I2C0_IC_INTR_STAT_R_ACTIVITY_Pos (8UL) /*!< R_ACTIVITY (Bit 8) */
#define I2C0_IC_INTR_STAT_R_ACTIVITY_Msk (0x100UL) /*!< R_ACTIVITY (Bitfield-Mask: 0x01) */
#define I2C0_IC_INTR_STAT_R_RX_DONE_Pos (7UL) /*!< R_RX_DONE (Bit 7) */
#define I2C0_IC_INTR_STAT_R_RX_DONE_Msk (0x80UL) /*!< R_RX_DONE (Bitfield-Mask: 0x01) */
#define I2C0_IC_INTR_STAT_R_TX_ABRT_Pos (6UL) /*!< R_TX_ABRT (Bit 6) */
#define I2C0_IC_INTR_STAT_R_TX_ABRT_Msk (0x40UL) /*!< R_TX_ABRT (Bitfield-Mask: 0x01) */
#define I2C0_IC_INTR_STAT_R_RD_REQ_Pos (5UL) /*!< R_RD_REQ (Bit 5) */
#define I2C0_IC_INTR_STAT_R_RD_REQ_Msk (0x20UL) /*!< R_RD_REQ (Bitfield-Mask: 0x01) */
#define I2C0_IC_INTR_STAT_R_TX_EMPTY_Pos (4UL) /*!< R_TX_EMPTY (Bit 4) */
#define I2C0_IC_INTR_STAT_R_TX_EMPTY_Msk (0x10UL) /*!< R_TX_EMPTY (Bitfield-Mask: 0x01) */
#define I2C0_IC_INTR_STAT_R_TX_OVER_Pos (3UL) /*!< R_TX_OVER (Bit 3) */
#define I2C0_IC_INTR_STAT_R_TX_OVER_Msk (0x8UL) /*!< R_TX_OVER (Bitfield-Mask: 0x01) */
#define I2C0_IC_INTR_STAT_R_RX_FULL_Pos (2UL) /*!< R_RX_FULL (Bit 2) */
#define I2C0_IC_INTR_STAT_R_RX_FULL_Msk (0x4UL) /*!< R_RX_FULL (Bitfield-Mask: 0x01) */
#define I2C0_IC_INTR_STAT_R_RX_OVER_Pos (1UL) /*!< R_RX_OVER (Bit 1) */
#define I2C0_IC_INTR_STAT_R_RX_OVER_Msk (0x2UL) /*!< R_RX_OVER (Bitfield-Mask: 0x01) */
#define I2C0_IC_INTR_STAT_R_RX_UNDER_Pos (0UL) /*!< R_RX_UNDER (Bit 0) */
#define I2C0_IC_INTR_STAT_R_RX_UNDER_Msk (0x1UL) /*!< R_RX_UNDER (Bitfield-Mask: 0x01) */
/* ===================================================== IC_INTR_MASK ====================================================== */
#define I2C0_IC_INTR_MASK_M_RESTART_DET_Pos (12UL) /*!< M_RESTART_DET (Bit 12) */
#define I2C0_IC_INTR_MASK_M_RESTART_DET_Msk (0x1000UL) /*!< M_RESTART_DET (Bitfield-Mask: 0x01) */
#define I2C0_IC_INTR_MASK_M_GEN_CALL_Pos (11UL) /*!< M_GEN_CALL (Bit 11) */
#define I2C0_IC_INTR_MASK_M_GEN_CALL_Msk (0x800UL) /*!< M_GEN_CALL (Bitfield-Mask: 0x01) */
#define I2C0_IC_INTR_MASK_M_START_DET_Pos (10UL) /*!< M_START_DET (Bit 10) */
#define I2C0_IC_INTR_MASK_M_START_DET_Msk (0x400UL) /*!< M_START_DET (Bitfield-Mask: 0x01) */
#define I2C0_IC_INTR_MASK_M_STOP_DET_Pos (9UL) /*!< M_STOP_DET (Bit 9) */
#define I2C0_IC_INTR_MASK_M_STOP_DET_Msk (0x200UL) /*!< M_STOP_DET (Bitfield-Mask: 0x01) */
#define I2C0_IC_INTR_MASK_M_ACTIVITY_Pos (8UL) /*!< M_ACTIVITY (Bit 8) */
#define I2C0_IC_INTR_MASK_M_ACTIVITY_Msk (0x100UL) /*!< M_ACTIVITY (Bitfield-Mask: 0x01) */
#define I2C0_IC_INTR_MASK_M_RX_DONE_Pos (7UL) /*!< M_RX_DONE (Bit 7) */
#define I2C0_IC_INTR_MASK_M_RX_DONE_Msk (0x80UL) /*!< M_RX_DONE (Bitfield-Mask: 0x01) */
#define I2C0_IC_INTR_MASK_M_TX_ABRT_Pos (6UL) /*!< M_TX_ABRT (Bit 6) */
#define I2C0_IC_INTR_MASK_M_TX_ABRT_Msk (0x40UL) /*!< M_TX_ABRT (Bitfield-Mask: 0x01) */
#define I2C0_IC_INTR_MASK_M_RD_REQ_Pos (5UL) /*!< M_RD_REQ (Bit 5) */
#define I2C0_IC_INTR_MASK_M_RD_REQ_Msk (0x20UL) /*!< M_RD_REQ (Bitfield-Mask: 0x01) */
#define I2C0_IC_INTR_MASK_M_TX_EMPTY_Pos (4UL) /*!< M_TX_EMPTY (Bit 4) */
#define I2C0_IC_INTR_MASK_M_TX_EMPTY_Msk (0x10UL) /*!< M_TX_EMPTY (Bitfield-Mask: 0x01) */
#define I2C0_IC_INTR_MASK_M_TX_OVER_Pos (3UL) /*!< M_TX_OVER (Bit 3) */
#define I2C0_IC_INTR_MASK_M_TX_OVER_Msk (0x8UL) /*!< M_TX_OVER (Bitfield-Mask: 0x01) */
#define I2C0_IC_INTR_MASK_M_RX_FULL_Pos (2UL) /*!< M_RX_FULL (Bit 2) */
#define I2C0_IC_INTR_MASK_M_RX_FULL_Msk (0x4UL) /*!< M_RX_FULL (Bitfield-Mask: 0x01) */
#define I2C0_IC_INTR_MASK_M_RX_OVER_Pos (1UL) /*!< M_RX_OVER (Bit 1) */
#define I2C0_IC_INTR_MASK_M_RX_OVER_Msk (0x2UL) /*!< M_RX_OVER (Bitfield-Mask: 0x01) */
#define I2C0_IC_INTR_MASK_M_RX_UNDER_Pos (0UL) /*!< M_RX_UNDER (Bit 0) */
#define I2C0_IC_INTR_MASK_M_RX_UNDER_Msk (0x1UL) /*!< M_RX_UNDER (Bitfield-Mask: 0x01) */
/* =================================================== IC_RAW_INTR_STAT ==================================================== */
#define I2C0_IC_RAW_INTR_STAT_RESTART_DET_Pos (12UL) /*!< RESTART_DET (Bit 12) */
#define I2C0_IC_RAW_INTR_STAT_RESTART_DET_Msk (0x1000UL) /*!< RESTART_DET (Bitfield-Mask: 0x01) */
#define I2C0_IC_RAW_INTR_STAT_GEN_CALL_Pos (11UL) /*!< GEN_CALL (Bit 11) */
#define I2C0_IC_RAW_INTR_STAT_GEN_CALL_Msk (0x800UL) /*!< GEN_CALL (Bitfield-Mask: 0x01) */
#define I2C0_IC_RAW_INTR_STAT_START_DET_Pos (10UL) /*!< START_DET (Bit 10) */
#define I2C0_IC_RAW_INTR_STAT_START_DET_Msk (0x400UL) /*!< START_DET (Bitfield-Mask: 0x01) */
#define I2C0_IC_RAW_INTR_STAT_STOP_DET_Pos (9UL) /*!< STOP_DET (Bit 9) */
#define I2C0_IC_RAW_INTR_STAT_STOP_DET_Msk (0x200UL) /*!< STOP_DET (Bitfield-Mask: 0x01) */
#define I2C0_IC_RAW_INTR_STAT_ACTIVITY_Pos (8UL) /*!< ACTIVITY (Bit 8) */
#define I2C0_IC_RAW_INTR_STAT_ACTIVITY_Msk (0x100UL) /*!< ACTIVITY (Bitfield-Mask: 0x01) */
#define I2C0_IC_RAW_INTR_STAT_RX_DONE_Pos (7UL) /*!< RX_DONE (Bit 7) */
#define I2C0_IC_RAW_INTR_STAT_RX_DONE_Msk (0x80UL) /*!< RX_DONE (Bitfield-Mask: 0x01) */
#define I2C0_IC_RAW_INTR_STAT_TX_ABRT_Pos (6UL) /*!< TX_ABRT (Bit 6) */
#define I2C0_IC_RAW_INTR_STAT_TX_ABRT_Msk (0x40UL) /*!< TX_ABRT (Bitfield-Mask: 0x01) */
#define I2C0_IC_RAW_INTR_STAT_RD_REQ_Pos (5UL) /*!< RD_REQ (Bit 5) */
#define I2C0_IC_RAW_INTR_STAT_RD_REQ_Msk (0x20UL) /*!< RD_REQ (Bitfield-Mask: 0x01) */
#define I2C0_IC_RAW_INTR_STAT_TX_EMPTY_Pos (4UL) /*!< TX_EMPTY (Bit 4) */
#define I2C0_IC_RAW_INTR_STAT_TX_EMPTY_Msk (0x10UL) /*!< TX_EMPTY (Bitfield-Mask: 0x01) */
#define I2C0_IC_RAW_INTR_STAT_TX_OVER_Pos (3UL) /*!< TX_OVER (Bit 3) */
#define I2C0_IC_RAW_INTR_STAT_TX_OVER_Msk (0x8UL) /*!< TX_OVER (Bitfield-Mask: 0x01) */
#define I2C0_IC_RAW_INTR_STAT_RX_FULL_Pos (2UL) /*!< RX_FULL (Bit 2) */
#define I2C0_IC_RAW_INTR_STAT_RX_FULL_Msk (0x4UL) /*!< RX_FULL (Bitfield-Mask: 0x01) */
#define I2C0_IC_RAW_INTR_STAT_RX_OVER_Pos (1UL) /*!< RX_OVER (Bit 1) */
#define I2C0_IC_RAW_INTR_STAT_RX_OVER_Msk (0x2UL) /*!< RX_OVER (Bitfield-Mask: 0x01) */
#define I2C0_IC_RAW_INTR_STAT_RX_UNDER_Pos (0UL) /*!< RX_UNDER (Bit 0) */
#define I2C0_IC_RAW_INTR_STAT_RX_UNDER_Msk (0x1UL) /*!< RX_UNDER (Bitfield-Mask: 0x01) */
/* ======================================================= IC_RX_TL ======================================================== */
#define I2C0_IC_RX_TL_RX_TL_Pos (0UL) /*!< RX_TL (Bit 0) */
#define I2C0_IC_RX_TL_RX_TL_Msk (0xffUL) /*!< RX_TL (Bitfield-Mask: 0xff) */
/* ======================================================= IC_TX_TL ======================================================== */
#define I2C0_IC_TX_TL_TX_TL_Pos (0UL) /*!< TX_TL (Bit 0) */
#define I2C0_IC_TX_TL_TX_TL_Msk (0xffUL) /*!< TX_TL (Bitfield-Mask: 0xff) */
/* ====================================================== IC_CLR_INTR ====================================================== */
#define I2C0_IC_CLR_INTR_CLR_INTR_Pos (0UL) /*!< CLR_INTR (Bit 0) */
#define I2C0_IC_CLR_INTR_CLR_INTR_Msk (0x1UL) /*!< CLR_INTR (Bitfield-Mask: 0x01) */
/* ==================================================== IC_CLR_RX_UNDER ==================================================== */
#define I2C0_IC_CLR_RX_UNDER_CLR_RX_UNDER_Pos (0UL) /*!< CLR_RX_UNDER (Bit 0) */
#define I2C0_IC_CLR_RX_UNDER_CLR_RX_UNDER_Msk (0x1UL) /*!< CLR_RX_UNDER (Bitfield-Mask: 0x01) */
/* ==================================================== IC_CLR_RX_OVER ===================================================== */
#define I2C0_IC_CLR_RX_OVER_CLR_RX_OVER_Pos (0UL) /*!< CLR_RX_OVER (Bit 0) */
#define I2C0_IC_CLR_RX_OVER_CLR_RX_OVER_Msk (0x1UL) /*!< CLR_RX_OVER (Bitfield-Mask: 0x01) */
/* ==================================================== IC_CLR_TX_OVER ===================================================== */
#define I2C0_IC_CLR_TX_OVER_CLR_TX_OVER_Pos (0UL) /*!< CLR_TX_OVER (Bit 0) */
#define I2C0_IC_CLR_TX_OVER_CLR_TX_OVER_Msk (0x1UL) /*!< CLR_TX_OVER (Bitfield-Mask: 0x01) */
/* ===================================================== IC_CLR_RD_REQ ===================================================== */
#define I2C0_IC_CLR_RD_REQ_CLR_RD_REQ_Pos (0UL) /*!< CLR_RD_REQ (Bit 0) */
#define I2C0_IC_CLR_RD_REQ_CLR_RD_REQ_Msk (0x1UL) /*!< CLR_RD_REQ (Bitfield-Mask: 0x01) */
/* ==================================================== IC_CLR_TX_ABRT ===================================================== */
#define I2C0_IC_CLR_TX_ABRT_CLR_TX_ABRT_Pos (0UL) /*!< CLR_TX_ABRT (Bit 0) */
#define I2C0_IC_CLR_TX_ABRT_CLR_TX_ABRT_Msk (0x1UL) /*!< CLR_TX_ABRT (Bitfield-Mask: 0x01) */
/* ==================================================== IC_CLR_RX_DONE ===================================================== */
#define I2C0_IC_CLR_RX_DONE_CLR_RX_DONE_Pos (0UL) /*!< CLR_RX_DONE (Bit 0) */
#define I2C0_IC_CLR_RX_DONE_CLR_RX_DONE_Msk (0x1UL) /*!< CLR_RX_DONE (Bitfield-Mask: 0x01) */
/* ==================================================== IC_CLR_ACTIVITY ==================================================== */
#define I2C0_IC_CLR_ACTIVITY_CLR_ACTIVITY_Pos (0UL) /*!< CLR_ACTIVITY (Bit 0) */
#define I2C0_IC_CLR_ACTIVITY_CLR_ACTIVITY_Msk (0x1UL) /*!< CLR_ACTIVITY (Bitfield-Mask: 0x01) */
/* ==================================================== IC_CLR_STOP_DET ==================================================== */
#define I2C0_IC_CLR_STOP_DET_CLR_STOP_DET_Pos (0UL) /*!< CLR_STOP_DET (Bit 0) */
#define I2C0_IC_CLR_STOP_DET_CLR_STOP_DET_Msk (0x1UL) /*!< CLR_STOP_DET (Bitfield-Mask: 0x01) */
/* =================================================== IC_CLR_START_DET ==================================================== */
#define I2C0_IC_CLR_START_DET_CLR_START_DET_Pos (0UL) /*!< CLR_START_DET (Bit 0) */
#define I2C0_IC_CLR_START_DET_CLR_START_DET_Msk (0x1UL) /*!< CLR_START_DET (Bitfield-Mask: 0x01) */
/* ==================================================== IC_CLR_GEN_CALL ==================================================== */
#define I2C0_IC_CLR_GEN_CALL_CLR_GEN_CALL_Pos (0UL) /*!< CLR_GEN_CALL (Bit 0) */
#define I2C0_IC_CLR_GEN_CALL_CLR_GEN_CALL_Msk (0x1UL) /*!< CLR_GEN_CALL (Bitfield-Mask: 0x01) */
/* ======================================================= IC_ENABLE ======================================================= */
#define I2C0_IC_ENABLE_TX_CMD_BLOCK_Pos (2UL) /*!< TX_CMD_BLOCK (Bit 2) */
#define I2C0_IC_ENABLE_TX_CMD_BLOCK_Msk (0x4UL) /*!< TX_CMD_BLOCK (Bitfield-Mask: 0x01) */
#define I2C0_IC_ENABLE_ABORT_Pos (1UL) /*!< ABORT (Bit 1) */
#define I2C0_IC_ENABLE_ABORT_Msk (0x2UL) /*!< ABORT (Bitfield-Mask: 0x01) */
#define I2C0_IC_ENABLE_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */
#define I2C0_IC_ENABLE_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */
/* ======================================================= IC_STATUS ======================================================= */
#define I2C0_IC_STATUS_SLV_ACTIVITY_Pos (6UL) /*!< SLV_ACTIVITY (Bit 6) */
#define I2C0_IC_STATUS_SLV_ACTIVITY_Msk (0x40UL) /*!< SLV_ACTIVITY (Bitfield-Mask: 0x01) */
#define I2C0_IC_STATUS_MST_ACTIVITY_Pos (5UL) /*!< MST_ACTIVITY (Bit 5) */
#define I2C0_IC_STATUS_MST_ACTIVITY_Msk (0x20UL) /*!< MST_ACTIVITY (Bitfield-Mask: 0x01) */
#define I2C0_IC_STATUS_RFF_Pos (4UL) /*!< RFF (Bit 4) */
#define I2C0_IC_STATUS_RFF_Msk (0x10UL) /*!< RFF (Bitfield-Mask: 0x01) */
#define I2C0_IC_STATUS_RFNE_Pos (3UL) /*!< RFNE (Bit 3) */
#define I2C0_IC_STATUS_RFNE_Msk (0x8UL) /*!< RFNE (Bitfield-Mask: 0x01) */
#define I2C0_IC_STATUS_TFE_Pos (2UL) /*!< TFE (Bit 2) */
#define I2C0_IC_STATUS_TFE_Msk (0x4UL) /*!< TFE (Bitfield-Mask: 0x01) */
#define I2C0_IC_STATUS_TFNF_Pos (1UL) /*!< TFNF (Bit 1) */
#define I2C0_IC_STATUS_TFNF_Msk (0x2UL) /*!< TFNF (Bitfield-Mask: 0x01) */
#define I2C0_IC_STATUS_ACTIVITY_Pos (0UL) /*!< ACTIVITY (Bit 0) */
#define I2C0_IC_STATUS_ACTIVITY_Msk (0x1UL) /*!< ACTIVITY (Bitfield-Mask: 0x01) */
/* ======================================================= IC_TXFLR ======================================================== */
#define I2C0_IC_TXFLR_TXFLR_Pos (0UL) /*!< TXFLR (Bit 0) */
#define I2C0_IC_TXFLR_TXFLR_Msk (0x1fUL) /*!< TXFLR (Bitfield-Mask: 0x1f) */
/* ======================================================= IC_RXFLR ======================================================== */
#define I2C0_IC_RXFLR_RXFLR_Pos (0UL) /*!< RXFLR (Bit 0) */
#define I2C0_IC_RXFLR_RXFLR_Msk (0x1fUL) /*!< RXFLR (Bitfield-Mask: 0x1f) */
/* ====================================================== IC_SDA_HOLD ====================================================== */
#define I2C0_IC_SDA_HOLD_IC_SDA_RX_HOLD_Pos (16UL) /*!< IC_SDA_RX_HOLD (Bit 16) */
#define I2C0_IC_SDA_HOLD_IC_SDA_RX_HOLD_Msk (0xff0000UL) /*!< IC_SDA_RX_HOLD (Bitfield-Mask: 0xff) */
#define I2C0_IC_SDA_HOLD_IC_SDA_TX_HOLD_Pos (0UL) /*!< IC_SDA_TX_HOLD (Bit 0) */
#define I2C0_IC_SDA_HOLD_IC_SDA_TX_HOLD_Msk (0xffffUL) /*!< IC_SDA_TX_HOLD (Bitfield-Mask: 0xffff) */
/* =================================================== IC_TX_ABRT_SOURCE =================================================== */
#define I2C0_IC_TX_ABRT_SOURCE_TX_FLUSH_CNT_Pos (23UL) /*!< TX_FLUSH_CNT (Bit 23) */
#define I2C0_IC_TX_ABRT_SOURCE_TX_FLUSH_CNT_Msk (0xff800000UL) /*!< TX_FLUSH_CNT (Bitfield-Mask: 0x1ff) */
#define I2C0_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_Pos (16UL) /*!< ABRT_USER_ABRT (Bit 16) */
#define I2C0_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_Msk (0x10000UL) /*!< ABRT_USER_ABRT (Bitfield-Mask: 0x01) */
#define I2C0_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_Pos (15UL) /*!< ABRT_SLVRD_INTX (Bit 15) */
#define I2C0_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_Msk (0x8000UL) /*!< ABRT_SLVRD_INTX (Bitfield-Mask: 0x01) */
#define I2C0_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_Pos (14UL) /*!< ABRT_SLV_ARBLOST (Bit 14) */
#define I2C0_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_Msk (0x4000UL) /*!< ABRT_SLV_ARBLOST (Bitfield-Mask: 0x01) */
#define I2C0_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_Pos (13UL) /*!< ABRT_SLVFLUSH_TXFIFO (Bit 13) */
#define I2C0_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_Msk (0x2000UL) /*!< ABRT_SLVFLUSH_TXFIFO (Bitfield-Mask: 0x01) */
#define I2C0_IC_TX_ABRT_SOURCE_ARB_LOST_Pos (12UL) /*!< ARB_LOST (Bit 12) */
#define I2C0_IC_TX_ABRT_SOURCE_ARB_LOST_Msk (0x1000UL) /*!< ARB_LOST (Bitfield-Mask: 0x01) */
#define I2C0_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_Pos (11UL) /*!< ABRT_MASTER_DIS (Bit 11) */
#define I2C0_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_Msk (0x800UL) /*!< ABRT_MASTER_DIS (Bitfield-Mask: 0x01) */
#define I2C0_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_Pos (10UL) /*!< ABRT_10B_RD_NORSTRT (Bit 10) */
#define I2C0_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_Msk (0x400UL) /*!< ABRT_10B_RD_NORSTRT (Bitfield-Mask: 0x01) */
#define I2C0_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_Pos (9UL) /*!< ABRT_SBYTE_NORSTRT (Bit 9) */
#define I2C0_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_Msk (0x200UL) /*!< ABRT_SBYTE_NORSTRT (Bitfield-Mask: 0x01) */
#define I2C0_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_Pos (8UL) /*!< ABRT_HS_NORSTRT (Bit 8) */
#define I2C0_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_Msk (0x100UL) /*!< ABRT_HS_NORSTRT (Bitfield-Mask: 0x01) */
#define I2C0_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_Pos (7UL) /*!< ABRT_SBYTE_ACKDET (Bit 7) */
#define I2C0_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_Msk (0x80UL) /*!< ABRT_SBYTE_ACKDET (Bitfield-Mask: 0x01) */
#define I2C0_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_Pos (6UL) /*!< ABRT_HS_ACKDET (Bit 6) */
#define I2C0_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_Msk (0x40UL) /*!< ABRT_HS_ACKDET (Bitfield-Mask: 0x01) */
#define I2C0_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_Pos (5UL) /*!< ABRT_GCALL_READ (Bit 5) */
#define I2C0_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_Msk (0x20UL) /*!< ABRT_GCALL_READ (Bitfield-Mask: 0x01) */
#define I2C0_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_Pos (4UL) /*!< ABRT_GCALL_NOACK (Bit 4) */
#define I2C0_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_Msk (0x10UL) /*!< ABRT_GCALL_NOACK (Bitfield-Mask: 0x01) */
#define I2C0_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_Pos (3UL) /*!< ABRT_TXDATA_NOACK (Bit 3) */
#define I2C0_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_Msk (0x8UL) /*!< ABRT_TXDATA_NOACK (Bitfield-Mask: 0x01) */
#define I2C0_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_Pos (2UL) /*!< ABRT_10ADDR2_NOACK (Bit 2) */
#define I2C0_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_Msk (0x4UL) /*!< ABRT_10ADDR2_NOACK (Bitfield-Mask: 0x01) */
#define I2C0_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_Pos (1UL) /*!< ABRT_10ADDR1_NOACK (Bit 1) */
#define I2C0_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_Msk (0x2UL) /*!< ABRT_10ADDR1_NOACK (Bitfield-Mask: 0x01) */
#define I2C0_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_Pos (0UL) /*!< ABRT_7B_ADDR_NOACK (Bit 0) */
#define I2C0_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_Msk (0x1UL) /*!< ABRT_7B_ADDR_NOACK (Bitfield-Mask: 0x01) */
/* ================================================= IC_SLV_DATA_NACK_ONLY ================================================= */
#define I2C0_IC_SLV_DATA_NACK_ONLY_NACK_Pos (0UL) /*!< NACK (Bit 0) */
#define I2C0_IC_SLV_DATA_NACK_ONLY_NACK_Msk (0x1UL) /*!< NACK (Bitfield-Mask: 0x01) */
/* ======================================================= IC_DMA_CR ======================================================= */
#define I2C0_IC_DMA_CR_TDMAE_Pos (1UL) /*!< TDMAE (Bit 1) */
#define I2C0_IC_DMA_CR_TDMAE_Msk (0x2UL) /*!< TDMAE (Bitfield-Mask: 0x01) */
#define I2C0_IC_DMA_CR_RDMAE_Pos (0UL) /*!< RDMAE (Bit 0) */
#define I2C0_IC_DMA_CR_RDMAE_Msk (0x1UL) /*!< RDMAE (Bitfield-Mask: 0x01) */
/* ====================================================== IC_DMA_TDLR ====================================================== */
#define I2C0_IC_DMA_TDLR_DMATDL_Pos (0UL) /*!< DMATDL (Bit 0) */
#define I2C0_IC_DMA_TDLR_DMATDL_Msk (0xfUL) /*!< DMATDL (Bitfield-Mask: 0x0f) */
/* ====================================================== IC_DMA_RDLR ====================================================== */
#define I2C0_IC_DMA_RDLR_DMARDL_Pos (0UL) /*!< DMARDL (Bit 0) */
#define I2C0_IC_DMA_RDLR_DMARDL_Msk (0xfUL) /*!< DMARDL (Bitfield-Mask: 0x0f) */
/* ===================================================== IC_SDA_SETUP ====================================================== */
#define I2C0_IC_SDA_SETUP_SDA_SETUP_Pos (0UL) /*!< SDA_SETUP (Bit 0) */
#define I2C0_IC_SDA_SETUP_SDA_SETUP_Msk (0xffUL) /*!< SDA_SETUP (Bitfield-Mask: 0xff) */
/* ================================================== IC_ACK_GENERAL_CALL ================================================== */
#define I2C0_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_Pos (0UL) /*!< ACK_GEN_CALL (Bit 0) */
#define I2C0_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_Msk (0x1UL) /*!< ACK_GEN_CALL (Bitfield-Mask: 0x01) */
/* =================================================== IC_ENABLE_STATUS ==================================================== */
#define I2C0_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_Pos (2UL) /*!< SLV_RX_DATA_LOST (Bit 2) */
#define I2C0_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_Msk (0x4UL) /*!< SLV_RX_DATA_LOST (Bitfield-Mask: 0x01) */
#define I2C0_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_Pos (1UL) /*!< SLV_DISABLED_WHILE_BUSY (Bit 1) */
#define I2C0_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_Msk (0x2UL) /*!< SLV_DISABLED_WHILE_BUSY (Bitfield-Mask: 0x01) */
#define I2C0_IC_ENABLE_STATUS_IC_EN_Pos (0UL) /*!< IC_EN (Bit 0) */
#define I2C0_IC_ENABLE_STATUS_IC_EN_Msk (0x1UL) /*!< IC_EN (Bitfield-Mask: 0x01) */
/* ===================================================== IC_FS_SPKLEN ====================================================== */
#define I2C0_IC_FS_SPKLEN_IC_FS_SPKLEN_Pos (0UL) /*!< IC_FS_SPKLEN (Bit 0) */
#define I2C0_IC_FS_SPKLEN_IC_FS_SPKLEN_Msk (0xffUL) /*!< IC_FS_SPKLEN (Bitfield-Mask: 0xff) */
/* ================================================== IC_CLR_RESTART_DET =================================================== */
#define I2C0_IC_CLR_RESTART_DET_CLR_RESTART_DET_Pos (0UL) /*!< CLR_RESTART_DET (Bit 0) */
#define I2C0_IC_CLR_RESTART_DET_CLR_RESTART_DET_Msk (0x1UL) /*!< CLR_RESTART_DET (Bitfield-Mask: 0x01) */
/* ==================================================== IC_COMP_PARAM_1 ==================================================== */
#define I2C0_IC_COMP_PARAM_1_TX_BUFFER_DEPTH_Pos (16UL) /*!< TX_BUFFER_DEPTH (Bit 16) */
#define I2C0_IC_COMP_PARAM_1_TX_BUFFER_DEPTH_Msk (0xff0000UL) /*!< TX_BUFFER_DEPTH (Bitfield-Mask: 0xff) */
#define I2C0_IC_COMP_PARAM_1_RX_BUFFER_DEPTH_Pos (8UL) /*!< RX_BUFFER_DEPTH (Bit 8) */
#define I2C0_IC_COMP_PARAM_1_RX_BUFFER_DEPTH_Msk (0xff00UL) /*!< RX_BUFFER_DEPTH (Bitfield-Mask: 0xff) */
#define I2C0_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS_Pos (7UL) /*!< ADD_ENCODED_PARAMS (Bit 7) */
#define I2C0_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS_Msk (0x80UL) /*!< ADD_ENCODED_PARAMS (Bitfield-Mask: 0x01) */
#define I2C0_IC_COMP_PARAM_1_HAS_DMA_Pos (6UL) /*!< HAS_DMA (Bit 6) */
#define I2C0_IC_COMP_PARAM_1_HAS_DMA_Msk (0x40UL) /*!< HAS_DMA (Bitfield-Mask: 0x01) */
#define I2C0_IC_COMP_PARAM_1_INTR_IO_Pos (5UL) /*!< INTR_IO (Bit 5) */
#define I2C0_IC_COMP_PARAM_1_INTR_IO_Msk (0x20UL) /*!< INTR_IO (Bitfield-Mask: 0x01) */
#define I2C0_IC_COMP_PARAM_1_HC_COUNT_VALUES_Pos (4UL) /*!< HC_COUNT_VALUES (Bit 4) */
#define I2C0_IC_COMP_PARAM_1_HC_COUNT_VALUES_Msk (0x10UL) /*!< HC_COUNT_VALUES (Bitfield-Mask: 0x01) */
#define I2C0_IC_COMP_PARAM_1_MAX_SPEED_MODE_Pos (2UL) /*!< MAX_SPEED_MODE (Bit 2) */
#define I2C0_IC_COMP_PARAM_1_MAX_SPEED_MODE_Msk (0xcUL) /*!< MAX_SPEED_MODE (Bitfield-Mask: 0x03) */
#define I2C0_IC_COMP_PARAM_1_APB_DATA_WIDTH_Pos (0UL) /*!< APB_DATA_WIDTH (Bit 0) */
#define I2C0_IC_COMP_PARAM_1_APB_DATA_WIDTH_Msk (0x3UL) /*!< APB_DATA_WIDTH (Bitfield-Mask: 0x03) */
/* ==================================================== IC_COMP_VERSION ==================================================== */
#define I2C0_IC_COMP_VERSION_IC_COMP_VERSION_Pos (0UL) /*!< IC_COMP_VERSION (Bit 0) */
#define I2C0_IC_COMP_VERSION_IC_COMP_VERSION_Msk (0xffffffffUL) /*!< IC_COMP_VERSION (Bitfield-Mask: 0xffffffff) */
/* ===================================================== IC_COMP_TYPE ====================================================== */
#define I2C0_IC_COMP_TYPE_IC_COMP_TYPE_Pos (0UL) /*!< IC_COMP_TYPE (Bit 0) */
#define I2C0_IC_COMP_TYPE_IC_COMP_TYPE_Msk (0xffffffffUL) /*!< IC_COMP_TYPE (Bitfield-Mask: 0xffffffff) */
/* =========================================================================================================================== */
/* ================ ADC ================ */
/* =========================================================================================================================== */
/* ========================================================== CS =========================================================== */
#define ADC_CS_RROBIN_Pos (16UL) /*!< RROBIN (Bit 16) */
#define ADC_CS_RROBIN_Msk (0x1f0000UL) /*!< RROBIN (Bitfield-Mask: 0x1f) */
#define ADC_CS_AINSEL_Pos (12UL) /*!< AINSEL (Bit 12) */
#define ADC_CS_AINSEL_Msk (0x7000UL) /*!< AINSEL (Bitfield-Mask: 0x07) */
#define ADC_CS_ERR_STICKY_Pos (10UL) /*!< ERR_STICKY (Bit 10) */
#define ADC_CS_ERR_STICKY_Msk (0x400UL) /*!< ERR_STICKY (Bitfield-Mask: 0x01) */
#define ADC_CS_ERR_Pos (9UL) /*!< ERR (Bit 9) */
#define ADC_CS_ERR_Msk (0x200UL) /*!< ERR (Bitfield-Mask: 0x01) */
#define ADC_CS_READY_Pos (8UL) /*!< READY (Bit 8) */
#define ADC_CS_READY_Msk (0x100UL) /*!< READY (Bitfield-Mask: 0x01) */
#define ADC_CS_START_MANY_Pos (3UL) /*!< START_MANY (Bit 3) */
#define ADC_CS_START_MANY_Msk (0x8UL) /*!< START_MANY (Bitfield-Mask: 0x01) */
#define ADC_CS_START_ONCE_Pos (2UL) /*!< START_ONCE (Bit 2) */
#define ADC_CS_START_ONCE_Msk (0x4UL) /*!< START_ONCE (Bitfield-Mask: 0x01) */
#define ADC_CS_TS_EN_Pos (1UL) /*!< TS_EN (Bit 1) */
#define ADC_CS_TS_EN_Msk (0x2UL) /*!< TS_EN (Bitfield-Mask: 0x01) */
#define ADC_CS_EN_Pos (0UL) /*!< EN (Bit 0) */
#define ADC_CS_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */
/* ======================================================== RESULT ========================================================= */
#define ADC_RESULT_RESULT_Pos (0UL) /*!< RESULT (Bit 0) */
#define ADC_RESULT_RESULT_Msk (0xfffUL) /*!< RESULT (Bitfield-Mask: 0xfff) */
/* ========================================================== FCS ========================================================== */
#define ADC_FCS_THRESH_Pos (24UL) /*!< THRESH (Bit 24) */
#define ADC_FCS_THRESH_Msk (0xf000000UL) /*!< THRESH (Bitfield-Mask: 0x0f) */
#define ADC_FCS_LEVEL_Pos (16UL) /*!< LEVEL (Bit 16) */
#define ADC_FCS_LEVEL_Msk (0xf0000UL) /*!< LEVEL (Bitfield-Mask: 0x0f) */
#define ADC_FCS_OVER_Pos (11UL) /*!< OVER (Bit 11) */
#define ADC_FCS_OVER_Msk (0x800UL) /*!< OVER (Bitfield-Mask: 0x01) */
#define ADC_FCS_UNDER_Pos (10UL) /*!< UNDER (Bit 10) */
#define ADC_FCS_UNDER_Msk (0x400UL) /*!< UNDER (Bitfield-Mask: 0x01) */
#define ADC_FCS_FULL_Pos (9UL) /*!< FULL (Bit 9) */
#define ADC_FCS_FULL_Msk (0x200UL) /*!< FULL (Bitfield-Mask: 0x01) */
#define ADC_FCS_EMPTY_Pos (8UL) /*!< EMPTY (Bit 8) */
#define ADC_FCS_EMPTY_Msk (0x100UL) /*!< EMPTY (Bitfield-Mask: 0x01) */
#define ADC_FCS_DREQ_EN_Pos (3UL) /*!< DREQ_EN (Bit 3) */
#define ADC_FCS_DREQ_EN_Msk (0x8UL) /*!< DREQ_EN (Bitfield-Mask: 0x01) */
#define ADC_FCS_ERR_Pos (2UL) /*!< ERR (Bit 2) */
#define ADC_FCS_ERR_Msk (0x4UL) /*!< ERR (Bitfield-Mask: 0x01) */
#define ADC_FCS_SHIFT_Pos (1UL) /*!< SHIFT (Bit 1) */
#define ADC_FCS_SHIFT_Msk (0x2UL) /*!< SHIFT (Bitfield-Mask: 0x01) */
#define ADC_FCS_EN_Pos (0UL) /*!< EN (Bit 0) */
#define ADC_FCS_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */
/* ========================================================= FIFO ========================================================== */
#define ADC_FIFO_ERR_Pos (15UL) /*!< ERR (Bit 15) */
#define ADC_FIFO_ERR_Msk (0x8000UL) /*!< ERR (Bitfield-Mask: 0x01) */
#define ADC_FIFO_VAL_Pos (0UL) /*!< VAL (Bit 0) */
#define ADC_FIFO_VAL_Msk (0xfffUL) /*!< VAL (Bitfield-Mask: 0xfff) */
/* ========================================================== DIV ========================================================== */
#define ADC_DIV_INT_Pos (8UL) /*!< INT (Bit 8) */
#define ADC_DIV_INT_Msk (0xffff00UL) /*!< INT (Bitfield-Mask: 0xffff) */
#define ADC_DIV_FRAC_Pos (0UL) /*!< FRAC (Bit 0) */
#define ADC_DIV_FRAC_Msk (0xffUL) /*!< FRAC (Bitfield-Mask: 0xff) */
/* ========================================================= INTR ========================================================== */
#define ADC_INTR_FIFO_Pos (0UL) /*!< FIFO (Bit 0) */
#define ADC_INTR_FIFO_Msk (0x1UL) /*!< FIFO (Bitfield-Mask: 0x01) */
/* ========================================================= INTE ========================================================== */
#define ADC_INTE_FIFO_Pos (0UL) /*!< FIFO (Bit 0) */
#define ADC_INTE_FIFO_Msk (0x1UL) /*!< FIFO (Bitfield-Mask: 0x01) */
/* ========================================================= INTF ========================================================== */
#define ADC_INTF_FIFO_Pos (0UL) /*!< FIFO (Bit 0) */
#define ADC_INTF_FIFO_Msk (0x1UL) /*!< FIFO (Bitfield-Mask: 0x01) */
/* ========================================================= INTS ========================================================== */
#define ADC_INTS_FIFO_Pos (0UL) /*!< FIFO (Bit 0) */
#define ADC_INTS_FIFO_Msk (0x1UL) /*!< FIFO (Bitfield-Mask: 0x01) */
/* =========================================================================================================================== */
/* ================ PWM ================ */
/* =========================================================================================================================== */
/* ======================================================== CH0_CSR ======================================================== */
#define PWM_CH0_CSR_PH_ADV_Pos (7UL) /*!< PH_ADV (Bit 7) */
#define PWM_CH0_CSR_PH_ADV_Msk (0x80UL) /*!< PH_ADV (Bitfield-Mask: 0x01) */
#define PWM_CH0_CSR_PH_RET_Pos (6UL) /*!< PH_RET (Bit 6) */
#define PWM_CH0_CSR_PH_RET_Msk (0x40UL) /*!< PH_RET (Bitfield-Mask: 0x01) */
#define PWM_CH0_CSR_DIVMODE_Pos (4UL) /*!< DIVMODE (Bit 4) */
#define PWM_CH0_CSR_DIVMODE_Msk (0x30UL) /*!< DIVMODE (Bitfield-Mask: 0x03) */
#define PWM_CH0_CSR_B_INV_Pos (3UL) /*!< B_INV (Bit 3) */
#define PWM_CH0_CSR_B_INV_Msk (0x8UL) /*!< B_INV (Bitfield-Mask: 0x01) */
#define PWM_CH0_CSR_A_INV_Pos (2UL) /*!< A_INV (Bit 2) */
#define PWM_CH0_CSR_A_INV_Msk (0x4UL) /*!< A_INV (Bitfield-Mask: 0x01) */
#define PWM_CH0_CSR_PH_CORRECT_Pos (1UL) /*!< PH_CORRECT (Bit 1) */
#define PWM_CH0_CSR_PH_CORRECT_Msk (0x2UL) /*!< PH_CORRECT (Bitfield-Mask: 0x01) */
#define PWM_CH0_CSR_EN_Pos (0UL) /*!< EN (Bit 0) */
#define PWM_CH0_CSR_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */
/* ======================================================== CH0_DIV ======================================================== */
#define PWM_CH0_DIV_INT_Pos (4UL) /*!< INT (Bit 4) */
#define PWM_CH0_DIV_INT_Msk (0xff0UL) /*!< INT (Bitfield-Mask: 0xff) */
#define PWM_CH0_DIV_FRAC_Pos (0UL) /*!< FRAC (Bit 0) */
#define PWM_CH0_DIV_FRAC_Msk (0xfUL) /*!< FRAC (Bitfield-Mask: 0x0f) */
/* ======================================================== CH0_CTR ======================================================== */
#define PWM_CH0_CTR_CH0_CTR_Pos (0UL) /*!< CH0_CTR (Bit 0) */
#define PWM_CH0_CTR_CH0_CTR_Msk (0xffffUL) /*!< CH0_CTR (Bitfield-Mask: 0xffff) */
/* ======================================================== CH0_CC ========================================================= */
#define PWM_CH0_CC_B_Pos (16UL) /*!< B (Bit 16) */
#define PWM_CH0_CC_B_Msk (0xffff0000UL) /*!< B (Bitfield-Mask: 0xffff) */
#define PWM_CH0_CC_A_Pos (0UL) /*!< A (Bit 0) */
#define PWM_CH0_CC_A_Msk (0xffffUL) /*!< A (Bitfield-Mask: 0xffff) */
/* ======================================================== CH0_TOP ======================================================== */
#define PWM_CH0_TOP_CH0_TOP_Pos (0UL) /*!< CH0_TOP (Bit 0) */
#define PWM_CH0_TOP_CH0_TOP_Msk (0xffffUL) /*!< CH0_TOP (Bitfield-Mask: 0xffff) */
/* ======================================================== CH1_CSR ======================================================== */
#define PWM_CH1_CSR_PH_ADV_Pos (7UL) /*!< PH_ADV (Bit 7) */
#define PWM_CH1_CSR_PH_ADV_Msk (0x80UL) /*!< PH_ADV (Bitfield-Mask: 0x01) */
#define PWM_CH1_CSR_PH_RET_Pos (6UL) /*!< PH_RET (Bit 6) */
#define PWM_CH1_CSR_PH_RET_Msk (0x40UL) /*!< PH_RET (Bitfield-Mask: 0x01) */
#define PWM_CH1_CSR_DIVMODE_Pos (4UL) /*!< DIVMODE (Bit 4) */
#define PWM_CH1_CSR_DIVMODE_Msk (0x30UL) /*!< DIVMODE (Bitfield-Mask: 0x03) */
#define PWM_CH1_CSR_B_INV_Pos (3UL) /*!< B_INV (Bit 3) */
#define PWM_CH1_CSR_B_INV_Msk (0x8UL) /*!< B_INV (Bitfield-Mask: 0x01) */
#define PWM_CH1_CSR_A_INV_Pos (2UL) /*!< A_INV (Bit 2) */
#define PWM_CH1_CSR_A_INV_Msk (0x4UL) /*!< A_INV (Bitfield-Mask: 0x01) */
#define PWM_CH1_CSR_PH_CORRECT_Pos (1UL) /*!< PH_CORRECT (Bit 1) */
#define PWM_CH1_CSR_PH_CORRECT_Msk (0x2UL) /*!< PH_CORRECT (Bitfield-Mask: 0x01) */
#define PWM_CH1_CSR_EN_Pos (0UL) /*!< EN (Bit 0) */
#define PWM_CH1_CSR_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */
/* ======================================================== CH1_DIV ======================================================== */
#define PWM_CH1_DIV_INT_Pos (4UL) /*!< INT (Bit 4) */
#define PWM_CH1_DIV_INT_Msk (0xff0UL) /*!< INT (Bitfield-Mask: 0xff) */
#define PWM_CH1_DIV_FRAC_Pos (0UL) /*!< FRAC (Bit 0) */
#define PWM_CH1_DIV_FRAC_Msk (0xfUL) /*!< FRAC (Bitfield-Mask: 0x0f) */
/* ======================================================== CH1_CTR ======================================================== */
#define PWM_CH1_CTR_CH1_CTR_Pos (0UL) /*!< CH1_CTR (Bit 0) */
#define PWM_CH1_CTR_CH1_CTR_Msk (0xffffUL) /*!< CH1_CTR (Bitfield-Mask: 0xffff) */
/* ======================================================== CH1_CC ========================================================= */
#define PWM_CH1_CC_B_Pos (16UL) /*!< B (Bit 16) */
#define PWM_CH1_CC_B_Msk (0xffff0000UL) /*!< B (Bitfield-Mask: 0xffff) */
#define PWM_CH1_CC_A_Pos (0UL) /*!< A (Bit 0) */
#define PWM_CH1_CC_A_Msk (0xffffUL) /*!< A (Bitfield-Mask: 0xffff) */
/* ======================================================== CH1_TOP ======================================================== */
#define PWM_CH1_TOP_CH1_TOP_Pos (0UL) /*!< CH1_TOP (Bit 0) */
#define PWM_CH1_TOP_CH1_TOP_Msk (0xffffUL) /*!< CH1_TOP (Bitfield-Mask: 0xffff) */
/* ======================================================== CH2_CSR ======================================================== */
#define PWM_CH2_CSR_PH_ADV_Pos (7UL) /*!< PH_ADV (Bit 7) */
#define PWM_CH2_CSR_PH_ADV_Msk (0x80UL) /*!< PH_ADV (Bitfield-Mask: 0x01) */
#define PWM_CH2_CSR_PH_RET_Pos (6UL) /*!< PH_RET (Bit 6) */
#define PWM_CH2_CSR_PH_RET_Msk (0x40UL) /*!< PH_RET (Bitfield-Mask: 0x01) */
#define PWM_CH2_CSR_DIVMODE_Pos (4UL) /*!< DIVMODE (Bit 4) */
#define PWM_CH2_CSR_DIVMODE_Msk (0x30UL) /*!< DIVMODE (Bitfield-Mask: 0x03) */
#define PWM_CH2_CSR_B_INV_Pos (3UL) /*!< B_INV (Bit 3) */
#define PWM_CH2_CSR_B_INV_Msk (0x8UL) /*!< B_INV (Bitfield-Mask: 0x01) */
#define PWM_CH2_CSR_A_INV_Pos (2UL) /*!< A_INV (Bit 2) */
#define PWM_CH2_CSR_A_INV_Msk (0x4UL) /*!< A_INV (Bitfield-Mask: 0x01) */
#define PWM_CH2_CSR_PH_CORRECT_Pos (1UL) /*!< PH_CORRECT (Bit 1) */
#define PWM_CH2_CSR_PH_CORRECT_Msk (0x2UL) /*!< PH_CORRECT (Bitfield-Mask: 0x01) */
#define PWM_CH2_CSR_EN_Pos (0UL) /*!< EN (Bit 0) */
#define PWM_CH2_CSR_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */
/* ======================================================== CH2_DIV ======================================================== */
#define PWM_CH2_DIV_INT_Pos (4UL) /*!< INT (Bit 4) */
#define PWM_CH2_DIV_INT_Msk (0xff0UL) /*!< INT (Bitfield-Mask: 0xff) */
#define PWM_CH2_DIV_FRAC_Pos (0UL) /*!< FRAC (Bit 0) */
#define PWM_CH2_DIV_FRAC_Msk (0xfUL) /*!< FRAC (Bitfield-Mask: 0x0f) */
/* ======================================================== CH2_CTR ======================================================== */
#define PWM_CH2_CTR_CH2_CTR_Pos (0UL) /*!< CH2_CTR (Bit 0) */
#define PWM_CH2_CTR_CH2_CTR_Msk (0xffffUL) /*!< CH2_CTR (Bitfield-Mask: 0xffff) */
/* ======================================================== CH2_CC ========================================================= */
#define PWM_CH2_CC_B_Pos (16UL) /*!< B (Bit 16) */
#define PWM_CH2_CC_B_Msk (0xffff0000UL) /*!< B (Bitfield-Mask: 0xffff) */
#define PWM_CH2_CC_A_Pos (0UL) /*!< A (Bit 0) */
#define PWM_CH2_CC_A_Msk (0xffffUL) /*!< A (Bitfield-Mask: 0xffff) */
/* ======================================================== CH2_TOP ======================================================== */
#define PWM_CH2_TOP_CH2_TOP_Pos (0UL) /*!< CH2_TOP (Bit 0) */
#define PWM_CH2_TOP_CH2_TOP_Msk (0xffffUL) /*!< CH2_TOP (Bitfield-Mask: 0xffff) */
/* ======================================================== CH3_CSR ======================================================== */
#define PWM_CH3_CSR_PH_ADV_Pos (7UL) /*!< PH_ADV (Bit 7) */
#define PWM_CH3_CSR_PH_ADV_Msk (0x80UL) /*!< PH_ADV (Bitfield-Mask: 0x01) */
#define PWM_CH3_CSR_PH_RET_Pos (6UL) /*!< PH_RET (Bit 6) */
#define PWM_CH3_CSR_PH_RET_Msk (0x40UL) /*!< PH_RET (Bitfield-Mask: 0x01) */
#define PWM_CH3_CSR_DIVMODE_Pos (4UL) /*!< DIVMODE (Bit 4) */
#define PWM_CH3_CSR_DIVMODE_Msk (0x30UL) /*!< DIVMODE (Bitfield-Mask: 0x03) */
#define PWM_CH3_CSR_B_INV_Pos (3UL) /*!< B_INV (Bit 3) */
#define PWM_CH3_CSR_B_INV_Msk (0x8UL) /*!< B_INV (Bitfield-Mask: 0x01) */
#define PWM_CH3_CSR_A_INV_Pos (2UL) /*!< A_INV (Bit 2) */
#define PWM_CH3_CSR_A_INV_Msk (0x4UL) /*!< A_INV (Bitfield-Mask: 0x01) */
#define PWM_CH3_CSR_PH_CORRECT_Pos (1UL) /*!< PH_CORRECT (Bit 1) */
#define PWM_CH3_CSR_PH_CORRECT_Msk (0x2UL) /*!< PH_CORRECT (Bitfield-Mask: 0x01) */
#define PWM_CH3_CSR_EN_Pos (0UL) /*!< EN (Bit 0) */
#define PWM_CH3_CSR_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */
/* ======================================================== CH3_DIV ======================================================== */
#define PWM_CH3_DIV_INT_Pos (4UL) /*!< INT (Bit 4) */
#define PWM_CH3_DIV_INT_Msk (0xff0UL) /*!< INT (Bitfield-Mask: 0xff) */
#define PWM_CH3_DIV_FRAC_Pos (0UL) /*!< FRAC (Bit 0) */
#define PWM_CH3_DIV_FRAC_Msk (0xfUL) /*!< FRAC (Bitfield-Mask: 0x0f) */
/* ======================================================== CH3_CTR ======================================================== */
#define PWM_CH3_CTR_CH3_CTR_Pos (0UL) /*!< CH3_CTR (Bit 0) */
#define PWM_CH3_CTR_CH3_CTR_Msk (0xffffUL) /*!< CH3_CTR (Bitfield-Mask: 0xffff) */
/* ======================================================== CH3_CC ========================================================= */
#define PWM_CH3_CC_B_Pos (16UL) /*!< B (Bit 16) */
#define PWM_CH3_CC_B_Msk (0xffff0000UL) /*!< B (Bitfield-Mask: 0xffff) */
#define PWM_CH3_CC_A_Pos (0UL) /*!< A (Bit 0) */
#define PWM_CH3_CC_A_Msk (0xffffUL) /*!< A (Bitfield-Mask: 0xffff) */
/* ======================================================== CH3_TOP ======================================================== */
#define PWM_CH3_TOP_CH3_TOP_Pos (0UL) /*!< CH3_TOP (Bit 0) */
#define PWM_CH3_TOP_CH3_TOP_Msk (0xffffUL) /*!< CH3_TOP (Bitfield-Mask: 0xffff) */
/* ======================================================== CH4_CSR ======================================================== */
#define PWM_CH4_CSR_PH_ADV_Pos (7UL) /*!< PH_ADV (Bit 7) */
#define PWM_CH4_CSR_PH_ADV_Msk (0x80UL) /*!< PH_ADV (Bitfield-Mask: 0x01) */
#define PWM_CH4_CSR_PH_RET_Pos (6UL) /*!< PH_RET (Bit 6) */
#define PWM_CH4_CSR_PH_RET_Msk (0x40UL) /*!< PH_RET (Bitfield-Mask: 0x01) */
#define PWM_CH4_CSR_DIVMODE_Pos (4UL) /*!< DIVMODE (Bit 4) */
#define PWM_CH4_CSR_DIVMODE_Msk (0x30UL) /*!< DIVMODE (Bitfield-Mask: 0x03) */
#define PWM_CH4_CSR_B_INV_Pos (3UL) /*!< B_INV (Bit 3) */
#define PWM_CH4_CSR_B_INV_Msk (0x8UL) /*!< B_INV (Bitfield-Mask: 0x01) */
#define PWM_CH4_CSR_A_INV_Pos (2UL) /*!< A_INV (Bit 2) */
#define PWM_CH4_CSR_A_INV_Msk (0x4UL) /*!< A_INV (Bitfield-Mask: 0x01) */
#define PWM_CH4_CSR_PH_CORRECT_Pos (1UL) /*!< PH_CORRECT (Bit 1) */
#define PWM_CH4_CSR_PH_CORRECT_Msk (0x2UL) /*!< PH_CORRECT (Bitfield-Mask: 0x01) */
#define PWM_CH4_CSR_EN_Pos (0UL) /*!< EN (Bit 0) */
#define PWM_CH4_CSR_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */
/* ======================================================== CH4_DIV ======================================================== */
#define PWM_CH4_DIV_INT_Pos (4UL) /*!< INT (Bit 4) */
#define PWM_CH4_DIV_INT_Msk (0xff0UL) /*!< INT (Bitfield-Mask: 0xff) */
#define PWM_CH4_DIV_FRAC_Pos (0UL) /*!< FRAC (Bit 0) */
#define PWM_CH4_DIV_FRAC_Msk (0xfUL) /*!< FRAC (Bitfield-Mask: 0x0f) */
/* ======================================================== CH4_CTR ======================================================== */
#define PWM_CH4_CTR_CH4_CTR_Pos (0UL) /*!< CH4_CTR (Bit 0) */
#define PWM_CH4_CTR_CH4_CTR_Msk (0xffffUL) /*!< CH4_CTR (Bitfield-Mask: 0xffff) */
/* ======================================================== CH4_CC ========================================================= */
#define PWM_CH4_CC_B_Pos (16UL) /*!< B (Bit 16) */
#define PWM_CH4_CC_B_Msk (0xffff0000UL) /*!< B (Bitfield-Mask: 0xffff) */
#define PWM_CH4_CC_A_Pos (0UL) /*!< A (Bit 0) */
#define PWM_CH4_CC_A_Msk (0xffffUL) /*!< A (Bitfield-Mask: 0xffff) */
/* ======================================================== CH4_TOP ======================================================== */
#define PWM_CH4_TOP_CH4_TOP_Pos (0UL) /*!< CH4_TOP (Bit 0) */
#define PWM_CH4_TOP_CH4_TOP_Msk (0xffffUL) /*!< CH4_TOP (Bitfield-Mask: 0xffff) */
/* ======================================================== CH5_CSR ======================================================== */
#define PWM_CH5_CSR_PH_ADV_Pos (7UL) /*!< PH_ADV (Bit 7) */
#define PWM_CH5_CSR_PH_ADV_Msk (0x80UL) /*!< PH_ADV (Bitfield-Mask: 0x01) */
#define PWM_CH5_CSR_PH_RET_Pos (6UL) /*!< PH_RET (Bit 6) */
#define PWM_CH5_CSR_PH_RET_Msk (0x40UL) /*!< PH_RET (Bitfield-Mask: 0x01) */
#define PWM_CH5_CSR_DIVMODE_Pos (4UL) /*!< DIVMODE (Bit 4) */
#define PWM_CH5_CSR_DIVMODE_Msk (0x30UL) /*!< DIVMODE (Bitfield-Mask: 0x03) */
#define PWM_CH5_CSR_B_INV_Pos (3UL) /*!< B_INV (Bit 3) */
#define PWM_CH5_CSR_B_INV_Msk (0x8UL) /*!< B_INV (Bitfield-Mask: 0x01) */
#define PWM_CH5_CSR_A_INV_Pos (2UL) /*!< A_INV (Bit 2) */
#define PWM_CH5_CSR_A_INV_Msk (0x4UL) /*!< A_INV (Bitfield-Mask: 0x01) */
#define PWM_CH5_CSR_PH_CORRECT_Pos (1UL) /*!< PH_CORRECT (Bit 1) */
#define PWM_CH5_CSR_PH_CORRECT_Msk (0x2UL) /*!< PH_CORRECT (Bitfield-Mask: 0x01) */
#define PWM_CH5_CSR_EN_Pos (0UL) /*!< EN (Bit 0) */
#define PWM_CH5_CSR_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */
/* ======================================================== CH5_DIV ======================================================== */
#define PWM_CH5_DIV_INT_Pos (4UL) /*!< INT (Bit 4) */
#define PWM_CH5_DIV_INT_Msk (0xff0UL) /*!< INT (Bitfield-Mask: 0xff) */
#define PWM_CH5_DIV_FRAC_Pos (0UL) /*!< FRAC (Bit 0) */
#define PWM_CH5_DIV_FRAC_Msk (0xfUL) /*!< FRAC (Bitfield-Mask: 0x0f) */
/* ======================================================== CH5_CTR ======================================================== */
#define PWM_CH5_CTR_CH5_CTR_Pos (0UL) /*!< CH5_CTR (Bit 0) */
#define PWM_CH5_CTR_CH5_CTR_Msk (0xffffUL) /*!< CH5_CTR (Bitfield-Mask: 0xffff) */
/* ======================================================== CH5_CC ========================================================= */
#define PWM_CH5_CC_B_Pos (16UL) /*!< B (Bit 16) */
#define PWM_CH5_CC_B_Msk (0xffff0000UL) /*!< B (Bitfield-Mask: 0xffff) */
#define PWM_CH5_CC_A_Pos (0UL) /*!< A (Bit 0) */
#define PWM_CH5_CC_A_Msk (0xffffUL) /*!< A (Bitfield-Mask: 0xffff) */
/* ======================================================== CH5_TOP ======================================================== */
#define PWM_CH5_TOP_CH5_TOP_Pos (0UL) /*!< CH5_TOP (Bit 0) */
#define PWM_CH5_TOP_CH5_TOP_Msk (0xffffUL) /*!< CH5_TOP (Bitfield-Mask: 0xffff) */
/* ======================================================== CH6_CSR ======================================================== */
#define PWM_CH6_CSR_PH_ADV_Pos (7UL) /*!< PH_ADV (Bit 7) */
#define PWM_CH6_CSR_PH_ADV_Msk (0x80UL) /*!< PH_ADV (Bitfield-Mask: 0x01) */
#define PWM_CH6_CSR_PH_RET_Pos (6UL) /*!< PH_RET (Bit 6) */
#define PWM_CH6_CSR_PH_RET_Msk (0x40UL) /*!< PH_RET (Bitfield-Mask: 0x01) */
#define PWM_CH6_CSR_DIVMODE_Pos (4UL) /*!< DIVMODE (Bit 4) */
#define PWM_CH6_CSR_DIVMODE_Msk (0x30UL) /*!< DIVMODE (Bitfield-Mask: 0x03) */
#define PWM_CH6_CSR_B_INV_Pos (3UL) /*!< B_INV (Bit 3) */
#define PWM_CH6_CSR_B_INV_Msk (0x8UL) /*!< B_INV (Bitfield-Mask: 0x01) */
#define PWM_CH6_CSR_A_INV_Pos (2UL) /*!< A_INV (Bit 2) */
#define PWM_CH6_CSR_A_INV_Msk (0x4UL) /*!< A_INV (Bitfield-Mask: 0x01) */
#define PWM_CH6_CSR_PH_CORRECT_Pos (1UL) /*!< PH_CORRECT (Bit 1) */
#define PWM_CH6_CSR_PH_CORRECT_Msk (0x2UL) /*!< PH_CORRECT (Bitfield-Mask: 0x01) */
#define PWM_CH6_CSR_EN_Pos (0UL) /*!< EN (Bit 0) */
#define PWM_CH6_CSR_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */
/* ======================================================== CH6_DIV ======================================================== */
#define PWM_CH6_DIV_INT_Pos (4UL) /*!< INT (Bit 4) */
#define PWM_CH6_DIV_INT_Msk (0xff0UL) /*!< INT (Bitfield-Mask: 0xff) */
#define PWM_CH6_DIV_FRAC_Pos (0UL) /*!< FRAC (Bit 0) */
#define PWM_CH6_DIV_FRAC_Msk (0xfUL) /*!< FRAC (Bitfield-Mask: 0x0f) */
/* ======================================================== CH6_CTR ======================================================== */
#define PWM_CH6_CTR_CH6_CTR_Pos (0UL) /*!< CH6_CTR (Bit 0) */
#define PWM_CH6_CTR_CH6_CTR_Msk (0xffffUL) /*!< CH6_CTR (Bitfield-Mask: 0xffff) */
/* ======================================================== CH6_CC ========================================================= */
#define PWM_CH6_CC_B_Pos (16UL) /*!< B (Bit 16) */
#define PWM_CH6_CC_B_Msk (0xffff0000UL) /*!< B (Bitfield-Mask: 0xffff) */
#define PWM_CH6_CC_A_Pos (0UL) /*!< A (Bit 0) */
#define PWM_CH6_CC_A_Msk (0xffffUL) /*!< A (Bitfield-Mask: 0xffff) */
/* ======================================================== CH6_TOP ======================================================== */
#define PWM_CH6_TOP_CH6_TOP_Pos (0UL) /*!< CH6_TOP (Bit 0) */
#define PWM_CH6_TOP_CH6_TOP_Msk (0xffffUL) /*!< CH6_TOP (Bitfield-Mask: 0xffff) */
/* ======================================================== CH7_CSR ======================================================== */
#define PWM_CH7_CSR_PH_ADV_Pos (7UL) /*!< PH_ADV (Bit 7) */
#define PWM_CH7_CSR_PH_ADV_Msk (0x80UL) /*!< PH_ADV (Bitfield-Mask: 0x01) */
#define PWM_CH7_CSR_PH_RET_Pos (6UL) /*!< PH_RET (Bit 6) */
#define PWM_CH7_CSR_PH_RET_Msk (0x40UL) /*!< PH_RET (Bitfield-Mask: 0x01) */
#define PWM_CH7_CSR_DIVMODE_Pos (4UL) /*!< DIVMODE (Bit 4) */
#define PWM_CH7_CSR_DIVMODE_Msk (0x30UL) /*!< DIVMODE (Bitfield-Mask: 0x03) */
#define PWM_CH7_CSR_B_INV_Pos (3UL) /*!< B_INV (Bit 3) */
#define PWM_CH7_CSR_B_INV_Msk (0x8UL) /*!< B_INV (Bitfield-Mask: 0x01) */
#define PWM_CH7_CSR_A_INV_Pos (2UL) /*!< A_INV (Bit 2) */
#define PWM_CH7_CSR_A_INV_Msk (0x4UL) /*!< A_INV (Bitfield-Mask: 0x01) */
#define PWM_CH7_CSR_PH_CORRECT_Pos (1UL) /*!< PH_CORRECT (Bit 1) */
#define PWM_CH7_CSR_PH_CORRECT_Msk (0x2UL) /*!< PH_CORRECT (Bitfield-Mask: 0x01) */
#define PWM_CH7_CSR_EN_Pos (0UL) /*!< EN (Bit 0) */
#define PWM_CH7_CSR_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */
/* ======================================================== CH7_DIV ======================================================== */
#define PWM_CH7_DIV_INT_Pos (4UL) /*!< INT (Bit 4) */
#define PWM_CH7_DIV_INT_Msk (0xff0UL) /*!< INT (Bitfield-Mask: 0xff) */
#define PWM_CH7_DIV_FRAC_Pos (0UL) /*!< FRAC (Bit 0) */
#define PWM_CH7_DIV_FRAC_Msk (0xfUL) /*!< FRAC (Bitfield-Mask: 0x0f) */
/* ======================================================== CH7_CTR ======================================================== */
#define PWM_CH7_CTR_CH7_CTR_Pos (0UL) /*!< CH7_CTR (Bit 0) */
#define PWM_CH7_CTR_CH7_CTR_Msk (0xffffUL) /*!< CH7_CTR (Bitfield-Mask: 0xffff) */
/* ======================================================== CH7_CC ========================================================= */
#define PWM_CH7_CC_B_Pos (16UL) /*!< B (Bit 16) */
#define PWM_CH7_CC_B_Msk (0xffff0000UL) /*!< B (Bitfield-Mask: 0xffff) */
#define PWM_CH7_CC_A_Pos (0UL) /*!< A (Bit 0) */
#define PWM_CH7_CC_A_Msk (0xffffUL) /*!< A (Bitfield-Mask: 0xffff) */
/* ======================================================== CH7_TOP ======================================================== */
#define PWM_CH7_TOP_CH7_TOP_Pos (0UL) /*!< CH7_TOP (Bit 0) */
#define PWM_CH7_TOP_CH7_TOP_Msk (0xffffUL) /*!< CH7_TOP (Bitfield-Mask: 0xffff) */
/* ========================================================== EN =========================================================== */
#define PWM_EN_CH7_Pos (7UL) /*!< CH7 (Bit 7) */
#define PWM_EN_CH7_Msk (0x80UL) /*!< CH7 (Bitfield-Mask: 0x01) */
#define PWM_EN_CH6_Pos (6UL) /*!< CH6 (Bit 6) */
#define PWM_EN_CH6_Msk (0x40UL) /*!< CH6 (Bitfield-Mask: 0x01) */
#define PWM_EN_CH5_Pos (5UL) /*!< CH5 (Bit 5) */
#define PWM_EN_CH5_Msk (0x20UL) /*!< CH5 (Bitfield-Mask: 0x01) */
#define PWM_EN_CH4_Pos (4UL) /*!< CH4 (Bit 4) */
#define PWM_EN_CH4_Msk (0x10UL) /*!< CH4 (Bitfield-Mask: 0x01) */
#define PWM_EN_CH3_Pos (3UL) /*!< CH3 (Bit 3) */
#define PWM_EN_CH3_Msk (0x8UL) /*!< CH3 (Bitfield-Mask: 0x01) */
#define PWM_EN_CH2_Pos (2UL) /*!< CH2 (Bit 2) */
#define PWM_EN_CH2_Msk (0x4UL) /*!< CH2 (Bitfield-Mask: 0x01) */
#define PWM_EN_CH1_Pos (1UL) /*!< CH1 (Bit 1) */
#define PWM_EN_CH1_Msk (0x2UL) /*!< CH1 (Bitfield-Mask: 0x01) */
#define PWM_EN_CH0_Pos (0UL) /*!< CH0 (Bit 0) */
#define PWM_EN_CH0_Msk (0x1UL) /*!< CH0 (Bitfield-Mask: 0x01) */
/* ========================================================= INTR ========================================================== */
#define PWM_INTR_CH7_Pos (7UL) /*!< CH7 (Bit 7) */
#define PWM_INTR_CH7_Msk (0x80UL) /*!< CH7 (Bitfield-Mask: 0x01) */
#define PWM_INTR_CH6_Pos (6UL) /*!< CH6 (Bit 6) */
#define PWM_INTR_CH6_Msk (0x40UL) /*!< CH6 (Bitfield-Mask: 0x01) */
#define PWM_INTR_CH5_Pos (5UL) /*!< CH5 (Bit 5) */
#define PWM_INTR_CH5_Msk (0x20UL) /*!< CH5 (Bitfield-Mask: 0x01) */
#define PWM_INTR_CH4_Pos (4UL) /*!< CH4 (Bit 4) */
#define PWM_INTR_CH4_Msk (0x10UL) /*!< CH4 (Bitfield-Mask: 0x01) */
#define PWM_INTR_CH3_Pos (3UL) /*!< CH3 (Bit 3) */
#define PWM_INTR_CH3_Msk (0x8UL) /*!< CH3 (Bitfield-Mask: 0x01) */
#define PWM_INTR_CH2_Pos (2UL) /*!< CH2 (Bit 2) */
#define PWM_INTR_CH2_Msk (0x4UL) /*!< CH2 (Bitfield-Mask: 0x01) */
#define PWM_INTR_CH1_Pos (1UL) /*!< CH1 (Bit 1) */
#define PWM_INTR_CH1_Msk (0x2UL) /*!< CH1 (Bitfield-Mask: 0x01) */
#define PWM_INTR_CH0_Pos (0UL) /*!< CH0 (Bit 0) */
#define PWM_INTR_CH0_Msk (0x1UL) /*!< CH0 (Bitfield-Mask: 0x01) */
/* ========================================================= INTE ========================================================== */
#define PWM_INTE_CH7_Pos (7UL) /*!< CH7 (Bit 7) */
#define PWM_INTE_CH7_Msk (0x80UL) /*!< CH7 (Bitfield-Mask: 0x01) */
#define PWM_INTE_CH6_Pos (6UL) /*!< CH6 (Bit 6) */
#define PWM_INTE_CH6_Msk (0x40UL) /*!< CH6 (Bitfield-Mask: 0x01) */
#define PWM_INTE_CH5_Pos (5UL) /*!< CH5 (Bit 5) */
#define PWM_INTE_CH5_Msk (0x20UL) /*!< CH5 (Bitfield-Mask: 0x01) */
#define PWM_INTE_CH4_Pos (4UL) /*!< CH4 (Bit 4) */
#define PWM_INTE_CH4_Msk (0x10UL) /*!< CH4 (Bitfield-Mask: 0x01) */
#define PWM_INTE_CH3_Pos (3UL) /*!< CH3 (Bit 3) */
#define PWM_INTE_CH3_Msk (0x8UL) /*!< CH3 (Bitfield-Mask: 0x01) */
#define PWM_INTE_CH2_Pos (2UL) /*!< CH2 (Bit 2) */
#define PWM_INTE_CH2_Msk (0x4UL) /*!< CH2 (Bitfield-Mask: 0x01) */
#define PWM_INTE_CH1_Pos (1UL) /*!< CH1 (Bit 1) */
#define PWM_INTE_CH1_Msk (0x2UL) /*!< CH1 (Bitfield-Mask: 0x01) */
#define PWM_INTE_CH0_Pos (0UL) /*!< CH0 (Bit 0) */
#define PWM_INTE_CH0_Msk (0x1UL) /*!< CH0 (Bitfield-Mask: 0x01) */
/* ========================================================= INTF ========================================================== */
#define PWM_INTF_CH7_Pos (7UL) /*!< CH7 (Bit 7) */
#define PWM_INTF_CH7_Msk (0x80UL) /*!< CH7 (Bitfield-Mask: 0x01) */
#define PWM_INTF_CH6_Pos (6UL) /*!< CH6 (Bit 6) */
#define PWM_INTF_CH6_Msk (0x40UL) /*!< CH6 (Bitfield-Mask: 0x01) */
#define PWM_INTF_CH5_Pos (5UL) /*!< CH5 (Bit 5) */
#define PWM_INTF_CH5_Msk (0x20UL) /*!< CH5 (Bitfield-Mask: 0x01) */
#define PWM_INTF_CH4_Pos (4UL) /*!< CH4 (Bit 4) */
#define PWM_INTF_CH4_Msk (0x10UL) /*!< CH4 (Bitfield-Mask: 0x01) */
#define PWM_INTF_CH3_Pos (3UL) /*!< CH3 (Bit 3) */
#define PWM_INTF_CH3_Msk (0x8UL) /*!< CH3 (Bitfield-Mask: 0x01) */
#define PWM_INTF_CH2_Pos (2UL) /*!< CH2 (Bit 2) */
#define PWM_INTF_CH2_Msk (0x4UL) /*!< CH2 (Bitfield-Mask: 0x01) */
#define PWM_INTF_CH1_Pos (1UL) /*!< CH1 (Bit 1) */
#define PWM_INTF_CH1_Msk (0x2UL) /*!< CH1 (Bitfield-Mask: 0x01) */
#define PWM_INTF_CH0_Pos (0UL) /*!< CH0 (Bit 0) */
#define PWM_INTF_CH0_Msk (0x1UL) /*!< CH0 (Bitfield-Mask: 0x01) */
/* ========================================================= INTS ========================================================== */
#define PWM_INTS_CH7_Pos (7UL) /*!< CH7 (Bit 7) */
#define PWM_INTS_CH7_Msk (0x80UL) /*!< CH7 (Bitfield-Mask: 0x01) */
#define PWM_INTS_CH6_Pos (6UL) /*!< CH6 (Bit 6) */
#define PWM_INTS_CH6_Msk (0x40UL) /*!< CH6 (Bitfield-Mask: 0x01) */
#define PWM_INTS_CH5_Pos (5UL) /*!< CH5 (Bit 5) */
#define PWM_INTS_CH5_Msk (0x20UL) /*!< CH5 (Bitfield-Mask: 0x01) */
#define PWM_INTS_CH4_Pos (4UL) /*!< CH4 (Bit 4) */
#define PWM_INTS_CH4_Msk (0x10UL) /*!< CH4 (Bitfield-Mask: 0x01) */
#define PWM_INTS_CH3_Pos (3UL) /*!< CH3 (Bit 3) */
#define PWM_INTS_CH3_Msk (0x8UL) /*!< CH3 (Bitfield-Mask: 0x01) */
#define PWM_INTS_CH2_Pos (2UL) /*!< CH2 (Bit 2) */
#define PWM_INTS_CH2_Msk (0x4UL) /*!< CH2 (Bitfield-Mask: 0x01) */
#define PWM_INTS_CH1_Pos (1UL) /*!< CH1 (Bit 1) */
#define PWM_INTS_CH1_Msk (0x2UL) /*!< CH1 (Bitfield-Mask: 0x01) */
#define PWM_INTS_CH0_Pos (0UL) /*!< CH0 (Bit 0) */
#define PWM_INTS_CH0_Msk (0x1UL) /*!< CH0 (Bitfield-Mask: 0x01) */
/* =========================================================================================================================== */
/* ================ TIMER ================ */
/* =========================================================================================================================== */
/* ======================================================== TIMEHW ========================================================= */
/* ======================================================== TIMELW ========================================================= */
/* ======================================================== TIMEHR ========================================================= */
/* ======================================================== TIMELR ========================================================= */
/* ======================================================== ALARM0 ========================================================= */
/* ======================================================== ALARM1 ========================================================= */
/* ======================================================== ALARM2 ========================================================= */
/* ======================================================== ALARM3 ========================================================= */
/* ========================================================= ARMED ========================================================= */
#define TIMER_ARMED_ARMED_Pos (0UL) /*!< ARMED (Bit 0) */
#define TIMER_ARMED_ARMED_Msk (0xfUL) /*!< ARMED (Bitfield-Mask: 0x0f) */
/* ======================================================= TIMERAWH ======================================================== */
/* ======================================================= TIMERAWL ======================================================== */
/* ======================================================= DBGPAUSE ======================================================== */
#define TIMER_DBGPAUSE_DBG1_Pos (2UL) /*!< DBG1 (Bit 2) */
#define TIMER_DBGPAUSE_DBG1_Msk (0x4UL) /*!< DBG1 (Bitfield-Mask: 0x01) */
#define TIMER_DBGPAUSE_DBG0_Pos (1UL) /*!< DBG0 (Bit 1) */
#define TIMER_DBGPAUSE_DBG0_Msk (0x2UL) /*!< DBG0 (Bitfield-Mask: 0x01) */
/* ========================================================= PAUSE ========================================================= */
#define TIMER_PAUSE_PAUSE_Pos (0UL) /*!< PAUSE (Bit 0) */
#define TIMER_PAUSE_PAUSE_Msk (0x1UL) /*!< PAUSE (Bitfield-Mask: 0x01) */
/* ========================================================= INTR ========================================================== */
#define TIMER_INTR_ALARM_3_Pos (3UL) /*!< ALARM_3 (Bit 3) */
#define TIMER_INTR_ALARM_3_Msk (0x8UL) /*!< ALARM_3 (Bitfield-Mask: 0x01) */
#define TIMER_INTR_ALARM_2_Pos (2UL) /*!< ALARM_2 (Bit 2) */
#define TIMER_INTR_ALARM_2_Msk (0x4UL) /*!< ALARM_2 (Bitfield-Mask: 0x01) */
#define TIMER_INTR_ALARM_1_Pos (1UL) /*!< ALARM_1 (Bit 1) */
#define TIMER_INTR_ALARM_1_Msk (0x2UL) /*!< ALARM_1 (Bitfield-Mask: 0x01) */
#define TIMER_INTR_ALARM_0_Pos (0UL) /*!< ALARM_0 (Bit 0) */
#define TIMER_INTR_ALARM_0_Msk (0x1UL) /*!< ALARM_0 (Bitfield-Mask: 0x01) */
/* ========================================================= INTE ========================================================== */
#define TIMER_INTE_ALARM_3_Pos (3UL) /*!< ALARM_3 (Bit 3) */
#define TIMER_INTE_ALARM_3_Msk (0x8UL) /*!< ALARM_3 (Bitfield-Mask: 0x01) */
#define TIMER_INTE_ALARM_2_Pos (2UL) /*!< ALARM_2 (Bit 2) */
#define TIMER_INTE_ALARM_2_Msk (0x4UL) /*!< ALARM_2 (Bitfield-Mask: 0x01) */
#define TIMER_INTE_ALARM_1_Pos (1UL) /*!< ALARM_1 (Bit 1) */
#define TIMER_INTE_ALARM_1_Msk (0x2UL) /*!< ALARM_1 (Bitfield-Mask: 0x01) */
#define TIMER_INTE_ALARM_0_Pos (0UL) /*!< ALARM_0 (Bit 0) */
#define TIMER_INTE_ALARM_0_Msk (0x1UL) /*!< ALARM_0 (Bitfield-Mask: 0x01) */
/* ========================================================= INTF ========================================================== */
#define TIMER_INTF_ALARM_3_Pos (3UL) /*!< ALARM_3 (Bit 3) */
#define TIMER_INTF_ALARM_3_Msk (0x8UL) /*!< ALARM_3 (Bitfield-Mask: 0x01) */
#define TIMER_INTF_ALARM_2_Pos (2UL) /*!< ALARM_2 (Bit 2) */
#define TIMER_INTF_ALARM_2_Msk (0x4UL) /*!< ALARM_2 (Bitfield-Mask: 0x01) */
#define TIMER_INTF_ALARM_1_Pos (1UL) /*!< ALARM_1 (Bit 1) */
#define TIMER_INTF_ALARM_1_Msk (0x2UL) /*!< ALARM_1 (Bitfield-Mask: 0x01) */
#define TIMER_INTF_ALARM_0_Pos (0UL) /*!< ALARM_0 (Bit 0) */
#define TIMER_INTF_ALARM_0_Msk (0x1UL) /*!< ALARM_0 (Bitfield-Mask: 0x01) */
/* ========================================================= INTS ========================================================== */
#define TIMER_INTS_ALARM_3_Pos (3UL) /*!< ALARM_3 (Bit 3) */
#define TIMER_INTS_ALARM_3_Msk (0x8UL) /*!< ALARM_3 (Bitfield-Mask: 0x01) */
#define TIMER_INTS_ALARM_2_Pos (2UL) /*!< ALARM_2 (Bit 2) */
#define TIMER_INTS_ALARM_2_Msk (0x4UL) /*!< ALARM_2 (Bitfield-Mask: 0x01) */
#define TIMER_INTS_ALARM_1_Pos (1UL) /*!< ALARM_1 (Bit 1) */
#define TIMER_INTS_ALARM_1_Msk (0x2UL) /*!< ALARM_1 (Bitfield-Mask: 0x01) */
#define TIMER_INTS_ALARM_0_Pos (0UL) /*!< ALARM_0 (Bit 0) */
#define TIMER_INTS_ALARM_0_Msk (0x1UL) /*!< ALARM_0 (Bitfield-Mask: 0x01) */
/* =========================================================================================================================== */
/* ================ WATCHDOG ================ */
/* =========================================================================================================================== */
/* ========================================================= CTRL ========================================================== */
#define WATCHDOG_CTRL_TRIGGER_Pos (31UL) /*!< TRIGGER (Bit 31) */
#define WATCHDOG_CTRL_TRIGGER_Msk (0x80000000UL) /*!< TRIGGER (Bitfield-Mask: 0x01) */
#define WATCHDOG_CTRL_ENABLE_Pos (30UL) /*!< ENABLE (Bit 30) */
#define WATCHDOG_CTRL_ENABLE_Msk (0x40000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */
#define WATCHDOG_CTRL_PAUSE_DBG1_Pos (26UL) /*!< PAUSE_DBG1 (Bit 26) */
#define WATCHDOG_CTRL_PAUSE_DBG1_Msk (0x4000000UL) /*!< PAUSE_DBG1 (Bitfield-Mask: 0x01) */
#define WATCHDOG_CTRL_PAUSE_DBG0_Pos (25UL) /*!< PAUSE_DBG0 (Bit 25) */
#define WATCHDOG_CTRL_PAUSE_DBG0_Msk (0x2000000UL) /*!< PAUSE_DBG0 (Bitfield-Mask: 0x01) */
#define WATCHDOG_CTRL_PAUSE_JTAG_Pos (24UL) /*!< PAUSE_JTAG (Bit 24) */
#define WATCHDOG_CTRL_PAUSE_JTAG_Msk (0x1000000UL) /*!< PAUSE_JTAG (Bitfield-Mask: 0x01) */
#define WATCHDOG_CTRL_TIME_Pos (0UL) /*!< TIME (Bit 0) */
#define WATCHDOG_CTRL_TIME_Msk (0xffffffUL) /*!< TIME (Bitfield-Mask: 0xffffff) */
/* ========================================================= LOAD ========================================================== */
#define WATCHDOG_LOAD_LOAD_Pos (0UL) /*!< LOAD (Bit 0) */
#define WATCHDOG_LOAD_LOAD_Msk (0xffffffUL) /*!< LOAD (Bitfield-Mask: 0xffffff) */
/* ======================================================== REASON ========================================================= */
#define WATCHDOG_REASON_FORCE_Pos (1UL) /*!< FORCE (Bit 1) */
#define WATCHDOG_REASON_FORCE_Msk (0x2UL) /*!< FORCE (Bitfield-Mask: 0x01) */
#define WATCHDOG_REASON_TIMER_Pos (0UL) /*!< TIMER (Bit 0) */
#define WATCHDOG_REASON_TIMER_Msk (0x1UL) /*!< TIMER (Bitfield-Mask: 0x01) */
/* ======================================================= SCRATCH0 ======================================================== */
/* ======================================================= SCRATCH1 ======================================================== */
/* ======================================================= SCRATCH2 ======================================================== */
/* ======================================================= SCRATCH3 ======================================================== */
/* ======================================================= SCRATCH4 ======================================================== */
/* ======================================================= SCRATCH5 ======================================================== */
/* ======================================================= SCRATCH6 ======================================================== */
/* ======================================================= SCRATCH7 ======================================================== */
/* ========================================================= TICK ========================================================== */
#define WATCHDOG_TICK_COUNT_Pos (11UL) /*!< COUNT (Bit 11) */
#define WATCHDOG_TICK_COUNT_Msk (0xff800UL) /*!< COUNT (Bitfield-Mask: 0x1ff) */
#define WATCHDOG_TICK_RUNNING_Pos (10UL) /*!< RUNNING (Bit 10) */
#define WATCHDOG_TICK_RUNNING_Msk (0x400UL) /*!< RUNNING (Bitfield-Mask: 0x01) */
#define WATCHDOG_TICK_ENABLE_Pos (9UL) /*!< ENABLE (Bit 9) */
#define WATCHDOG_TICK_ENABLE_Msk (0x200UL) /*!< ENABLE (Bitfield-Mask: 0x01) */
#define WATCHDOG_TICK_CYCLES_Pos (0UL) /*!< CYCLES (Bit 0) */
#define WATCHDOG_TICK_CYCLES_Msk (0x1ffUL) /*!< CYCLES (Bitfield-Mask: 0x1ff) */
/* =========================================================================================================================== */
/* ================ RTC ================ */
/* =========================================================================================================================== */
/* ======================================================= CLKDIV_M1 ======================================================= */
#define RTC_CLKDIV_M1_CLKDIV_M1_Pos (0UL) /*!< CLKDIV_M1 (Bit 0) */
#define RTC_CLKDIV_M1_CLKDIV_M1_Msk (0xffffUL) /*!< CLKDIV_M1 (Bitfield-Mask: 0xffff) */
/* ======================================================== SETUP_0 ======================================================== */
#define RTC_SETUP_0_YEAR_Pos (12UL) /*!< YEAR (Bit 12) */
#define RTC_SETUP_0_YEAR_Msk (0xfff000UL) /*!< YEAR (Bitfield-Mask: 0xfff) */
#define RTC_SETUP_0_MONTH_Pos (8UL) /*!< MONTH (Bit 8) */
#define RTC_SETUP_0_MONTH_Msk (0xf00UL) /*!< MONTH (Bitfield-Mask: 0x0f) */
#define RTC_SETUP_0_DAY_Pos (0UL) /*!< DAY (Bit 0) */
#define RTC_SETUP_0_DAY_Msk (0x1fUL) /*!< DAY (Bitfield-Mask: 0x1f) */
/* ======================================================== SETUP_1 ======================================================== */
#define RTC_SETUP_1_DOTW_Pos (24UL) /*!< DOTW (Bit 24) */
#define RTC_SETUP_1_DOTW_Msk (0x7000000UL) /*!< DOTW (Bitfield-Mask: 0x07) */
#define RTC_SETUP_1_HOUR_Pos (16UL) /*!< HOUR (Bit 16) */
#define RTC_SETUP_1_HOUR_Msk (0x1f0000UL) /*!< HOUR (Bitfield-Mask: 0x1f) */
#define RTC_SETUP_1_MIN_Pos (8UL) /*!< MIN (Bit 8) */
#define RTC_SETUP_1_MIN_Msk (0x3f00UL) /*!< MIN (Bitfield-Mask: 0x3f) */
#define RTC_SETUP_1_SEC_Pos (0UL) /*!< SEC (Bit 0) */
#define RTC_SETUP_1_SEC_Msk (0x3fUL) /*!< SEC (Bitfield-Mask: 0x3f) */
/* ========================================================= CTRL ========================================================== */
#define RTC_CTRL_FORCE_NOTLEAPYEAR_Pos (8UL) /*!< FORCE_NOTLEAPYEAR (Bit 8) */
#define RTC_CTRL_FORCE_NOTLEAPYEAR_Msk (0x100UL) /*!< FORCE_NOTLEAPYEAR (Bitfield-Mask: 0x01) */
#define RTC_CTRL_LOAD_Pos (4UL) /*!< LOAD (Bit 4) */
#define RTC_CTRL_LOAD_Msk (0x10UL) /*!< LOAD (Bitfield-Mask: 0x01) */
#define RTC_CTRL_RTC_ACTIVE_Pos (1UL) /*!< RTC_ACTIVE (Bit 1) */
#define RTC_CTRL_RTC_ACTIVE_Msk (0x2UL) /*!< RTC_ACTIVE (Bitfield-Mask: 0x01) */
#define RTC_CTRL_RTC_ENABLE_Pos (0UL) /*!< RTC_ENABLE (Bit 0) */
#define RTC_CTRL_RTC_ENABLE_Msk (0x1UL) /*!< RTC_ENABLE (Bitfield-Mask: 0x01) */
/* ====================================================== IRQ_SETUP_0 ====================================================== */
#define RTC_IRQ_SETUP_0_MATCH_ACTIVE_Pos (29UL) /*!< MATCH_ACTIVE (Bit 29) */
#define RTC_IRQ_SETUP_0_MATCH_ACTIVE_Msk (0x20000000UL) /*!< MATCH_ACTIVE (Bitfield-Mask: 0x01) */
#define RTC_IRQ_SETUP_0_MATCH_ENA_Pos (28UL) /*!< MATCH_ENA (Bit 28) */
#define RTC_IRQ_SETUP_0_MATCH_ENA_Msk (0x10000000UL) /*!< MATCH_ENA (Bitfield-Mask: 0x01) */
#define RTC_IRQ_SETUP_0_YEAR_ENA_Pos (26UL) /*!< YEAR_ENA (Bit 26) */
#define RTC_IRQ_SETUP_0_YEAR_ENA_Msk (0x4000000UL) /*!< YEAR_ENA (Bitfield-Mask: 0x01) */
#define RTC_IRQ_SETUP_0_MONTH_ENA_Pos (25UL) /*!< MONTH_ENA (Bit 25) */
#define RTC_IRQ_SETUP_0_MONTH_ENA_Msk (0x2000000UL) /*!< MONTH_ENA (Bitfield-Mask: 0x01) */
#define RTC_IRQ_SETUP_0_DAY_ENA_Pos (24UL) /*!< DAY_ENA (Bit 24) */
#define RTC_IRQ_SETUP_0_DAY_ENA_Msk (0x1000000UL) /*!< DAY_ENA (Bitfield-Mask: 0x01) */
#define RTC_IRQ_SETUP_0_YEAR_Pos (12UL) /*!< YEAR (Bit 12) */
#define RTC_IRQ_SETUP_0_YEAR_Msk (0xfff000UL) /*!< YEAR (Bitfield-Mask: 0xfff) */
#define RTC_IRQ_SETUP_0_MONTH_Pos (8UL) /*!< MONTH (Bit 8) */
#define RTC_IRQ_SETUP_0_MONTH_Msk (0xf00UL) /*!< MONTH (Bitfield-Mask: 0x0f) */
#define RTC_IRQ_SETUP_0_DAY_Pos (0UL) /*!< DAY (Bit 0) */
#define RTC_IRQ_SETUP_0_DAY_Msk (0x1fUL) /*!< DAY (Bitfield-Mask: 0x1f) */
/* ====================================================== IRQ_SETUP_1 ====================================================== */
#define RTC_IRQ_SETUP_1_DOTW_ENA_Pos (31UL) /*!< DOTW_ENA (Bit 31) */
#define RTC_IRQ_SETUP_1_DOTW_ENA_Msk (0x80000000UL) /*!< DOTW_ENA (Bitfield-Mask: 0x01) */
#define RTC_IRQ_SETUP_1_HOUR_ENA_Pos (30UL) /*!< HOUR_ENA (Bit 30) */
#define RTC_IRQ_SETUP_1_HOUR_ENA_Msk (0x40000000UL) /*!< HOUR_ENA (Bitfield-Mask: 0x01) */
#define RTC_IRQ_SETUP_1_MIN_ENA_Pos (29UL) /*!< MIN_ENA (Bit 29) */
#define RTC_IRQ_SETUP_1_MIN_ENA_Msk (0x20000000UL) /*!< MIN_ENA (Bitfield-Mask: 0x01) */
#define RTC_IRQ_SETUP_1_SEC_ENA_Pos (28UL) /*!< SEC_ENA (Bit 28) */
#define RTC_IRQ_SETUP_1_SEC_ENA_Msk (0x10000000UL) /*!< SEC_ENA (Bitfield-Mask: 0x01) */
#define RTC_IRQ_SETUP_1_DOTW_Pos (24UL) /*!< DOTW (Bit 24) */
#define RTC_IRQ_SETUP_1_DOTW_Msk (0x7000000UL) /*!< DOTW (Bitfield-Mask: 0x07) */
#define RTC_IRQ_SETUP_1_HOUR_Pos (16UL) /*!< HOUR (Bit 16) */
#define RTC_IRQ_SETUP_1_HOUR_Msk (0x1f0000UL) /*!< HOUR (Bitfield-Mask: 0x1f) */
#define RTC_IRQ_SETUP_1_MIN_Pos (8UL) /*!< MIN (Bit 8) */
#define RTC_IRQ_SETUP_1_MIN_Msk (0x3f00UL) /*!< MIN (Bitfield-Mask: 0x3f) */
#define RTC_IRQ_SETUP_1_SEC_Pos (0UL) /*!< SEC (Bit 0) */
#define RTC_IRQ_SETUP_1_SEC_Msk (0x3fUL) /*!< SEC (Bitfield-Mask: 0x3f) */
/* ========================================================= RTC_1 ========================================================= */
#define RTC_RTC_1_YEAR_Pos (12UL) /*!< YEAR (Bit 12) */
#define RTC_RTC_1_YEAR_Msk (0xfff000UL) /*!< YEAR (Bitfield-Mask: 0xfff) */
#define RTC_RTC_1_MONTH_Pos (8UL) /*!< MONTH (Bit 8) */
#define RTC_RTC_1_MONTH_Msk (0xf00UL) /*!< MONTH (Bitfield-Mask: 0x0f) */
#define RTC_RTC_1_DAY_Pos (0UL) /*!< DAY (Bit 0) */
#define RTC_RTC_1_DAY_Msk (0x1fUL) /*!< DAY (Bitfield-Mask: 0x1f) */
/* ========================================================= RTC_0 ========================================================= */
#define RTC_RTC_0_DOTW_Pos (24UL) /*!< DOTW (Bit 24) */
#define RTC_RTC_0_DOTW_Msk (0x7000000UL) /*!< DOTW (Bitfield-Mask: 0x07) */
#define RTC_RTC_0_HOUR_Pos (16UL) /*!< HOUR (Bit 16) */
#define RTC_RTC_0_HOUR_Msk (0x1f0000UL) /*!< HOUR (Bitfield-Mask: 0x1f) */
#define RTC_RTC_0_MIN_Pos (8UL) /*!< MIN (Bit 8) */
#define RTC_RTC_0_MIN_Msk (0x3f00UL) /*!< MIN (Bitfield-Mask: 0x3f) */
#define RTC_RTC_0_SEC_Pos (0UL) /*!< SEC (Bit 0) */
#define RTC_RTC_0_SEC_Msk (0x3fUL) /*!< SEC (Bitfield-Mask: 0x3f) */
/* ========================================================= INTR ========================================================== */
#define RTC_INTR_RTC_Pos (0UL) /*!< RTC (Bit 0) */
#define RTC_INTR_RTC_Msk (0x1UL) /*!< RTC (Bitfield-Mask: 0x01) */
/* ========================================================= INTE ========================================================== */
#define RTC_INTE_RTC_Pos (0UL) /*!< RTC (Bit 0) */
#define RTC_INTE_RTC_Msk (0x1UL) /*!< RTC (Bitfield-Mask: 0x01) */
/* ========================================================= INTF ========================================================== */
#define RTC_INTF_RTC_Pos (0UL) /*!< RTC (Bit 0) */
#define RTC_INTF_RTC_Msk (0x1UL) /*!< RTC (Bitfield-Mask: 0x01) */
/* ========================================================= INTS ========================================================== */
#define RTC_INTS_RTC_Pos (0UL) /*!< RTC (Bit 0) */
#define RTC_INTS_RTC_Msk (0x1UL) /*!< RTC (Bitfield-Mask: 0x01) */
/* =========================================================================================================================== */
/* ================ ROSC ================ */
/* =========================================================================================================================== */
/* ========================================================= CTRL ========================================================== */
#define ROSC_CTRL_ENABLE_Pos (12UL) /*!< ENABLE (Bit 12) */
#define ROSC_CTRL_ENABLE_Msk (0xfff000UL) /*!< ENABLE (Bitfield-Mask: 0xfff) */
#define ROSC_CTRL_FREQ_RANGE_Pos (0UL) /*!< FREQ_RANGE (Bit 0) */
#define ROSC_CTRL_FREQ_RANGE_Msk (0xfffUL) /*!< FREQ_RANGE (Bitfield-Mask: 0xfff) */
/* ========================================================= FREQA ========================================================= */
#define ROSC_FREQA_PASSWD_Pos (16UL) /*!< PASSWD (Bit 16) */
#define ROSC_FREQA_PASSWD_Msk (0xffff0000UL) /*!< PASSWD (Bitfield-Mask: 0xffff) */
#define ROSC_FREQA_DS3_Pos (12UL) /*!< DS3 (Bit 12) */
#define ROSC_FREQA_DS3_Msk (0x7000UL) /*!< DS3 (Bitfield-Mask: 0x07) */
#define ROSC_FREQA_DS2_Pos (8UL) /*!< DS2 (Bit 8) */
#define ROSC_FREQA_DS2_Msk (0x700UL) /*!< DS2 (Bitfield-Mask: 0x07) */
#define ROSC_FREQA_DS1_Pos (4UL) /*!< DS1 (Bit 4) */
#define ROSC_FREQA_DS1_Msk (0x70UL) /*!< DS1 (Bitfield-Mask: 0x07) */
#define ROSC_FREQA_DS0_Pos (0UL) /*!< DS0 (Bit 0) */
#define ROSC_FREQA_DS0_Msk (0x7UL) /*!< DS0 (Bitfield-Mask: 0x07) */
/* ========================================================= FREQB ========================================================= */
#define ROSC_FREQB_PASSWD_Pos (16UL) /*!< PASSWD (Bit 16) */
#define ROSC_FREQB_PASSWD_Msk (0xffff0000UL) /*!< PASSWD (Bitfield-Mask: 0xffff) */
#define ROSC_FREQB_DS7_Pos (12UL) /*!< DS7 (Bit 12) */
#define ROSC_FREQB_DS7_Msk (0x7000UL) /*!< DS7 (Bitfield-Mask: 0x07) */
#define ROSC_FREQB_DS6_Pos (8UL) /*!< DS6 (Bit 8) */
#define ROSC_FREQB_DS6_Msk (0x700UL) /*!< DS6 (Bitfield-Mask: 0x07) */
#define ROSC_FREQB_DS5_Pos (4UL) /*!< DS5 (Bit 4) */
#define ROSC_FREQB_DS5_Msk (0x70UL) /*!< DS5 (Bitfield-Mask: 0x07) */
#define ROSC_FREQB_DS4_Pos (0UL) /*!< DS4 (Bit 0) */
#define ROSC_FREQB_DS4_Msk (0x7UL) /*!< DS4 (Bitfield-Mask: 0x07) */
/* ======================================================== DORMANT ======================================================== */
/* ========================================================== DIV ========================================================== */
#define ROSC_DIV_DIV_Pos (0UL) /*!< DIV (Bit 0) */
#define ROSC_DIV_DIV_Msk (0xfffUL) /*!< DIV (Bitfield-Mask: 0xfff) */
/* ========================================================= PHASE ========================================================= */
#define ROSC_PHASE_PASSWD_Pos (4UL) /*!< PASSWD (Bit 4) */
#define ROSC_PHASE_PASSWD_Msk (0xff0UL) /*!< PASSWD (Bitfield-Mask: 0xff) */
#define ROSC_PHASE_ENABLE_Pos (3UL) /*!< ENABLE (Bit 3) */
#define ROSC_PHASE_ENABLE_Msk (0x8UL) /*!< ENABLE (Bitfield-Mask: 0x01) */
#define ROSC_PHASE_FLIP_Pos (2UL) /*!< FLIP (Bit 2) */
#define ROSC_PHASE_FLIP_Msk (0x4UL) /*!< FLIP (Bitfield-Mask: 0x01) */
#define ROSC_PHASE_SHIFT_Pos (0UL) /*!< SHIFT (Bit 0) */
#define ROSC_PHASE_SHIFT_Msk (0x3UL) /*!< SHIFT (Bitfield-Mask: 0x03) */
/* ======================================================== STATUS ========================================================= */
#define ROSC_STATUS_STABLE_Pos (31UL) /*!< STABLE (Bit 31) */
#define ROSC_STATUS_STABLE_Msk (0x80000000UL) /*!< STABLE (Bitfield-Mask: 0x01) */
#define ROSC_STATUS_BADWRITE_Pos (24UL) /*!< BADWRITE (Bit 24) */
#define ROSC_STATUS_BADWRITE_Msk (0x1000000UL) /*!< BADWRITE (Bitfield-Mask: 0x01) */
#define ROSC_STATUS_DIV_RUNNING_Pos (16UL) /*!< DIV_RUNNING (Bit 16) */
#define ROSC_STATUS_DIV_RUNNING_Msk (0x10000UL) /*!< DIV_RUNNING (Bitfield-Mask: 0x01) */
#define ROSC_STATUS_ENABLED_Pos (12UL) /*!< ENABLED (Bit 12) */
#define ROSC_STATUS_ENABLED_Msk (0x1000UL) /*!< ENABLED (Bitfield-Mask: 0x01) */
/* ======================================================= RANDOMBIT ======================================================= */
#define ROSC_RANDOMBIT_RANDOMBIT_Pos (0UL) /*!< RANDOMBIT (Bit 0) */
#define ROSC_RANDOMBIT_RANDOMBIT_Msk (0x1UL) /*!< RANDOMBIT (Bitfield-Mask: 0x01) */
/* ========================================================= COUNT ========================================================= */
#define ROSC_COUNT_COUNT_Pos (0UL) /*!< COUNT (Bit 0) */
#define ROSC_COUNT_COUNT_Msk (0xffUL) /*!< COUNT (Bitfield-Mask: 0xff) */
/* =========================================================================================================================== */
/* ================ VREG_AND_CHIP_RESET ================ */
/* =========================================================================================================================== */
/* ========================================================= VREG ========================================================== */
#define VREG_AND_CHIP_RESET_VREG_ROK_Pos (12UL) /*!< ROK (Bit 12) */
#define VREG_AND_CHIP_RESET_VREG_ROK_Msk (0x1000UL) /*!< ROK (Bitfield-Mask: 0x01) */
#define VREG_AND_CHIP_RESET_VREG_VSEL_Pos (4UL) /*!< VSEL (Bit 4) */
#define VREG_AND_CHIP_RESET_VREG_VSEL_Msk (0xf0UL) /*!< VSEL (Bitfield-Mask: 0x0f) */
#define VREG_AND_CHIP_RESET_VREG_HIZ_Pos (1UL) /*!< HIZ (Bit 1) */
#define VREG_AND_CHIP_RESET_VREG_HIZ_Msk (0x2UL) /*!< HIZ (Bitfield-Mask: 0x01) */
#define VREG_AND_CHIP_RESET_VREG_EN_Pos (0UL) /*!< EN (Bit 0) */
#define VREG_AND_CHIP_RESET_VREG_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */
/* ========================================================== BOD ========================================================== */
#define VREG_AND_CHIP_RESET_BOD_VSEL_Pos (4UL) /*!< VSEL (Bit 4) */
#define VREG_AND_CHIP_RESET_BOD_VSEL_Msk (0xf0UL) /*!< VSEL (Bitfield-Mask: 0x0f) */
#define VREG_AND_CHIP_RESET_BOD_EN_Pos (0UL) /*!< EN (Bit 0) */
#define VREG_AND_CHIP_RESET_BOD_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */
/* ====================================================== CHIP_RESET ======================================================= */
#define VREG_AND_CHIP_RESET_CHIP_RESET_PSM_RESTART_FLAG_Pos (24UL) /*!< PSM_RESTART_FLAG (Bit 24) */
#define VREG_AND_CHIP_RESET_CHIP_RESET_PSM_RESTART_FLAG_Msk (0x1000000UL) /*!< PSM_RESTART_FLAG (Bitfield-Mask: 0x01) */
#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_PSM_RESTART_Pos (20UL) /*!< HAD_PSM_RESTART (Bit 20) */
#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_PSM_RESTART_Msk (0x100000UL) /*!< HAD_PSM_RESTART (Bitfield-Mask: 0x01) */
#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_RUN_Pos (16UL) /*!< HAD_RUN (Bit 16) */
#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_RUN_Msk (0x10000UL) /*!< HAD_RUN (Bitfield-Mask: 0x01) */
#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR_Pos (8UL) /*!< HAD_POR (Bit 8) */
#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR_Msk (0x100UL) /*!< HAD_POR (Bitfield-Mask: 0x01) */
/* =========================================================================================================================== */
/* ================ TBMAN ================ */
/* =========================================================================================================================== */
/* ======================================================= PLATFORM ======================================================== */
#define TBMAN_PLATFORM_FPGA_Pos (1UL) /*!< FPGA (Bit 1) */
#define TBMAN_PLATFORM_FPGA_Msk (0x2UL) /*!< FPGA (Bitfield-Mask: 0x01) */
#define TBMAN_PLATFORM_ASIC_Pos (0UL) /*!< ASIC (Bit 0) */
#define TBMAN_PLATFORM_ASIC_Msk (0x1UL) /*!< ASIC (Bitfield-Mask: 0x01) */
/* =========================================================================================================================== */
/* ================ DMA ================ */
/* =========================================================================================================================== */
/* ===================================================== CH0_READ_ADDR ===================================================== */
/* ==================================================== CH0_WRITE_ADDR ===================================================== */
/* ==================================================== CH0_TRANS_COUNT ==================================================== */
/* ===================================================== CH0_CTRL_TRIG ===================================================== */
#define DMA_CH0_CTRL_TRIG_AHB_ERROR_Pos (31UL) /*!< AHB_ERROR (Bit 31) */
#define DMA_CH0_CTRL_TRIG_AHB_ERROR_Msk (0x80000000UL) /*!< AHB_ERROR (Bitfield-Mask: 0x01) */
#define DMA_CH0_CTRL_TRIG_READ_ERROR_Pos (30UL) /*!< READ_ERROR (Bit 30) */
#define DMA_CH0_CTRL_TRIG_READ_ERROR_Msk (0x40000000UL) /*!< READ_ERROR (Bitfield-Mask: 0x01) */
#define DMA_CH0_CTRL_TRIG_WRITE_ERROR_Pos (29UL) /*!< WRITE_ERROR (Bit 29) */
#define DMA_CH0_CTRL_TRIG_WRITE_ERROR_Msk (0x20000000UL) /*!< WRITE_ERROR (Bitfield-Mask: 0x01) */
#define DMA_CH0_CTRL_TRIG_BUSY_Pos (24UL) /*!< BUSY (Bit 24) */
#define DMA_CH0_CTRL_TRIG_BUSY_Msk (0x1000000UL) /*!< BUSY (Bitfield-Mask: 0x01) */
#define DMA_CH0_CTRL_TRIG_SNIFF_EN_Pos (23UL) /*!< SNIFF_EN (Bit 23) */
#define DMA_CH0_CTRL_TRIG_SNIFF_EN_Msk (0x800000UL) /*!< SNIFF_EN (Bitfield-Mask: 0x01) */
#define DMA_CH0_CTRL_TRIG_BSWAP_Pos (22UL) /*!< BSWAP (Bit 22) */
#define DMA_CH0_CTRL_TRIG_BSWAP_Msk (0x400000UL) /*!< BSWAP (Bitfield-Mask: 0x01) */
#define DMA_CH0_CTRL_TRIG_IRQ_QUIET_Pos (21UL) /*!< IRQ_QUIET (Bit 21) */
#define DMA_CH0_CTRL_TRIG_IRQ_QUIET_Msk (0x200000UL) /*!< IRQ_QUIET (Bitfield-Mask: 0x01) */
#define DMA_CH0_CTRL_TRIG_TREQ_SEL_Pos (15UL) /*!< TREQ_SEL (Bit 15) */
#define DMA_CH0_CTRL_TRIG_TREQ_SEL_Msk (0x1f8000UL) /*!< TREQ_SEL (Bitfield-Mask: 0x3f) */
#define DMA_CH0_CTRL_TRIG_CHAIN_TO_Pos (11UL) /*!< CHAIN_TO (Bit 11) */
#define DMA_CH0_CTRL_TRIG_CHAIN_TO_Msk (0x7800UL) /*!< CHAIN_TO (Bitfield-Mask: 0x0f) */
#define DMA_CH0_CTRL_TRIG_RING_SEL_Pos (10UL) /*!< RING_SEL (Bit 10) */
#define DMA_CH0_CTRL_TRIG_RING_SEL_Msk (0x400UL) /*!< RING_SEL (Bitfield-Mask: 0x01) */
#define DMA_CH0_CTRL_TRIG_RING_SIZE_Pos (6UL) /*!< RING_SIZE (Bit 6) */
#define DMA_CH0_CTRL_TRIG_RING_SIZE_Msk (0x3c0UL) /*!< RING_SIZE (Bitfield-Mask: 0x0f) */
#define DMA_CH0_CTRL_TRIG_INCR_WRITE_Pos (5UL) /*!< INCR_WRITE (Bit 5) */
#define DMA_CH0_CTRL_TRIG_INCR_WRITE_Msk (0x20UL) /*!< INCR_WRITE (Bitfield-Mask: 0x01) */
#define DMA_CH0_CTRL_TRIG_INCR_READ_Pos (4UL) /*!< INCR_READ (Bit 4) */
#define DMA_CH0_CTRL_TRIG_INCR_READ_Msk (0x10UL) /*!< INCR_READ (Bitfield-Mask: 0x01) */
#define DMA_CH0_CTRL_TRIG_DATA_SIZE_Pos (2UL) /*!< DATA_SIZE (Bit 2) */
#define DMA_CH0_CTRL_TRIG_DATA_SIZE_Msk (0xcUL) /*!< DATA_SIZE (Bitfield-Mask: 0x03) */
#define DMA_CH0_CTRL_TRIG_HIGH_PRIORITY_Pos (1UL) /*!< HIGH_PRIORITY (Bit 1) */
#define DMA_CH0_CTRL_TRIG_HIGH_PRIORITY_Msk (0x2UL) /*!< HIGH_PRIORITY (Bitfield-Mask: 0x01) */
#define DMA_CH0_CTRL_TRIG_EN_Pos (0UL) /*!< EN (Bit 0) */
#define DMA_CH0_CTRL_TRIG_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */
/* ===================================================== CH0_AL1_CTRL ====================================================== */
/* =================================================== CH0_AL1_READ_ADDR =================================================== */
/* ================================================== CH0_AL1_WRITE_ADDR =================================================== */
/* =============================================== CH0_AL1_TRANS_COUNT_TRIG ================================================ */
/* ===================================================== CH0_AL2_CTRL ====================================================== */
/* ================================================== CH0_AL2_TRANS_COUNT ================================================== */
/* =================================================== CH0_AL2_READ_ADDR =================================================== */
/* ================================================ CH0_AL2_WRITE_ADDR_TRIG ================================================ */
/* ===================================================== CH0_AL3_CTRL ====================================================== */
/* ================================================== CH0_AL3_WRITE_ADDR =================================================== */
/* ================================================== CH0_AL3_TRANS_COUNT ================================================== */
/* ================================================ CH0_AL3_READ_ADDR_TRIG ================================================= */
/* ===================================================== CH1_READ_ADDR ===================================================== */
/* ==================================================== CH1_WRITE_ADDR ===================================================== */
/* ==================================================== CH1_TRANS_COUNT ==================================================== */
/* ===================================================== CH1_CTRL_TRIG ===================================================== */
#define DMA_CH1_CTRL_TRIG_AHB_ERROR_Pos (31UL) /*!< AHB_ERROR (Bit 31) */
#define DMA_CH1_CTRL_TRIG_AHB_ERROR_Msk (0x80000000UL) /*!< AHB_ERROR (Bitfield-Mask: 0x01) */
#define DMA_CH1_CTRL_TRIG_READ_ERROR_Pos (30UL) /*!< READ_ERROR (Bit 30) */
#define DMA_CH1_CTRL_TRIG_READ_ERROR_Msk (0x40000000UL) /*!< READ_ERROR (Bitfield-Mask: 0x01) */
#define DMA_CH1_CTRL_TRIG_WRITE_ERROR_Pos (29UL) /*!< WRITE_ERROR (Bit 29) */
#define DMA_CH1_CTRL_TRIG_WRITE_ERROR_Msk (0x20000000UL) /*!< WRITE_ERROR (Bitfield-Mask: 0x01) */
#define DMA_CH1_CTRL_TRIG_BUSY_Pos (24UL) /*!< BUSY (Bit 24) */
#define DMA_CH1_CTRL_TRIG_BUSY_Msk (0x1000000UL) /*!< BUSY (Bitfield-Mask: 0x01) */
#define DMA_CH1_CTRL_TRIG_SNIFF_EN_Pos (23UL) /*!< SNIFF_EN (Bit 23) */
#define DMA_CH1_CTRL_TRIG_SNIFF_EN_Msk (0x800000UL) /*!< SNIFF_EN (Bitfield-Mask: 0x01) */
#define DMA_CH1_CTRL_TRIG_BSWAP_Pos (22UL) /*!< BSWAP (Bit 22) */
#define DMA_CH1_CTRL_TRIG_BSWAP_Msk (0x400000UL) /*!< BSWAP (Bitfield-Mask: 0x01) */
#define DMA_CH1_CTRL_TRIG_IRQ_QUIET_Pos (21UL) /*!< IRQ_QUIET (Bit 21) */
#define DMA_CH1_CTRL_TRIG_IRQ_QUIET_Msk (0x200000UL) /*!< IRQ_QUIET (Bitfield-Mask: 0x01) */
#define DMA_CH1_CTRL_TRIG_TREQ_SEL_Pos (15UL) /*!< TREQ_SEL (Bit 15) */
#define DMA_CH1_CTRL_TRIG_TREQ_SEL_Msk (0x1f8000UL) /*!< TREQ_SEL (Bitfield-Mask: 0x3f) */
#define DMA_CH1_CTRL_TRIG_CHAIN_TO_Pos (11UL) /*!< CHAIN_TO (Bit 11) */
#define DMA_CH1_CTRL_TRIG_CHAIN_TO_Msk (0x7800UL) /*!< CHAIN_TO (Bitfield-Mask: 0x0f) */
#define DMA_CH1_CTRL_TRIG_RING_SEL_Pos (10UL) /*!< RING_SEL (Bit 10) */
#define DMA_CH1_CTRL_TRIG_RING_SEL_Msk (0x400UL) /*!< RING_SEL (Bitfield-Mask: 0x01) */
#define DMA_CH1_CTRL_TRIG_RING_SIZE_Pos (6UL) /*!< RING_SIZE (Bit 6) */
#define DMA_CH1_CTRL_TRIG_RING_SIZE_Msk (0x3c0UL) /*!< RING_SIZE (Bitfield-Mask: 0x0f) */
#define DMA_CH1_CTRL_TRIG_INCR_WRITE_Pos (5UL) /*!< INCR_WRITE (Bit 5) */
#define DMA_CH1_CTRL_TRIG_INCR_WRITE_Msk (0x20UL) /*!< INCR_WRITE (Bitfield-Mask: 0x01) */
#define DMA_CH1_CTRL_TRIG_INCR_READ_Pos (4UL) /*!< INCR_READ (Bit 4) */
#define DMA_CH1_CTRL_TRIG_INCR_READ_Msk (0x10UL) /*!< INCR_READ (Bitfield-Mask: 0x01) */
#define DMA_CH1_CTRL_TRIG_DATA_SIZE_Pos (2UL) /*!< DATA_SIZE (Bit 2) */
#define DMA_CH1_CTRL_TRIG_DATA_SIZE_Msk (0xcUL) /*!< DATA_SIZE (Bitfield-Mask: 0x03) */
#define DMA_CH1_CTRL_TRIG_HIGH_PRIORITY_Pos (1UL) /*!< HIGH_PRIORITY (Bit 1) */
#define DMA_CH1_CTRL_TRIG_HIGH_PRIORITY_Msk (0x2UL) /*!< HIGH_PRIORITY (Bitfield-Mask: 0x01) */
#define DMA_CH1_CTRL_TRIG_EN_Pos (0UL) /*!< EN (Bit 0) */
#define DMA_CH1_CTRL_TRIG_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */
/* ===================================================== CH1_AL1_CTRL ====================================================== */
/* =================================================== CH1_AL1_READ_ADDR =================================================== */
/* ================================================== CH1_AL1_WRITE_ADDR =================================================== */
/* =============================================== CH1_AL1_TRANS_COUNT_TRIG ================================================ */
/* ===================================================== CH1_AL2_CTRL ====================================================== */
/* ================================================== CH1_AL2_TRANS_COUNT ================================================== */
/* =================================================== CH1_AL2_READ_ADDR =================================================== */
/* ================================================ CH1_AL2_WRITE_ADDR_TRIG ================================================ */
/* ===================================================== CH1_AL3_CTRL ====================================================== */
/* ================================================== CH1_AL3_WRITE_ADDR =================================================== */
/* ================================================== CH1_AL3_TRANS_COUNT ================================================== */
/* ================================================ CH1_AL3_READ_ADDR_TRIG ================================================= */
/* ===================================================== CH2_READ_ADDR ===================================================== */
/* ==================================================== CH2_WRITE_ADDR ===================================================== */
/* ==================================================== CH2_TRANS_COUNT ==================================================== */
/* ===================================================== CH2_CTRL_TRIG ===================================================== */
#define DMA_CH2_CTRL_TRIG_AHB_ERROR_Pos (31UL) /*!< AHB_ERROR (Bit 31) */
#define DMA_CH2_CTRL_TRIG_AHB_ERROR_Msk (0x80000000UL) /*!< AHB_ERROR (Bitfield-Mask: 0x01) */
#define DMA_CH2_CTRL_TRIG_READ_ERROR_Pos (30UL) /*!< READ_ERROR (Bit 30) */
#define DMA_CH2_CTRL_TRIG_READ_ERROR_Msk (0x40000000UL) /*!< READ_ERROR (Bitfield-Mask: 0x01) */
#define DMA_CH2_CTRL_TRIG_WRITE_ERROR_Pos (29UL) /*!< WRITE_ERROR (Bit 29) */
#define DMA_CH2_CTRL_TRIG_WRITE_ERROR_Msk (0x20000000UL) /*!< WRITE_ERROR (Bitfield-Mask: 0x01) */
#define DMA_CH2_CTRL_TRIG_BUSY_Pos (24UL) /*!< BUSY (Bit 24) */
#define DMA_CH2_CTRL_TRIG_BUSY_Msk (0x1000000UL) /*!< BUSY (Bitfield-Mask: 0x01) */
#define DMA_CH2_CTRL_TRIG_SNIFF_EN_Pos (23UL) /*!< SNIFF_EN (Bit 23) */
#define DMA_CH2_CTRL_TRIG_SNIFF_EN_Msk (0x800000UL) /*!< SNIFF_EN (Bitfield-Mask: 0x01) */
#define DMA_CH2_CTRL_TRIG_BSWAP_Pos (22UL) /*!< BSWAP (Bit 22) */
#define DMA_CH2_CTRL_TRIG_BSWAP_Msk (0x400000UL) /*!< BSWAP (Bitfield-Mask: 0x01) */
#define DMA_CH2_CTRL_TRIG_IRQ_QUIET_Pos (21UL) /*!< IRQ_QUIET (Bit 21) */
#define DMA_CH2_CTRL_TRIG_IRQ_QUIET_Msk (0x200000UL) /*!< IRQ_QUIET (Bitfield-Mask: 0x01) */
#define DMA_CH2_CTRL_TRIG_TREQ_SEL_Pos (15UL) /*!< TREQ_SEL (Bit 15) */
#define DMA_CH2_CTRL_TRIG_TREQ_SEL_Msk (0x1f8000UL) /*!< TREQ_SEL (Bitfield-Mask: 0x3f) */
#define DMA_CH2_CTRL_TRIG_CHAIN_TO_Pos (11UL) /*!< CHAIN_TO (Bit 11) */
#define DMA_CH2_CTRL_TRIG_CHAIN_TO_Msk (0x7800UL) /*!< CHAIN_TO (Bitfield-Mask: 0x0f) */
#define DMA_CH2_CTRL_TRIG_RING_SEL_Pos (10UL) /*!< RING_SEL (Bit 10) */
#define DMA_CH2_CTRL_TRIG_RING_SEL_Msk (0x400UL) /*!< RING_SEL (Bitfield-Mask: 0x01) */
#define DMA_CH2_CTRL_TRIG_RING_SIZE_Pos (6UL) /*!< RING_SIZE (Bit 6) */
#define DMA_CH2_CTRL_TRIG_RING_SIZE_Msk (0x3c0UL) /*!< RING_SIZE (Bitfield-Mask: 0x0f) */
#define DMA_CH2_CTRL_TRIG_INCR_WRITE_Pos (5UL) /*!< INCR_WRITE (Bit 5) */
#define DMA_CH2_CTRL_TRIG_INCR_WRITE_Msk (0x20UL) /*!< INCR_WRITE (Bitfield-Mask: 0x01) */
#define DMA_CH2_CTRL_TRIG_INCR_READ_Pos (4UL) /*!< INCR_READ (Bit 4) */
#define DMA_CH2_CTRL_TRIG_INCR_READ_Msk (0x10UL) /*!< INCR_READ (Bitfield-Mask: 0x01) */
#define DMA_CH2_CTRL_TRIG_DATA_SIZE_Pos (2UL) /*!< DATA_SIZE (Bit 2) */
#define DMA_CH2_CTRL_TRIG_DATA_SIZE_Msk (0xcUL) /*!< DATA_SIZE (Bitfield-Mask: 0x03) */
#define DMA_CH2_CTRL_TRIG_HIGH_PRIORITY_Pos (1UL) /*!< HIGH_PRIORITY (Bit 1) */
#define DMA_CH2_CTRL_TRIG_HIGH_PRIORITY_Msk (0x2UL) /*!< HIGH_PRIORITY (Bitfield-Mask: 0x01) */
#define DMA_CH2_CTRL_TRIG_EN_Pos (0UL) /*!< EN (Bit 0) */
#define DMA_CH2_CTRL_TRIG_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */
/* ===================================================== CH2_AL1_CTRL ====================================================== */
/* =================================================== CH2_AL1_READ_ADDR =================================================== */
/* ================================================== CH2_AL1_WRITE_ADDR =================================================== */
/* =============================================== CH2_AL1_TRANS_COUNT_TRIG ================================================ */
/* ===================================================== CH2_AL2_CTRL ====================================================== */
/* ================================================== CH2_AL2_TRANS_COUNT ================================================== */
/* =================================================== CH2_AL2_READ_ADDR =================================================== */
/* ================================================ CH2_AL2_WRITE_ADDR_TRIG ================================================ */
/* ===================================================== CH2_AL3_CTRL ====================================================== */
/* ================================================== CH2_AL3_WRITE_ADDR =================================================== */
/* ================================================== CH2_AL3_TRANS_COUNT ================================================== */
/* ================================================ CH2_AL3_READ_ADDR_TRIG ================================================= */
/* ===================================================== CH3_READ_ADDR ===================================================== */
/* ==================================================== CH3_WRITE_ADDR ===================================================== */
/* ==================================================== CH3_TRANS_COUNT ==================================================== */
/* ===================================================== CH3_CTRL_TRIG ===================================================== */
#define DMA_CH3_CTRL_TRIG_AHB_ERROR_Pos (31UL) /*!< AHB_ERROR (Bit 31) */
#define DMA_CH3_CTRL_TRIG_AHB_ERROR_Msk (0x80000000UL) /*!< AHB_ERROR (Bitfield-Mask: 0x01) */
#define DMA_CH3_CTRL_TRIG_READ_ERROR_Pos (30UL) /*!< READ_ERROR (Bit 30) */
#define DMA_CH3_CTRL_TRIG_READ_ERROR_Msk (0x40000000UL) /*!< READ_ERROR (Bitfield-Mask: 0x01) */
#define DMA_CH3_CTRL_TRIG_WRITE_ERROR_Pos (29UL) /*!< WRITE_ERROR (Bit 29) */
#define DMA_CH3_CTRL_TRIG_WRITE_ERROR_Msk (0x20000000UL) /*!< WRITE_ERROR (Bitfield-Mask: 0x01) */
#define DMA_CH3_CTRL_TRIG_BUSY_Pos (24UL) /*!< BUSY (Bit 24) */
#define DMA_CH3_CTRL_TRIG_BUSY_Msk (0x1000000UL) /*!< BUSY (Bitfield-Mask: 0x01) */
#define DMA_CH3_CTRL_TRIG_SNIFF_EN_Pos (23UL) /*!< SNIFF_EN (Bit 23) */
#define DMA_CH3_CTRL_TRIG_SNIFF_EN_Msk (0x800000UL) /*!< SNIFF_EN (Bitfield-Mask: 0x01) */
#define DMA_CH3_CTRL_TRIG_BSWAP_Pos (22UL) /*!< BSWAP (Bit 22) */
#define DMA_CH3_CTRL_TRIG_BSWAP_Msk (0x400000UL) /*!< BSWAP (Bitfield-Mask: 0x01) */
#define DMA_CH3_CTRL_TRIG_IRQ_QUIET_Pos (21UL) /*!< IRQ_QUIET (Bit 21) */
#define DMA_CH3_CTRL_TRIG_IRQ_QUIET_Msk (0x200000UL) /*!< IRQ_QUIET (Bitfield-Mask: 0x01) */
#define DMA_CH3_CTRL_TRIG_TREQ_SEL_Pos (15UL) /*!< TREQ_SEL (Bit 15) */
#define DMA_CH3_CTRL_TRIG_TREQ_SEL_Msk (0x1f8000UL) /*!< TREQ_SEL (Bitfield-Mask: 0x3f) */
#define DMA_CH3_CTRL_TRIG_CHAIN_TO_Pos (11UL) /*!< CHAIN_TO (Bit 11) */
#define DMA_CH3_CTRL_TRIG_CHAIN_TO_Msk (0x7800UL) /*!< CHAIN_TO (Bitfield-Mask: 0x0f) */
#define DMA_CH3_CTRL_TRIG_RING_SEL_Pos (10UL) /*!< RING_SEL (Bit 10) */
#define DMA_CH3_CTRL_TRIG_RING_SEL_Msk (0x400UL) /*!< RING_SEL (Bitfield-Mask: 0x01) */
#define DMA_CH3_CTRL_TRIG_RING_SIZE_Pos (6UL) /*!< RING_SIZE (Bit 6) */
#define DMA_CH3_CTRL_TRIG_RING_SIZE_Msk (0x3c0UL) /*!< RING_SIZE (Bitfield-Mask: 0x0f) */
#define DMA_CH3_CTRL_TRIG_INCR_WRITE_Pos (5UL) /*!< INCR_WRITE (Bit 5) */
#define DMA_CH3_CTRL_TRIG_INCR_WRITE_Msk (0x20UL) /*!< INCR_WRITE (Bitfield-Mask: 0x01) */
#define DMA_CH3_CTRL_TRIG_INCR_READ_Pos (4UL) /*!< INCR_READ (Bit 4) */
#define DMA_CH3_CTRL_TRIG_INCR_READ_Msk (0x10UL) /*!< INCR_READ (Bitfield-Mask: 0x01) */
#define DMA_CH3_CTRL_TRIG_DATA_SIZE_Pos (2UL) /*!< DATA_SIZE (Bit 2) */
#define DMA_CH3_CTRL_TRIG_DATA_SIZE_Msk (0xcUL) /*!< DATA_SIZE (Bitfield-Mask: 0x03) */
#define DMA_CH3_CTRL_TRIG_HIGH_PRIORITY_Pos (1UL) /*!< HIGH_PRIORITY (Bit 1) */
#define DMA_CH3_CTRL_TRIG_HIGH_PRIORITY_Msk (0x2UL) /*!< HIGH_PRIORITY (Bitfield-Mask: 0x01) */
#define DMA_CH3_CTRL_TRIG_EN_Pos (0UL) /*!< EN (Bit 0) */
#define DMA_CH3_CTRL_TRIG_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */
/* ===================================================== CH3_AL1_CTRL ====================================================== */
/* =================================================== CH3_AL1_READ_ADDR =================================================== */
/* ================================================== CH3_AL1_WRITE_ADDR =================================================== */
/* =============================================== CH3_AL1_TRANS_COUNT_TRIG ================================================ */
/* ===================================================== CH3_AL2_CTRL ====================================================== */
/* ================================================== CH3_AL2_TRANS_COUNT ================================================== */
/* =================================================== CH3_AL2_READ_ADDR =================================================== */
/* ================================================ CH3_AL2_WRITE_ADDR_TRIG ================================================ */
/* ===================================================== CH3_AL3_CTRL ====================================================== */
/* ================================================== CH3_AL3_WRITE_ADDR =================================================== */
/* ================================================== CH3_AL3_TRANS_COUNT ================================================== */
/* ================================================ CH3_AL3_READ_ADDR_TRIG ================================================= */
/* ===================================================== CH4_READ_ADDR ===================================================== */
/* ==================================================== CH4_WRITE_ADDR ===================================================== */
/* ==================================================== CH4_TRANS_COUNT ==================================================== */
/* ===================================================== CH4_CTRL_TRIG ===================================================== */
#define DMA_CH4_CTRL_TRIG_AHB_ERROR_Pos (31UL) /*!< AHB_ERROR (Bit 31) */
#define DMA_CH4_CTRL_TRIG_AHB_ERROR_Msk (0x80000000UL) /*!< AHB_ERROR (Bitfield-Mask: 0x01) */
#define DMA_CH4_CTRL_TRIG_READ_ERROR_Pos (30UL) /*!< READ_ERROR (Bit 30) */
#define DMA_CH4_CTRL_TRIG_READ_ERROR_Msk (0x40000000UL) /*!< READ_ERROR (Bitfield-Mask: 0x01) */
#define DMA_CH4_CTRL_TRIG_WRITE_ERROR_Pos (29UL) /*!< WRITE_ERROR (Bit 29) */
#define DMA_CH4_CTRL_TRIG_WRITE_ERROR_Msk (0x20000000UL) /*!< WRITE_ERROR (Bitfield-Mask: 0x01) */
#define DMA_CH4_CTRL_TRIG_BUSY_Pos (24UL) /*!< BUSY (Bit 24) */
#define DMA_CH4_CTRL_TRIG_BUSY_Msk (0x1000000UL) /*!< BUSY (Bitfield-Mask: 0x01) */
#define DMA_CH4_CTRL_TRIG_SNIFF_EN_Pos (23UL) /*!< SNIFF_EN (Bit 23) */
#define DMA_CH4_CTRL_TRIG_SNIFF_EN_Msk (0x800000UL) /*!< SNIFF_EN (Bitfield-Mask: 0x01) */
#define DMA_CH4_CTRL_TRIG_BSWAP_Pos (22UL) /*!< BSWAP (Bit 22) */
#define DMA_CH4_CTRL_TRIG_BSWAP_Msk (0x400000UL) /*!< BSWAP (Bitfield-Mask: 0x01) */
#define DMA_CH4_CTRL_TRIG_IRQ_QUIET_Pos (21UL) /*!< IRQ_QUIET (Bit 21) */
#define DMA_CH4_CTRL_TRIG_IRQ_QUIET_Msk (0x200000UL) /*!< IRQ_QUIET (Bitfield-Mask: 0x01) */
#define DMA_CH4_CTRL_TRIG_TREQ_SEL_Pos (15UL) /*!< TREQ_SEL (Bit 15) */
#define DMA_CH4_CTRL_TRIG_TREQ_SEL_Msk (0x1f8000UL) /*!< TREQ_SEL (Bitfield-Mask: 0x3f) */
#define DMA_CH4_CTRL_TRIG_CHAIN_TO_Pos (11UL) /*!< CHAIN_TO (Bit 11) */
#define DMA_CH4_CTRL_TRIG_CHAIN_TO_Msk (0x7800UL) /*!< CHAIN_TO (Bitfield-Mask: 0x0f) */
#define DMA_CH4_CTRL_TRIG_RING_SEL_Pos (10UL) /*!< RING_SEL (Bit 10) */
#define DMA_CH4_CTRL_TRIG_RING_SEL_Msk (0x400UL) /*!< RING_SEL (Bitfield-Mask: 0x01) */
#define DMA_CH4_CTRL_TRIG_RING_SIZE_Pos (6UL) /*!< RING_SIZE (Bit 6) */
#define DMA_CH4_CTRL_TRIG_RING_SIZE_Msk (0x3c0UL) /*!< RING_SIZE (Bitfield-Mask: 0x0f) */
#define DMA_CH4_CTRL_TRIG_INCR_WRITE_Pos (5UL) /*!< INCR_WRITE (Bit 5) */
#define DMA_CH4_CTRL_TRIG_INCR_WRITE_Msk (0x20UL) /*!< INCR_WRITE (Bitfield-Mask: 0x01) */
#define DMA_CH4_CTRL_TRIG_INCR_READ_Pos (4UL) /*!< INCR_READ (Bit 4) */
#define DMA_CH4_CTRL_TRIG_INCR_READ_Msk (0x10UL) /*!< INCR_READ (Bitfield-Mask: 0x01) */
#define DMA_CH4_CTRL_TRIG_DATA_SIZE_Pos (2UL) /*!< DATA_SIZE (Bit 2) */
#define DMA_CH4_CTRL_TRIG_DATA_SIZE_Msk (0xcUL) /*!< DATA_SIZE (Bitfield-Mask: 0x03) */
#define DMA_CH4_CTRL_TRIG_HIGH_PRIORITY_Pos (1UL) /*!< HIGH_PRIORITY (Bit 1) */
#define DMA_CH4_CTRL_TRIG_HIGH_PRIORITY_Msk (0x2UL) /*!< HIGH_PRIORITY (Bitfield-Mask: 0x01) */
#define DMA_CH4_CTRL_TRIG_EN_Pos (0UL) /*!< EN (Bit 0) */
#define DMA_CH4_CTRL_TRIG_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */
/* ===================================================== CH4_AL1_CTRL ====================================================== */
/* =================================================== CH4_AL1_READ_ADDR =================================================== */
/* ================================================== CH4_AL1_WRITE_ADDR =================================================== */
/* =============================================== CH4_AL1_TRANS_COUNT_TRIG ================================================ */
/* ===================================================== CH4_AL2_CTRL ====================================================== */
/* ================================================== CH4_AL2_TRANS_COUNT ================================================== */
/* =================================================== CH4_AL2_READ_ADDR =================================================== */
/* ================================================ CH4_AL2_WRITE_ADDR_TRIG ================================================ */
/* ===================================================== CH4_AL3_CTRL ====================================================== */
/* ================================================== CH4_AL3_WRITE_ADDR =================================================== */
/* ================================================== CH4_AL3_TRANS_COUNT ================================================== */
/* ================================================ CH4_AL3_READ_ADDR_TRIG ================================================= */
/* ===================================================== CH5_READ_ADDR ===================================================== */
/* ==================================================== CH5_WRITE_ADDR ===================================================== */
/* ==================================================== CH5_TRANS_COUNT ==================================================== */
/* ===================================================== CH5_CTRL_TRIG ===================================================== */
#define DMA_CH5_CTRL_TRIG_AHB_ERROR_Pos (31UL) /*!< AHB_ERROR (Bit 31) */
#define DMA_CH5_CTRL_TRIG_AHB_ERROR_Msk (0x80000000UL) /*!< AHB_ERROR (Bitfield-Mask: 0x01) */
#define DMA_CH5_CTRL_TRIG_READ_ERROR_Pos (30UL) /*!< READ_ERROR (Bit 30) */
#define DMA_CH5_CTRL_TRIG_READ_ERROR_Msk (0x40000000UL) /*!< READ_ERROR (Bitfield-Mask: 0x01) */
#define DMA_CH5_CTRL_TRIG_WRITE_ERROR_Pos (29UL) /*!< WRITE_ERROR (Bit 29) */
#define DMA_CH5_CTRL_TRIG_WRITE_ERROR_Msk (0x20000000UL) /*!< WRITE_ERROR (Bitfield-Mask: 0x01) */
#define DMA_CH5_CTRL_TRIG_BUSY_Pos (24UL) /*!< BUSY (Bit 24) */
#define DMA_CH5_CTRL_TRIG_BUSY_Msk (0x1000000UL) /*!< BUSY (Bitfield-Mask: 0x01) */
#define DMA_CH5_CTRL_TRIG_SNIFF_EN_Pos (23UL) /*!< SNIFF_EN (Bit 23) */
#define DMA_CH5_CTRL_TRIG_SNIFF_EN_Msk (0x800000UL) /*!< SNIFF_EN (Bitfield-Mask: 0x01) */
#define DMA_CH5_CTRL_TRIG_BSWAP_Pos (22UL) /*!< BSWAP (Bit 22) */
#define DMA_CH5_CTRL_TRIG_BSWAP_Msk (0x400000UL) /*!< BSWAP (Bitfield-Mask: 0x01) */
#define DMA_CH5_CTRL_TRIG_IRQ_QUIET_Pos (21UL) /*!< IRQ_QUIET (Bit 21) */
#define DMA_CH5_CTRL_TRIG_IRQ_QUIET_Msk (0x200000UL) /*!< IRQ_QUIET (Bitfield-Mask: 0x01) */
#define DMA_CH5_CTRL_TRIG_TREQ_SEL_Pos (15UL) /*!< TREQ_SEL (Bit 15) */
#define DMA_CH5_CTRL_TRIG_TREQ_SEL_Msk (0x1f8000UL) /*!< TREQ_SEL (Bitfield-Mask: 0x3f) */
#define DMA_CH5_CTRL_TRIG_CHAIN_TO_Pos (11UL) /*!< CHAIN_TO (Bit 11) */
#define DMA_CH5_CTRL_TRIG_CHAIN_TO_Msk (0x7800UL) /*!< CHAIN_TO (Bitfield-Mask: 0x0f) */
#define DMA_CH5_CTRL_TRIG_RING_SEL_Pos (10UL) /*!< RING_SEL (Bit 10) */
#define DMA_CH5_CTRL_TRIG_RING_SEL_Msk (0x400UL) /*!< RING_SEL (Bitfield-Mask: 0x01) */
#define DMA_CH5_CTRL_TRIG_RING_SIZE_Pos (6UL) /*!< RING_SIZE (Bit 6) */
#define DMA_CH5_CTRL_TRIG_RING_SIZE_Msk (0x3c0UL) /*!< RING_SIZE (Bitfield-Mask: 0x0f) */
#define DMA_CH5_CTRL_TRIG_INCR_WRITE_Pos (5UL) /*!< INCR_WRITE (Bit 5) */
#define DMA_CH5_CTRL_TRIG_INCR_WRITE_Msk (0x20UL) /*!< INCR_WRITE (Bitfield-Mask: 0x01) */
#define DMA_CH5_CTRL_TRIG_INCR_READ_Pos (4UL) /*!< INCR_READ (Bit 4) */
#define DMA_CH5_CTRL_TRIG_INCR_READ_Msk (0x10UL) /*!< INCR_READ (Bitfield-Mask: 0x01) */
#define DMA_CH5_CTRL_TRIG_DATA_SIZE_Pos (2UL) /*!< DATA_SIZE (Bit 2) */
#define DMA_CH5_CTRL_TRIG_DATA_SIZE_Msk (0xcUL) /*!< DATA_SIZE (Bitfield-Mask: 0x03) */
#define DMA_CH5_CTRL_TRIG_HIGH_PRIORITY_Pos (1UL) /*!< HIGH_PRIORITY (Bit 1) */
#define DMA_CH5_CTRL_TRIG_HIGH_PRIORITY_Msk (0x2UL) /*!< HIGH_PRIORITY (Bitfield-Mask: 0x01) */
#define DMA_CH5_CTRL_TRIG_EN_Pos (0UL) /*!< EN (Bit 0) */
#define DMA_CH5_CTRL_TRIG_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */
/* ===================================================== CH5_AL1_CTRL ====================================================== */
/* =================================================== CH5_AL1_READ_ADDR =================================================== */
/* ================================================== CH5_AL1_WRITE_ADDR =================================================== */
/* =============================================== CH5_AL1_TRANS_COUNT_TRIG ================================================ */
/* ===================================================== CH5_AL2_CTRL ====================================================== */
/* ================================================== CH5_AL2_TRANS_COUNT ================================================== */
/* =================================================== CH5_AL2_READ_ADDR =================================================== */
/* ================================================ CH5_AL2_WRITE_ADDR_TRIG ================================================ */
/* ===================================================== CH5_AL3_CTRL ====================================================== */
/* ================================================== CH5_AL3_WRITE_ADDR =================================================== */
/* ================================================== CH5_AL3_TRANS_COUNT ================================================== */
/* ================================================ CH5_AL3_READ_ADDR_TRIG ================================================= */
/* ===================================================== CH6_READ_ADDR ===================================================== */
/* ==================================================== CH6_WRITE_ADDR ===================================================== */
/* ==================================================== CH6_TRANS_COUNT ==================================================== */
/* ===================================================== CH6_CTRL_TRIG ===================================================== */
#define DMA_CH6_CTRL_TRIG_AHB_ERROR_Pos (31UL) /*!< AHB_ERROR (Bit 31) */
#define DMA_CH6_CTRL_TRIG_AHB_ERROR_Msk (0x80000000UL) /*!< AHB_ERROR (Bitfield-Mask: 0x01) */
#define DMA_CH6_CTRL_TRIG_READ_ERROR_Pos (30UL) /*!< READ_ERROR (Bit 30) */
#define DMA_CH6_CTRL_TRIG_READ_ERROR_Msk (0x40000000UL) /*!< READ_ERROR (Bitfield-Mask: 0x01) */
#define DMA_CH6_CTRL_TRIG_WRITE_ERROR_Pos (29UL) /*!< WRITE_ERROR (Bit 29) */
#define DMA_CH6_CTRL_TRIG_WRITE_ERROR_Msk (0x20000000UL) /*!< WRITE_ERROR (Bitfield-Mask: 0x01) */
#define DMA_CH6_CTRL_TRIG_BUSY_Pos (24UL) /*!< BUSY (Bit 24) */
#define DMA_CH6_CTRL_TRIG_BUSY_Msk (0x1000000UL) /*!< BUSY (Bitfield-Mask: 0x01) */
#define DMA_CH6_CTRL_TRIG_SNIFF_EN_Pos (23UL) /*!< SNIFF_EN (Bit 23) */
#define DMA_CH6_CTRL_TRIG_SNIFF_EN_Msk (0x800000UL) /*!< SNIFF_EN (Bitfield-Mask: 0x01) */
#define DMA_CH6_CTRL_TRIG_BSWAP_Pos (22UL) /*!< BSWAP (Bit 22) */
#define DMA_CH6_CTRL_TRIG_BSWAP_Msk (0x400000UL) /*!< BSWAP (Bitfield-Mask: 0x01) */
#define DMA_CH6_CTRL_TRIG_IRQ_QUIET_Pos (21UL) /*!< IRQ_QUIET (Bit 21) */
#define DMA_CH6_CTRL_TRIG_IRQ_QUIET_Msk (0x200000UL) /*!< IRQ_QUIET (Bitfield-Mask: 0x01) */
#define DMA_CH6_CTRL_TRIG_TREQ_SEL_Pos (15UL) /*!< TREQ_SEL (Bit 15) */
#define DMA_CH6_CTRL_TRIG_TREQ_SEL_Msk (0x1f8000UL) /*!< TREQ_SEL (Bitfield-Mask: 0x3f) */
#define DMA_CH6_CTRL_TRIG_CHAIN_TO_Pos (11UL) /*!< CHAIN_TO (Bit 11) */
#define DMA_CH6_CTRL_TRIG_CHAIN_TO_Msk (0x7800UL) /*!< CHAIN_TO (Bitfield-Mask: 0x0f) */
#define DMA_CH6_CTRL_TRIG_RING_SEL_Pos (10UL) /*!< RING_SEL (Bit 10) */
#define DMA_CH6_CTRL_TRIG_RING_SEL_Msk (0x400UL) /*!< RING_SEL (Bitfield-Mask: 0x01) */
#define DMA_CH6_CTRL_TRIG_RING_SIZE_Pos (6UL) /*!< RING_SIZE (Bit 6) */
#define DMA_CH6_CTRL_TRIG_RING_SIZE_Msk (0x3c0UL) /*!< RING_SIZE (Bitfield-Mask: 0x0f) */
#define DMA_CH6_CTRL_TRIG_INCR_WRITE_Pos (5UL) /*!< INCR_WRITE (Bit 5) */
#define DMA_CH6_CTRL_TRIG_INCR_WRITE_Msk (0x20UL) /*!< INCR_WRITE (Bitfield-Mask: 0x01) */
#define DMA_CH6_CTRL_TRIG_INCR_READ_Pos (4UL) /*!< INCR_READ (Bit 4) */
#define DMA_CH6_CTRL_TRIG_INCR_READ_Msk (0x10UL) /*!< INCR_READ (Bitfield-Mask: 0x01) */
#define DMA_CH6_CTRL_TRIG_DATA_SIZE_Pos (2UL) /*!< DATA_SIZE (Bit 2) */
#define DMA_CH6_CTRL_TRIG_DATA_SIZE_Msk (0xcUL) /*!< DATA_SIZE (Bitfield-Mask: 0x03) */
#define DMA_CH6_CTRL_TRIG_HIGH_PRIORITY_Pos (1UL) /*!< HIGH_PRIORITY (Bit 1) */
#define DMA_CH6_CTRL_TRIG_HIGH_PRIORITY_Msk (0x2UL) /*!< HIGH_PRIORITY (Bitfield-Mask: 0x01) */
#define DMA_CH6_CTRL_TRIG_EN_Pos (0UL) /*!< EN (Bit 0) */
#define DMA_CH6_CTRL_TRIG_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */
/* ===================================================== CH6_AL1_CTRL ====================================================== */
/* =================================================== CH6_AL1_READ_ADDR =================================================== */
/* ================================================== CH6_AL1_WRITE_ADDR =================================================== */
/* =============================================== CH6_AL1_TRANS_COUNT_TRIG ================================================ */
/* ===================================================== CH6_AL2_CTRL ====================================================== */
/* ================================================== CH6_AL2_TRANS_COUNT ================================================== */
/* =================================================== CH6_AL2_READ_ADDR =================================================== */
/* ================================================ CH6_AL2_WRITE_ADDR_TRIG ================================================ */
/* ===================================================== CH6_AL3_CTRL ====================================================== */
/* ================================================== CH6_AL3_WRITE_ADDR =================================================== */
/* ================================================== CH6_AL3_TRANS_COUNT ================================================== */
/* ================================================ CH6_AL3_READ_ADDR_TRIG ================================================= */
/* ===================================================== CH7_READ_ADDR ===================================================== */
/* ==================================================== CH7_WRITE_ADDR ===================================================== */
/* ==================================================== CH7_TRANS_COUNT ==================================================== */
/* ===================================================== CH7_CTRL_TRIG ===================================================== */
#define DMA_CH7_CTRL_TRIG_AHB_ERROR_Pos (31UL) /*!< AHB_ERROR (Bit 31) */
#define DMA_CH7_CTRL_TRIG_AHB_ERROR_Msk (0x80000000UL) /*!< AHB_ERROR (Bitfield-Mask: 0x01) */
#define DMA_CH7_CTRL_TRIG_READ_ERROR_Pos (30UL) /*!< READ_ERROR (Bit 30) */
#define DMA_CH7_CTRL_TRIG_READ_ERROR_Msk (0x40000000UL) /*!< READ_ERROR (Bitfield-Mask: 0x01) */
#define DMA_CH7_CTRL_TRIG_WRITE_ERROR_Pos (29UL) /*!< WRITE_ERROR (Bit 29) */
#define DMA_CH7_CTRL_TRIG_WRITE_ERROR_Msk (0x20000000UL) /*!< WRITE_ERROR (Bitfield-Mask: 0x01) */
#define DMA_CH7_CTRL_TRIG_BUSY_Pos (24UL) /*!< BUSY (Bit 24) */
#define DMA_CH7_CTRL_TRIG_BUSY_Msk (0x1000000UL) /*!< BUSY (Bitfield-Mask: 0x01) */
#define DMA_CH7_CTRL_TRIG_SNIFF_EN_Pos (23UL) /*!< SNIFF_EN (Bit 23) */
#define DMA_CH7_CTRL_TRIG_SNIFF_EN_Msk (0x800000UL) /*!< SNIFF_EN (Bitfield-Mask: 0x01) */
#define DMA_CH7_CTRL_TRIG_BSWAP_Pos (22UL) /*!< BSWAP (Bit 22) */
#define DMA_CH7_CTRL_TRIG_BSWAP_Msk (0x400000UL) /*!< BSWAP (Bitfield-Mask: 0x01) */
#define DMA_CH7_CTRL_TRIG_IRQ_QUIET_Pos (21UL) /*!< IRQ_QUIET (Bit 21) */
#define DMA_CH7_CTRL_TRIG_IRQ_QUIET_Msk (0x200000UL) /*!< IRQ_QUIET (Bitfield-Mask: 0x01) */
#define DMA_CH7_CTRL_TRIG_TREQ_SEL_Pos (15UL) /*!< TREQ_SEL (Bit 15) */
#define DMA_CH7_CTRL_TRIG_TREQ_SEL_Msk (0x1f8000UL) /*!< TREQ_SEL (Bitfield-Mask: 0x3f) */
#define DMA_CH7_CTRL_TRIG_CHAIN_TO_Pos (11UL) /*!< CHAIN_TO (Bit 11) */
#define DMA_CH7_CTRL_TRIG_CHAIN_TO_Msk (0x7800UL) /*!< CHAIN_TO (Bitfield-Mask: 0x0f) */
#define DMA_CH7_CTRL_TRIG_RING_SEL_Pos (10UL) /*!< RING_SEL (Bit 10) */
#define DMA_CH7_CTRL_TRIG_RING_SEL_Msk (0x400UL) /*!< RING_SEL (Bitfield-Mask: 0x01) */
#define DMA_CH7_CTRL_TRIG_RING_SIZE_Pos (6UL) /*!< RING_SIZE (Bit 6) */
#define DMA_CH7_CTRL_TRIG_RING_SIZE_Msk (0x3c0UL) /*!< RING_SIZE (Bitfield-Mask: 0x0f) */
#define DMA_CH7_CTRL_TRIG_INCR_WRITE_Pos (5UL) /*!< INCR_WRITE (Bit 5) */
#define DMA_CH7_CTRL_TRIG_INCR_WRITE_Msk (0x20UL) /*!< INCR_WRITE (Bitfield-Mask: 0x01) */
#define DMA_CH7_CTRL_TRIG_INCR_READ_Pos (4UL) /*!< INCR_READ (Bit 4) */
#define DMA_CH7_CTRL_TRIG_INCR_READ_Msk (0x10UL) /*!< INCR_READ (Bitfield-Mask: 0x01) */
#define DMA_CH7_CTRL_TRIG_DATA_SIZE_Pos (2UL) /*!< DATA_SIZE (Bit 2) */
#define DMA_CH7_CTRL_TRIG_DATA_SIZE_Msk (0xcUL) /*!< DATA_SIZE (Bitfield-Mask: 0x03) */
#define DMA_CH7_CTRL_TRIG_HIGH_PRIORITY_Pos (1UL) /*!< HIGH_PRIORITY (Bit 1) */
#define DMA_CH7_CTRL_TRIG_HIGH_PRIORITY_Msk (0x2UL) /*!< HIGH_PRIORITY (Bitfield-Mask: 0x01) */
#define DMA_CH7_CTRL_TRIG_EN_Pos (0UL) /*!< EN (Bit 0) */
#define DMA_CH7_CTRL_TRIG_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */
/* ===================================================== CH7_AL1_CTRL ====================================================== */
/* =================================================== CH7_AL1_READ_ADDR =================================================== */
/* ================================================== CH7_AL1_WRITE_ADDR =================================================== */
/* =============================================== CH7_AL1_TRANS_COUNT_TRIG ================================================ */
/* ===================================================== CH7_AL2_CTRL ====================================================== */
/* ================================================== CH7_AL2_TRANS_COUNT ================================================== */
/* =================================================== CH7_AL2_READ_ADDR =================================================== */
/* ================================================ CH7_AL2_WRITE_ADDR_TRIG ================================================ */
/* ===================================================== CH7_AL3_CTRL ====================================================== */
/* ================================================== CH7_AL3_WRITE_ADDR =================================================== */
/* ================================================== CH7_AL3_TRANS_COUNT ================================================== */
/* ================================================ CH7_AL3_READ_ADDR_TRIG ================================================= */
/* ===================================================== CH8_READ_ADDR ===================================================== */
/* ==================================================== CH8_WRITE_ADDR ===================================================== */
/* ==================================================== CH8_TRANS_COUNT ==================================================== */
/* ===================================================== CH8_CTRL_TRIG ===================================================== */
#define DMA_CH8_CTRL_TRIG_AHB_ERROR_Pos (31UL) /*!< AHB_ERROR (Bit 31) */
#define DMA_CH8_CTRL_TRIG_AHB_ERROR_Msk (0x80000000UL) /*!< AHB_ERROR (Bitfield-Mask: 0x01) */
#define DMA_CH8_CTRL_TRIG_READ_ERROR_Pos (30UL) /*!< READ_ERROR (Bit 30) */
#define DMA_CH8_CTRL_TRIG_READ_ERROR_Msk (0x40000000UL) /*!< READ_ERROR (Bitfield-Mask: 0x01) */
#define DMA_CH8_CTRL_TRIG_WRITE_ERROR_Pos (29UL) /*!< WRITE_ERROR (Bit 29) */
#define DMA_CH8_CTRL_TRIG_WRITE_ERROR_Msk (0x20000000UL) /*!< WRITE_ERROR (Bitfield-Mask: 0x01) */
#define DMA_CH8_CTRL_TRIG_BUSY_Pos (24UL) /*!< BUSY (Bit 24) */
#define DMA_CH8_CTRL_TRIG_BUSY_Msk (0x1000000UL) /*!< BUSY (Bitfield-Mask: 0x01) */
#define DMA_CH8_CTRL_TRIG_SNIFF_EN_Pos (23UL) /*!< SNIFF_EN (Bit 23) */
#define DMA_CH8_CTRL_TRIG_SNIFF_EN_Msk (0x800000UL) /*!< SNIFF_EN (Bitfield-Mask: 0x01) */
#define DMA_CH8_CTRL_TRIG_BSWAP_Pos (22UL) /*!< BSWAP (Bit 22) */
#define DMA_CH8_CTRL_TRIG_BSWAP_Msk (0x400000UL) /*!< BSWAP (Bitfield-Mask: 0x01) */
#define DMA_CH8_CTRL_TRIG_IRQ_QUIET_Pos (21UL) /*!< IRQ_QUIET (Bit 21) */
#define DMA_CH8_CTRL_TRIG_IRQ_QUIET_Msk (0x200000UL) /*!< IRQ_QUIET (Bitfield-Mask: 0x01) */
#define DMA_CH8_CTRL_TRIG_TREQ_SEL_Pos (15UL) /*!< TREQ_SEL (Bit 15) */
#define DMA_CH8_CTRL_TRIG_TREQ_SEL_Msk (0x1f8000UL) /*!< TREQ_SEL (Bitfield-Mask: 0x3f) */
#define DMA_CH8_CTRL_TRIG_CHAIN_TO_Pos (11UL) /*!< CHAIN_TO (Bit 11) */
#define DMA_CH8_CTRL_TRIG_CHAIN_TO_Msk (0x7800UL) /*!< CHAIN_TO (Bitfield-Mask: 0x0f) */
#define DMA_CH8_CTRL_TRIG_RING_SEL_Pos (10UL) /*!< RING_SEL (Bit 10) */
#define DMA_CH8_CTRL_TRIG_RING_SEL_Msk (0x400UL) /*!< RING_SEL (Bitfield-Mask: 0x01) */
#define DMA_CH8_CTRL_TRIG_RING_SIZE_Pos (6UL) /*!< RING_SIZE (Bit 6) */
#define DMA_CH8_CTRL_TRIG_RING_SIZE_Msk (0x3c0UL) /*!< RING_SIZE (Bitfield-Mask: 0x0f) */
#define DMA_CH8_CTRL_TRIG_INCR_WRITE_Pos (5UL) /*!< INCR_WRITE (Bit 5) */
#define DMA_CH8_CTRL_TRIG_INCR_WRITE_Msk (0x20UL) /*!< INCR_WRITE (Bitfield-Mask: 0x01) */
#define DMA_CH8_CTRL_TRIG_INCR_READ_Pos (4UL) /*!< INCR_READ (Bit 4) */
#define DMA_CH8_CTRL_TRIG_INCR_READ_Msk (0x10UL) /*!< INCR_READ (Bitfield-Mask: 0x01) */
#define DMA_CH8_CTRL_TRIG_DATA_SIZE_Pos (2UL) /*!< DATA_SIZE (Bit 2) */
#define DMA_CH8_CTRL_TRIG_DATA_SIZE_Msk (0xcUL) /*!< DATA_SIZE (Bitfield-Mask: 0x03) */
#define DMA_CH8_CTRL_TRIG_HIGH_PRIORITY_Pos (1UL) /*!< HIGH_PRIORITY (Bit 1) */
#define DMA_CH8_CTRL_TRIG_HIGH_PRIORITY_Msk (0x2UL) /*!< HIGH_PRIORITY (Bitfield-Mask: 0x01) */
#define DMA_CH8_CTRL_TRIG_EN_Pos (0UL) /*!< EN (Bit 0) */
#define DMA_CH8_CTRL_TRIG_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */
/* ===================================================== CH8_AL1_CTRL ====================================================== */
/* =================================================== CH8_AL1_READ_ADDR =================================================== */
/* ================================================== CH8_AL1_WRITE_ADDR =================================================== */
/* =============================================== CH8_AL1_TRANS_COUNT_TRIG ================================================ */
/* ===================================================== CH8_AL2_CTRL ====================================================== */
/* ================================================== CH8_AL2_TRANS_COUNT ================================================== */
/* =================================================== CH8_AL2_READ_ADDR =================================================== */
/* ================================================ CH8_AL2_WRITE_ADDR_TRIG ================================================ */
/* ===================================================== CH8_AL3_CTRL ====================================================== */
/* ================================================== CH8_AL3_WRITE_ADDR =================================================== */
/* ================================================== CH8_AL3_TRANS_COUNT ================================================== */
/* ================================================ CH8_AL3_READ_ADDR_TRIG ================================================= */
/* ===================================================== CH9_READ_ADDR ===================================================== */
/* ==================================================== CH9_WRITE_ADDR ===================================================== */
/* ==================================================== CH9_TRANS_COUNT ==================================================== */
/* ===================================================== CH9_CTRL_TRIG ===================================================== */
#define DMA_CH9_CTRL_TRIG_AHB_ERROR_Pos (31UL) /*!< AHB_ERROR (Bit 31) */
#define DMA_CH9_CTRL_TRIG_AHB_ERROR_Msk (0x80000000UL) /*!< AHB_ERROR (Bitfield-Mask: 0x01) */
#define DMA_CH9_CTRL_TRIG_READ_ERROR_Pos (30UL) /*!< READ_ERROR (Bit 30) */
#define DMA_CH9_CTRL_TRIG_READ_ERROR_Msk (0x40000000UL) /*!< READ_ERROR (Bitfield-Mask: 0x01) */
#define DMA_CH9_CTRL_TRIG_WRITE_ERROR_Pos (29UL) /*!< WRITE_ERROR (Bit 29) */
#define DMA_CH9_CTRL_TRIG_WRITE_ERROR_Msk (0x20000000UL) /*!< WRITE_ERROR (Bitfield-Mask: 0x01) */
#define DMA_CH9_CTRL_TRIG_BUSY_Pos (24UL) /*!< BUSY (Bit 24) */
#define DMA_CH9_CTRL_TRIG_BUSY_Msk (0x1000000UL) /*!< BUSY (Bitfield-Mask: 0x01) */
#define DMA_CH9_CTRL_TRIG_SNIFF_EN_Pos (23UL) /*!< SNIFF_EN (Bit 23) */
#define DMA_CH9_CTRL_TRIG_SNIFF_EN_Msk (0x800000UL) /*!< SNIFF_EN (Bitfield-Mask: 0x01) */
#define DMA_CH9_CTRL_TRIG_BSWAP_Pos (22UL) /*!< BSWAP (Bit 22) */
#define DMA_CH9_CTRL_TRIG_BSWAP_Msk (0x400000UL) /*!< BSWAP (Bitfield-Mask: 0x01) */
#define DMA_CH9_CTRL_TRIG_IRQ_QUIET_Pos (21UL) /*!< IRQ_QUIET (Bit 21) */
#define DMA_CH9_CTRL_TRIG_IRQ_QUIET_Msk (0x200000UL) /*!< IRQ_QUIET (Bitfield-Mask: 0x01) */
#define DMA_CH9_CTRL_TRIG_TREQ_SEL_Pos (15UL) /*!< TREQ_SEL (Bit 15) */
#define DMA_CH9_CTRL_TRIG_TREQ_SEL_Msk (0x1f8000UL) /*!< TREQ_SEL (Bitfield-Mask: 0x3f) */
#define DMA_CH9_CTRL_TRIG_CHAIN_TO_Pos (11UL) /*!< CHAIN_TO (Bit 11) */
#define DMA_CH9_CTRL_TRIG_CHAIN_TO_Msk (0x7800UL) /*!< CHAIN_TO (Bitfield-Mask: 0x0f) */
#define DMA_CH9_CTRL_TRIG_RING_SEL_Pos (10UL) /*!< RING_SEL (Bit 10) */
#define DMA_CH9_CTRL_TRIG_RING_SEL_Msk (0x400UL) /*!< RING_SEL (Bitfield-Mask: 0x01) */
#define DMA_CH9_CTRL_TRIG_RING_SIZE_Pos (6UL) /*!< RING_SIZE (Bit 6) */
#define DMA_CH9_CTRL_TRIG_RING_SIZE_Msk (0x3c0UL) /*!< RING_SIZE (Bitfield-Mask: 0x0f) */
#define DMA_CH9_CTRL_TRIG_INCR_WRITE_Pos (5UL) /*!< INCR_WRITE (Bit 5) */
#define DMA_CH9_CTRL_TRIG_INCR_WRITE_Msk (0x20UL) /*!< INCR_WRITE (Bitfield-Mask: 0x01) */
#define DMA_CH9_CTRL_TRIG_INCR_READ_Pos (4UL) /*!< INCR_READ (Bit 4) */
#define DMA_CH9_CTRL_TRIG_INCR_READ_Msk (0x10UL) /*!< INCR_READ (Bitfield-Mask: 0x01) */
#define DMA_CH9_CTRL_TRIG_DATA_SIZE_Pos (2UL) /*!< DATA_SIZE (Bit 2) */
#define DMA_CH9_CTRL_TRIG_DATA_SIZE_Msk (0xcUL) /*!< DATA_SIZE (Bitfield-Mask: 0x03) */
#define DMA_CH9_CTRL_TRIG_HIGH_PRIORITY_Pos (1UL) /*!< HIGH_PRIORITY (Bit 1) */
#define DMA_CH9_CTRL_TRIG_HIGH_PRIORITY_Msk (0x2UL) /*!< HIGH_PRIORITY (Bitfield-Mask: 0x01) */
#define DMA_CH9_CTRL_TRIG_EN_Pos (0UL) /*!< EN (Bit 0) */
#define DMA_CH9_CTRL_TRIG_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */
/* ===================================================== CH9_AL1_CTRL ====================================================== */
/* =================================================== CH9_AL1_READ_ADDR =================================================== */
/* ================================================== CH9_AL1_WRITE_ADDR =================================================== */
/* =============================================== CH9_AL1_TRANS_COUNT_TRIG ================================================ */
/* ===================================================== CH9_AL2_CTRL ====================================================== */
/* ================================================== CH9_AL2_TRANS_COUNT ================================================== */
/* =================================================== CH9_AL2_READ_ADDR =================================================== */
/* ================================================ CH9_AL2_WRITE_ADDR_TRIG ================================================ */
/* ===================================================== CH9_AL3_CTRL ====================================================== */
/* ================================================== CH9_AL3_WRITE_ADDR =================================================== */
/* ================================================== CH9_AL3_TRANS_COUNT ================================================== */
/* ================================================ CH9_AL3_READ_ADDR_TRIG ================================================= */
/* ==================================================== CH10_READ_ADDR ===================================================== */
/* ==================================================== CH10_WRITE_ADDR ==================================================== */
/* =================================================== CH10_TRANS_COUNT ==================================================== */
/* ==================================================== CH10_CTRL_TRIG ===================================================== */
#define DMA_CH10_CTRL_TRIG_AHB_ERROR_Pos (31UL) /*!< AHB_ERROR (Bit 31) */
#define DMA_CH10_CTRL_TRIG_AHB_ERROR_Msk (0x80000000UL) /*!< AHB_ERROR (Bitfield-Mask: 0x01) */
#define DMA_CH10_CTRL_TRIG_READ_ERROR_Pos (30UL) /*!< READ_ERROR (Bit 30) */
#define DMA_CH10_CTRL_TRIG_READ_ERROR_Msk (0x40000000UL) /*!< READ_ERROR (Bitfield-Mask: 0x01) */
#define DMA_CH10_CTRL_TRIG_WRITE_ERROR_Pos (29UL) /*!< WRITE_ERROR (Bit 29) */
#define DMA_CH10_CTRL_TRIG_WRITE_ERROR_Msk (0x20000000UL) /*!< WRITE_ERROR (Bitfield-Mask: 0x01) */
#define DMA_CH10_CTRL_TRIG_BUSY_Pos (24UL) /*!< BUSY (Bit 24) */
#define DMA_CH10_CTRL_TRIG_BUSY_Msk (0x1000000UL) /*!< BUSY (Bitfield-Mask: 0x01) */
#define DMA_CH10_CTRL_TRIG_SNIFF_EN_Pos (23UL) /*!< SNIFF_EN (Bit 23) */
#define DMA_CH10_CTRL_TRIG_SNIFF_EN_Msk (0x800000UL) /*!< SNIFF_EN (Bitfield-Mask: 0x01) */
#define DMA_CH10_CTRL_TRIG_BSWAP_Pos (22UL) /*!< BSWAP (Bit 22) */
#define DMA_CH10_CTRL_TRIG_BSWAP_Msk (0x400000UL) /*!< BSWAP (Bitfield-Mask: 0x01) */
#define DMA_CH10_CTRL_TRIG_IRQ_QUIET_Pos (21UL) /*!< IRQ_QUIET (Bit 21) */
#define DMA_CH10_CTRL_TRIG_IRQ_QUIET_Msk (0x200000UL) /*!< IRQ_QUIET (Bitfield-Mask: 0x01) */
#define DMA_CH10_CTRL_TRIG_TREQ_SEL_Pos (15UL) /*!< TREQ_SEL (Bit 15) */
#define DMA_CH10_CTRL_TRIG_TREQ_SEL_Msk (0x1f8000UL) /*!< TREQ_SEL (Bitfield-Mask: 0x3f) */
#define DMA_CH10_CTRL_TRIG_CHAIN_TO_Pos (11UL) /*!< CHAIN_TO (Bit 11) */
#define DMA_CH10_CTRL_TRIG_CHAIN_TO_Msk (0x7800UL) /*!< CHAIN_TO (Bitfield-Mask: 0x0f) */
#define DMA_CH10_CTRL_TRIG_RING_SEL_Pos (10UL) /*!< RING_SEL (Bit 10) */
#define DMA_CH10_CTRL_TRIG_RING_SEL_Msk (0x400UL) /*!< RING_SEL (Bitfield-Mask: 0x01) */
#define DMA_CH10_CTRL_TRIG_RING_SIZE_Pos (6UL) /*!< RING_SIZE (Bit 6) */
#define DMA_CH10_CTRL_TRIG_RING_SIZE_Msk (0x3c0UL) /*!< RING_SIZE (Bitfield-Mask: 0x0f) */
#define DMA_CH10_CTRL_TRIG_INCR_WRITE_Pos (5UL) /*!< INCR_WRITE (Bit 5) */
#define DMA_CH10_CTRL_TRIG_INCR_WRITE_Msk (0x20UL) /*!< INCR_WRITE (Bitfield-Mask: 0x01) */
#define DMA_CH10_CTRL_TRIG_INCR_READ_Pos (4UL) /*!< INCR_READ (Bit 4) */
#define DMA_CH10_CTRL_TRIG_INCR_READ_Msk (0x10UL) /*!< INCR_READ (Bitfield-Mask: 0x01) */
#define DMA_CH10_CTRL_TRIG_DATA_SIZE_Pos (2UL) /*!< DATA_SIZE (Bit 2) */
#define DMA_CH10_CTRL_TRIG_DATA_SIZE_Msk (0xcUL) /*!< DATA_SIZE (Bitfield-Mask: 0x03) */
#define DMA_CH10_CTRL_TRIG_HIGH_PRIORITY_Pos (1UL) /*!< HIGH_PRIORITY (Bit 1) */
#define DMA_CH10_CTRL_TRIG_HIGH_PRIORITY_Msk (0x2UL) /*!< HIGH_PRIORITY (Bitfield-Mask: 0x01) */
#define DMA_CH10_CTRL_TRIG_EN_Pos (0UL) /*!< EN (Bit 0) */
#define DMA_CH10_CTRL_TRIG_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */
/* ===================================================== CH10_AL1_CTRL ===================================================== */
/* ================================================== CH10_AL1_READ_ADDR =================================================== */
/* ================================================== CH10_AL1_WRITE_ADDR ================================================== */
/* =============================================== CH10_AL1_TRANS_COUNT_TRIG =============================================== */
/* ===================================================== CH10_AL2_CTRL ===================================================== */
/* ================================================= CH10_AL2_TRANS_COUNT ================================================== */
/* ================================================== CH10_AL2_READ_ADDR =================================================== */
/* =============================================== CH10_AL2_WRITE_ADDR_TRIG ================================================ */
/* ===================================================== CH10_AL3_CTRL ===================================================== */
/* ================================================== CH10_AL3_WRITE_ADDR ================================================== */
/* ================================================= CH10_AL3_TRANS_COUNT ================================================== */
/* ================================================ CH10_AL3_READ_ADDR_TRIG ================================================ */
/* ==================================================== CH11_READ_ADDR ===================================================== */
/* ==================================================== CH11_WRITE_ADDR ==================================================== */
/* =================================================== CH11_TRANS_COUNT ==================================================== */
/* ==================================================== CH11_CTRL_TRIG ===================================================== */
#define DMA_CH11_CTRL_TRIG_AHB_ERROR_Pos (31UL) /*!< AHB_ERROR (Bit 31) */
#define DMA_CH11_CTRL_TRIG_AHB_ERROR_Msk (0x80000000UL) /*!< AHB_ERROR (Bitfield-Mask: 0x01) */
#define DMA_CH11_CTRL_TRIG_READ_ERROR_Pos (30UL) /*!< READ_ERROR (Bit 30) */
#define DMA_CH11_CTRL_TRIG_READ_ERROR_Msk (0x40000000UL) /*!< READ_ERROR (Bitfield-Mask: 0x01) */
#define DMA_CH11_CTRL_TRIG_WRITE_ERROR_Pos (29UL) /*!< WRITE_ERROR (Bit 29) */
#define DMA_CH11_CTRL_TRIG_WRITE_ERROR_Msk (0x20000000UL) /*!< WRITE_ERROR (Bitfield-Mask: 0x01) */
#define DMA_CH11_CTRL_TRIG_BUSY_Pos (24UL) /*!< BUSY (Bit 24) */
#define DMA_CH11_CTRL_TRIG_BUSY_Msk (0x1000000UL) /*!< BUSY (Bitfield-Mask: 0x01) */
#define DMA_CH11_CTRL_TRIG_SNIFF_EN_Pos (23UL) /*!< SNIFF_EN (Bit 23) */
#define DMA_CH11_CTRL_TRIG_SNIFF_EN_Msk (0x800000UL) /*!< SNIFF_EN (Bitfield-Mask: 0x01) */
#define DMA_CH11_CTRL_TRIG_BSWAP_Pos (22UL) /*!< BSWAP (Bit 22) */
#define DMA_CH11_CTRL_TRIG_BSWAP_Msk (0x400000UL) /*!< BSWAP (Bitfield-Mask: 0x01) */
#define DMA_CH11_CTRL_TRIG_IRQ_QUIET_Pos (21UL) /*!< IRQ_QUIET (Bit 21) */
#define DMA_CH11_CTRL_TRIG_IRQ_QUIET_Msk (0x200000UL) /*!< IRQ_QUIET (Bitfield-Mask: 0x01) */
#define DMA_CH11_CTRL_TRIG_TREQ_SEL_Pos (15UL) /*!< TREQ_SEL (Bit 15) */
#define DMA_CH11_CTRL_TRIG_TREQ_SEL_Msk (0x1f8000UL) /*!< TREQ_SEL (Bitfield-Mask: 0x3f) */
#define DMA_CH11_CTRL_TRIG_CHAIN_TO_Pos (11UL) /*!< CHAIN_TO (Bit 11) */
#define DMA_CH11_CTRL_TRIG_CHAIN_TO_Msk (0x7800UL) /*!< CHAIN_TO (Bitfield-Mask: 0x0f) */
#define DMA_CH11_CTRL_TRIG_RING_SEL_Pos (10UL) /*!< RING_SEL (Bit 10) */
#define DMA_CH11_CTRL_TRIG_RING_SEL_Msk (0x400UL) /*!< RING_SEL (Bitfield-Mask: 0x01) */
#define DMA_CH11_CTRL_TRIG_RING_SIZE_Pos (6UL) /*!< RING_SIZE (Bit 6) */
#define DMA_CH11_CTRL_TRIG_RING_SIZE_Msk (0x3c0UL) /*!< RING_SIZE (Bitfield-Mask: 0x0f) */
#define DMA_CH11_CTRL_TRIG_INCR_WRITE_Pos (5UL) /*!< INCR_WRITE (Bit 5) */
#define DMA_CH11_CTRL_TRIG_INCR_WRITE_Msk (0x20UL) /*!< INCR_WRITE (Bitfield-Mask: 0x01) */
#define DMA_CH11_CTRL_TRIG_INCR_READ_Pos (4UL) /*!< INCR_READ (Bit 4) */
#define DMA_CH11_CTRL_TRIG_INCR_READ_Msk (0x10UL) /*!< INCR_READ (Bitfield-Mask: 0x01) */
#define DMA_CH11_CTRL_TRIG_DATA_SIZE_Pos (2UL) /*!< DATA_SIZE (Bit 2) */
#define DMA_CH11_CTRL_TRIG_DATA_SIZE_Msk (0xcUL) /*!< DATA_SIZE (Bitfield-Mask: 0x03) */
#define DMA_CH11_CTRL_TRIG_HIGH_PRIORITY_Pos (1UL) /*!< HIGH_PRIORITY (Bit 1) */
#define DMA_CH11_CTRL_TRIG_HIGH_PRIORITY_Msk (0x2UL) /*!< HIGH_PRIORITY (Bitfield-Mask: 0x01) */
#define DMA_CH11_CTRL_TRIG_EN_Pos (0UL) /*!< EN (Bit 0) */
#define DMA_CH11_CTRL_TRIG_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */
/* ===================================================== CH11_AL1_CTRL ===================================================== */
/* ================================================== CH11_AL1_READ_ADDR =================================================== */
/* ================================================== CH11_AL1_WRITE_ADDR ================================================== */
/* =============================================== CH11_AL1_TRANS_COUNT_TRIG =============================================== */
/* ===================================================== CH11_AL2_CTRL ===================================================== */
/* ================================================= CH11_AL2_TRANS_COUNT ================================================== */
/* ================================================== CH11_AL2_READ_ADDR =================================================== */
/* =============================================== CH11_AL2_WRITE_ADDR_TRIG ================================================ */
/* ===================================================== CH11_AL3_CTRL ===================================================== */
/* ================================================== CH11_AL3_WRITE_ADDR ================================================== */
/* ================================================= CH11_AL3_TRANS_COUNT ================================================== */
/* ================================================ CH11_AL3_READ_ADDR_TRIG ================================================ */
/* ========================================================= INTR ========================================================== */
#define DMA_INTR_INTR_Pos (0UL) /*!< INTR (Bit 0) */
#define DMA_INTR_INTR_Msk (0xffffUL) /*!< INTR (Bitfield-Mask: 0xffff) */
/* ========================================================= INTE0 ========================================================= */
#define DMA_INTE0_INTE0_Pos (0UL) /*!< INTE0 (Bit 0) */
#define DMA_INTE0_INTE0_Msk (0xffffUL) /*!< INTE0 (Bitfield-Mask: 0xffff) */
/* ========================================================= INTF0 ========================================================= */
#define DMA_INTF0_INTF0_Pos (0UL) /*!< INTF0 (Bit 0) */
#define DMA_INTF0_INTF0_Msk (0xffffUL) /*!< INTF0 (Bitfield-Mask: 0xffff) */
/* ========================================================= INTS0 ========================================================= */
#define DMA_INTS0_INTS0_Pos (0UL) /*!< INTS0 (Bit 0) */
#define DMA_INTS0_INTS0_Msk (0xffffUL) /*!< INTS0 (Bitfield-Mask: 0xffff) */
/* ========================================================= INTE1 ========================================================= */
#define DMA_INTE1_INTE1_Pos (0UL) /*!< INTE1 (Bit 0) */
#define DMA_INTE1_INTE1_Msk (0xffffUL) /*!< INTE1 (Bitfield-Mask: 0xffff) */
/* ========================================================= INTF1 ========================================================= */
#define DMA_INTF1_INTF1_Pos (0UL) /*!< INTF1 (Bit 0) */
#define DMA_INTF1_INTF1_Msk (0xffffUL) /*!< INTF1 (Bitfield-Mask: 0xffff) */
/* ========================================================= INTS1 ========================================================= */
#define DMA_INTS1_INTS1_Pos (0UL) /*!< INTS1 (Bit 0) */
#define DMA_INTS1_INTS1_Msk (0xffffUL) /*!< INTS1 (Bitfield-Mask: 0xffff) */
/* ======================================================== TIMER0 ========================================================= */
#define DMA_TIMER0_X_Pos (16UL) /*!< X (Bit 16) */
#define DMA_TIMER0_X_Msk (0xffff0000UL) /*!< X (Bitfield-Mask: 0xffff) */
#define DMA_TIMER0_Y_Pos (0UL) /*!< Y (Bit 0) */
#define DMA_TIMER0_Y_Msk (0xffffUL) /*!< Y (Bitfield-Mask: 0xffff) */
/* ======================================================== TIMER1 ========================================================= */
#define DMA_TIMER1_X_Pos (16UL) /*!< X (Bit 16) */
#define DMA_TIMER1_X_Msk (0xffff0000UL) /*!< X (Bitfield-Mask: 0xffff) */
#define DMA_TIMER1_Y_Pos (0UL) /*!< Y (Bit 0) */
#define DMA_TIMER1_Y_Msk (0xffffUL) /*!< Y (Bitfield-Mask: 0xffff) */
/* ======================================================== TIMER2 ========================================================= */
#define DMA_TIMER2_X_Pos (16UL) /*!< X (Bit 16) */
#define DMA_TIMER2_X_Msk (0xffff0000UL) /*!< X (Bitfield-Mask: 0xffff) */
#define DMA_TIMER2_Y_Pos (0UL) /*!< Y (Bit 0) */
#define DMA_TIMER2_Y_Msk (0xffffUL) /*!< Y (Bitfield-Mask: 0xffff) */
/* ======================================================== TIMER3 ========================================================= */
#define DMA_TIMER3_X_Pos (16UL) /*!< X (Bit 16) */
#define DMA_TIMER3_X_Msk (0xffff0000UL) /*!< X (Bitfield-Mask: 0xffff) */
#define DMA_TIMER3_Y_Pos (0UL) /*!< Y (Bit 0) */
#define DMA_TIMER3_Y_Msk (0xffffUL) /*!< Y (Bitfield-Mask: 0xffff) */
/* ================================================== MULTI_CHAN_TRIGGER =================================================== */
#define DMA_MULTI_CHAN_TRIGGER_MULTI_CHAN_TRIGGER_Pos (0UL) /*!< MULTI_CHAN_TRIGGER (Bit 0) */
#define DMA_MULTI_CHAN_TRIGGER_MULTI_CHAN_TRIGGER_Msk (0xffffUL) /*!< MULTI_CHAN_TRIGGER (Bitfield-Mask: 0xffff) */
/* ====================================================== SNIFF_CTRL ======================================================= */
#define DMA_SNIFF_CTRL_OUT_INV_Pos (11UL) /*!< OUT_INV (Bit 11) */
#define DMA_SNIFF_CTRL_OUT_INV_Msk (0x800UL) /*!< OUT_INV (Bitfield-Mask: 0x01) */
#define DMA_SNIFF_CTRL_OUT_REV_Pos (10UL) /*!< OUT_REV (Bit 10) */
#define DMA_SNIFF_CTRL_OUT_REV_Msk (0x400UL) /*!< OUT_REV (Bitfield-Mask: 0x01) */
#define DMA_SNIFF_CTRL_BSWAP_Pos (9UL) /*!< BSWAP (Bit 9) */
#define DMA_SNIFF_CTRL_BSWAP_Msk (0x200UL) /*!< BSWAP (Bitfield-Mask: 0x01) */
#define DMA_SNIFF_CTRL_CALC_Pos (5UL) /*!< CALC (Bit 5) */
#define DMA_SNIFF_CTRL_CALC_Msk (0x1e0UL) /*!< CALC (Bitfield-Mask: 0x0f) */
#define DMA_SNIFF_CTRL_DMACH_Pos (1UL) /*!< DMACH (Bit 1) */
#define DMA_SNIFF_CTRL_DMACH_Msk (0x1eUL) /*!< DMACH (Bitfield-Mask: 0x0f) */
#define DMA_SNIFF_CTRL_EN_Pos (0UL) /*!< EN (Bit 0) */
#define DMA_SNIFF_CTRL_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */
/* ====================================================== SNIFF_DATA ======================================================= */
/* ====================================================== FIFO_LEVELS ====================================================== */
#define DMA_FIFO_LEVELS_RAF_LVL_Pos (16UL) /*!< RAF_LVL (Bit 16) */
#define DMA_FIFO_LEVELS_RAF_LVL_Msk (0xff0000UL) /*!< RAF_LVL (Bitfield-Mask: 0xff) */
#define DMA_FIFO_LEVELS_WAF_LVL_Pos (8UL) /*!< WAF_LVL (Bit 8) */
#define DMA_FIFO_LEVELS_WAF_LVL_Msk (0xff00UL) /*!< WAF_LVL (Bitfield-Mask: 0xff) */
#define DMA_FIFO_LEVELS_TDF_LVL_Pos (0UL) /*!< TDF_LVL (Bit 0) */
#define DMA_FIFO_LEVELS_TDF_LVL_Msk (0xffUL) /*!< TDF_LVL (Bitfield-Mask: 0xff) */
/* ====================================================== CHAN_ABORT ======================================================= */
#define DMA_CHAN_ABORT_CHAN_ABORT_Pos (0UL) /*!< CHAN_ABORT (Bit 0) */
#define DMA_CHAN_ABORT_CHAN_ABORT_Msk (0xffffUL) /*!< CHAN_ABORT (Bitfield-Mask: 0xffff) */
/* ====================================================== N_CHANNELS ======================================================= */
#define DMA_N_CHANNELS_N_CHANNELS_Pos (0UL) /*!< N_CHANNELS (Bit 0) */
#define DMA_N_CHANNELS_N_CHANNELS_Msk (0x1fUL) /*!< N_CHANNELS (Bitfield-Mask: 0x1f) */
/* ==================================================== CH0_DBG_CTDREQ ===================================================== */
#define DMA_CH0_DBG_CTDREQ_CH0_DBG_CTDREQ_Pos (0UL) /*!< CH0_DBG_CTDREQ (Bit 0) */
#define DMA_CH0_DBG_CTDREQ_CH0_DBG_CTDREQ_Msk (0x3fUL) /*!< CH0_DBG_CTDREQ (Bitfield-Mask: 0x3f) */
/* ====================================================== CH0_DBG_TCR ====================================================== */
/* ==================================================== CH1_DBG_CTDREQ ===================================================== */
#define DMA_CH1_DBG_CTDREQ_CH1_DBG_CTDREQ_Pos (0UL) /*!< CH1_DBG_CTDREQ (Bit 0) */
#define DMA_CH1_DBG_CTDREQ_CH1_DBG_CTDREQ_Msk (0x3fUL) /*!< CH1_DBG_CTDREQ (Bitfield-Mask: 0x3f) */
/* ====================================================== CH1_DBG_TCR ====================================================== */
/* ==================================================== CH2_DBG_CTDREQ ===================================================== */
#define DMA_CH2_DBG_CTDREQ_CH2_DBG_CTDREQ_Pos (0UL) /*!< CH2_DBG_CTDREQ (Bit 0) */
#define DMA_CH2_DBG_CTDREQ_CH2_DBG_CTDREQ_Msk (0x3fUL) /*!< CH2_DBG_CTDREQ (Bitfield-Mask: 0x3f) */
/* ====================================================== CH2_DBG_TCR ====================================================== */
/* ==================================================== CH3_DBG_CTDREQ ===================================================== */
#define DMA_CH3_DBG_CTDREQ_CH3_DBG_CTDREQ_Pos (0UL) /*!< CH3_DBG_CTDREQ (Bit 0) */
#define DMA_CH3_DBG_CTDREQ_CH3_DBG_CTDREQ_Msk (0x3fUL) /*!< CH3_DBG_CTDREQ (Bitfield-Mask: 0x3f) */
/* ====================================================== CH3_DBG_TCR ====================================================== */
/* ==================================================== CH4_DBG_CTDREQ ===================================================== */
#define DMA_CH4_DBG_CTDREQ_CH4_DBG_CTDREQ_Pos (0UL) /*!< CH4_DBG_CTDREQ (Bit 0) */
#define DMA_CH4_DBG_CTDREQ_CH4_DBG_CTDREQ_Msk (0x3fUL) /*!< CH4_DBG_CTDREQ (Bitfield-Mask: 0x3f) */
/* ====================================================== CH4_DBG_TCR ====================================================== */
/* ==================================================== CH5_DBG_CTDREQ ===================================================== */
#define DMA_CH5_DBG_CTDREQ_CH5_DBG_CTDREQ_Pos (0UL) /*!< CH5_DBG_CTDREQ (Bit 0) */
#define DMA_CH5_DBG_CTDREQ_CH5_DBG_CTDREQ_Msk (0x3fUL) /*!< CH5_DBG_CTDREQ (Bitfield-Mask: 0x3f) */
/* ====================================================== CH5_DBG_TCR ====================================================== */
/* ==================================================== CH6_DBG_CTDREQ ===================================================== */
#define DMA_CH6_DBG_CTDREQ_CH6_DBG_CTDREQ_Pos (0UL) /*!< CH6_DBG_CTDREQ (Bit 0) */
#define DMA_CH6_DBG_CTDREQ_CH6_DBG_CTDREQ_Msk (0x3fUL) /*!< CH6_DBG_CTDREQ (Bitfield-Mask: 0x3f) */
/* ====================================================== CH6_DBG_TCR ====================================================== */
/* ==================================================== CH7_DBG_CTDREQ ===================================================== */
#define DMA_CH7_DBG_CTDREQ_CH7_DBG_CTDREQ_Pos (0UL) /*!< CH7_DBG_CTDREQ (Bit 0) */
#define DMA_CH7_DBG_CTDREQ_CH7_DBG_CTDREQ_Msk (0x3fUL) /*!< CH7_DBG_CTDREQ (Bitfield-Mask: 0x3f) */
/* ====================================================== CH7_DBG_TCR ====================================================== */
/* ==================================================== CH8_DBG_CTDREQ ===================================================== */
#define DMA_CH8_DBG_CTDREQ_CH8_DBG_CTDREQ_Pos (0UL) /*!< CH8_DBG_CTDREQ (Bit 0) */
#define DMA_CH8_DBG_CTDREQ_CH8_DBG_CTDREQ_Msk (0x3fUL) /*!< CH8_DBG_CTDREQ (Bitfield-Mask: 0x3f) */
/* ====================================================== CH8_DBG_TCR ====================================================== */
/* ==================================================== CH9_DBG_CTDREQ ===================================================== */
#define DMA_CH9_DBG_CTDREQ_CH9_DBG_CTDREQ_Pos (0UL) /*!< CH9_DBG_CTDREQ (Bit 0) */
#define DMA_CH9_DBG_CTDREQ_CH9_DBG_CTDREQ_Msk (0x3fUL) /*!< CH9_DBG_CTDREQ (Bitfield-Mask: 0x3f) */
/* ====================================================== CH9_DBG_TCR ====================================================== */
/* ==================================================== CH10_DBG_CTDREQ ==================================================== */
#define DMA_CH10_DBG_CTDREQ_CH10_DBG_CTDREQ_Pos (0UL) /*!< CH10_DBG_CTDREQ (Bit 0) */
#define DMA_CH10_DBG_CTDREQ_CH10_DBG_CTDREQ_Msk (0x3fUL) /*!< CH10_DBG_CTDREQ (Bitfield-Mask: 0x3f) */
/* ===================================================== CH10_DBG_TCR ====================================================== */
/* ==================================================== CH11_DBG_CTDREQ ==================================================== */
#define DMA_CH11_DBG_CTDREQ_CH11_DBG_CTDREQ_Pos (0UL) /*!< CH11_DBG_CTDREQ (Bit 0) */
#define DMA_CH11_DBG_CTDREQ_CH11_DBG_CTDREQ_Msk (0x3fUL) /*!< CH11_DBG_CTDREQ (Bitfield-Mask: 0x3f) */
/* ===================================================== CH11_DBG_TCR ====================================================== */
/* =========================================================================================================================== */
/* ================ USBCTRL_DPRAM ================ */
/* =========================================================================================================================== */
/* =================================================== SETUP_PACKET_LOW ==================================================== */
#define USBCTRL_DPRAM_SETUP_PACKET_LOW_WVALUE_Pos (16UL) /*!< WVALUE (Bit 16) */
#define USBCTRL_DPRAM_SETUP_PACKET_LOW_WVALUE_Msk (0xffff0000UL) /*!< WVALUE (Bitfield-Mask: 0xffff) */
#define USBCTRL_DPRAM_SETUP_PACKET_LOW_BREQUEST_Pos (8UL) /*!< BREQUEST (Bit 8) */
#define USBCTRL_DPRAM_SETUP_PACKET_LOW_BREQUEST_Msk (0xff00UL) /*!< BREQUEST (Bitfield-Mask: 0xff) */
#define USBCTRL_DPRAM_SETUP_PACKET_LOW_BMREQUESTTYPE_Pos (0UL) /*!< BMREQUESTTYPE (Bit 0) */
#define USBCTRL_DPRAM_SETUP_PACKET_LOW_BMREQUESTTYPE_Msk (0xffUL) /*!< BMREQUESTTYPE (Bitfield-Mask: 0xff) */
/* =================================================== SETUP_PACKET_HIGH =================================================== */
#define USBCTRL_DPRAM_SETUP_PACKET_HIGH_WLENGTH_Pos (16UL) /*!< WLENGTH (Bit 16) */
#define USBCTRL_DPRAM_SETUP_PACKET_HIGH_WLENGTH_Msk (0xffff0000UL) /*!< WLENGTH (Bitfield-Mask: 0xffff) */
#define USBCTRL_DPRAM_SETUP_PACKET_HIGH_WINDEX_Pos (0UL) /*!< WINDEX (Bit 0) */
#define USBCTRL_DPRAM_SETUP_PACKET_HIGH_WINDEX_Msk (0xffffUL) /*!< WINDEX (Bitfield-Mask: 0xffff) */
/* ==================================================== EP1_IN_CONTROL ===================================================== */
#define USBCTRL_DPRAM_EP1_IN_CONTROL_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */
#define USBCTRL_DPRAM_EP1_IN_CONTROL_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP1_IN_CONTROL_DOUBLE_BUFFERED_Pos (30UL) /*!< DOUBLE_BUFFERED (Bit 30) */
#define USBCTRL_DPRAM_EP1_IN_CONTROL_DOUBLE_BUFFERED_Msk (0x40000000UL) /*!< DOUBLE_BUFFERED (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_BUFF_Pos (29UL) /*!< INTERRUPT_PER_BUFF (Bit 29) */
#define USBCTRL_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_BUFF_Msk (0x20000000UL) /*!< INTERRUPT_PER_BUFF (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Pos (28UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bit 28) */
#define USBCTRL_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Msk (0x10000000UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_Pos (26UL) /*!< ENDPOINT_TYPE (Bit 26) */
#define USBCTRL_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_Msk (0xc000000UL) /*!< ENDPOINT_TYPE (Bitfield-Mask: 0x03) */
#define USBCTRL_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_STALL_Pos (17UL) /*!< INTERRUPT_ON_STALL (Bit 17) */
#define USBCTRL_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_STALL_Msk (0x20000UL) /*!< INTERRUPT_ON_STALL (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_NAK_Pos (16UL) /*!< INTERRUPT_ON_NAK (Bit 16) */
#define USBCTRL_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_NAK_Msk (0x10000UL) /*!< INTERRUPT_ON_NAK (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP1_IN_CONTROL_BUFFER_ADDRESS_Pos (0UL) /*!< BUFFER_ADDRESS (Bit 0) */
#define USBCTRL_DPRAM_EP1_IN_CONTROL_BUFFER_ADDRESS_Msk (0xffffUL) /*!< BUFFER_ADDRESS (Bitfield-Mask: 0xffff) */
/* ==================================================== EP1_OUT_CONTROL ==================================================== */
#define USBCTRL_DPRAM_EP1_OUT_CONTROL_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */
#define USBCTRL_DPRAM_EP1_OUT_CONTROL_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP1_OUT_CONTROL_DOUBLE_BUFFERED_Pos (30UL) /*!< DOUBLE_BUFFERED (Bit 30) */
#define USBCTRL_DPRAM_EP1_OUT_CONTROL_DOUBLE_BUFFERED_Msk (0x40000000UL) /*!< DOUBLE_BUFFERED (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_BUFF_Pos (29UL) /*!< INTERRUPT_PER_BUFF (Bit 29) */
#define USBCTRL_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_BUFF_Msk (0x20000000UL) /*!< INTERRUPT_PER_BUFF (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Pos (28UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bit 28) */
#define USBCTRL_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Msk (0x10000000UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_Pos (26UL) /*!< ENDPOINT_TYPE (Bit 26) */
#define USBCTRL_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_Msk (0xc000000UL) /*!< ENDPOINT_TYPE (Bitfield-Mask: 0x03) */
#define USBCTRL_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_STALL_Pos (17UL) /*!< INTERRUPT_ON_STALL (Bit 17) */
#define USBCTRL_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_STALL_Msk (0x20000UL) /*!< INTERRUPT_ON_STALL (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_NAK_Pos (16UL) /*!< INTERRUPT_ON_NAK (Bit 16) */
#define USBCTRL_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_NAK_Msk (0x10000UL) /*!< INTERRUPT_ON_NAK (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP1_OUT_CONTROL_BUFFER_ADDRESS_Pos (0UL) /*!< BUFFER_ADDRESS (Bit 0) */
#define USBCTRL_DPRAM_EP1_OUT_CONTROL_BUFFER_ADDRESS_Msk (0xffffUL) /*!< BUFFER_ADDRESS (Bitfield-Mask: 0xffff) */
/* ==================================================== EP2_IN_CONTROL ===================================================== */
#define USBCTRL_DPRAM_EP2_IN_CONTROL_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */
#define USBCTRL_DPRAM_EP2_IN_CONTROL_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP2_IN_CONTROL_DOUBLE_BUFFERED_Pos (30UL) /*!< DOUBLE_BUFFERED (Bit 30) */
#define USBCTRL_DPRAM_EP2_IN_CONTROL_DOUBLE_BUFFERED_Msk (0x40000000UL) /*!< DOUBLE_BUFFERED (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_BUFF_Pos (29UL) /*!< INTERRUPT_PER_BUFF (Bit 29) */
#define USBCTRL_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_BUFF_Msk (0x20000000UL) /*!< INTERRUPT_PER_BUFF (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Pos (28UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bit 28) */
#define USBCTRL_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Msk (0x10000000UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_Pos (26UL) /*!< ENDPOINT_TYPE (Bit 26) */
#define USBCTRL_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_Msk (0xc000000UL) /*!< ENDPOINT_TYPE (Bitfield-Mask: 0x03) */
#define USBCTRL_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_STALL_Pos (17UL) /*!< INTERRUPT_ON_STALL (Bit 17) */
#define USBCTRL_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_STALL_Msk (0x20000UL) /*!< INTERRUPT_ON_STALL (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_NAK_Pos (16UL) /*!< INTERRUPT_ON_NAK (Bit 16) */
#define USBCTRL_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_NAK_Msk (0x10000UL) /*!< INTERRUPT_ON_NAK (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP2_IN_CONTROL_BUFFER_ADDRESS_Pos (0UL) /*!< BUFFER_ADDRESS (Bit 0) */
#define USBCTRL_DPRAM_EP2_IN_CONTROL_BUFFER_ADDRESS_Msk (0xffffUL) /*!< BUFFER_ADDRESS (Bitfield-Mask: 0xffff) */
/* ==================================================== EP2_OUT_CONTROL ==================================================== */
#define USBCTRL_DPRAM_EP2_OUT_CONTROL_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */
#define USBCTRL_DPRAM_EP2_OUT_CONTROL_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP2_OUT_CONTROL_DOUBLE_BUFFERED_Pos (30UL) /*!< DOUBLE_BUFFERED (Bit 30) */
#define USBCTRL_DPRAM_EP2_OUT_CONTROL_DOUBLE_BUFFERED_Msk (0x40000000UL) /*!< DOUBLE_BUFFERED (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_BUFF_Pos (29UL) /*!< INTERRUPT_PER_BUFF (Bit 29) */
#define USBCTRL_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_BUFF_Msk (0x20000000UL) /*!< INTERRUPT_PER_BUFF (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Pos (28UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bit 28) */
#define USBCTRL_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Msk (0x10000000UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_Pos (26UL) /*!< ENDPOINT_TYPE (Bit 26) */
#define USBCTRL_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_Msk (0xc000000UL) /*!< ENDPOINT_TYPE (Bitfield-Mask: 0x03) */
#define USBCTRL_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_STALL_Pos (17UL) /*!< INTERRUPT_ON_STALL (Bit 17) */
#define USBCTRL_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_STALL_Msk (0x20000UL) /*!< INTERRUPT_ON_STALL (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_NAK_Pos (16UL) /*!< INTERRUPT_ON_NAK (Bit 16) */
#define USBCTRL_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_NAK_Msk (0x10000UL) /*!< INTERRUPT_ON_NAK (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP2_OUT_CONTROL_BUFFER_ADDRESS_Pos (0UL) /*!< BUFFER_ADDRESS (Bit 0) */
#define USBCTRL_DPRAM_EP2_OUT_CONTROL_BUFFER_ADDRESS_Msk (0xffffUL) /*!< BUFFER_ADDRESS (Bitfield-Mask: 0xffff) */
/* ==================================================== EP3_IN_CONTROL ===================================================== */
#define USBCTRL_DPRAM_EP3_IN_CONTROL_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */
#define USBCTRL_DPRAM_EP3_IN_CONTROL_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP3_IN_CONTROL_DOUBLE_BUFFERED_Pos (30UL) /*!< DOUBLE_BUFFERED (Bit 30) */
#define USBCTRL_DPRAM_EP3_IN_CONTROL_DOUBLE_BUFFERED_Msk (0x40000000UL) /*!< DOUBLE_BUFFERED (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_BUFF_Pos (29UL) /*!< INTERRUPT_PER_BUFF (Bit 29) */
#define USBCTRL_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_BUFF_Msk (0x20000000UL) /*!< INTERRUPT_PER_BUFF (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Pos (28UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bit 28) */
#define USBCTRL_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Msk (0x10000000UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_Pos (26UL) /*!< ENDPOINT_TYPE (Bit 26) */
#define USBCTRL_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_Msk (0xc000000UL) /*!< ENDPOINT_TYPE (Bitfield-Mask: 0x03) */
#define USBCTRL_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_STALL_Pos (17UL) /*!< INTERRUPT_ON_STALL (Bit 17) */
#define USBCTRL_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_STALL_Msk (0x20000UL) /*!< INTERRUPT_ON_STALL (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_NAK_Pos (16UL) /*!< INTERRUPT_ON_NAK (Bit 16) */
#define USBCTRL_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_NAK_Msk (0x10000UL) /*!< INTERRUPT_ON_NAK (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP3_IN_CONTROL_BUFFER_ADDRESS_Pos (0UL) /*!< BUFFER_ADDRESS (Bit 0) */
#define USBCTRL_DPRAM_EP3_IN_CONTROL_BUFFER_ADDRESS_Msk (0xffffUL) /*!< BUFFER_ADDRESS (Bitfield-Mask: 0xffff) */
/* ==================================================== EP3_OUT_CONTROL ==================================================== */
#define USBCTRL_DPRAM_EP3_OUT_CONTROL_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */
#define USBCTRL_DPRAM_EP3_OUT_CONTROL_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP3_OUT_CONTROL_DOUBLE_BUFFERED_Pos (30UL) /*!< DOUBLE_BUFFERED (Bit 30) */
#define USBCTRL_DPRAM_EP3_OUT_CONTROL_DOUBLE_BUFFERED_Msk (0x40000000UL) /*!< DOUBLE_BUFFERED (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_BUFF_Pos (29UL) /*!< INTERRUPT_PER_BUFF (Bit 29) */
#define USBCTRL_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_BUFF_Msk (0x20000000UL) /*!< INTERRUPT_PER_BUFF (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Pos (28UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bit 28) */
#define USBCTRL_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Msk (0x10000000UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_Pos (26UL) /*!< ENDPOINT_TYPE (Bit 26) */
#define USBCTRL_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_Msk (0xc000000UL) /*!< ENDPOINT_TYPE (Bitfield-Mask: 0x03) */
#define USBCTRL_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_STALL_Pos (17UL) /*!< INTERRUPT_ON_STALL (Bit 17) */
#define USBCTRL_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_STALL_Msk (0x20000UL) /*!< INTERRUPT_ON_STALL (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_NAK_Pos (16UL) /*!< INTERRUPT_ON_NAK (Bit 16) */
#define USBCTRL_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_NAK_Msk (0x10000UL) /*!< INTERRUPT_ON_NAK (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP3_OUT_CONTROL_BUFFER_ADDRESS_Pos (0UL) /*!< BUFFER_ADDRESS (Bit 0) */
#define USBCTRL_DPRAM_EP3_OUT_CONTROL_BUFFER_ADDRESS_Msk (0xffffUL) /*!< BUFFER_ADDRESS (Bitfield-Mask: 0xffff) */
/* ==================================================== EP4_IN_CONTROL ===================================================== */
#define USBCTRL_DPRAM_EP4_IN_CONTROL_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */
#define USBCTRL_DPRAM_EP4_IN_CONTROL_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP4_IN_CONTROL_DOUBLE_BUFFERED_Pos (30UL) /*!< DOUBLE_BUFFERED (Bit 30) */
#define USBCTRL_DPRAM_EP4_IN_CONTROL_DOUBLE_BUFFERED_Msk (0x40000000UL) /*!< DOUBLE_BUFFERED (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_BUFF_Pos (29UL) /*!< INTERRUPT_PER_BUFF (Bit 29) */
#define USBCTRL_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_BUFF_Msk (0x20000000UL) /*!< INTERRUPT_PER_BUFF (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Pos (28UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bit 28) */
#define USBCTRL_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Msk (0x10000000UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_Pos (26UL) /*!< ENDPOINT_TYPE (Bit 26) */
#define USBCTRL_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_Msk (0xc000000UL) /*!< ENDPOINT_TYPE (Bitfield-Mask: 0x03) */
#define USBCTRL_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_STALL_Pos (17UL) /*!< INTERRUPT_ON_STALL (Bit 17) */
#define USBCTRL_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_STALL_Msk (0x20000UL) /*!< INTERRUPT_ON_STALL (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_NAK_Pos (16UL) /*!< INTERRUPT_ON_NAK (Bit 16) */
#define USBCTRL_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_NAK_Msk (0x10000UL) /*!< INTERRUPT_ON_NAK (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP4_IN_CONTROL_BUFFER_ADDRESS_Pos (0UL) /*!< BUFFER_ADDRESS (Bit 0) */
#define USBCTRL_DPRAM_EP4_IN_CONTROL_BUFFER_ADDRESS_Msk (0xffffUL) /*!< BUFFER_ADDRESS (Bitfield-Mask: 0xffff) */
/* ==================================================== EP4_OUT_CONTROL ==================================================== */
#define USBCTRL_DPRAM_EP4_OUT_CONTROL_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */
#define USBCTRL_DPRAM_EP4_OUT_CONTROL_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP4_OUT_CONTROL_DOUBLE_BUFFERED_Pos (30UL) /*!< DOUBLE_BUFFERED (Bit 30) */
#define USBCTRL_DPRAM_EP4_OUT_CONTROL_DOUBLE_BUFFERED_Msk (0x40000000UL) /*!< DOUBLE_BUFFERED (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_BUFF_Pos (29UL) /*!< INTERRUPT_PER_BUFF (Bit 29) */
#define USBCTRL_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_BUFF_Msk (0x20000000UL) /*!< INTERRUPT_PER_BUFF (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Pos (28UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bit 28) */
#define USBCTRL_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Msk (0x10000000UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_Pos (26UL) /*!< ENDPOINT_TYPE (Bit 26) */
#define USBCTRL_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_Msk (0xc000000UL) /*!< ENDPOINT_TYPE (Bitfield-Mask: 0x03) */
#define USBCTRL_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_STALL_Pos (17UL) /*!< INTERRUPT_ON_STALL (Bit 17) */
#define USBCTRL_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_STALL_Msk (0x20000UL) /*!< INTERRUPT_ON_STALL (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_NAK_Pos (16UL) /*!< INTERRUPT_ON_NAK (Bit 16) */
#define USBCTRL_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_NAK_Msk (0x10000UL) /*!< INTERRUPT_ON_NAK (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP4_OUT_CONTROL_BUFFER_ADDRESS_Pos (0UL) /*!< BUFFER_ADDRESS (Bit 0) */
#define USBCTRL_DPRAM_EP4_OUT_CONTROL_BUFFER_ADDRESS_Msk (0xffffUL) /*!< BUFFER_ADDRESS (Bitfield-Mask: 0xffff) */
/* ==================================================== EP5_IN_CONTROL ===================================================== */
#define USBCTRL_DPRAM_EP5_IN_CONTROL_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */
#define USBCTRL_DPRAM_EP5_IN_CONTROL_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP5_IN_CONTROL_DOUBLE_BUFFERED_Pos (30UL) /*!< DOUBLE_BUFFERED (Bit 30) */
#define USBCTRL_DPRAM_EP5_IN_CONTROL_DOUBLE_BUFFERED_Msk (0x40000000UL) /*!< DOUBLE_BUFFERED (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_BUFF_Pos (29UL) /*!< INTERRUPT_PER_BUFF (Bit 29) */
#define USBCTRL_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_BUFF_Msk (0x20000000UL) /*!< INTERRUPT_PER_BUFF (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Pos (28UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bit 28) */
#define USBCTRL_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Msk (0x10000000UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_Pos (26UL) /*!< ENDPOINT_TYPE (Bit 26) */
#define USBCTRL_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_Msk (0xc000000UL) /*!< ENDPOINT_TYPE (Bitfield-Mask: 0x03) */
#define USBCTRL_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_STALL_Pos (17UL) /*!< INTERRUPT_ON_STALL (Bit 17) */
#define USBCTRL_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_STALL_Msk (0x20000UL) /*!< INTERRUPT_ON_STALL (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_NAK_Pos (16UL) /*!< INTERRUPT_ON_NAK (Bit 16) */
#define USBCTRL_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_NAK_Msk (0x10000UL) /*!< INTERRUPT_ON_NAK (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP5_IN_CONTROL_BUFFER_ADDRESS_Pos (0UL) /*!< BUFFER_ADDRESS (Bit 0) */
#define USBCTRL_DPRAM_EP5_IN_CONTROL_BUFFER_ADDRESS_Msk (0xffffUL) /*!< BUFFER_ADDRESS (Bitfield-Mask: 0xffff) */
/* ==================================================== EP5_OUT_CONTROL ==================================================== */
#define USBCTRL_DPRAM_EP5_OUT_CONTROL_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */
#define USBCTRL_DPRAM_EP5_OUT_CONTROL_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP5_OUT_CONTROL_DOUBLE_BUFFERED_Pos (30UL) /*!< DOUBLE_BUFFERED (Bit 30) */
#define USBCTRL_DPRAM_EP5_OUT_CONTROL_DOUBLE_BUFFERED_Msk (0x40000000UL) /*!< DOUBLE_BUFFERED (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_BUFF_Pos (29UL) /*!< INTERRUPT_PER_BUFF (Bit 29) */
#define USBCTRL_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_BUFF_Msk (0x20000000UL) /*!< INTERRUPT_PER_BUFF (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Pos (28UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bit 28) */
#define USBCTRL_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Msk (0x10000000UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_Pos (26UL) /*!< ENDPOINT_TYPE (Bit 26) */
#define USBCTRL_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_Msk (0xc000000UL) /*!< ENDPOINT_TYPE (Bitfield-Mask: 0x03) */
#define USBCTRL_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_STALL_Pos (17UL) /*!< INTERRUPT_ON_STALL (Bit 17) */
#define USBCTRL_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_STALL_Msk (0x20000UL) /*!< INTERRUPT_ON_STALL (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_NAK_Pos (16UL) /*!< INTERRUPT_ON_NAK (Bit 16) */
#define USBCTRL_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_NAK_Msk (0x10000UL) /*!< INTERRUPT_ON_NAK (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP5_OUT_CONTROL_BUFFER_ADDRESS_Pos (0UL) /*!< BUFFER_ADDRESS (Bit 0) */
#define USBCTRL_DPRAM_EP5_OUT_CONTROL_BUFFER_ADDRESS_Msk (0xffffUL) /*!< BUFFER_ADDRESS (Bitfield-Mask: 0xffff) */
/* ==================================================== EP6_IN_CONTROL ===================================================== */
#define USBCTRL_DPRAM_EP6_IN_CONTROL_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */
#define USBCTRL_DPRAM_EP6_IN_CONTROL_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP6_IN_CONTROL_DOUBLE_BUFFERED_Pos (30UL) /*!< DOUBLE_BUFFERED (Bit 30) */
#define USBCTRL_DPRAM_EP6_IN_CONTROL_DOUBLE_BUFFERED_Msk (0x40000000UL) /*!< DOUBLE_BUFFERED (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_BUFF_Pos (29UL) /*!< INTERRUPT_PER_BUFF (Bit 29) */
#define USBCTRL_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_BUFF_Msk (0x20000000UL) /*!< INTERRUPT_PER_BUFF (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Pos (28UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bit 28) */
#define USBCTRL_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Msk (0x10000000UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_Pos (26UL) /*!< ENDPOINT_TYPE (Bit 26) */
#define USBCTRL_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_Msk (0xc000000UL) /*!< ENDPOINT_TYPE (Bitfield-Mask: 0x03) */
#define USBCTRL_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_STALL_Pos (17UL) /*!< INTERRUPT_ON_STALL (Bit 17) */
#define USBCTRL_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_STALL_Msk (0x20000UL) /*!< INTERRUPT_ON_STALL (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_NAK_Pos (16UL) /*!< INTERRUPT_ON_NAK (Bit 16) */
#define USBCTRL_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_NAK_Msk (0x10000UL) /*!< INTERRUPT_ON_NAK (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP6_IN_CONTROL_BUFFER_ADDRESS_Pos (0UL) /*!< BUFFER_ADDRESS (Bit 0) */
#define USBCTRL_DPRAM_EP6_IN_CONTROL_BUFFER_ADDRESS_Msk (0xffffUL) /*!< BUFFER_ADDRESS (Bitfield-Mask: 0xffff) */
/* ==================================================== EP6_OUT_CONTROL ==================================================== */
#define USBCTRL_DPRAM_EP6_OUT_CONTROL_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */
#define USBCTRL_DPRAM_EP6_OUT_CONTROL_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP6_OUT_CONTROL_DOUBLE_BUFFERED_Pos (30UL) /*!< DOUBLE_BUFFERED (Bit 30) */
#define USBCTRL_DPRAM_EP6_OUT_CONTROL_DOUBLE_BUFFERED_Msk (0x40000000UL) /*!< DOUBLE_BUFFERED (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_BUFF_Pos (29UL) /*!< INTERRUPT_PER_BUFF (Bit 29) */
#define USBCTRL_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_BUFF_Msk (0x20000000UL) /*!< INTERRUPT_PER_BUFF (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Pos (28UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bit 28) */
#define USBCTRL_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Msk (0x10000000UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_Pos (26UL) /*!< ENDPOINT_TYPE (Bit 26) */
#define USBCTRL_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_Msk (0xc000000UL) /*!< ENDPOINT_TYPE (Bitfield-Mask: 0x03) */
#define USBCTRL_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_STALL_Pos (17UL) /*!< INTERRUPT_ON_STALL (Bit 17) */
#define USBCTRL_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_STALL_Msk (0x20000UL) /*!< INTERRUPT_ON_STALL (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_NAK_Pos (16UL) /*!< INTERRUPT_ON_NAK (Bit 16) */
#define USBCTRL_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_NAK_Msk (0x10000UL) /*!< INTERRUPT_ON_NAK (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP6_OUT_CONTROL_BUFFER_ADDRESS_Pos (0UL) /*!< BUFFER_ADDRESS (Bit 0) */
#define USBCTRL_DPRAM_EP6_OUT_CONTROL_BUFFER_ADDRESS_Msk (0xffffUL) /*!< BUFFER_ADDRESS (Bitfield-Mask: 0xffff) */
/* ==================================================== EP7_IN_CONTROL ===================================================== */
#define USBCTRL_DPRAM_EP7_IN_CONTROL_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */
#define USBCTRL_DPRAM_EP7_IN_CONTROL_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP7_IN_CONTROL_DOUBLE_BUFFERED_Pos (30UL) /*!< DOUBLE_BUFFERED (Bit 30) */
#define USBCTRL_DPRAM_EP7_IN_CONTROL_DOUBLE_BUFFERED_Msk (0x40000000UL) /*!< DOUBLE_BUFFERED (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_BUFF_Pos (29UL) /*!< INTERRUPT_PER_BUFF (Bit 29) */
#define USBCTRL_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_BUFF_Msk (0x20000000UL) /*!< INTERRUPT_PER_BUFF (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Pos (28UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bit 28) */
#define USBCTRL_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Msk (0x10000000UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_Pos (26UL) /*!< ENDPOINT_TYPE (Bit 26) */
#define USBCTRL_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_Msk (0xc000000UL) /*!< ENDPOINT_TYPE (Bitfield-Mask: 0x03) */
#define USBCTRL_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_STALL_Pos (17UL) /*!< INTERRUPT_ON_STALL (Bit 17) */
#define USBCTRL_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_STALL_Msk (0x20000UL) /*!< INTERRUPT_ON_STALL (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_NAK_Pos (16UL) /*!< INTERRUPT_ON_NAK (Bit 16) */
#define USBCTRL_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_NAK_Msk (0x10000UL) /*!< INTERRUPT_ON_NAK (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP7_IN_CONTROL_BUFFER_ADDRESS_Pos (0UL) /*!< BUFFER_ADDRESS (Bit 0) */
#define USBCTRL_DPRAM_EP7_IN_CONTROL_BUFFER_ADDRESS_Msk (0xffffUL) /*!< BUFFER_ADDRESS (Bitfield-Mask: 0xffff) */
/* ==================================================== EP7_OUT_CONTROL ==================================================== */
#define USBCTRL_DPRAM_EP7_OUT_CONTROL_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */
#define USBCTRL_DPRAM_EP7_OUT_CONTROL_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP7_OUT_CONTROL_DOUBLE_BUFFERED_Pos (30UL) /*!< DOUBLE_BUFFERED (Bit 30) */
#define USBCTRL_DPRAM_EP7_OUT_CONTROL_DOUBLE_BUFFERED_Msk (0x40000000UL) /*!< DOUBLE_BUFFERED (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_BUFF_Pos (29UL) /*!< INTERRUPT_PER_BUFF (Bit 29) */
#define USBCTRL_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_BUFF_Msk (0x20000000UL) /*!< INTERRUPT_PER_BUFF (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Pos (28UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bit 28) */
#define USBCTRL_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Msk (0x10000000UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_Pos (26UL) /*!< ENDPOINT_TYPE (Bit 26) */
#define USBCTRL_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_Msk (0xc000000UL) /*!< ENDPOINT_TYPE (Bitfield-Mask: 0x03) */
#define USBCTRL_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_STALL_Pos (17UL) /*!< INTERRUPT_ON_STALL (Bit 17) */
#define USBCTRL_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_STALL_Msk (0x20000UL) /*!< INTERRUPT_ON_STALL (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_NAK_Pos (16UL) /*!< INTERRUPT_ON_NAK (Bit 16) */
#define USBCTRL_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_NAK_Msk (0x10000UL) /*!< INTERRUPT_ON_NAK (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP7_OUT_CONTROL_BUFFER_ADDRESS_Pos (0UL) /*!< BUFFER_ADDRESS (Bit 0) */
#define USBCTRL_DPRAM_EP7_OUT_CONTROL_BUFFER_ADDRESS_Msk (0xffffUL) /*!< BUFFER_ADDRESS (Bitfield-Mask: 0xffff) */
/* ==================================================== EP8_IN_CONTROL ===================================================== */
#define USBCTRL_DPRAM_EP8_IN_CONTROL_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */
#define USBCTRL_DPRAM_EP8_IN_CONTROL_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP8_IN_CONTROL_DOUBLE_BUFFERED_Pos (30UL) /*!< DOUBLE_BUFFERED (Bit 30) */
#define USBCTRL_DPRAM_EP8_IN_CONTROL_DOUBLE_BUFFERED_Msk (0x40000000UL) /*!< DOUBLE_BUFFERED (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_BUFF_Pos (29UL) /*!< INTERRUPT_PER_BUFF (Bit 29) */
#define USBCTRL_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_BUFF_Msk (0x20000000UL) /*!< INTERRUPT_PER_BUFF (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Pos (28UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bit 28) */
#define USBCTRL_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Msk (0x10000000UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_Pos (26UL) /*!< ENDPOINT_TYPE (Bit 26) */
#define USBCTRL_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_Msk (0xc000000UL) /*!< ENDPOINT_TYPE (Bitfield-Mask: 0x03) */
#define USBCTRL_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_STALL_Pos (17UL) /*!< INTERRUPT_ON_STALL (Bit 17) */
#define USBCTRL_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_STALL_Msk (0x20000UL) /*!< INTERRUPT_ON_STALL (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_NAK_Pos (16UL) /*!< INTERRUPT_ON_NAK (Bit 16) */
#define USBCTRL_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_NAK_Msk (0x10000UL) /*!< INTERRUPT_ON_NAK (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP8_IN_CONTROL_BUFFER_ADDRESS_Pos (0UL) /*!< BUFFER_ADDRESS (Bit 0) */
#define USBCTRL_DPRAM_EP8_IN_CONTROL_BUFFER_ADDRESS_Msk (0xffffUL) /*!< BUFFER_ADDRESS (Bitfield-Mask: 0xffff) */
/* ==================================================== EP8_OUT_CONTROL ==================================================== */
#define USBCTRL_DPRAM_EP8_OUT_CONTROL_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */
#define USBCTRL_DPRAM_EP8_OUT_CONTROL_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP8_OUT_CONTROL_DOUBLE_BUFFERED_Pos (30UL) /*!< DOUBLE_BUFFERED (Bit 30) */
#define USBCTRL_DPRAM_EP8_OUT_CONTROL_DOUBLE_BUFFERED_Msk (0x40000000UL) /*!< DOUBLE_BUFFERED (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_BUFF_Pos (29UL) /*!< INTERRUPT_PER_BUFF (Bit 29) */
#define USBCTRL_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_BUFF_Msk (0x20000000UL) /*!< INTERRUPT_PER_BUFF (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Pos (28UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bit 28) */
#define USBCTRL_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Msk (0x10000000UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_Pos (26UL) /*!< ENDPOINT_TYPE (Bit 26) */
#define USBCTRL_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_Msk (0xc000000UL) /*!< ENDPOINT_TYPE (Bitfield-Mask: 0x03) */
#define USBCTRL_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_STALL_Pos (17UL) /*!< INTERRUPT_ON_STALL (Bit 17) */
#define USBCTRL_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_STALL_Msk (0x20000UL) /*!< INTERRUPT_ON_STALL (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_NAK_Pos (16UL) /*!< INTERRUPT_ON_NAK (Bit 16) */
#define USBCTRL_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_NAK_Msk (0x10000UL) /*!< INTERRUPT_ON_NAK (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP8_OUT_CONTROL_BUFFER_ADDRESS_Pos (0UL) /*!< BUFFER_ADDRESS (Bit 0) */
#define USBCTRL_DPRAM_EP8_OUT_CONTROL_BUFFER_ADDRESS_Msk (0xffffUL) /*!< BUFFER_ADDRESS (Bitfield-Mask: 0xffff) */
/* ==================================================== EP9_IN_CONTROL ===================================================== */
#define USBCTRL_DPRAM_EP9_IN_CONTROL_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */
#define USBCTRL_DPRAM_EP9_IN_CONTROL_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP9_IN_CONTROL_DOUBLE_BUFFERED_Pos (30UL) /*!< DOUBLE_BUFFERED (Bit 30) */
#define USBCTRL_DPRAM_EP9_IN_CONTROL_DOUBLE_BUFFERED_Msk (0x40000000UL) /*!< DOUBLE_BUFFERED (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_BUFF_Pos (29UL) /*!< INTERRUPT_PER_BUFF (Bit 29) */
#define USBCTRL_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_BUFF_Msk (0x20000000UL) /*!< INTERRUPT_PER_BUFF (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Pos (28UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bit 28) */
#define USBCTRL_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Msk (0x10000000UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_Pos (26UL) /*!< ENDPOINT_TYPE (Bit 26) */
#define USBCTRL_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_Msk (0xc000000UL) /*!< ENDPOINT_TYPE (Bitfield-Mask: 0x03) */
#define USBCTRL_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_STALL_Pos (17UL) /*!< INTERRUPT_ON_STALL (Bit 17) */
#define USBCTRL_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_STALL_Msk (0x20000UL) /*!< INTERRUPT_ON_STALL (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_NAK_Pos (16UL) /*!< INTERRUPT_ON_NAK (Bit 16) */
#define USBCTRL_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_NAK_Msk (0x10000UL) /*!< INTERRUPT_ON_NAK (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP9_IN_CONTROL_BUFFER_ADDRESS_Pos (0UL) /*!< BUFFER_ADDRESS (Bit 0) */
#define USBCTRL_DPRAM_EP9_IN_CONTROL_BUFFER_ADDRESS_Msk (0xffffUL) /*!< BUFFER_ADDRESS (Bitfield-Mask: 0xffff) */
/* ==================================================== EP9_OUT_CONTROL ==================================================== */
#define USBCTRL_DPRAM_EP9_OUT_CONTROL_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */
#define USBCTRL_DPRAM_EP9_OUT_CONTROL_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP9_OUT_CONTROL_DOUBLE_BUFFERED_Pos (30UL) /*!< DOUBLE_BUFFERED (Bit 30) */
#define USBCTRL_DPRAM_EP9_OUT_CONTROL_DOUBLE_BUFFERED_Msk (0x40000000UL) /*!< DOUBLE_BUFFERED (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_BUFF_Pos (29UL) /*!< INTERRUPT_PER_BUFF (Bit 29) */
#define USBCTRL_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_BUFF_Msk (0x20000000UL) /*!< INTERRUPT_PER_BUFF (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Pos (28UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bit 28) */
#define USBCTRL_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Msk (0x10000000UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_Pos (26UL) /*!< ENDPOINT_TYPE (Bit 26) */
#define USBCTRL_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_Msk (0xc000000UL) /*!< ENDPOINT_TYPE (Bitfield-Mask: 0x03) */
#define USBCTRL_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_STALL_Pos (17UL) /*!< INTERRUPT_ON_STALL (Bit 17) */
#define USBCTRL_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_STALL_Msk (0x20000UL) /*!< INTERRUPT_ON_STALL (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_NAK_Pos (16UL) /*!< INTERRUPT_ON_NAK (Bit 16) */
#define USBCTRL_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_NAK_Msk (0x10000UL) /*!< INTERRUPT_ON_NAK (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP9_OUT_CONTROL_BUFFER_ADDRESS_Pos (0UL) /*!< BUFFER_ADDRESS (Bit 0) */
#define USBCTRL_DPRAM_EP9_OUT_CONTROL_BUFFER_ADDRESS_Msk (0xffffUL) /*!< BUFFER_ADDRESS (Bitfield-Mask: 0xffff) */
/* ==================================================== EP10_IN_CONTROL ==================================================== */
#define USBCTRL_DPRAM_EP10_IN_CONTROL_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */
#define USBCTRL_DPRAM_EP10_IN_CONTROL_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP10_IN_CONTROL_DOUBLE_BUFFERED_Pos (30UL) /*!< DOUBLE_BUFFERED (Bit 30) */
#define USBCTRL_DPRAM_EP10_IN_CONTROL_DOUBLE_BUFFERED_Msk (0x40000000UL) /*!< DOUBLE_BUFFERED (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_BUFF_Pos (29UL) /*!< INTERRUPT_PER_BUFF (Bit 29) */
#define USBCTRL_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_BUFF_Msk (0x20000000UL) /*!< INTERRUPT_PER_BUFF (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Pos (28UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bit 28) */
#define USBCTRL_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Msk (0x10000000UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_Pos (26UL) /*!< ENDPOINT_TYPE (Bit 26) */
#define USBCTRL_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_Msk (0xc000000UL) /*!< ENDPOINT_TYPE (Bitfield-Mask: 0x03) */
#define USBCTRL_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_STALL_Pos (17UL) /*!< INTERRUPT_ON_STALL (Bit 17) */
#define USBCTRL_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_STALL_Msk (0x20000UL) /*!< INTERRUPT_ON_STALL (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_NAK_Pos (16UL) /*!< INTERRUPT_ON_NAK (Bit 16) */
#define USBCTRL_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_NAK_Msk (0x10000UL) /*!< INTERRUPT_ON_NAK (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP10_IN_CONTROL_BUFFER_ADDRESS_Pos (0UL) /*!< BUFFER_ADDRESS (Bit 0) */
#define USBCTRL_DPRAM_EP10_IN_CONTROL_BUFFER_ADDRESS_Msk (0xffffUL) /*!< BUFFER_ADDRESS (Bitfield-Mask: 0xffff) */
/* =================================================== EP10_OUT_CONTROL ==================================================== */
#define USBCTRL_DPRAM_EP10_OUT_CONTROL_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */
#define USBCTRL_DPRAM_EP10_OUT_CONTROL_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP10_OUT_CONTROL_DOUBLE_BUFFERED_Pos (30UL) /*!< DOUBLE_BUFFERED (Bit 30) */
#define USBCTRL_DPRAM_EP10_OUT_CONTROL_DOUBLE_BUFFERED_Msk (0x40000000UL) /*!< DOUBLE_BUFFERED (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_BUFF_Pos (29UL) /*!< INTERRUPT_PER_BUFF (Bit 29) */
#define USBCTRL_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_BUFF_Msk (0x20000000UL) /*!< INTERRUPT_PER_BUFF (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Pos (28UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bit 28) */
#define USBCTRL_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Msk (0x10000000UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_Pos (26UL) /*!< ENDPOINT_TYPE (Bit 26) */
#define USBCTRL_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_Msk (0xc000000UL) /*!< ENDPOINT_TYPE (Bitfield-Mask: 0x03) */
#define USBCTRL_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_STALL_Pos (17UL) /*!< INTERRUPT_ON_STALL (Bit 17) */
#define USBCTRL_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_STALL_Msk (0x20000UL) /*!< INTERRUPT_ON_STALL (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_NAK_Pos (16UL) /*!< INTERRUPT_ON_NAK (Bit 16) */
#define USBCTRL_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_NAK_Msk (0x10000UL) /*!< INTERRUPT_ON_NAK (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP10_OUT_CONTROL_BUFFER_ADDRESS_Pos (0UL) /*!< BUFFER_ADDRESS (Bit 0) */
#define USBCTRL_DPRAM_EP10_OUT_CONTROL_BUFFER_ADDRESS_Msk (0xffffUL) /*!< BUFFER_ADDRESS (Bitfield-Mask: 0xffff) */
/* ==================================================== EP11_IN_CONTROL ==================================================== */
#define USBCTRL_DPRAM_EP11_IN_CONTROL_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */
#define USBCTRL_DPRAM_EP11_IN_CONTROL_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP11_IN_CONTROL_DOUBLE_BUFFERED_Pos (30UL) /*!< DOUBLE_BUFFERED (Bit 30) */
#define USBCTRL_DPRAM_EP11_IN_CONTROL_DOUBLE_BUFFERED_Msk (0x40000000UL) /*!< DOUBLE_BUFFERED (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_BUFF_Pos (29UL) /*!< INTERRUPT_PER_BUFF (Bit 29) */
#define USBCTRL_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_BUFF_Msk (0x20000000UL) /*!< INTERRUPT_PER_BUFF (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Pos (28UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bit 28) */
#define USBCTRL_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Msk (0x10000000UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_Pos (26UL) /*!< ENDPOINT_TYPE (Bit 26) */
#define USBCTRL_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_Msk (0xc000000UL) /*!< ENDPOINT_TYPE (Bitfield-Mask: 0x03) */
#define USBCTRL_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_STALL_Pos (17UL) /*!< INTERRUPT_ON_STALL (Bit 17) */
#define USBCTRL_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_STALL_Msk (0x20000UL) /*!< INTERRUPT_ON_STALL (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_NAK_Pos (16UL) /*!< INTERRUPT_ON_NAK (Bit 16) */
#define USBCTRL_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_NAK_Msk (0x10000UL) /*!< INTERRUPT_ON_NAK (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP11_IN_CONTROL_BUFFER_ADDRESS_Pos (0UL) /*!< BUFFER_ADDRESS (Bit 0) */
#define USBCTRL_DPRAM_EP11_IN_CONTROL_BUFFER_ADDRESS_Msk (0xffffUL) /*!< BUFFER_ADDRESS (Bitfield-Mask: 0xffff) */
/* =================================================== EP11_OUT_CONTROL ==================================================== */
#define USBCTRL_DPRAM_EP11_OUT_CONTROL_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */
#define USBCTRL_DPRAM_EP11_OUT_CONTROL_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP11_OUT_CONTROL_DOUBLE_BUFFERED_Pos (30UL) /*!< DOUBLE_BUFFERED (Bit 30) */
#define USBCTRL_DPRAM_EP11_OUT_CONTROL_DOUBLE_BUFFERED_Msk (0x40000000UL) /*!< DOUBLE_BUFFERED (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_BUFF_Pos (29UL) /*!< INTERRUPT_PER_BUFF (Bit 29) */
#define USBCTRL_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_BUFF_Msk (0x20000000UL) /*!< INTERRUPT_PER_BUFF (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Pos (28UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bit 28) */
#define USBCTRL_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Msk (0x10000000UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_Pos (26UL) /*!< ENDPOINT_TYPE (Bit 26) */
#define USBCTRL_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_Msk (0xc000000UL) /*!< ENDPOINT_TYPE (Bitfield-Mask: 0x03) */
#define USBCTRL_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_STALL_Pos (17UL) /*!< INTERRUPT_ON_STALL (Bit 17) */
#define USBCTRL_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_STALL_Msk (0x20000UL) /*!< INTERRUPT_ON_STALL (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_NAK_Pos (16UL) /*!< INTERRUPT_ON_NAK (Bit 16) */
#define USBCTRL_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_NAK_Msk (0x10000UL) /*!< INTERRUPT_ON_NAK (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP11_OUT_CONTROL_BUFFER_ADDRESS_Pos (0UL) /*!< BUFFER_ADDRESS (Bit 0) */
#define USBCTRL_DPRAM_EP11_OUT_CONTROL_BUFFER_ADDRESS_Msk (0xffffUL) /*!< BUFFER_ADDRESS (Bitfield-Mask: 0xffff) */
/* ==================================================== EP12_IN_CONTROL ==================================================== */
#define USBCTRL_DPRAM_EP12_IN_CONTROL_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */
#define USBCTRL_DPRAM_EP12_IN_CONTROL_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP12_IN_CONTROL_DOUBLE_BUFFERED_Pos (30UL) /*!< DOUBLE_BUFFERED (Bit 30) */
#define USBCTRL_DPRAM_EP12_IN_CONTROL_DOUBLE_BUFFERED_Msk (0x40000000UL) /*!< DOUBLE_BUFFERED (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_BUFF_Pos (29UL) /*!< INTERRUPT_PER_BUFF (Bit 29) */
#define USBCTRL_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_BUFF_Msk (0x20000000UL) /*!< INTERRUPT_PER_BUFF (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Pos (28UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bit 28) */
#define USBCTRL_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Msk (0x10000000UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_Pos (26UL) /*!< ENDPOINT_TYPE (Bit 26) */
#define USBCTRL_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_Msk (0xc000000UL) /*!< ENDPOINT_TYPE (Bitfield-Mask: 0x03) */
#define USBCTRL_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_STALL_Pos (17UL) /*!< INTERRUPT_ON_STALL (Bit 17) */
#define USBCTRL_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_STALL_Msk (0x20000UL) /*!< INTERRUPT_ON_STALL (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_NAK_Pos (16UL) /*!< INTERRUPT_ON_NAK (Bit 16) */
#define USBCTRL_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_NAK_Msk (0x10000UL) /*!< INTERRUPT_ON_NAK (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP12_IN_CONTROL_BUFFER_ADDRESS_Pos (0UL) /*!< BUFFER_ADDRESS (Bit 0) */
#define USBCTRL_DPRAM_EP12_IN_CONTROL_BUFFER_ADDRESS_Msk (0xffffUL) /*!< BUFFER_ADDRESS (Bitfield-Mask: 0xffff) */
/* =================================================== EP12_OUT_CONTROL ==================================================== */
#define USBCTRL_DPRAM_EP12_OUT_CONTROL_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */
#define USBCTRL_DPRAM_EP12_OUT_CONTROL_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP12_OUT_CONTROL_DOUBLE_BUFFERED_Pos (30UL) /*!< DOUBLE_BUFFERED (Bit 30) */
#define USBCTRL_DPRAM_EP12_OUT_CONTROL_DOUBLE_BUFFERED_Msk (0x40000000UL) /*!< DOUBLE_BUFFERED (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_BUFF_Pos (29UL) /*!< INTERRUPT_PER_BUFF (Bit 29) */
#define USBCTRL_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_BUFF_Msk (0x20000000UL) /*!< INTERRUPT_PER_BUFF (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Pos (28UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bit 28) */
#define USBCTRL_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Msk (0x10000000UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_Pos (26UL) /*!< ENDPOINT_TYPE (Bit 26) */
#define USBCTRL_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_Msk (0xc000000UL) /*!< ENDPOINT_TYPE (Bitfield-Mask: 0x03) */
#define USBCTRL_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_STALL_Pos (17UL) /*!< INTERRUPT_ON_STALL (Bit 17) */
#define USBCTRL_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_STALL_Msk (0x20000UL) /*!< INTERRUPT_ON_STALL (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_NAK_Pos (16UL) /*!< INTERRUPT_ON_NAK (Bit 16) */
#define USBCTRL_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_NAK_Msk (0x10000UL) /*!< INTERRUPT_ON_NAK (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP12_OUT_CONTROL_BUFFER_ADDRESS_Pos (0UL) /*!< BUFFER_ADDRESS (Bit 0) */
#define USBCTRL_DPRAM_EP12_OUT_CONTROL_BUFFER_ADDRESS_Msk (0xffffUL) /*!< BUFFER_ADDRESS (Bitfield-Mask: 0xffff) */
/* ==================================================== EP13_IN_CONTROL ==================================================== */
#define USBCTRL_DPRAM_EP13_IN_CONTROL_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */
#define USBCTRL_DPRAM_EP13_IN_CONTROL_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP13_IN_CONTROL_DOUBLE_BUFFERED_Pos (30UL) /*!< DOUBLE_BUFFERED (Bit 30) */
#define USBCTRL_DPRAM_EP13_IN_CONTROL_DOUBLE_BUFFERED_Msk (0x40000000UL) /*!< DOUBLE_BUFFERED (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_BUFF_Pos (29UL) /*!< INTERRUPT_PER_BUFF (Bit 29) */
#define USBCTRL_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_BUFF_Msk (0x20000000UL) /*!< INTERRUPT_PER_BUFF (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Pos (28UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bit 28) */
#define USBCTRL_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Msk (0x10000000UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_Pos (26UL) /*!< ENDPOINT_TYPE (Bit 26) */
#define USBCTRL_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_Msk (0xc000000UL) /*!< ENDPOINT_TYPE (Bitfield-Mask: 0x03) */
#define USBCTRL_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_STALL_Pos (17UL) /*!< INTERRUPT_ON_STALL (Bit 17) */
#define USBCTRL_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_STALL_Msk (0x20000UL) /*!< INTERRUPT_ON_STALL (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_NAK_Pos (16UL) /*!< INTERRUPT_ON_NAK (Bit 16) */
#define USBCTRL_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_NAK_Msk (0x10000UL) /*!< INTERRUPT_ON_NAK (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP13_IN_CONTROL_BUFFER_ADDRESS_Pos (0UL) /*!< BUFFER_ADDRESS (Bit 0) */
#define USBCTRL_DPRAM_EP13_IN_CONTROL_BUFFER_ADDRESS_Msk (0xffffUL) /*!< BUFFER_ADDRESS (Bitfield-Mask: 0xffff) */
/* =================================================== EP13_OUT_CONTROL ==================================================== */
#define USBCTRL_DPRAM_EP13_OUT_CONTROL_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */
#define USBCTRL_DPRAM_EP13_OUT_CONTROL_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP13_OUT_CONTROL_DOUBLE_BUFFERED_Pos (30UL) /*!< DOUBLE_BUFFERED (Bit 30) */
#define USBCTRL_DPRAM_EP13_OUT_CONTROL_DOUBLE_BUFFERED_Msk (0x40000000UL) /*!< DOUBLE_BUFFERED (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_BUFF_Pos (29UL) /*!< INTERRUPT_PER_BUFF (Bit 29) */
#define USBCTRL_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_BUFF_Msk (0x20000000UL) /*!< INTERRUPT_PER_BUFF (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Pos (28UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bit 28) */
#define USBCTRL_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Msk (0x10000000UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_Pos (26UL) /*!< ENDPOINT_TYPE (Bit 26) */
#define USBCTRL_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_Msk (0xc000000UL) /*!< ENDPOINT_TYPE (Bitfield-Mask: 0x03) */
#define USBCTRL_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_STALL_Pos (17UL) /*!< INTERRUPT_ON_STALL (Bit 17) */
#define USBCTRL_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_STALL_Msk (0x20000UL) /*!< INTERRUPT_ON_STALL (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_NAK_Pos (16UL) /*!< INTERRUPT_ON_NAK (Bit 16) */
#define USBCTRL_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_NAK_Msk (0x10000UL) /*!< INTERRUPT_ON_NAK (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP13_OUT_CONTROL_BUFFER_ADDRESS_Pos (0UL) /*!< BUFFER_ADDRESS (Bit 0) */
#define USBCTRL_DPRAM_EP13_OUT_CONTROL_BUFFER_ADDRESS_Msk (0xffffUL) /*!< BUFFER_ADDRESS (Bitfield-Mask: 0xffff) */
/* ==================================================== EP14_IN_CONTROL ==================================================== */
#define USBCTRL_DPRAM_EP14_IN_CONTROL_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */
#define USBCTRL_DPRAM_EP14_IN_CONTROL_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP14_IN_CONTROL_DOUBLE_BUFFERED_Pos (30UL) /*!< DOUBLE_BUFFERED (Bit 30) */
#define USBCTRL_DPRAM_EP14_IN_CONTROL_DOUBLE_BUFFERED_Msk (0x40000000UL) /*!< DOUBLE_BUFFERED (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_BUFF_Pos (29UL) /*!< INTERRUPT_PER_BUFF (Bit 29) */
#define USBCTRL_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_BUFF_Msk (0x20000000UL) /*!< INTERRUPT_PER_BUFF (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Pos (28UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bit 28) */
#define USBCTRL_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Msk (0x10000000UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_Pos (26UL) /*!< ENDPOINT_TYPE (Bit 26) */
#define USBCTRL_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_Msk (0xc000000UL) /*!< ENDPOINT_TYPE (Bitfield-Mask: 0x03) */
#define USBCTRL_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_STALL_Pos (17UL) /*!< INTERRUPT_ON_STALL (Bit 17) */
#define USBCTRL_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_STALL_Msk (0x20000UL) /*!< INTERRUPT_ON_STALL (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_NAK_Pos (16UL) /*!< INTERRUPT_ON_NAK (Bit 16) */
#define USBCTRL_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_NAK_Msk (0x10000UL) /*!< INTERRUPT_ON_NAK (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP14_IN_CONTROL_BUFFER_ADDRESS_Pos (0UL) /*!< BUFFER_ADDRESS (Bit 0) */
#define USBCTRL_DPRAM_EP14_IN_CONTROL_BUFFER_ADDRESS_Msk (0xffffUL) /*!< BUFFER_ADDRESS (Bitfield-Mask: 0xffff) */
/* =================================================== EP14_OUT_CONTROL ==================================================== */
#define USBCTRL_DPRAM_EP14_OUT_CONTROL_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */
#define USBCTRL_DPRAM_EP14_OUT_CONTROL_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP14_OUT_CONTROL_DOUBLE_BUFFERED_Pos (30UL) /*!< DOUBLE_BUFFERED (Bit 30) */
#define USBCTRL_DPRAM_EP14_OUT_CONTROL_DOUBLE_BUFFERED_Msk (0x40000000UL) /*!< DOUBLE_BUFFERED (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_BUFF_Pos (29UL) /*!< INTERRUPT_PER_BUFF (Bit 29) */
#define USBCTRL_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_BUFF_Msk (0x20000000UL) /*!< INTERRUPT_PER_BUFF (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Pos (28UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bit 28) */
#define USBCTRL_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Msk (0x10000000UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_Pos (26UL) /*!< ENDPOINT_TYPE (Bit 26) */
#define USBCTRL_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_Msk (0xc000000UL) /*!< ENDPOINT_TYPE (Bitfield-Mask: 0x03) */
#define USBCTRL_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_STALL_Pos (17UL) /*!< INTERRUPT_ON_STALL (Bit 17) */
#define USBCTRL_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_STALL_Msk (0x20000UL) /*!< INTERRUPT_ON_STALL (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_NAK_Pos (16UL) /*!< INTERRUPT_ON_NAK (Bit 16) */
#define USBCTRL_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_NAK_Msk (0x10000UL) /*!< INTERRUPT_ON_NAK (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP14_OUT_CONTROL_BUFFER_ADDRESS_Pos (0UL) /*!< BUFFER_ADDRESS (Bit 0) */
#define USBCTRL_DPRAM_EP14_OUT_CONTROL_BUFFER_ADDRESS_Msk (0xffffUL) /*!< BUFFER_ADDRESS (Bitfield-Mask: 0xffff) */
/* ==================================================== EP15_IN_CONTROL ==================================================== */
#define USBCTRL_DPRAM_EP15_IN_CONTROL_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */
#define USBCTRL_DPRAM_EP15_IN_CONTROL_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP15_IN_CONTROL_DOUBLE_BUFFERED_Pos (30UL) /*!< DOUBLE_BUFFERED (Bit 30) */
#define USBCTRL_DPRAM_EP15_IN_CONTROL_DOUBLE_BUFFERED_Msk (0x40000000UL) /*!< DOUBLE_BUFFERED (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_BUFF_Pos (29UL) /*!< INTERRUPT_PER_BUFF (Bit 29) */
#define USBCTRL_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_BUFF_Msk (0x20000000UL) /*!< INTERRUPT_PER_BUFF (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Pos (28UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bit 28) */
#define USBCTRL_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Msk (0x10000000UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_Pos (26UL) /*!< ENDPOINT_TYPE (Bit 26) */
#define USBCTRL_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_Msk (0xc000000UL) /*!< ENDPOINT_TYPE (Bitfield-Mask: 0x03) */
#define USBCTRL_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_STALL_Pos (17UL) /*!< INTERRUPT_ON_STALL (Bit 17) */
#define USBCTRL_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_STALL_Msk (0x20000UL) /*!< INTERRUPT_ON_STALL (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_NAK_Pos (16UL) /*!< INTERRUPT_ON_NAK (Bit 16) */
#define USBCTRL_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_NAK_Msk (0x10000UL) /*!< INTERRUPT_ON_NAK (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP15_IN_CONTROL_BUFFER_ADDRESS_Pos (0UL) /*!< BUFFER_ADDRESS (Bit 0) */
#define USBCTRL_DPRAM_EP15_IN_CONTROL_BUFFER_ADDRESS_Msk (0xffffUL) /*!< BUFFER_ADDRESS (Bitfield-Mask: 0xffff) */
/* =================================================== EP15_OUT_CONTROL ==================================================== */
#define USBCTRL_DPRAM_EP15_OUT_CONTROL_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */
#define USBCTRL_DPRAM_EP15_OUT_CONTROL_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP15_OUT_CONTROL_DOUBLE_BUFFERED_Pos (30UL) /*!< DOUBLE_BUFFERED (Bit 30) */
#define USBCTRL_DPRAM_EP15_OUT_CONTROL_DOUBLE_BUFFERED_Msk (0x40000000UL) /*!< DOUBLE_BUFFERED (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_BUFF_Pos (29UL) /*!< INTERRUPT_PER_BUFF (Bit 29) */
#define USBCTRL_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_BUFF_Msk (0x20000000UL) /*!< INTERRUPT_PER_BUFF (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Pos (28UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bit 28) */
#define USBCTRL_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Msk (0x10000000UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_Pos (26UL) /*!< ENDPOINT_TYPE (Bit 26) */
#define USBCTRL_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_Msk (0xc000000UL) /*!< ENDPOINT_TYPE (Bitfield-Mask: 0x03) */
#define USBCTRL_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_STALL_Pos (17UL) /*!< INTERRUPT_ON_STALL (Bit 17) */
#define USBCTRL_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_STALL_Msk (0x20000UL) /*!< INTERRUPT_ON_STALL (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_NAK_Pos (16UL) /*!< INTERRUPT_ON_NAK (Bit 16) */
#define USBCTRL_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_NAK_Msk (0x10000UL) /*!< INTERRUPT_ON_NAK (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP15_OUT_CONTROL_BUFFER_ADDRESS_Pos (0UL) /*!< BUFFER_ADDRESS (Bit 0) */
#define USBCTRL_DPRAM_EP15_OUT_CONTROL_BUFFER_ADDRESS_Msk (0xffffUL) /*!< BUFFER_ADDRESS (Bitfield-Mask: 0xffff) */
/* ================================================= EP0_IN_BUFFER_CONTROL ================================================= */
#define USBCTRL_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */
#define USBCTRL_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */
#define USBCTRL_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP0_IN_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */
#define USBCTRL_DPRAM_EP0_IN_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */
#define USBCTRL_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */
#define USBCTRL_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */
#define USBCTRL_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */
#define USBCTRL_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */
#define USBCTRL_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */
#define USBCTRL_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */
#define USBCTRL_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP0_IN_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */
#define USBCTRL_DPRAM_EP0_IN_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP0_IN_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */
#define USBCTRL_DPRAM_EP0_IN_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP0_IN_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */
#define USBCTRL_DPRAM_EP0_IN_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */
#define USBCTRL_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */
#define USBCTRL_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */
/* ================================================ EP0_OUT_BUFFER_CONTROL ================================================= */
#define USBCTRL_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */
#define USBCTRL_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */
#define USBCTRL_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */
#define USBCTRL_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */
#define USBCTRL_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */
#define USBCTRL_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */
#define USBCTRL_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */
#define USBCTRL_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */
#define USBCTRL_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */
#define USBCTRL_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */
#define USBCTRL_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */
#define USBCTRL_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP0_OUT_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */
#define USBCTRL_DPRAM_EP0_OUT_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP0_OUT_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */
#define USBCTRL_DPRAM_EP0_OUT_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */
#define USBCTRL_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */
#define USBCTRL_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */
/* ================================================= EP1_IN_BUFFER_CONTROL ================================================= */
#define USBCTRL_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */
#define USBCTRL_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */
#define USBCTRL_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP1_IN_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */
#define USBCTRL_DPRAM_EP1_IN_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */
#define USBCTRL_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */
#define USBCTRL_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */
#define USBCTRL_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */
#define USBCTRL_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */
#define USBCTRL_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */
#define USBCTRL_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */
#define USBCTRL_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP1_IN_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */
#define USBCTRL_DPRAM_EP1_IN_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP1_IN_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */
#define USBCTRL_DPRAM_EP1_IN_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP1_IN_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */
#define USBCTRL_DPRAM_EP1_IN_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */
#define USBCTRL_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */
#define USBCTRL_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */
/* ================================================ EP1_OUT_BUFFER_CONTROL ================================================= */
#define USBCTRL_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */
#define USBCTRL_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */
#define USBCTRL_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */
#define USBCTRL_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */
#define USBCTRL_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */
#define USBCTRL_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */
#define USBCTRL_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */
#define USBCTRL_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */
#define USBCTRL_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */
#define USBCTRL_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */
#define USBCTRL_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */
#define USBCTRL_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP1_OUT_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */
#define USBCTRL_DPRAM_EP1_OUT_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP1_OUT_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */
#define USBCTRL_DPRAM_EP1_OUT_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */
#define USBCTRL_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */
#define USBCTRL_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */
/* ================================================= EP2_IN_BUFFER_CONTROL ================================================= */
#define USBCTRL_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */
#define USBCTRL_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */
#define USBCTRL_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP2_IN_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */
#define USBCTRL_DPRAM_EP2_IN_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */
#define USBCTRL_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */
#define USBCTRL_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */
#define USBCTRL_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */
#define USBCTRL_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */
#define USBCTRL_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */
#define USBCTRL_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */
#define USBCTRL_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP2_IN_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */
#define USBCTRL_DPRAM_EP2_IN_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP2_IN_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */
#define USBCTRL_DPRAM_EP2_IN_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP2_IN_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */
#define USBCTRL_DPRAM_EP2_IN_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */
#define USBCTRL_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */
#define USBCTRL_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */
/* ================================================ EP2_OUT_BUFFER_CONTROL ================================================= */
#define USBCTRL_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */
#define USBCTRL_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */
#define USBCTRL_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */
#define USBCTRL_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */
#define USBCTRL_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */
#define USBCTRL_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */
#define USBCTRL_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */
#define USBCTRL_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */
#define USBCTRL_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */
#define USBCTRL_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */
#define USBCTRL_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */
#define USBCTRL_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP2_OUT_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */
#define USBCTRL_DPRAM_EP2_OUT_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP2_OUT_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */
#define USBCTRL_DPRAM_EP2_OUT_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */
#define USBCTRL_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */
#define USBCTRL_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */
/* ================================================= EP3_IN_BUFFER_CONTROL ================================================= */
#define USBCTRL_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */
#define USBCTRL_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */
#define USBCTRL_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP3_IN_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */
#define USBCTRL_DPRAM_EP3_IN_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */
#define USBCTRL_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */
#define USBCTRL_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */
#define USBCTRL_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */
#define USBCTRL_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */
#define USBCTRL_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */
#define USBCTRL_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */
#define USBCTRL_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP3_IN_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */
#define USBCTRL_DPRAM_EP3_IN_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP3_IN_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */
#define USBCTRL_DPRAM_EP3_IN_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP3_IN_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */
#define USBCTRL_DPRAM_EP3_IN_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */
#define USBCTRL_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */
#define USBCTRL_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */
/* ================================================ EP3_OUT_BUFFER_CONTROL ================================================= */
#define USBCTRL_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */
#define USBCTRL_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */
#define USBCTRL_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */
#define USBCTRL_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */
#define USBCTRL_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */
#define USBCTRL_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */
#define USBCTRL_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */
#define USBCTRL_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */
#define USBCTRL_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */
#define USBCTRL_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */
#define USBCTRL_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */
#define USBCTRL_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP3_OUT_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */
#define USBCTRL_DPRAM_EP3_OUT_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP3_OUT_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */
#define USBCTRL_DPRAM_EP3_OUT_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */
#define USBCTRL_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */
#define USBCTRL_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */
/* ================================================= EP4_IN_BUFFER_CONTROL ================================================= */
#define USBCTRL_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */
#define USBCTRL_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */
#define USBCTRL_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP4_IN_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */
#define USBCTRL_DPRAM_EP4_IN_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */
#define USBCTRL_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */
#define USBCTRL_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */
#define USBCTRL_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */
#define USBCTRL_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */
#define USBCTRL_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */
#define USBCTRL_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */
#define USBCTRL_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP4_IN_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */
#define USBCTRL_DPRAM_EP4_IN_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP4_IN_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */
#define USBCTRL_DPRAM_EP4_IN_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP4_IN_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */
#define USBCTRL_DPRAM_EP4_IN_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */
#define USBCTRL_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */
#define USBCTRL_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */
/* ================================================ EP4_OUT_BUFFER_CONTROL ================================================= */
#define USBCTRL_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */
#define USBCTRL_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */
#define USBCTRL_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */
#define USBCTRL_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */
#define USBCTRL_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */
#define USBCTRL_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */
#define USBCTRL_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */
#define USBCTRL_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */
#define USBCTRL_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */
#define USBCTRL_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */
#define USBCTRL_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */
#define USBCTRL_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP4_OUT_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */
#define USBCTRL_DPRAM_EP4_OUT_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP4_OUT_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */
#define USBCTRL_DPRAM_EP4_OUT_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */
#define USBCTRL_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */
#define USBCTRL_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */
/* ================================================= EP5_IN_BUFFER_CONTROL ================================================= */
#define USBCTRL_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */
#define USBCTRL_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */
#define USBCTRL_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP5_IN_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */
#define USBCTRL_DPRAM_EP5_IN_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */
#define USBCTRL_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */
#define USBCTRL_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */
#define USBCTRL_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */
#define USBCTRL_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */
#define USBCTRL_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */
#define USBCTRL_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */
#define USBCTRL_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP5_IN_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */
#define USBCTRL_DPRAM_EP5_IN_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP5_IN_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */
#define USBCTRL_DPRAM_EP5_IN_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP5_IN_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */
#define USBCTRL_DPRAM_EP5_IN_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */
#define USBCTRL_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */
#define USBCTRL_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */
/* ================================================ EP5_OUT_BUFFER_CONTROL ================================================= */
#define USBCTRL_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */
#define USBCTRL_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */
#define USBCTRL_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */
#define USBCTRL_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */
#define USBCTRL_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */
#define USBCTRL_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */
#define USBCTRL_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */
#define USBCTRL_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */
#define USBCTRL_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */
#define USBCTRL_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */
#define USBCTRL_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */
#define USBCTRL_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP5_OUT_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */
#define USBCTRL_DPRAM_EP5_OUT_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP5_OUT_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */
#define USBCTRL_DPRAM_EP5_OUT_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */
#define USBCTRL_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */
#define USBCTRL_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */
/* ================================================= EP6_IN_BUFFER_CONTROL ================================================= */
#define USBCTRL_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */
#define USBCTRL_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */
#define USBCTRL_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP6_IN_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */
#define USBCTRL_DPRAM_EP6_IN_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */
#define USBCTRL_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */
#define USBCTRL_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */
#define USBCTRL_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */
#define USBCTRL_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */
#define USBCTRL_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */
#define USBCTRL_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */
#define USBCTRL_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP6_IN_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */
#define USBCTRL_DPRAM_EP6_IN_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP6_IN_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */
#define USBCTRL_DPRAM_EP6_IN_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP6_IN_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */
#define USBCTRL_DPRAM_EP6_IN_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */
#define USBCTRL_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */
#define USBCTRL_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */
/* ================================================ EP6_OUT_BUFFER_CONTROL ================================================= */
#define USBCTRL_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */
#define USBCTRL_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */
#define USBCTRL_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */
#define USBCTRL_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */
#define USBCTRL_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */
#define USBCTRL_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */
#define USBCTRL_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */
#define USBCTRL_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */
#define USBCTRL_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */
#define USBCTRL_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */
#define USBCTRL_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */
#define USBCTRL_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP6_OUT_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */
#define USBCTRL_DPRAM_EP6_OUT_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP6_OUT_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */
#define USBCTRL_DPRAM_EP6_OUT_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */
#define USBCTRL_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */
#define USBCTRL_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */
/* ================================================= EP7_IN_BUFFER_CONTROL ================================================= */
#define USBCTRL_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */
#define USBCTRL_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */
#define USBCTRL_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP7_IN_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */
#define USBCTRL_DPRAM_EP7_IN_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */
#define USBCTRL_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */
#define USBCTRL_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */
#define USBCTRL_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */
#define USBCTRL_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */
#define USBCTRL_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */
#define USBCTRL_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */
#define USBCTRL_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP7_IN_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */
#define USBCTRL_DPRAM_EP7_IN_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP7_IN_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */
#define USBCTRL_DPRAM_EP7_IN_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP7_IN_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */
#define USBCTRL_DPRAM_EP7_IN_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */
#define USBCTRL_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */
#define USBCTRL_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */
/* ================================================ EP7_OUT_BUFFER_CONTROL ================================================= */
#define USBCTRL_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */
#define USBCTRL_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */
#define USBCTRL_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */
#define USBCTRL_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */
#define USBCTRL_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */
#define USBCTRL_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */
#define USBCTRL_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */
#define USBCTRL_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */
#define USBCTRL_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */
#define USBCTRL_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */
#define USBCTRL_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */
#define USBCTRL_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP7_OUT_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */
#define USBCTRL_DPRAM_EP7_OUT_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP7_OUT_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */
#define USBCTRL_DPRAM_EP7_OUT_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */
#define USBCTRL_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */
#define USBCTRL_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */
/* ================================================= EP8_IN_BUFFER_CONTROL ================================================= */
#define USBCTRL_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */
#define USBCTRL_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */
#define USBCTRL_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP8_IN_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */
#define USBCTRL_DPRAM_EP8_IN_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */
#define USBCTRL_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */
#define USBCTRL_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */
#define USBCTRL_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */
#define USBCTRL_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */
#define USBCTRL_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */
#define USBCTRL_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */
#define USBCTRL_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP8_IN_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */
#define USBCTRL_DPRAM_EP8_IN_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP8_IN_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */
#define USBCTRL_DPRAM_EP8_IN_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP8_IN_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */
#define USBCTRL_DPRAM_EP8_IN_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */
#define USBCTRL_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */
#define USBCTRL_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */
/* ================================================ EP8_OUT_BUFFER_CONTROL ================================================= */
#define USBCTRL_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */
#define USBCTRL_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */
#define USBCTRL_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */
#define USBCTRL_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */
#define USBCTRL_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */
#define USBCTRL_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */
#define USBCTRL_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */
#define USBCTRL_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */
#define USBCTRL_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */
#define USBCTRL_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */
#define USBCTRL_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */
#define USBCTRL_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP8_OUT_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */
#define USBCTRL_DPRAM_EP8_OUT_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP8_OUT_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */
#define USBCTRL_DPRAM_EP8_OUT_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */
#define USBCTRL_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */
#define USBCTRL_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */
/* ================================================= EP9_IN_BUFFER_CONTROL ================================================= */
#define USBCTRL_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */
#define USBCTRL_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */
#define USBCTRL_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP9_IN_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */
#define USBCTRL_DPRAM_EP9_IN_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */
#define USBCTRL_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */
#define USBCTRL_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */
#define USBCTRL_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */
#define USBCTRL_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */
#define USBCTRL_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */
#define USBCTRL_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */
#define USBCTRL_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP9_IN_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */
#define USBCTRL_DPRAM_EP9_IN_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP9_IN_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */
#define USBCTRL_DPRAM_EP9_IN_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP9_IN_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */
#define USBCTRL_DPRAM_EP9_IN_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */
#define USBCTRL_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */
#define USBCTRL_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */
/* ================================================ EP9_OUT_BUFFER_CONTROL ================================================= */
#define USBCTRL_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */
#define USBCTRL_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */
#define USBCTRL_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */
#define USBCTRL_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */
#define USBCTRL_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */
#define USBCTRL_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */
#define USBCTRL_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */
#define USBCTRL_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */
#define USBCTRL_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */
#define USBCTRL_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */
#define USBCTRL_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */
#define USBCTRL_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP9_OUT_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */
#define USBCTRL_DPRAM_EP9_OUT_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP9_OUT_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */
#define USBCTRL_DPRAM_EP9_OUT_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */
#define USBCTRL_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */
#define USBCTRL_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */
/* ================================================ EP10_IN_BUFFER_CONTROL ================================================= */
#define USBCTRL_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */
#define USBCTRL_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */
#define USBCTRL_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP10_IN_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */
#define USBCTRL_DPRAM_EP10_IN_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */
#define USBCTRL_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */
#define USBCTRL_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */
#define USBCTRL_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */
#define USBCTRL_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */
#define USBCTRL_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */
#define USBCTRL_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */
#define USBCTRL_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP10_IN_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */
#define USBCTRL_DPRAM_EP10_IN_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP10_IN_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */
#define USBCTRL_DPRAM_EP10_IN_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP10_IN_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */
#define USBCTRL_DPRAM_EP10_IN_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */
#define USBCTRL_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */
#define USBCTRL_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */
/* ================================================ EP10_OUT_BUFFER_CONTROL ================================================ */
#define USBCTRL_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */
#define USBCTRL_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */
#define USBCTRL_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */
#define USBCTRL_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */
#define USBCTRL_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */
#define USBCTRL_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */
#define USBCTRL_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */
#define USBCTRL_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */
#define USBCTRL_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */
#define USBCTRL_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */
#define USBCTRL_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */
#define USBCTRL_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP10_OUT_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */
#define USBCTRL_DPRAM_EP10_OUT_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP10_OUT_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */
#define USBCTRL_DPRAM_EP10_OUT_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */
#define USBCTRL_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */
#define USBCTRL_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */
/* ================================================ EP11_IN_BUFFER_CONTROL ================================================= */
#define USBCTRL_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */
#define USBCTRL_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */
#define USBCTRL_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP11_IN_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */
#define USBCTRL_DPRAM_EP11_IN_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */
#define USBCTRL_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */
#define USBCTRL_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */
#define USBCTRL_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */
#define USBCTRL_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */
#define USBCTRL_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */
#define USBCTRL_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */
#define USBCTRL_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP11_IN_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */
#define USBCTRL_DPRAM_EP11_IN_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP11_IN_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */
#define USBCTRL_DPRAM_EP11_IN_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP11_IN_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */
#define USBCTRL_DPRAM_EP11_IN_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */
#define USBCTRL_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */
#define USBCTRL_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */
/* ================================================ EP11_OUT_BUFFER_CONTROL ================================================ */
#define USBCTRL_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */
#define USBCTRL_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */
#define USBCTRL_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */
#define USBCTRL_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */
#define USBCTRL_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */
#define USBCTRL_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */
#define USBCTRL_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */
#define USBCTRL_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */
#define USBCTRL_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */
#define USBCTRL_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */
#define USBCTRL_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */
#define USBCTRL_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP11_OUT_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */
#define USBCTRL_DPRAM_EP11_OUT_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP11_OUT_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */
#define USBCTRL_DPRAM_EP11_OUT_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */
#define USBCTRL_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */
#define USBCTRL_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */
/* ================================================ EP12_IN_BUFFER_CONTROL ================================================= */
#define USBCTRL_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */
#define USBCTRL_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */
#define USBCTRL_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP12_IN_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */
#define USBCTRL_DPRAM_EP12_IN_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */
#define USBCTRL_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */
#define USBCTRL_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */
#define USBCTRL_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */
#define USBCTRL_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */
#define USBCTRL_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */
#define USBCTRL_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */
#define USBCTRL_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP12_IN_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */
#define USBCTRL_DPRAM_EP12_IN_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP12_IN_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */
#define USBCTRL_DPRAM_EP12_IN_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP12_IN_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */
#define USBCTRL_DPRAM_EP12_IN_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */
#define USBCTRL_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */
#define USBCTRL_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */
/* ================================================ EP12_OUT_BUFFER_CONTROL ================================================ */
#define USBCTRL_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */
#define USBCTRL_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */
#define USBCTRL_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */
#define USBCTRL_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */
#define USBCTRL_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */
#define USBCTRL_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */
#define USBCTRL_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */
#define USBCTRL_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */
#define USBCTRL_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */
#define USBCTRL_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */
#define USBCTRL_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */
#define USBCTRL_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP12_OUT_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */
#define USBCTRL_DPRAM_EP12_OUT_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP12_OUT_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */
#define USBCTRL_DPRAM_EP12_OUT_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */
#define USBCTRL_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */
#define USBCTRL_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */
/* ================================================ EP13_IN_BUFFER_CONTROL ================================================= */
#define USBCTRL_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */
#define USBCTRL_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */
#define USBCTRL_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP13_IN_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */
#define USBCTRL_DPRAM_EP13_IN_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */
#define USBCTRL_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */
#define USBCTRL_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */
#define USBCTRL_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */
#define USBCTRL_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */
#define USBCTRL_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */
#define USBCTRL_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */
#define USBCTRL_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP13_IN_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */
#define USBCTRL_DPRAM_EP13_IN_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP13_IN_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */
#define USBCTRL_DPRAM_EP13_IN_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP13_IN_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */
#define USBCTRL_DPRAM_EP13_IN_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */
#define USBCTRL_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */
#define USBCTRL_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */
/* ================================================ EP13_OUT_BUFFER_CONTROL ================================================ */
#define USBCTRL_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */
#define USBCTRL_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */
#define USBCTRL_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */
#define USBCTRL_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */
#define USBCTRL_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */
#define USBCTRL_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */
#define USBCTRL_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */
#define USBCTRL_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */
#define USBCTRL_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */
#define USBCTRL_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */
#define USBCTRL_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */
#define USBCTRL_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP13_OUT_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */
#define USBCTRL_DPRAM_EP13_OUT_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP13_OUT_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */
#define USBCTRL_DPRAM_EP13_OUT_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */
#define USBCTRL_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */
#define USBCTRL_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */
/* ================================================ EP14_IN_BUFFER_CONTROL ================================================= */
#define USBCTRL_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */
#define USBCTRL_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */
#define USBCTRL_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP14_IN_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */
#define USBCTRL_DPRAM_EP14_IN_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */
#define USBCTRL_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */
#define USBCTRL_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */
#define USBCTRL_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */
#define USBCTRL_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */
#define USBCTRL_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */
#define USBCTRL_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */
#define USBCTRL_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP14_IN_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */
#define USBCTRL_DPRAM_EP14_IN_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP14_IN_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */
#define USBCTRL_DPRAM_EP14_IN_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP14_IN_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */
#define USBCTRL_DPRAM_EP14_IN_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */
#define USBCTRL_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */
#define USBCTRL_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */
/* ================================================ EP14_OUT_BUFFER_CONTROL ================================================ */
#define USBCTRL_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */
#define USBCTRL_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */
#define USBCTRL_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */
#define USBCTRL_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */
#define USBCTRL_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */
#define USBCTRL_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */
#define USBCTRL_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */
#define USBCTRL_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */
#define USBCTRL_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */
#define USBCTRL_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */
#define USBCTRL_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */
#define USBCTRL_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP14_OUT_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */
#define USBCTRL_DPRAM_EP14_OUT_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP14_OUT_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */
#define USBCTRL_DPRAM_EP14_OUT_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */
#define USBCTRL_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */
#define USBCTRL_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */
/* ================================================ EP15_IN_BUFFER_CONTROL ================================================= */
#define USBCTRL_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */
#define USBCTRL_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */
#define USBCTRL_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP15_IN_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */
#define USBCTRL_DPRAM_EP15_IN_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */
#define USBCTRL_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */
#define USBCTRL_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */
#define USBCTRL_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */
#define USBCTRL_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */
#define USBCTRL_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */
#define USBCTRL_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */
#define USBCTRL_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP15_IN_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */
#define USBCTRL_DPRAM_EP15_IN_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP15_IN_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */
#define USBCTRL_DPRAM_EP15_IN_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP15_IN_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */
#define USBCTRL_DPRAM_EP15_IN_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */
#define USBCTRL_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */
#define USBCTRL_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */
/* ================================================ EP15_OUT_BUFFER_CONTROL ================================================ */
#define USBCTRL_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */
#define USBCTRL_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */
#define USBCTRL_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */
#define USBCTRL_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */
#define USBCTRL_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */
#define USBCTRL_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */
#define USBCTRL_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */
#define USBCTRL_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */
#define USBCTRL_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */
#define USBCTRL_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */
#define USBCTRL_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */
#define USBCTRL_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP15_OUT_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */
#define USBCTRL_DPRAM_EP15_OUT_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP15_OUT_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */
#define USBCTRL_DPRAM_EP15_OUT_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */
#define USBCTRL_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */
#define USBCTRL_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */
#define USBCTRL_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */
/* =========================================================================================================================== */
/* ================ USBCTRL_REGS ================ */
/* =========================================================================================================================== */
/* ======================================================= ADDR_ENDP ======================================================= */
#define USBCTRL_REGS_ADDR_ENDP_ENDPOINT_Pos (16UL) /*!< ENDPOINT (Bit 16) */
#define USBCTRL_REGS_ADDR_ENDP_ENDPOINT_Msk (0xf0000UL) /*!< ENDPOINT (Bitfield-Mask: 0x0f) */
#define USBCTRL_REGS_ADDR_ENDP_ADDRESS_Pos (0UL) /*!< ADDRESS (Bit 0) */
#define USBCTRL_REGS_ADDR_ENDP_ADDRESS_Msk (0x7fUL) /*!< ADDRESS (Bitfield-Mask: 0x7f) */
/* ====================================================== ADDR_ENDP1 ======================================================= */
#define USBCTRL_REGS_ADDR_ENDP1_INTEP_PREAMBLE_Pos (26UL) /*!< INTEP_PREAMBLE (Bit 26) */
#define USBCTRL_REGS_ADDR_ENDP1_INTEP_PREAMBLE_Msk (0x4000000UL) /*!< INTEP_PREAMBLE (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_ADDR_ENDP1_INTEP_DIR_Pos (25UL) /*!< INTEP_DIR (Bit 25) */
#define USBCTRL_REGS_ADDR_ENDP1_INTEP_DIR_Msk (0x2000000UL) /*!< INTEP_DIR (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_ADDR_ENDP1_ENDPOINT_Pos (16UL) /*!< ENDPOINT (Bit 16) */
#define USBCTRL_REGS_ADDR_ENDP1_ENDPOINT_Msk (0xf0000UL) /*!< ENDPOINT (Bitfield-Mask: 0x0f) */
#define USBCTRL_REGS_ADDR_ENDP1_ADDRESS_Pos (0UL) /*!< ADDRESS (Bit 0) */
#define USBCTRL_REGS_ADDR_ENDP1_ADDRESS_Msk (0x7fUL) /*!< ADDRESS (Bitfield-Mask: 0x7f) */
/* ====================================================== ADDR_ENDP2 ======================================================= */
#define USBCTRL_REGS_ADDR_ENDP2_INTEP_PREAMBLE_Pos (26UL) /*!< INTEP_PREAMBLE (Bit 26) */
#define USBCTRL_REGS_ADDR_ENDP2_INTEP_PREAMBLE_Msk (0x4000000UL) /*!< INTEP_PREAMBLE (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_ADDR_ENDP2_INTEP_DIR_Pos (25UL) /*!< INTEP_DIR (Bit 25) */
#define USBCTRL_REGS_ADDR_ENDP2_INTEP_DIR_Msk (0x2000000UL) /*!< INTEP_DIR (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_ADDR_ENDP2_ENDPOINT_Pos (16UL) /*!< ENDPOINT (Bit 16) */
#define USBCTRL_REGS_ADDR_ENDP2_ENDPOINT_Msk (0xf0000UL) /*!< ENDPOINT (Bitfield-Mask: 0x0f) */
#define USBCTRL_REGS_ADDR_ENDP2_ADDRESS_Pos (0UL) /*!< ADDRESS (Bit 0) */
#define USBCTRL_REGS_ADDR_ENDP2_ADDRESS_Msk (0x7fUL) /*!< ADDRESS (Bitfield-Mask: 0x7f) */
/* ====================================================== ADDR_ENDP3 ======================================================= */
#define USBCTRL_REGS_ADDR_ENDP3_INTEP_PREAMBLE_Pos (26UL) /*!< INTEP_PREAMBLE (Bit 26) */
#define USBCTRL_REGS_ADDR_ENDP3_INTEP_PREAMBLE_Msk (0x4000000UL) /*!< INTEP_PREAMBLE (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_ADDR_ENDP3_INTEP_DIR_Pos (25UL) /*!< INTEP_DIR (Bit 25) */
#define USBCTRL_REGS_ADDR_ENDP3_INTEP_DIR_Msk (0x2000000UL) /*!< INTEP_DIR (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_ADDR_ENDP3_ENDPOINT_Pos (16UL) /*!< ENDPOINT (Bit 16) */
#define USBCTRL_REGS_ADDR_ENDP3_ENDPOINT_Msk (0xf0000UL) /*!< ENDPOINT (Bitfield-Mask: 0x0f) */
#define USBCTRL_REGS_ADDR_ENDP3_ADDRESS_Pos (0UL) /*!< ADDRESS (Bit 0) */
#define USBCTRL_REGS_ADDR_ENDP3_ADDRESS_Msk (0x7fUL) /*!< ADDRESS (Bitfield-Mask: 0x7f) */
/* ====================================================== ADDR_ENDP4 ======================================================= */
#define USBCTRL_REGS_ADDR_ENDP4_INTEP_PREAMBLE_Pos (26UL) /*!< INTEP_PREAMBLE (Bit 26) */
#define USBCTRL_REGS_ADDR_ENDP4_INTEP_PREAMBLE_Msk (0x4000000UL) /*!< INTEP_PREAMBLE (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_ADDR_ENDP4_INTEP_DIR_Pos (25UL) /*!< INTEP_DIR (Bit 25) */
#define USBCTRL_REGS_ADDR_ENDP4_INTEP_DIR_Msk (0x2000000UL) /*!< INTEP_DIR (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_ADDR_ENDP4_ENDPOINT_Pos (16UL) /*!< ENDPOINT (Bit 16) */
#define USBCTRL_REGS_ADDR_ENDP4_ENDPOINT_Msk (0xf0000UL) /*!< ENDPOINT (Bitfield-Mask: 0x0f) */
#define USBCTRL_REGS_ADDR_ENDP4_ADDRESS_Pos (0UL) /*!< ADDRESS (Bit 0) */
#define USBCTRL_REGS_ADDR_ENDP4_ADDRESS_Msk (0x7fUL) /*!< ADDRESS (Bitfield-Mask: 0x7f) */
/* ====================================================== ADDR_ENDP5 ======================================================= */
#define USBCTRL_REGS_ADDR_ENDP5_INTEP_PREAMBLE_Pos (26UL) /*!< INTEP_PREAMBLE (Bit 26) */
#define USBCTRL_REGS_ADDR_ENDP5_INTEP_PREAMBLE_Msk (0x4000000UL) /*!< INTEP_PREAMBLE (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_ADDR_ENDP5_INTEP_DIR_Pos (25UL) /*!< INTEP_DIR (Bit 25) */
#define USBCTRL_REGS_ADDR_ENDP5_INTEP_DIR_Msk (0x2000000UL) /*!< INTEP_DIR (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_ADDR_ENDP5_ENDPOINT_Pos (16UL) /*!< ENDPOINT (Bit 16) */
#define USBCTRL_REGS_ADDR_ENDP5_ENDPOINT_Msk (0xf0000UL) /*!< ENDPOINT (Bitfield-Mask: 0x0f) */
#define USBCTRL_REGS_ADDR_ENDP5_ADDRESS_Pos (0UL) /*!< ADDRESS (Bit 0) */
#define USBCTRL_REGS_ADDR_ENDP5_ADDRESS_Msk (0x7fUL) /*!< ADDRESS (Bitfield-Mask: 0x7f) */
/* ====================================================== ADDR_ENDP6 ======================================================= */
#define USBCTRL_REGS_ADDR_ENDP6_INTEP_PREAMBLE_Pos (26UL) /*!< INTEP_PREAMBLE (Bit 26) */
#define USBCTRL_REGS_ADDR_ENDP6_INTEP_PREAMBLE_Msk (0x4000000UL) /*!< INTEP_PREAMBLE (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_ADDR_ENDP6_INTEP_DIR_Pos (25UL) /*!< INTEP_DIR (Bit 25) */
#define USBCTRL_REGS_ADDR_ENDP6_INTEP_DIR_Msk (0x2000000UL) /*!< INTEP_DIR (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_ADDR_ENDP6_ENDPOINT_Pos (16UL) /*!< ENDPOINT (Bit 16) */
#define USBCTRL_REGS_ADDR_ENDP6_ENDPOINT_Msk (0xf0000UL) /*!< ENDPOINT (Bitfield-Mask: 0x0f) */
#define USBCTRL_REGS_ADDR_ENDP6_ADDRESS_Pos (0UL) /*!< ADDRESS (Bit 0) */
#define USBCTRL_REGS_ADDR_ENDP6_ADDRESS_Msk (0x7fUL) /*!< ADDRESS (Bitfield-Mask: 0x7f) */
/* ====================================================== ADDR_ENDP7 ======================================================= */
#define USBCTRL_REGS_ADDR_ENDP7_INTEP_PREAMBLE_Pos (26UL) /*!< INTEP_PREAMBLE (Bit 26) */
#define USBCTRL_REGS_ADDR_ENDP7_INTEP_PREAMBLE_Msk (0x4000000UL) /*!< INTEP_PREAMBLE (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_ADDR_ENDP7_INTEP_DIR_Pos (25UL) /*!< INTEP_DIR (Bit 25) */
#define USBCTRL_REGS_ADDR_ENDP7_INTEP_DIR_Msk (0x2000000UL) /*!< INTEP_DIR (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_ADDR_ENDP7_ENDPOINT_Pos (16UL) /*!< ENDPOINT (Bit 16) */
#define USBCTRL_REGS_ADDR_ENDP7_ENDPOINT_Msk (0xf0000UL) /*!< ENDPOINT (Bitfield-Mask: 0x0f) */
#define USBCTRL_REGS_ADDR_ENDP7_ADDRESS_Pos (0UL) /*!< ADDRESS (Bit 0) */
#define USBCTRL_REGS_ADDR_ENDP7_ADDRESS_Msk (0x7fUL) /*!< ADDRESS (Bitfield-Mask: 0x7f) */
/* ====================================================== ADDR_ENDP8 ======================================================= */
#define USBCTRL_REGS_ADDR_ENDP8_INTEP_PREAMBLE_Pos (26UL) /*!< INTEP_PREAMBLE (Bit 26) */
#define USBCTRL_REGS_ADDR_ENDP8_INTEP_PREAMBLE_Msk (0x4000000UL) /*!< INTEP_PREAMBLE (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_ADDR_ENDP8_INTEP_DIR_Pos (25UL) /*!< INTEP_DIR (Bit 25) */
#define USBCTRL_REGS_ADDR_ENDP8_INTEP_DIR_Msk (0x2000000UL) /*!< INTEP_DIR (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_ADDR_ENDP8_ENDPOINT_Pos (16UL) /*!< ENDPOINT (Bit 16) */
#define USBCTRL_REGS_ADDR_ENDP8_ENDPOINT_Msk (0xf0000UL) /*!< ENDPOINT (Bitfield-Mask: 0x0f) */
#define USBCTRL_REGS_ADDR_ENDP8_ADDRESS_Pos (0UL) /*!< ADDRESS (Bit 0) */
#define USBCTRL_REGS_ADDR_ENDP8_ADDRESS_Msk (0x7fUL) /*!< ADDRESS (Bitfield-Mask: 0x7f) */
/* ====================================================== ADDR_ENDP9 ======================================================= */
#define USBCTRL_REGS_ADDR_ENDP9_INTEP_PREAMBLE_Pos (26UL) /*!< INTEP_PREAMBLE (Bit 26) */
#define USBCTRL_REGS_ADDR_ENDP9_INTEP_PREAMBLE_Msk (0x4000000UL) /*!< INTEP_PREAMBLE (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_ADDR_ENDP9_INTEP_DIR_Pos (25UL) /*!< INTEP_DIR (Bit 25) */
#define USBCTRL_REGS_ADDR_ENDP9_INTEP_DIR_Msk (0x2000000UL) /*!< INTEP_DIR (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_ADDR_ENDP9_ENDPOINT_Pos (16UL) /*!< ENDPOINT (Bit 16) */
#define USBCTRL_REGS_ADDR_ENDP9_ENDPOINT_Msk (0xf0000UL) /*!< ENDPOINT (Bitfield-Mask: 0x0f) */
#define USBCTRL_REGS_ADDR_ENDP9_ADDRESS_Pos (0UL) /*!< ADDRESS (Bit 0) */
#define USBCTRL_REGS_ADDR_ENDP9_ADDRESS_Msk (0x7fUL) /*!< ADDRESS (Bitfield-Mask: 0x7f) */
/* ====================================================== ADDR_ENDP10 ====================================================== */
#define USBCTRL_REGS_ADDR_ENDP10_INTEP_PREAMBLE_Pos (26UL) /*!< INTEP_PREAMBLE (Bit 26) */
#define USBCTRL_REGS_ADDR_ENDP10_INTEP_PREAMBLE_Msk (0x4000000UL) /*!< INTEP_PREAMBLE (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_ADDR_ENDP10_INTEP_DIR_Pos (25UL) /*!< INTEP_DIR (Bit 25) */
#define USBCTRL_REGS_ADDR_ENDP10_INTEP_DIR_Msk (0x2000000UL) /*!< INTEP_DIR (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_ADDR_ENDP10_ENDPOINT_Pos (16UL) /*!< ENDPOINT (Bit 16) */
#define USBCTRL_REGS_ADDR_ENDP10_ENDPOINT_Msk (0xf0000UL) /*!< ENDPOINT (Bitfield-Mask: 0x0f) */
#define USBCTRL_REGS_ADDR_ENDP10_ADDRESS_Pos (0UL) /*!< ADDRESS (Bit 0) */
#define USBCTRL_REGS_ADDR_ENDP10_ADDRESS_Msk (0x7fUL) /*!< ADDRESS (Bitfield-Mask: 0x7f) */
/* ====================================================== ADDR_ENDP11 ====================================================== */
#define USBCTRL_REGS_ADDR_ENDP11_INTEP_PREAMBLE_Pos (26UL) /*!< INTEP_PREAMBLE (Bit 26) */
#define USBCTRL_REGS_ADDR_ENDP11_INTEP_PREAMBLE_Msk (0x4000000UL) /*!< INTEP_PREAMBLE (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_ADDR_ENDP11_INTEP_DIR_Pos (25UL) /*!< INTEP_DIR (Bit 25) */
#define USBCTRL_REGS_ADDR_ENDP11_INTEP_DIR_Msk (0x2000000UL) /*!< INTEP_DIR (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_ADDR_ENDP11_ENDPOINT_Pos (16UL) /*!< ENDPOINT (Bit 16) */
#define USBCTRL_REGS_ADDR_ENDP11_ENDPOINT_Msk (0xf0000UL) /*!< ENDPOINT (Bitfield-Mask: 0x0f) */
#define USBCTRL_REGS_ADDR_ENDP11_ADDRESS_Pos (0UL) /*!< ADDRESS (Bit 0) */
#define USBCTRL_REGS_ADDR_ENDP11_ADDRESS_Msk (0x7fUL) /*!< ADDRESS (Bitfield-Mask: 0x7f) */
/* ====================================================== ADDR_ENDP12 ====================================================== */
#define USBCTRL_REGS_ADDR_ENDP12_INTEP_PREAMBLE_Pos (26UL) /*!< INTEP_PREAMBLE (Bit 26) */
#define USBCTRL_REGS_ADDR_ENDP12_INTEP_PREAMBLE_Msk (0x4000000UL) /*!< INTEP_PREAMBLE (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_ADDR_ENDP12_INTEP_DIR_Pos (25UL) /*!< INTEP_DIR (Bit 25) */
#define USBCTRL_REGS_ADDR_ENDP12_INTEP_DIR_Msk (0x2000000UL) /*!< INTEP_DIR (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_ADDR_ENDP12_ENDPOINT_Pos (16UL) /*!< ENDPOINT (Bit 16) */
#define USBCTRL_REGS_ADDR_ENDP12_ENDPOINT_Msk (0xf0000UL) /*!< ENDPOINT (Bitfield-Mask: 0x0f) */
#define USBCTRL_REGS_ADDR_ENDP12_ADDRESS_Pos (0UL) /*!< ADDRESS (Bit 0) */
#define USBCTRL_REGS_ADDR_ENDP12_ADDRESS_Msk (0x7fUL) /*!< ADDRESS (Bitfield-Mask: 0x7f) */
/* ====================================================== ADDR_ENDP13 ====================================================== */
#define USBCTRL_REGS_ADDR_ENDP13_INTEP_PREAMBLE_Pos (26UL) /*!< INTEP_PREAMBLE (Bit 26) */
#define USBCTRL_REGS_ADDR_ENDP13_INTEP_PREAMBLE_Msk (0x4000000UL) /*!< INTEP_PREAMBLE (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_ADDR_ENDP13_INTEP_DIR_Pos (25UL) /*!< INTEP_DIR (Bit 25) */
#define USBCTRL_REGS_ADDR_ENDP13_INTEP_DIR_Msk (0x2000000UL) /*!< INTEP_DIR (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_ADDR_ENDP13_ENDPOINT_Pos (16UL) /*!< ENDPOINT (Bit 16) */
#define USBCTRL_REGS_ADDR_ENDP13_ENDPOINT_Msk (0xf0000UL) /*!< ENDPOINT (Bitfield-Mask: 0x0f) */
#define USBCTRL_REGS_ADDR_ENDP13_ADDRESS_Pos (0UL) /*!< ADDRESS (Bit 0) */
#define USBCTRL_REGS_ADDR_ENDP13_ADDRESS_Msk (0x7fUL) /*!< ADDRESS (Bitfield-Mask: 0x7f) */
/* ====================================================== ADDR_ENDP14 ====================================================== */
#define USBCTRL_REGS_ADDR_ENDP14_INTEP_PREAMBLE_Pos (26UL) /*!< INTEP_PREAMBLE (Bit 26) */
#define USBCTRL_REGS_ADDR_ENDP14_INTEP_PREAMBLE_Msk (0x4000000UL) /*!< INTEP_PREAMBLE (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_ADDR_ENDP14_INTEP_DIR_Pos (25UL) /*!< INTEP_DIR (Bit 25) */
#define USBCTRL_REGS_ADDR_ENDP14_INTEP_DIR_Msk (0x2000000UL) /*!< INTEP_DIR (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_ADDR_ENDP14_ENDPOINT_Pos (16UL) /*!< ENDPOINT (Bit 16) */
#define USBCTRL_REGS_ADDR_ENDP14_ENDPOINT_Msk (0xf0000UL) /*!< ENDPOINT (Bitfield-Mask: 0x0f) */
#define USBCTRL_REGS_ADDR_ENDP14_ADDRESS_Pos (0UL) /*!< ADDRESS (Bit 0) */
#define USBCTRL_REGS_ADDR_ENDP14_ADDRESS_Msk (0x7fUL) /*!< ADDRESS (Bitfield-Mask: 0x7f) */
/* ====================================================== ADDR_ENDP15 ====================================================== */
#define USBCTRL_REGS_ADDR_ENDP15_INTEP_PREAMBLE_Pos (26UL) /*!< INTEP_PREAMBLE (Bit 26) */
#define USBCTRL_REGS_ADDR_ENDP15_INTEP_PREAMBLE_Msk (0x4000000UL) /*!< INTEP_PREAMBLE (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_ADDR_ENDP15_INTEP_DIR_Pos (25UL) /*!< INTEP_DIR (Bit 25) */
#define USBCTRL_REGS_ADDR_ENDP15_INTEP_DIR_Msk (0x2000000UL) /*!< INTEP_DIR (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_ADDR_ENDP15_ENDPOINT_Pos (16UL) /*!< ENDPOINT (Bit 16) */
#define USBCTRL_REGS_ADDR_ENDP15_ENDPOINT_Msk (0xf0000UL) /*!< ENDPOINT (Bitfield-Mask: 0x0f) */
#define USBCTRL_REGS_ADDR_ENDP15_ADDRESS_Pos (0UL) /*!< ADDRESS (Bit 0) */
#define USBCTRL_REGS_ADDR_ENDP15_ADDRESS_Msk (0x7fUL) /*!< ADDRESS (Bitfield-Mask: 0x7f) */
/* ======================================================= MAIN_CTRL ======================================================= */
#define USBCTRL_REGS_MAIN_CTRL_SIM_TIMING_Pos (31UL) /*!< SIM_TIMING (Bit 31) */
#define USBCTRL_REGS_MAIN_CTRL_SIM_TIMING_Msk (0x80000000UL) /*!< SIM_TIMING (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_MAIN_CTRL_HOST_NDEVICE_Pos (1UL) /*!< HOST_NDEVICE (Bit 1) */
#define USBCTRL_REGS_MAIN_CTRL_HOST_NDEVICE_Msk (0x2UL) /*!< HOST_NDEVICE (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_MAIN_CTRL_CONTROLLER_EN_Pos (0UL) /*!< CONTROLLER_EN (Bit 0) */
#define USBCTRL_REGS_MAIN_CTRL_CONTROLLER_EN_Msk (0x1UL) /*!< CONTROLLER_EN (Bitfield-Mask: 0x01) */
/* ======================================================== SOF_WR ========================================================= */
#define USBCTRL_REGS_SOF_WR_COUNT_Pos (0UL) /*!< COUNT (Bit 0) */
#define USBCTRL_REGS_SOF_WR_COUNT_Msk (0x7ffUL) /*!< COUNT (Bitfield-Mask: 0x7ff) */
/* ======================================================== SOF_RD ========================================================= */
#define USBCTRL_REGS_SOF_RD_COUNT_Pos (0UL) /*!< COUNT (Bit 0) */
#define USBCTRL_REGS_SOF_RD_COUNT_Msk (0x7ffUL) /*!< COUNT (Bitfield-Mask: 0x7ff) */
/* ======================================================= SIE_CTRL ======================================================== */
#define USBCTRL_REGS_SIE_CTRL_EP0_INT_STALL_Pos (31UL) /*!< EP0_INT_STALL (Bit 31) */
#define USBCTRL_REGS_SIE_CTRL_EP0_INT_STALL_Msk (0x80000000UL) /*!< EP0_INT_STALL (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_SIE_CTRL_EP0_DOUBLE_BUF_Pos (30UL) /*!< EP0_DOUBLE_BUF (Bit 30) */
#define USBCTRL_REGS_SIE_CTRL_EP0_DOUBLE_BUF_Msk (0x40000000UL) /*!< EP0_DOUBLE_BUF (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_SIE_CTRL_EP0_INT_1BUF_Pos (29UL) /*!< EP0_INT_1BUF (Bit 29) */
#define USBCTRL_REGS_SIE_CTRL_EP0_INT_1BUF_Msk (0x20000000UL) /*!< EP0_INT_1BUF (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_SIE_CTRL_EP0_INT_2BUF_Pos (28UL) /*!< EP0_INT_2BUF (Bit 28) */
#define USBCTRL_REGS_SIE_CTRL_EP0_INT_2BUF_Msk (0x10000000UL) /*!< EP0_INT_2BUF (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_SIE_CTRL_EP0_INT_NAK_Pos (27UL) /*!< EP0_INT_NAK (Bit 27) */
#define USBCTRL_REGS_SIE_CTRL_EP0_INT_NAK_Msk (0x8000000UL) /*!< EP0_INT_NAK (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_SIE_CTRL_DIRECT_EN_Pos (26UL) /*!< DIRECT_EN (Bit 26) */
#define USBCTRL_REGS_SIE_CTRL_DIRECT_EN_Msk (0x4000000UL) /*!< DIRECT_EN (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_SIE_CTRL_DIRECT_DP_Pos (25UL) /*!< DIRECT_DP (Bit 25) */
#define USBCTRL_REGS_SIE_CTRL_DIRECT_DP_Msk (0x2000000UL) /*!< DIRECT_DP (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_SIE_CTRL_DIRECT_DM_Pos (24UL) /*!< DIRECT_DM (Bit 24) */
#define USBCTRL_REGS_SIE_CTRL_DIRECT_DM_Msk (0x1000000UL) /*!< DIRECT_DM (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_SIE_CTRL_TRANSCEIVER_PD_Pos (18UL) /*!< TRANSCEIVER_PD (Bit 18) */
#define USBCTRL_REGS_SIE_CTRL_TRANSCEIVER_PD_Msk (0x40000UL) /*!< TRANSCEIVER_PD (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_SIE_CTRL_RPU_OPT_Pos (17UL) /*!< RPU_OPT (Bit 17) */
#define USBCTRL_REGS_SIE_CTRL_RPU_OPT_Msk (0x20000UL) /*!< RPU_OPT (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_SIE_CTRL_PULLUP_EN_Pos (16UL) /*!< PULLUP_EN (Bit 16) */
#define USBCTRL_REGS_SIE_CTRL_PULLUP_EN_Msk (0x10000UL) /*!< PULLUP_EN (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_SIE_CTRL_PULLDOWN_EN_Pos (15UL) /*!< PULLDOWN_EN (Bit 15) */
#define USBCTRL_REGS_SIE_CTRL_PULLDOWN_EN_Msk (0x8000UL) /*!< PULLDOWN_EN (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_SIE_CTRL_RESET_BUS_Pos (13UL) /*!< RESET_BUS (Bit 13) */
#define USBCTRL_REGS_SIE_CTRL_RESET_BUS_Msk (0x2000UL) /*!< RESET_BUS (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_SIE_CTRL_RESUME_Pos (12UL) /*!< RESUME (Bit 12) */
#define USBCTRL_REGS_SIE_CTRL_RESUME_Msk (0x1000UL) /*!< RESUME (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_SIE_CTRL_VBUS_EN_Pos (11UL) /*!< VBUS_EN (Bit 11) */
#define USBCTRL_REGS_SIE_CTRL_VBUS_EN_Msk (0x800UL) /*!< VBUS_EN (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_SIE_CTRL_KEEP_ALIVE_EN_Pos (10UL) /*!< KEEP_ALIVE_EN (Bit 10) */
#define USBCTRL_REGS_SIE_CTRL_KEEP_ALIVE_EN_Msk (0x400UL) /*!< KEEP_ALIVE_EN (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_SIE_CTRL_SOF_EN_Pos (9UL) /*!< SOF_EN (Bit 9) */
#define USBCTRL_REGS_SIE_CTRL_SOF_EN_Msk (0x200UL) /*!< SOF_EN (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_SIE_CTRL_SOF_SYNC_Pos (8UL) /*!< SOF_SYNC (Bit 8) */
#define USBCTRL_REGS_SIE_CTRL_SOF_SYNC_Msk (0x100UL) /*!< SOF_SYNC (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_SIE_CTRL_PREAMBLE_EN_Pos (6UL) /*!< PREAMBLE_EN (Bit 6) */
#define USBCTRL_REGS_SIE_CTRL_PREAMBLE_EN_Msk (0x40UL) /*!< PREAMBLE_EN (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_SIE_CTRL_STOP_TRANS_Pos (4UL) /*!< STOP_TRANS (Bit 4) */
#define USBCTRL_REGS_SIE_CTRL_STOP_TRANS_Msk (0x10UL) /*!< STOP_TRANS (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_SIE_CTRL_RECEIVE_DATA_Pos (3UL) /*!< RECEIVE_DATA (Bit 3) */
#define USBCTRL_REGS_SIE_CTRL_RECEIVE_DATA_Msk (0x8UL) /*!< RECEIVE_DATA (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_SIE_CTRL_SEND_DATA_Pos (2UL) /*!< SEND_DATA (Bit 2) */
#define USBCTRL_REGS_SIE_CTRL_SEND_DATA_Msk (0x4UL) /*!< SEND_DATA (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_SIE_CTRL_SEND_SETUP_Pos (1UL) /*!< SEND_SETUP (Bit 1) */
#define USBCTRL_REGS_SIE_CTRL_SEND_SETUP_Msk (0x2UL) /*!< SEND_SETUP (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_SIE_CTRL_START_TRANS_Pos (0UL) /*!< START_TRANS (Bit 0) */
#define USBCTRL_REGS_SIE_CTRL_START_TRANS_Msk (0x1UL) /*!< START_TRANS (Bitfield-Mask: 0x01) */
/* ====================================================== SIE_STATUS ======================================================= */
#define USBCTRL_REGS_SIE_STATUS_DATA_SEQ_ERROR_Pos (31UL) /*!< DATA_SEQ_ERROR (Bit 31) */
#define USBCTRL_REGS_SIE_STATUS_DATA_SEQ_ERROR_Msk (0x80000000UL) /*!< DATA_SEQ_ERROR (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_SIE_STATUS_ACK_REC_Pos (30UL) /*!< ACK_REC (Bit 30) */
#define USBCTRL_REGS_SIE_STATUS_ACK_REC_Msk (0x40000000UL) /*!< ACK_REC (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_SIE_STATUS_STALL_REC_Pos (29UL) /*!< STALL_REC (Bit 29) */
#define USBCTRL_REGS_SIE_STATUS_STALL_REC_Msk (0x20000000UL) /*!< STALL_REC (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_SIE_STATUS_NAK_REC_Pos (28UL) /*!< NAK_REC (Bit 28) */
#define USBCTRL_REGS_SIE_STATUS_NAK_REC_Msk (0x10000000UL) /*!< NAK_REC (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_SIE_STATUS_RX_TIMEOUT_Pos (27UL) /*!< RX_TIMEOUT (Bit 27) */
#define USBCTRL_REGS_SIE_STATUS_RX_TIMEOUT_Msk (0x8000000UL) /*!< RX_TIMEOUT (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_SIE_STATUS_RX_OVERFLOW_Pos (26UL) /*!< RX_OVERFLOW (Bit 26) */
#define USBCTRL_REGS_SIE_STATUS_RX_OVERFLOW_Msk (0x4000000UL) /*!< RX_OVERFLOW (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_SIE_STATUS_BIT_STUFF_ERROR_Pos (25UL) /*!< BIT_STUFF_ERROR (Bit 25) */
#define USBCTRL_REGS_SIE_STATUS_BIT_STUFF_ERROR_Msk (0x2000000UL) /*!< BIT_STUFF_ERROR (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_SIE_STATUS_CRC_ERROR_Pos (24UL) /*!< CRC_ERROR (Bit 24) */
#define USBCTRL_REGS_SIE_STATUS_CRC_ERROR_Msk (0x1000000UL) /*!< CRC_ERROR (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_SIE_STATUS_BUS_RESET_Pos (19UL) /*!< BUS_RESET (Bit 19) */
#define USBCTRL_REGS_SIE_STATUS_BUS_RESET_Msk (0x80000UL) /*!< BUS_RESET (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_SIE_STATUS_TRANS_COMPLETE_Pos (18UL) /*!< TRANS_COMPLETE (Bit 18) */
#define USBCTRL_REGS_SIE_STATUS_TRANS_COMPLETE_Msk (0x40000UL) /*!< TRANS_COMPLETE (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_SIE_STATUS_SETUP_REC_Pos (17UL) /*!< SETUP_REC (Bit 17) */
#define USBCTRL_REGS_SIE_STATUS_SETUP_REC_Msk (0x20000UL) /*!< SETUP_REC (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_SIE_STATUS_CONNECTED_Pos (16UL) /*!< CONNECTED (Bit 16) */
#define USBCTRL_REGS_SIE_STATUS_CONNECTED_Msk (0x10000UL) /*!< CONNECTED (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_SIE_STATUS_RESUME_Pos (11UL) /*!< RESUME (Bit 11) */
#define USBCTRL_REGS_SIE_STATUS_RESUME_Msk (0x800UL) /*!< RESUME (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_SIE_STATUS_VBUS_OVER_CURR_Pos (10UL) /*!< VBUS_OVER_CURR (Bit 10) */
#define USBCTRL_REGS_SIE_STATUS_VBUS_OVER_CURR_Msk (0x400UL) /*!< VBUS_OVER_CURR (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_SIE_STATUS_SPEED_Pos (8UL) /*!< SPEED (Bit 8) */
#define USBCTRL_REGS_SIE_STATUS_SPEED_Msk (0x300UL) /*!< SPEED (Bitfield-Mask: 0x03) */
#define USBCTRL_REGS_SIE_STATUS_SUSPENDED_Pos (4UL) /*!< SUSPENDED (Bit 4) */
#define USBCTRL_REGS_SIE_STATUS_SUSPENDED_Msk (0x10UL) /*!< SUSPENDED (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_SIE_STATUS_LINE_STATE_Pos (2UL) /*!< LINE_STATE (Bit 2) */
#define USBCTRL_REGS_SIE_STATUS_LINE_STATE_Msk (0xcUL) /*!< LINE_STATE (Bitfield-Mask: 0x03) */
#define USBCTRL_REGS_SIE_STATUS_VBUS_DETECTED_Pos (0UL) /*!< VBUS_DETECTED (Bit 0) */
#define USBCTRL_REGS_SIE_STATUS_VBUS_DETECTED_Msk (0x1UL) /*!< VBUS_DETECTED (Bitfield-Mask: 0x01) */
/* ====================================================== INT_EP_CTRL ====================================================== */
#define USBCTRL_REGS_INT_EP_CTRL_INT_EP_ACTIVE_Pos (1UL) /*!< INT_EP_ACTIVE (Bit 1) */
#define USBCTRL_REGS_INT_EP_CTRL_INT_EP_ACTIVE_Msk (0xfffeUL) /*!< INT_EP_ACTIVE (Bitfield-Mask: 0x7fff) */
/* ====================================================== BUFF_STATUS ====================================================== */
#define USBCTRL_REGS_BUFF_STATUS_EP15_OUT_Pos (31UL) /*!< EP15_OUT (Bit 31) */
#define USBCTRL_REGS_BUFF_STATUS_EP15_OUT_Msk (0x80000000UL) /*!< EP15_OUT (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_BUFF_STATUS_EP15_IN_Pos (30UL) /*!< EP15_IN (Bit 30) */
#define USBCTRL_REGS_BUFF_STATUS_EP15_IN_Msk (0x40000000UL) /*!< EP15_IN (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_BUFF_STATUS_EP14_OUT_Pos (29UL) /*!< EP14_OUT (Bit 29) */
#define USBCTRL_REGS_BUFF_STATUS_EP14_OUT_Msk (0x20000000UL) /*!< EP14_OUT (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_BUFF_STATUS_EP14_IN_Pos (28UL) /*!< EP14_IN (Bit 28) */
#define USBCTRL_REGS_BUFF_STATUS_EP14_IN_Msk (0x10000000UL) /*!< EP14_IN (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_BUFF_STATUS_EP13_OUT_Pos (27UL) /*!< EP13_OUT (Bit 27) */
#define USBCTRL_REGS_BUFF_STATUS_EP13_OUT_Msk (0x8000000UL) /*!< EP13_OUT (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_BUFF_STATUS_EP13_IN_Pos (26UL) /*!< EP13_IN (Bit 26) */
#define USBCTRL_REGS_BUFF_STATUS_EP13_IN_Msk (0x4000000UL) /*!< EP13_IN (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_BUFF_STATUS_EP12_OUT_Pos (25UL) /*!< EP12_OUT (Bit 25) */
#define USBCTRL_REGS_BUFF_STATUS_EP12_OUT_Msk (0x2000000UL) /*!< EP12_OUT (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_BUFF_STATUS_EP12_IN_Pos (24UL) /*!< EP12_IN (Bit 24) */
#define USBCTRL_REGS_BUFF_STATUS_EP12_IN_Msk (0x1000000UL) /*!< EP12_IN (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_BUFF_STATUS_EP11_OUT_Pos (23UL) /*!< EP11_OUT (Bit 23) */
#define USBCTRL_REGS_BUFF_STATUS_EP11_OUT_Msk (0x800000UL) /*!< EP11_OUT (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_BUFF_STATUS_EP11_IN_Pos (22UL) /*!< EP11_IN (Bit 22) */
#define USBCTRL_REGS_BUFF_STATUS_EP11_IN_Msk (0x400000UL) /*!< EP11_IN (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_BUFF_STATUS_EP10_OUT_Pos (21UL) /*!< EP10_OUT (Bit 21) */
#define USBCTRL_REGS_BUFF_STATUS_EP10_OUT_Msk (0x200000UL) /*!< EP10_OUT (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_BUFF_STATUS_EP10_IN_Pos (20UL) /*!< EP10_IN (Bit 20) */
#define USBCTRL_REGS_BUFF_STATUS_EP10_IN_Msk (0x100000UL) /*!< EP10_IN (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_BUFF_STATUS_EP9_OUT_Pos (19UL) /*!< EP9_OUT (Bit 19) */
#define USBCTRL_REGS_BUFF_STATUS_EP9_OUT_Msk (0x80000UL) /*!< EP9_OUT (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_BUFF_STATUS_EP9_IN_Pos (18UL) /*!< EP9_IN (Bit 18) */
#define USBCTRL_REGS_BUFF_STATUS_EP9_IN_Msk (0x40000UL) /*!< EP9_IN (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_BUFF_STATUS_EP8_OUT_Pos (17UL) /*!< EP8_OUT (Bit 17) */
#define USBCTRL_REGS_BUFF_STATUS_EP8_OUT_Msk (0x20000UL) /*!< EP8_OUT (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_BUFF_STATUS_EP8_IN_Pos (16UL) /*!< EP8_IN (Bit 16) */
#define USBCTRL_REGS_BUFF_STATUS_EP8_IN_Msk (0x10000UL) /*!< EP8_IN (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_BUFF_STATUS_EP7_OUT_Pos (15UL) /*!< EP7_OUT (Bit 15) */
#define USBCTRL_REGS_BUFF_STATUS_EP7_OUT_Msk (0x8000UL) /*!< EP7_OUT (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_BUFF_STATUS_EP7_IN_Pos (14UL) /*!< EP7_IN (Bit 14) */
#define USBCTRL_REGS_BUFF_STATUS_EP7_IN_Msk (0x4000UL) /*!< EP7_IN (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_BUFF_STATUS_EP6_OUT_Pos (13UL) /*!< EP6_OUT (Bit 13) */
#define USBCTRL_REGS_BUFF_STATUS_EP6_OUT_Msk (0x2000UL) /*!< EP6_OUT (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_BUFF_STATUS_EP6_IN_Pos (12UL) /*!< EP6_IN (Bit 12) */
#define USBCTRL_REGS_BUFF_STATUS_EP6_IN_Msk (0x1000UL) /*!< EP6_IN (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_BUFF_STATUS_EP5_OUT_Pos (11UL) /*!< EP5_OUT (Bit 11) */
#define USBCTRL_REGS_BUFF_STATUS_EP5_OUT_Msk (0x800UL) /*!< EP5_OUT (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_BUFF_STATUS_EP5_IN_Pos (10UL) /*!< EP5_IN (Bit 10) */
#define USBCTRL_REGS_BUFF_STATUS_EP5_IN_Msk (0x400UL) /*!< EP5_IN (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_BUFF_STATUS_EP4_OUT_Pos (9UL) /*!< EP4_OUT (Bit 9) */
#define USBCTRL_REGS_BUFF_STATUS_EP4_OUT_Msk (0x200UL) /*!< EP4_OUT (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_BUFF_STATUS_EP4_IN_Pos (8UL) /*!< EP4_IN (Bit 8) */
#define USBCTRL_REGS_BUFF_STATUS_EP4_IN_Msk (0x100UL) /*!< EP4_IN (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_BUFF_STATUS_EP3_OUT_Pos (7UL) /*!< EP3_OUT (Bit 7) */
#define USBCTRL_REGS_BUFF_STATUS_EP3_OUT_Msk (0x80UL) /*!< EP3_OUT (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_BUFF_STATUS_EP3_IN_Pos (6UL) /*!< EP3_IN (Bit 6) */
#define USBCTRL_REGS_BUFF_STATUS_EP3_IN_Msk (0x40UL) /*!< EP3_IN (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_BUFF_STATUS_EP2_OUT_Pos (5UL) /*!< EP2_OUT (Bit 5) */
#define USBCTRL_REGS_BUFF_STATUS_EP2_OUT_Msk (0x20UL) /*!< EP2_OUT (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_BUFF_STATUS_EP2_IN_Pos (4UL) /*!< EP2_IN (Bit 4) */
#define USBCTRL_REGS_BUFF_STATUS_EP2_IN_Msk (0x10UL) /*!< EP2_IN (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_BUFF_STATUS_EP1_OUT_Pos (3UL) /*!< EP1_OUT (Bit 3) */
#define USBCTRL_REGS_BUFF_STATUS_EP1_OUT_Msk (0x8UL) /*!< EP1_OUT (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_BUFF_STATUS_EP1_IN_Pos (2UL) /*!< EP1_IN (Bit 2) */
#define USBCTRL_REGS_BUFF_STATUS_EP1_IN_Msk (0x4UL) /*!< EP1_IN (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_BUFF_STATUS_EP0_OUT_Pos (1UL) /*!< EP0_OUT (Bit 1) */
#define USBCTRL_REGS_BUFF_STATUS_EP0_OUT_Msk (0x2UL) /*!< EP0_OUT (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_BUFF_STATUS_EP0_IN_Pos (0UL) /*!< EP0_IN (Bit 0) */
#define USBCTRL_REGS_BUFF_STATUS_EP0_IN_Msk (0x1UL) /*!< EP0_IN (Bitfield-Mask: 0x01) */
/* ================================================ BUFF_CPU_SHOULD_HANDLE ================================================= */
#define USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP15_OUT_Pos (31UL) /*!< EP15_OUT (Bit 31) */
#define USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP15_OUT_Msk (0x80000000UL) /*!< EP15_OUT (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP15_IN_Pos (30UL) /*!< EP15_IN (Bit 30) */
#define USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP15_IN_Msk (0x40000000UL) /*!< EP15_IN (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP14_OUT_Pos (29UL) /*!< EP14_OUT (Bit 29) */
#define USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP14_OUT_Msk (0x20000000UL) /*!< EP14_OUT (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP14_IN_Pos (28UL) /*!< EP14_IN (Bit 28) */
#define USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP14_IN_Msk (0x10000000UL) /*!< EP14_IN (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP13_OUT_Pos (27UL) /*!< EP13_OUT (Bit 27) */
#define USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP13_OUT_Msk (0x8000000UL) /*!< EP13_OUT (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP13_IN_Pos (26UL) /*!< EP13_IN (Bit 26) */
#define USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP13_IN_Msk (0x4000000UL) /*!< EP13_IN (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP12_OUT_Pos (25UL) /*!< EP12_OUT (Bit 25) */
#define USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP12_OUT_Msk (0x2000000UL) /*!< EP12_OUT (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP12_IN_Pos (24UL) /*!< EP12_IN (Bit 24) */
#define USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP12_IN_Msk (0x1000000UL) /*!< EP12_IN (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP11_OUT_Pos (23UL) /*!< EP11_OUT (Bit 23) */
#define USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP11_OUT_Msk (0x800000UL) /*!< EP11_OUT (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP11_IN_Pos (22UL) /*!< EP11_IN (Bit 22) */
#define USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP11_IN_Msk (0x400000UL) /*!< EP11_IN (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP10_OUT_Pos (21UL) /*!< EP10_OUT (Bit 21) */
#define USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP10_OUT_Msk (0x200000UL) /*!< EP10_OUT (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP10_IN_Pos (20UL) /*!< EP10_IN (Bit 20) */
#define USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP10_IN_Msk (0x100000UL) /*!< EP10_IN (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP9_OUT_Pos (19UL) /*!< EP9_OUT (Bit 19) */
#define USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP9_OUT_Msk (0x80000UL) /*!< EP9_OUT (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP9_IN_Pos (18UL) /*!< EP9_IN (Bit 18) */
#define USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP9_IN_Msk (0x40000UL) /*!< EP9_IN (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP8_OUT_Pos (17UL) /*!< EP8_OUT (Bit 17) */
#define USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP8_OUT_Msk (0x20000UL) /*!< EP8_OUT (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP8_IN_Pos (16UL) /*!< EP8_IN (Bit 16) */
#define USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP8_IN_Msk (0x10000UL) /*!< EP8_IN (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP7_OUT_Pos (15UL) /*!< EP7_OUT (Bit 15) */
#define USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP7_OUT_Msk (0x8000UL) /*!< EP7_OUT (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP7_IN_Pos (14UL) /*!< EP7_IN (Bit 14) */
#define USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP7_IN_Msk (0x4000UL) /*!< EP7_IN (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP6_OUT_Pos (13UL) /*!< EP6_OUT (Bit 13) */
#define USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP6_OUT_Msk (0x2000UL) /*!< EP6_OUT (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP6_IN_Pos (12UL) /*!< EP6_IN (Bit 12) */
#define USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP6_IN_Msk (0x1000UL) /*!< EP6_IN (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP5_OUT_Pos (11UL) /*!< EP5_OUT (Bit 11) */
#define USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP5_OUT_Msk (0x800UL) /*!< EP5_OUT (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP5_IN_Pos (10UL) /*!< EP5_IN (Bit 10) */
#define USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP5_IN_Msk (0x400UL) /*!< EP5_IN (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP4_OUT_Pos (9UL) /*!< EP4_OUT (Bit 9) */
#define USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP4_OUT_Msk (0x200UL) /*!< EP4_OUT (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP4_IN_Pos (8UL) /*!< EP4_IN (Bit 8) */
#define USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP4_IN_Msk (0x100UL) /*!< EP4_IN (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP3_OUT_Pos (7UL) /*!< EP3_OUT (Bit 7) */
#define USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP3_OUT_Msk (0x80UL) /*!< EP3_OUT (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP3_IN_Pos (6UL) /*!< EP3_IN (Bit 6) */
#define USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP3_IN_Msk (0x40UL) /*!< EP3_IN (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP2_OUT_Pos (5UL) /*!< EP2_OUT (Bit 5) */
#define USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP2_OUT_Msk (0x20UL) /*!< EP2_OUT (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP2_IN_Pos (4UL) /*!< EP2_IN (Bit 4) */
#define USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP2_IN_Msk (0x10UL) /*!< EP2_IN (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP1_OUT_Pos (3UL) /*!< EP1_OUT (Bit 3) */
#define USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP1_OUT_Msk (0x8UL) /*!< EP1_OUT (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP1_IN_Pos (2UL) /*!< EP1_IN (Bit 2) */
#define USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP1_IN_Msk (0x4UL) /*!< EP1_IN (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP0_OUT_Pos (1UL) /*!< EP0_OUT (Bit 1) */
#define USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP0_OUT_Msk (0x2UL) /*!< EP0_OUT (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP0_IN_Pos (0UL) /*!< EP0_IN (Bit 0) */
#define USBCTRL_REGS_BUFF_CPU_SHOULD_HANDLE_EP0_IN_Msk (0x1UL) /*!< EP0_IN (Bitfield-Mask: 0x01) */
/* ======================================================= EP_ABORT ======================================================== */
#define USBCTRL_REGS_EP_ABORT_EP15_OUT_Pos (31UL) /*!< EP15_OUT (Bit 31) */
#define USBCTRL_REGS_EP_ABORT_EP15_OUT_Msk (0x80000000UL) /*!< EP15_OUT (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_EP_ABORT_EP15_IN_Pos (30UL) /*!< EP15_IN (Bit 30) */
#define USBCTRL_REGS_EP_ABORT_EP15_IN_Msk (0x40000000UL) /*!< EP15_IN (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_EP_ABORT_EP14_OUT_Pos (29UL) /*!< EP14_OUT (Bit 29) */
#define USBCTRL_REGS_EP_ABORT_EP14_OUT_Msk (0x20000000UL) /*!< EP14_OUT (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_EP_ABORT_EP14_IN_Pos (28UL) /*!< EP14_IN (Bit 28) */
#define USBCTRL_REGS_EP_ABORT_EP14_IN_Msk (0x10000000UL) /*!< EP14_IN (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_EP_ABORT_EP13_OUT_Pos (27UL) /*!< EP13_OUT (Bit 27) */
#define USBCTRL_REGS_EP_ABORT_EP13_OUT_Msk (0x8000000UL) /*!< EP13_OUT (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_EP_ABORT_EP13_IN_Pos (26UL) /*!< EP13_IN (Bit 26) */
#define USBCTRL_REGS_EP_ABORT_EP13_IN_Msk (0x4000000UL) /*!< EP13_IN (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_EP_ABORT_EP12_OUT_Pos (25UL) /*!< EP12_OUT (Bit 25) */
#define USBCTRL_REGS_EP_ABORT_EP12_OUT_Msk (0x2000000UL) /*!< EP12_OUT (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_EP_ABORT_EP12_IN_Pos (24UL) /*!< EP12_IN (Bit 24) */
#define USBCTRL_REGS_EP_ABORT_EP12_IN_Msk (0x1000000UL) /*!< EP12_IN (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_EP_ABORT_EP11_OUT_Pos (23UL) /*!< EP11_OUT (Bit 23) */
#define USBCTRL_REGS_EP_ABORT_EP11_OUT_Msk (0x800000UL) /*!< EP11_OUT (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_EP_ABORT_EP11_IN_Pos (22UL) /*!< EP11_IN (Bit 22) */
#define USBCTRL_REGS_EP_ABORT_EP11_IN_Msk (0x400000UL) /*!< EP11_IN (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_EP_ABORT_EP10_OUT_Pos (21UL) /*!< EP10_OUT (Bit 21) */
#define USBCTRL_REGS_EP_ABORT_EP10_OUT_Msk (0x200000UL) /*!< EP10_OUT (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_EP_ABORT_EP10_IN_Pos (20UL) /*!< EP10_IN (Bit 20) */
#define USBCTRL_REGS_EP_ABORT_EP10_IN_Msk (0x100000UL) /*!< EP10_IN (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_EP_ABORT_EP9_OUT_Pos (19UL) /*!< EP9_OUT (Bit 19) */
#define USBCTRL_REGS_EP_ABORT_EP9_OUT_Msk (0x80000UL) /*!< EP9_OUT (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_EP_ABORT_EP9_IN_Pos (18UL) /*!< EP9_IN (Bit 18) */
#define USBCTRL_REGS_EP_ABORT_EP9_IN_Msk (0x40000UL) /*!< EP9_IN (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_EP_ABORT_EP8_OUT_Pos (17UL) /*!< EP8_OUT (Bit 17) */
#define USBCTRL_REGS_EP_ABORT_EP8_OUT_Msk (0x20000UL) /*!< EP8_OUT (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_EP_ABORT_EP8_IN_Pos (16UL) /*!< EP8_IN (Bit 16) */
#define USBCTRL_REGS_EP_ABORT_EP8_IN_Msk (0x10000UL) /*!< EP8_IN (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_EP_ABORT_EP7_OUT_Pos (15UL) /*!< EP7_OUT (Bit 15) */
#define USBCTRL_REGS_EP_ABORT_EP7_OUT_Msk (0x8000UL) /*!< EP7_OUT (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_EP_ABORT_EP7_IN_Pos (14UL) /*!< EP7_IN (Bit 14) */
#define USBCTRL_REGS_EP_ABORT_EP7_IN_Msk (0x4000UL) /*!< EP7_IN (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_EP_ABORT_EP6_OUT_Pos (13UL) /*!< EP6_OUT (Bit 13) */
#define USBCTRL_REGS_EP_ABORT_EP6_OUT_Msk (0x2000UL) /*!< EP6_OUT (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_EP_ABORT_EP6_IN_Pos (12UL) /*!< EP6_IN (Bit 12) */
#define USBCTRL_REGS_EP_ABORT_EP6_IN_Msk (0x1000UL) /*!< EP6_IN (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_EP_ABORT_EP5_OUT_Pos (11UL) /*!< EP5_OUT (Bit 11) */
#define USBCTRL_REGS_EP_ABORT_EP5_OUT_Msk (0x800UL) /*!< EP5_OUT (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_EP_ABORT_EP5_IN_Pos (10UL) /*!< EP5_IN (Bit 10) */
#define USBCTRL_REGS_EP_ABORT_EP5_IN_Msk (0x400UL) /*!< EP5_IN (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_EP_ABORT_EP4_OUT_Pos (9UL) /*!< EP4_OUT (Bit 9) */
#define USBCTRL_REGS_EP_ABORT_EP4_OUT_Msk (0x200UL) /*!< EP4_OUT (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_EP_ABORT_EP4_IN_Pos (8UL) /*!< EP4_IN (Bit 8) */
#define USBCTRL_REGS_EP_ABORT_EP4_IN_Msk (0x100UL) /*!< EP4_IN (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_EP_ABORT_EP3_OUT_Pos (7UL) /*!< EP3_OUT (Bit 7) */
#define USBCTRL_REGS_EP_ABORT_EP3_OUT_Msk (0x80UL) /*!< EP3_OUT (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_EP_ABORT_EP3_IN_Pos (6UL) /*!< EP3_IN (Bit 6) */
#define USBCTRL_REGS_EP_ABORT_EP3_IN_Msk (0x40UL) /*!< EP3_IN (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_EP_ABORT_EP2_OUT_Pos (5UL) /*!< EP2_OUT (Bit 5) */
#define USBCTRL_REGS_EP_ABORT_EP2_OUT_Msk (0x20UL) /*!< EP2_OUT (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_EP_ABORT_EP2_IN_Pos (4UL) /*!< EP2_IN (Bit 4) */
#define USBCTRL_REGS_EP_ABORT_EP2_IN_Msk (0x10UL) /*!< EP2_IN (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_EP_ABORT_EP1_OUT_Pos (3UL) /*!< EP1_OUT (Bit 3) */
#define USBCTRL_REGS_EP_ABORT_EP1_OUT_Msk (0x8UL) /*!< EP1_OUT (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_EP_ABORT_EP1_IN_Pos (2UL) /*!< EP1_IN (Bit 2) */
#define USBCTRL_REGS_EP_ABORT_EP1_IN_Msk (0x4UL) /*!< EP1_IN (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_EP_ABORT_EP0_OUT_Pos (1UL) /*!< EP0_OUT (Bit 1) */
#define USBCTRL_REGS_EP_ABORT_EP0_OUT_Msk (0x2UL) /*!< EP0_OUT (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_EP_ABORT_EP0_IN_Pos (0UL) /*!< EP0_IN (Bit 0) */
#define USBCTRL_REGS_EP_ABORT_EP0_IN_Msk (0x1UL) /*!< EP0_IN (Bitfield-Mask: 0x01) */
/* ===================================================== EP_ABORT_DONE ===================================================== */
#define USBCTRL_REGS_EP_ABORT_DONE_EP15_OUT_Pos (31UL) /*!< EP15_OUT (Bit 31) */
#define USBCTRL_REGS_EP_ABORT_DONE_EP15_OUT_Msk (0x80000000UL) /*!< EP15_OUT (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_EP_ABORT_DONE_EP15_IN_Pos (30UL) /*!< EP15_IN (Bit 30) */
#define USBCTRL_REGS_EP_ABORT_DONE_EP15_IN_Msk (0x40000000UL) /*!< EP15_IN (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_EP_ABORT_DONE_EP14_OUT_Pos (29UL) /*!< EP14_OUT (Bit 29) */
#define USBCTRL_REGS_EP_ABORT_DONE_EP14_OUT_Msk (0x20000000UL) /*!< EP14_OUT (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_EP_ABORT_DONE_EP14_IN_Pos (28UL) /*!< EP14_IN (Bit 28) */
#define USBCTRL_REGS_EP_ABORT_DONE_EP14_IN_Msk (0x10000000UL) /*!< EP14_IN (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_EP_ABORT_DONE_EP13_OUT_Pos (27UL) /*!< EP13_OUT (Bit 27) */
#define USBCTRL_REGS_EP_ABORT_DONE_EP13_OUT_Msk (0x8000000UL) /*!< EP13_OUT (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_EP_ABORT_DONE_EP13_IN_Pos (26UL) /*!< EP13_IN (Bit 26) */
#define USBCTRL_REGS_EP_ABORT_DONE_EP13_IN_Msk (0x4000000UL) /*!< EP13_IN (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_EP_ABORT_DONE_EP12_OUT_Pos (25UL) /*!< EP12_OUT (Bit 25) */
#define USBCTRL_REGS_EP_ABORT_DONE_EP12_OUT_Msk (0x2000000UL) /*!< EP12_OUT (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_EP_ABORT_DONE_EP12_IN_Pos (24UL) /*!< EP12_IN (Bit 24) */
#define USBCTRL_REGS_EP_ABORT_DONE_EP12_IN_Msk (0x1000000UL) /*!< EP12_IN (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_EP_ABORT_DONE_EP11_OUT_Pos (23UL) /*!< EP11_OUT (Bit 23) */
#define USBCTRL_REGS_EP_ABORT_DONE_EP11_OUT_Msk (0x800000UL) /*!< EP11_OUT (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_EP_ABORT_DONE_EP11_IN_Pos (22UL) /*!< EP11_IN (Bit 22) */
#define USBCTRL_REGS_EP_ABORT_DONE_EP11_IN_Msk (0x400000UL) /*!< EP11_IN (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_EP_ABORT_DONE_EP10_OUT_Pos (21UL) /*!< EP10_OUT (Bit 21) */
#define USBCTRL_REGS_EP_ABORT_DONE_EP10_OUT_Msk (0x200000UL) /*!< EP10_OUT (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_EP_ABORT_DONE_EP10_IN_Pos (20UL) /*!< EP10_IN (Bit 20) */
#define USBCTRL_REGS_EP_ABORT_DONE_EP10_IN_Msk (0x100000UL) /*!< EP10_IN (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_EP_ABORT_DONE_EP9_OUT_Pos (19UL) /*!< EP9_OUT (Bit 19) */
#define USBCTRL_REGS_EP_ABORT_DONE_EP9_OUT_Msk (0x80000UL) /*!< EP9_OUT (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_EP_ABORT_DONE_EP9_IN_Pos (18UL) /*!< EP9_IN (Bit 18) */
#define USBCTRL_REGS_EP_ABORT_DONE_EP9_IN_Msk (0x40000UL) /*!< EP9_IN (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_EP_ABORT_DONE_EP8_OUT_Pos (17UL) /*!< EP8_OUT (Bit 17) */
#define USBCTRL_REGS_EP_ABORT_DONE_EP8_OUT_Msk (0x20000UL) /*!< EP8_OUT (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_EP_ABORT_DONE_EP8_IN_Pos (16UL) /*!< EP8_IN (Bit 16) */
#define USBCTRL_REGS_EP_ABORT_DONE_EP8_IN_Msk (0x10000UL) /*!< EP8_IN (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_EP_ABORT_DONE_EP7_OUT_Pos (15UL) /*!< EP7_OUT (Bit 15) */
#define USBCTRL_REGS_EP_ABORT_DONE_EP7_OUT_Msk (0x8000UL) /*!< EP7_OUT (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_EP_ABORT_DONE_EP7_IN_Pos (14UL) /*!< EP7_IN (Bit 14) */
#define USBCTRL_REGS_EP_ABORT_DONE_EP7_IN_Msk (0x4000UL) /*!< EP7_IN (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_EP_ABORT_DONE_EP6_OUT_Pos (13UL) /*!< EP6_OUT (Bit 13) */
#define USBCTRL_REGS_EP_ABORT_DONE_EP6_OUT_Msk (0x2000UL) /*!< EP6_OUT (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_EP_ABORT_DONE_EP6_IN_Pos (12UL) /*!< EP6_IN (Bit 12) */
#define USBCTRL_REGS_EP_ABORT_DONE_EP6_IN_Msk (0x1000UL) /*!< EP6_IN (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_EP_ABORT_DONE_EP5_OUT_Pos (11UL) /*!< EP5_OUT (Bit 11) */
#define USBCTRL_REGS_EP_ABORT_DONE_EP5_OUT_Msk (0x800UL) /*!< EP5_OUT (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_EP_ABORT_DONE_EP5_IN_Pos (10UL) /*!< EP5_IN (Bit 10) */
#define USBCTRL_REGS_EP_ABORT_DONE_EP5_IN_Msk (0x400UL) /*!< EP5_IN (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_EP_ABORT_DONE_EP4_OUT_Pos (9UL) /*!< EP4_OUT (Bit 9) */
#define USBCTRL_REGS_EP_ABORT_DONE_EP4_OUT_Msk (0x200UL) /*!< EP4_OUT (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_EP_ABORT_DONE_EP4_IN_Pos (8UL) /*!< EP4_IN (Bit 8) */
#define USBCTRL_REGS_EP_ABORT_DONE_EP4_IN_Msk (0x100UL) /*!< EP4_IN (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_EP_ABORT_DONE_EP3_OUT_Pos (7UL) /*!< EP3_OUT (Bit 7) */
#define USBCTRL_REGS_EP_ABORT_DONE_EP3_OUT_Msk (0x80UL) /*!< EP3_OUT (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_EP_ABORT_DONE_EP3_IN_Pos (6UL) /*!< EP3_IN (Bit 6) */
#define USBCTRL_REGS_EP_ABORT_DONE_EP3_IN_Msk (0x40UL) /*!< EP3_IN (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_EP_ABORT_DONE_EP2_OUT_Pos (5UL) /*!< EP2_OUT (Bit 5) */
#define USBCTRL_REGS_EP_ABORT_DONE_EP2_OUT_Msk (0x20UL) /*!< EP2_OUT (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_EP_ABORT_DONE_EP2_IN_Pos (4UL) /*!< EP2_IN (Bit 4) */
#define USBCTRL_REGS_EP_ABORT_DONE_EP2_IN_Msk (0x10UL) /*!< EP2_IN (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_EP_ABORT_DONE_EP1_OUT_Pos (3UL) /*!< EP1_OUT (Bit 3) */
#define USBCTRL_REGS_EP_ABORT_DONE_EP1_OUT_Msk (0x8UL) /*!< EP1_OUT (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_EP_ABORT_DONE_EP1_IN_Pos (2UL) /*!< EP1_IN (Bit 2) */
#define USBCTRL_REGS_EP_ABORT_DONE_EP1_IN_Msk (0x4UL) /*!< EP1_IN (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_EP_ABORT_DONE_EP0_OUT_Pos (1UL) /*!< EP0_OUT (Bit 1) */
#define USBCTRL_REGS_EP_ABORT_DONE_EP0_OUT_Msk (0x2UL) /*!< EP0_OUT (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_EP_ABORT_DONE_EP0_IN_Pos (0UL) /*!< EP0_IN (Bit 0) */
#define USBCTRL_REGS_EP_ABORT_DONE_EP0_IN_Msk (0x1UL) /*!< EP0_IN (Bitfield-Mask: 0x01) */
/* ===================================================== EP_STALL_ARM ====================================================== */
#define USBCTRL_REGS_EP_STALL_ARM_EP0_OUT_Pos (1UL) /*!< EP0_OUT (Bit 1) */
#define USBCTRL_REGS_EP_STALL_ARM_EP0_OUT_Msk (0x2UL) /*!< EP0_OUT (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_EP_STALL_ARM_EP0_IN_Pos (0UL) /*!< EP0_IN (Bit 0) */
#define USBCTRL_REGS_EP_STALL_ARM_EP0_IN_Msk (0x1UL) /*!< EP0_IN (Bitfield-Mask: 0x01) */
/* ======================================================= NAK_POLL ======================================================== */
#define USBCTRL_REGS_NAK_POLL_DELAY_FS_Pos (16UL) /*!< DELAY_FS (Bit 16) */
#define USBCTRL_REGS_NAK_POLL_DELAY_FS_Msk (0x3ff0000UL) /*!< DELAY_FS (Bitfield-Mask: 0x3ff) */
#define USBCTRL_REGS_NAK_POLL_DELAY_LS_Pos (0UL) /*!< DELAY_LS (Bit 0) */
#define USBCTRL_REGS_NAK_POLL_DELAY_LS_Msk (0x3ffUL) /*!< DELAY_LS (Bitfield-Mask: 0x3ff) */
/* ================================================== EP_STATUS_STALL_NAK ================================================== */
#define USBCTRL_REGS_EP_STATUS_STALL_NAK_EP15_OUT_Pos (31UL) /*!< EP15_OUT (Bit 31) */
#define USBCTRL_REGS_EP_STATUS_STALL_NAK_EP15_OUT_Msk (0x80000000UL) /*!< EP15_OUT (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_EP_STATUS_STALL_NAK_EP15_IN_Pos (30UL) /*!< EP15_IN (Bit 30) */
#define USBCTRL_REGS_EP_STATUS_STALL_NAK_EP15_IN_Msk (0x40000000UL) /*!< EP15_IN (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_EP_STATUS_STALL_NAK_EP14_OUT_Pos (29UL) /*!< EP14_OUT (Bit 29) */
#define USBCTRL_REGS_EP_STATUS_STALL_NAK_EP14_OUT_Msk (0x20000000UL) /*!< EP14_OUT (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_EP_STATUS_STALL_NAK_EP14_IN_Pos (28UL) /*!< EP14_IN (Bit 28) */
#define USBCTRL_REGS_EP_STATUS_STALL_NAK_EP14_IN_Msk (0x10000000UL) /*!< EP14_IN (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_EP_STATUS_STALL_NAK_EP13_OUT_Pos (27UL) /*!< EP13_OUT (Bit 27) */
#define USBCTRL_REGS_EP_STATUS_STALL_NAK_EP13_OUT_Msk (0x8000000UL) /*!< EP13_OUT (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_EP_STATUS_STALL_NAK_EP13_IN_Pos (26UL) /*!< EP13_IN (Bit 26) */
#define USBCTRL_REGS_EP_STATUS_STALL_NAK_EP13_IN_Msk (0x4000000UL) /*!< EP13_IN (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_EP_STATUS_STALL_NAK_EP12_OUT_Pos (25UL) /*!< EP12_OUT (Bit 25) */
#define USBCTRL_REGS_EP_STATUS_STALL_NAK_EP12_OUT_Msk (0x2000000UL) /*!< EP12_OUT (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_EP_STATUS_STALL_NAK_EP12_IN_Pos (24UL) /*!< EP12_IN (Bit 24) */
#define USBCTRL_REGS_EP_STATUS_STALL_NAK_EP12_IN_Msk (0x1000000UL) /*!< EP12_IN (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_EP_STATUS_STALL_NAK_EP11_OUT_Pos (23UL) /*!< EP11_OUT (Bit 23) */
#define USBCTRL_REGS_EP_STATUS_STALL_NAK_EP11_OUT_Msk (0x800000UL) /*!< EP11_OUT (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_EP_STATUS_STALL_NAK_EP11_IN_Pos (22UL) /*!< EP11_IN (Bit 22) */
#define USBCTRL_REGS_EP_STATUS_STALL_NAK_EP11_IN_Msk (0x400000UL) /*!< EP11_IN (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_EP_STATUS_STALL_NAK_EP10_OUT_Pos (21UL) /*!< EP10_OUT (Bit 21) */
#define USBCTRL_REGS_EP_STATUS_STALL_NAK_EP10_OUT_Msk (0x200000UL) /*!< EP10_OUT (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_EP_STATUS_STALL_NAK_EP10_IN_Pos (20UL) /*!< EP10_IN (Bit 20) */
#define USBCTRL_REGS_EP_STATUS_STALL_NAK_EP10_IN_Msk (0x100000UL) /*!< EP10_IN (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_EP_STATUS_STALL_NAK_EP9_OUT_Pos (19UL) /*!< EP9_OUT (Bit 19) */
#define USBCTRL_REGS_EP_STATUS_STALL_NAK_EP9_OUT_Msk (0x80000UL) /*!< EP9_OUT (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_EP_STATUS_STALL_NAK_EP9_IN_Pos (18UL) /*!< EP9_IN (Bit 18) */
#define USBCTRL_REGS_EP_STATUS_STALL_NAK_EP9_IN_Msk (0x40000UL) /*!< EP9_IN (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_EP_STATUS_STALL_NAK_EP8_OUT_Pos (17UL) /*!< EP8_OUT (Bit 17) */
#define USBCTRL_REGS_EP_STATUS_STALL_NAK_EP8_OUT_Msk (0x20000UL) /*!< EP8_OUT (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_EP_STATUS_STALL_NAK_EP8_IN_Pos (16UL) /*!< EP8_IN (Bit 16) */
#define USBCTRL_REGS_EP_STATUS_STALL_NAK_EP8_IN_Msk (0x10000UL) /*!< EP8_IN (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_EP_STATUS_STALL_NAK_EP7_OUT_Pos (15UL) /*!< EP7_OUT (Bit 15) */
#define USBCTRL_REGS_EP_STATUS_STALL_NAK_EP7_OUT_Msk (0x8000UL) /*!< EP7_OUT (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_EP_STATUS_STALL_NAK_EP7_IN_Pos (14UL) /*!< EP7_IN (Bit 14) */
#define USBCTRL_REGS_EP_STATUS_STALL_NAK_EP7_IN_Msk (0x4000UL) /*!< EP7_IN (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_EP_STATUS_STALL_NAK_EP6_OUT_Pos (13UL) /*!< EP6_OUT (Bit 13) */
#define USBCTRL_REGS_EP_STATUS_STALL_NAK_EP6_OUT_Msk (0x2000UL) /*!< EP6_OUT (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_EP_STATUS_STALL_NAK_EP6_IN_Pos (12UL) /*!< EP6_IN (Bit 12) */
#define USBCTRL_REGS_EP_STATUS_STALL_NAK_EP6_IN_Msk (0x1000UL) /*!< EP6_IN (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_EP_STATUS_STALL_NAK_EP5_OUT_Pos (11UL) /*!< EP5_OUT (Bit 11) */
#define USBCTRL_REGS_EP_STATUS_STALL_NAK_EP5_OUT_Msk (0x800UL) /*!< EP5_OUT (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_EP_STATUS_STALL_NAK_EP5_IN_Pos (10UL) /*!< EP5_IN (Bit 10) */
#define USBCTRL_REGS_EP_STATUS_STALL_NAK_EP5_IN_Msk (0x400UL) /*!< EP5_IN (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_EP_STATUS_STALL_NAK_EP4_OUT_Pos (9UL) /*!< EP4_OUT (Bit 9) */
#define USBCTRL_REGS_EP_STATUS_STALL_NAK_EP4_OUT_Msk (0x200UL) /*!< EP4_OUT (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_EP_STATUS_STALL_NAK_EP4_IN_Pos (8UL) /*!< EP4_IN (Bit 8) */
#define USBCTRL_REGS_EP_STATUS_STALL_NAK_EP4_IN_Msk (0x100UL) /*!< EP4_IN (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_EP_STATUS_STALL_NAK_EP3_OUT_Pos (7UL) /*!< EP3_OUT (Bit 7) */
#define USBCTRL_REGS_EP_STATUS_STALL_NAK_EP3_OUT_Msk (0x80UL) /*!< EP3_OUT (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_EP_STATUS_STALL_NAK_EP3_IN_Pos (6UL) /*!< EP3_IN (Bit 6) */
#define USBCTRL_REGS_EP_STATUS_STALL_NAK_EP3_IN_Msk (0x40UL) /*!< EP3_IN (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_EP_STATUS_STALL_NAK_EP2_OUT_Pos (5UL) /*!< EP2_OUT (Bit 5) */
#define USBCTRL_REGS_EP_STATUS_STALL_NAK_EP2_OUT_Msk (0x20UL) /*!< EP2_OUT (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_EP_STATUS_STALL_NAK_EP2_IN_Pos (4UL) /*!< EP2_IN (Bit 4) */
#define USBCTRL_REGS_EP_STATUS_STALL_NAK_EP2_IN_Msk (0x10UL) /*!< EP2_IN (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_EP_STATUS_STALL_NAK_EP1_OUT_Pos (3UL) /*!< EP1_OUT (Bit 3) */
#define USBCTRL_REGS_EP_STATUS_STALL_NAK_EP1_OUT_Msk (0x8UL) /*!< EP1_OUT (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_EP_STATUS_STALL_NAK_EP1_IN_Pos (2UL) /*!< EP1_IN (Bit 2) */
#define USBCTRL_REGS_EP_STATUS_STALL_NAK_EP1_IN_Msk (0x4UL) /*!< EP1_IN (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_EP_STATUS_STALL_NAK_EP0_OUT_Pos (1UL) /*!< EP0_OUT (Bit 1) */
#define USBCTRL_REGS_EP_STATUS_STALL_NAK_EP0_OUT_Msk (0x2UL) /*!< EP0_OUT (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_EP_STATUS_STALL_NAK_EP0_IN_Pos (0UL) /*!< EP0_IN (Bit 0) */
#define USBCTRL_REGS_EP_STATUS_STALL_NAK_EP0_IN_Msk (0x1UL) /*!< EP0_IN (Bitfield-Mask: 0x01) */
/* ====================================================== USB_MUXING ======================================================= */
#define USBCTRL_REGS_USB_MUXING_SOFTCON_Pos (3UL) /*!< SOFTCON (Bit 3) */
#define USBCTRL_REGS_USB_MUXING_SOFTCON_Msk (0x8UL) /*!< SOFTCON (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_USB_MUXING_TO_DIGITAL_PAD_Pos (2UL) /*!< TO_DIGITAL_PAD (Bit 2) */
#define USBCTRL_REGS_USB_MUXING_TO_DIGITAL_PAD_Msk (0x4UL) /*!< TO_DIGITAL_PAD (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_USB_MUXING_TO_EXTPHY_Pos (1UL) /*!< TO_EXTPHY (Bit 1) */
#define USBCTRL_REGS_USB_MUXING_TO_EXTPHY_Msk (0x2UL) /*!< TO_EXTPHY (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_USB_MUXING_TO_PHY_Pos (0UL) /*!< TO_PHY (Bit 0) */
#define USBCTRL_REGS_USB_MUXING_TO_PHY_Msk (0x1UL) /*!< TO_PHY (Bitfield-Mask: 0x01) */
/* ======================================================== USB_PWR ======================================================== */
#define USBCTRL_REGS_USB_PWR_OVERCURR_DETECT_EN_Pos (5UL) /*!< OVERCURR_DETECT_EN (Bit 5) */
#define USBCTRL_REGS_USB_PWR_OVERCURR_DETECT_EN_Msk (0x20UL) /*!< OVERCURR_DETECT_EN (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_USB_PWR_OVERCURR_DETECT_Pos (4UL) /*!< OVERCURR_DETECT (Bit 4) */
#define USBCTRL_REGS_USB_PWR_OVERCURR_DETECT_Msk (0x10UL) /*!< OVERCURR_DETECT (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_USB_PWR_VBUS_DETECT_OVERRIDE_EN_Pos (3UL) /*!< VBUS_DETECT_OVERRIDE_EN (Bit 3) */
#define USBCTRL_REGS_USB_PWR_VBUS_DETECT_OVERRIDE_EN_Msk (0x8UL) /*!< VBUS_DETECT_OVERRIDE_EN (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_USB_PWR_VBUS_DETECT_Pos (2UL) /*!< VBUS_DETECT (Bit 2) */
#define USBCTRL_REGS_USB_PWR_VBUS_DETECT_Msk (0x4UL) /*!< VBUS_DETECT (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_USB_PWR_VBUS_EN_OVERRIDE_EN_Pos (1UL) /*!< VBUS_EN_OVERRIDE_EN (Bit 1) */
#define USBCTRL_REGS_USB_PWR_VBUS_EN_OVERRIDE_EN_Msk (0x2UL) /*!< VBUS_EN_OVERRIDE_EN (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_USB_PWR_VBUS_EN_Pos (0UL) /*!< VBUS_EN (Bit 0) */
#define USBCTRL_REGS_USB_PWR_VBUS_EN_Msk (0x1UL) /*!< VBUS_EN (Bitfield-Mask: 0x01) */
/* ===================================================== USBPHY_DIRECT ===================================================== */
#define USBCTRL_REGS_USBPHY_DIRECT_DM_OVV_Pos (22UL) /*!< DM_OVV (Bit 22) */
#define USBCTRL_REGS_USBPHY_DIRECT_DM_OVV_Msk (0x400000UL) /*!< DM_OVV (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_USBPHY_DIRECT_DP_OVV_Pos (21UL) /*!< DP_OVV (Bit 21) */
#define USBCTRL_REGS_USBPHY_DIRECT_DP_OVV_Msk (0x200000UL) /*!< DP_OVV (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_USBPHY_DIRECT_DM_OVCN_Pos (20UL) /*!< DM_OVCN (Bit 20) */
#define USBCTRL_REGS_USBPHY_DIRECT_DM_OVCN_Msk (0x100000UL) /*!< DM_OVCN (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_USBPHY_DIRECT_DP_OVCN_Pos (19UL) /*!< DP_OVCN (Bit 19) */
#define USBCTRL_REGS_USBPHY_DIRECT_DP_OVCN_Msk (0x80000UL) /*!< DP_OVCN (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_USBPHY_DIRECT_RX_DM_Pos (18UL) /*!< RX_DM (Bit 18) */
#define USBCTRL_REGS_USBPHY_DIRECT_RX_DM_Msk (0x40000UL) /*!< RX_DM (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_USBPHY_DIRECT_RX_DP_Pos (17UL) /*!< RX_DP (Bit 17) */
#define USBCTRL_REGS_USBPHY_DIRECT_RX_DP_Msk (0x20000UL) /*!< RX_DP (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_USBPHY_DIRECT_RX_DD_Pos (16UL) /*!< RX_DD (Bit 16) */
#define USBCTRL_REGS_USBPHY_DIRECT_RX_DD_Msk (0x10000UL) /*!< RX_DD (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_USBPHY_DIRECT_TX_DIFFMODE_Pos (15UL) /*!< TX_DIFFMODE (Bit 15) */
#define USBCTRL_REGS_USBPHY_DIRECT_TX_DIFFMODE_Msk (0x8000UL) /*!< TX_DIFFMODE (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_USBPHY_DIRECT_TX_FSSLEW_Pos (14UL) /*!< TX_FSSLEW (Bit 14) */
#define USBCTRL_REGS_USBPHY_DIRECT_TX_FSSLEW_Msk (0x4000UL) /*!< TX_FSSLEW (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_USBPHY_DIRECT_TX_PD_Pos (13UL) /*!< TX_PD (Bit 13) */
#define USBCTRL_REGS_USBPHY_DIRECT_TX_PD_Msk (0x2000UL) /*!< TX_PD (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_USBPHY_DIRECT_RX_PD_Pos (12UL) /*!< RX_PD (Bit 12) */
#define USBCTRL_REGS_USBPHY_DIRECT_RX_PD_Msk (0x1000UL) /*!< RX_PD (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_USBPHY_DIRECT_TX_DM_Pos (11UL) /*!< TX_DM (Bit 11) */
#define USBCTRL_REGS_USBPHY_DIRECT_TX_DM_Msk (0x800UL) /*!< TX_DM (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_USBPHY_DIRECT_TX_DP_Pos (10UL) /*!< TX_DP (Bit 10) */
#define USBCTRL_REGS_USBPHY_DIRECT_TX_DP_Msk (0x400UL) /*!< TX_DP (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_USBPHY_DIRECT_TX_DM_OE_Pos (9UL) /*!< TX_DM_OE (Bit 9) */
#define USBCTRL_REGS_USBPHY_DIRECT_TX_DM_OE_Msk (0x200UL) /*!< TX_DM_OE (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_USBPHY_DIRECT_TX_DP_OE_Pos (8UL) /*!< TX_DP_OE (Bit 8) */
#define USBCTRL_REGS_USBPHY_DIRECT_TX_DP_OE_Msk (0x100UL) /*!< TX_DP_OE (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_USBPHY_DIRECT_DM_PULLDN_EN_Pos (6UL) /*!< DM_PULLDN_EN (Bit 6) */
#define USBCTRL_REGS_USBPHY_DIRECT_DM_PULLDN_EN_Msk (0x40UL) /*!< DM_PULLDN_EN (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_USBPHY_DIRECT_DM_PULLUP_EN_Pos (5UL) /*!< DM_PULLUP_EN (Bit 5) */
#define USBCTRL_REGS_USBPHY_DIRECT_DM_PULLUP_EN_Msk (0x20UL) /*!< DM_PULLUP_EN (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_USBPHY_DIRECT_DM_PULLUP_HISEL_Pos (4UL) /*!< DM_PULLUP_HISEL (Bit 4) */
#define USBCTRL_REGS_USBPHY_DIRECT_DM_PULLUP_HISEL_Msk (0x10UL) /*!< DM_PULLUP_HISEL (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_USBPHY_DIRECT_DP_PULLDN_EN_Pos (2UL) /*!< DP_PULLDN_EN (Bit 2) */
#define USBCTRL_REGS_USBPHY_DIRECT_DP_PULLDN_EN_Msk (0x4UL) /*!< DP_PULLDN_EN (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_USBPHY_DIRECT_DP_PULLUP_EN_Pos (1UL) /*!< DP_PULLUP_EN (Bit 1) */
#define USBCTRL_REGS_USBPHY_DIRECT_DP_PULLUP_EN_Msk (0x2UL) /*!< DP_PULLUP_EN (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_USBPHY_DIRECT_DP_PULLUP_HISEL_Pos (0UL) /*!< DP_PULLUP_HISEL (Bit 0) */
#define USBCTRL_REGS_USBPHY_DIRECT_DP_PULLUP_HISEL_Msk (0x1UL) /*!< DP_PULLUP_HISEL (Bitfield-Mask: 0x01) */
/* ================================================ USBPHY_DIRECT_OVERRIDE ================================================= */
#define USBCTRL_REGS_USBPHY_DIRECT_OVERRIDE_TX_DIFFMODE_OVERRIDE_EN_Pos (15UL) /*!< TX_DIFFMODE_OVERRIDE_EN (Bit 15) */
#define USBCTRL_REGS_USBPHY_DIRECT_OVERRIDE_TX_DIFFMODE_OVERRIDE_EN_Msk (0x8000UL) /*!< TX_DIFFMODE_OVERRIDE_EN (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_OVERRIDE_EN_Pos (12UL) /*!< DM_PULLUP_OVERRIDE_EN (Bit 12) */
#define USBCTRL_REGS_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_OVERRIDE_EN_Msk (0x1000UL) /*!< DM_PULLUP_OVERRIDE_EN (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_USBPHY_DIRECT_OVERRIDE_TX_FSSLEW_OVERRIDE_EN_Pos (11UL) /*!< TX_FSSLEW_OVERRIDE_EN (Bit 11) */
#define USBCTRL_REGS_USBPHY_DIRECT_OVERRIDE_TX_FSSLEW_OVERRIDE_EN_Msk (0x800UL) /*!< TX_FSSLEW_OVERRIDE_EN (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_USBPHY_DIRECT_OVERRIDE_TX_PD_OVERRIDE_EN_Pos (10UL) /*!< TX_PD_OVERRIDE_EN (Bit 10) */
#define USBCTRL_REGS_USBPHY_DIRECT_OVERRIDE_TX_PD_OVERRIDE_EN_Msk (0x400UL) /*!< TX_PD_OVERRIDE_EN (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_USBPHY_DIRECT_OVERRIDE_RX_PD_OVERRIDE_EN_Pos (9UL) /*!< RX_PD_OVERRIDE_EN (Bit 9) */
#define USBCTRL_REGS_USBPHY_DIRECT_OVERRIDE_RX_PD_OVERRIDE_EN_Msk (0x200UL) /*!< RX_PD_OVERRIDE_EN (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_USBPHY_DIRECT_OVERRIDE_TX_DM_OVERRIDE_EN_Pos (8UL) /*!< TX_DM_OVERRIDE_EN (Bit 8) */
#define USBCTRL_REGS_USBPHY_DIRECT_OVERRIDE_TX_DM_OVERRIDE_EN_Msk (0x100UL) /*!< TX_DM_OVERRIDE_EN (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_USBPHY_DIRECT_OVERRIDE_TX_DP_OVERRIDE_EN_Pos (7UL) /*!< TX_DP_OVERRIDE_EN (Bit 7) */
#define USBCTRL_REGS_USBPHY_DIRECT_OVERRIDE_TX_DP_OVERRIDE_EN_Msk (0x80UL) /*!< TX_DP_OVERRIDE_EN (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_USBPHY_DIRECT_OVERRIDE_TX_DM_OE_OVERRIDE_EN_Pos (6UL) /*!< TX_DM_OE_OVERRIDE_EN (Bit 6) */
#define USBCTRL_REGS_USBPHY_DIRECT_OVERRIDE_TX_DM_OE_OVERRIDE_EN_Msk (0x40UL) /*!< TX_DM_OE_OVERRIDE_EN (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_USBPHY_DIRECT_OVERRIDE_TX_DP_OE_OVERRIDE_EN_Pos (5UL) /*!< TX_DP_OE_OVERRIDE_EN (Bit 5) */
#define USBCTRL_REGS_USBPHY_DIRECT_OVERRIDE_TX_DP_OE_OVERRIDE_EN_Msk (0x20UL) /*!< TX_DP_OE_OVERRIDE_EN (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_USBPHY_DIRECT_OVERRIDE_DM_PULLDN_EN_OVERRIDE_EN_Pos (4UL) /*!< DM_PULLDN_EN_OVERRIDE_EN (Bit 4) */
#define USBCTRL_REGS_USBPHY_DIRECT_OVERRIDE_DM_PULLDN_EN_OVERRIDE_EN_Msk (0x10UL) /*!< DM_PULLDN_EN_OVERRIDE_EN (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_USBPHY_DIRECT_OVERRIDE_DP_PULLDN_EN_OVERRIDE_EN_Pos (3UL) /*!< DP_PULLDN_EN_OVERRIDE_EN (Bit 3) */
#define USBCTRL_REGS_USBPHY_DIRECT_OVERRIDE_DP_PULLDN_EN_OVERRIDE_EN_Msk (0x8UL) /*!< DP_PULLDN_EN_OVERRIDE_EN (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN_Pos (2UL) /*!< DP_PULLUP_EN_OVERRIDE_EN (Bit 2) */
#define USBCTRL_REGS_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN_Msk (0x4UL) /*!< DP_PULLUP_EN_OVERRIDE_EN (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_HISEL_OVERRIDE_EN_Pos (1UL) /*!< DM_PULLUP_HISEL_OVERRIDE_EN (Bit 1) */
#define USBCTRL_REGS_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_HISEL_OVERRIDE_EN_Msk (0x2UL) /*!< DM_PULLUP_HISEL_OVERRIDE_EN (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_HISEL_OVERRIDE_EN_Pos (0UL) /*!< DP_PULLUP_HISEL_OVERRIDE_EN (Bit 0) */
#define USBCTRL_REGS_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_HISEL_OVERRIDE_EN_Msk (0x1UL) /*!< DP_PULLUP_HISEL_OVERRIDE_EN (Bitfield-Mask: 0x01) */
/* ====================================================== USBPHY_TRIM ====================================================== */
#define USBCTRL_REGS_USBPHY_TRIM_DM_PULLDN_TRIM_Pos (8UL) /*!< DM_PULLDN_TRIM (Bit 8) */
#define USBCTRL_REGS_USBPHY_TRIM_DM_PULLDN_TRIM_Msk (0x1f00UL) /*!< DM_PULLDN_TRIM (Bitfield-Mask: 0x1f) */
#define USBCTRL_REGS_USBPHY_TRIM_DP_PULLDN_TRIM_Pos (0UL) /*!< DP_PULLDN_TRIM (Bit 0) */
#define USBCTRL_REGS_USBPHY_TRIM_DP_PULLDN_TRIM_Msk (0x1fUL) /*!< DP_PULLDN_TRIM (Bitfield-Mask: 0x1f) */
/* ========================================================= INTR ========================================================== */
#define USBCTRL_REGS_INTR_EP_STALL_NAK_Pos (19UL) /*!< EP_STALL_NAK (Bit 19) */
#define USBCTRL_REGS_INTR_EP_STALL_NAK_Msk (0x80000UL) /*!< EP_STALL_NAK (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_INTR_ABORT_DONE_Pos (18UL) /*!< ABORT_DONE (Bit 18) */
#define USBCTRL_REGS_INTR_ABORT_DONE_Msk (0x40000UL) /*!< ABORT_DONE (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_INTR_DEV_SOF_Pos (17UL) /*!< DEV_SOF (Bit 17) */
#define USBCTRL_REGS_INTR_DEV_SOF_Msk (0x20000UL) /*!< DEV_SOF (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_INTR_SETUP_REQ_Pos (16UL) /*!< SETUP_REQ (Bit 16) */
#define USBCTRL_REGS_INTR_SETUP_REQ_Msk (0x10000UL) /*!< SETUP_REQ (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_INTR_DEV_RESUME_FROM_HOST_Pos (15UL) /*!< DEV_RESUME_FROM_HOST (Bit 15) */
#define USBCTRL_REGS_INTR_DEV_RESUME_FROM_HOST_Msk (0x8000UL) /*!< DEV_RESUME_FROM_HOST (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_INTR_DEV_SUSPEND_Pos (14UL) /*!< DEV_SUSPEND (Bit 14) */
#define USBCTRL_REGS_INTR_DEV_SUSPEND_Msk (0x4000UL) /*!< DEV_SUSPEND (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_INTR_DEV_CONN_DIS_Pos (13UL) /*!< DEV_CONN_DIS (Bit 13) */
#define USBCTRL_REGS_INTR_DEV_CONN_DIS_Msk (0x2000UL) /*!< DEV_CONN_DIS (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_INTR_BUS_RESET_Pos (12UL) /*!< BUS_RESET (Bit 12) */
#define USBCTRL_REGS_INTR_BUS_RESET_Msk (0x1000UL) /*!< BUS_RESET (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_INTR_VBUS_DETECT_Pos (11UL) /*!< VBUS_DETECT (Bit 11) */
#define USBCTRL_REGS_INTR_VBUS_DETECT_Msk (0x800UL) /*!< VBUS_DETECT (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_INTR_STALL_Pos (10UL) /*!< STALL (Bit 10) */
#define USBCTRL_REGS_INTR_STALL_Msk (0x400UL) /*!< STALL (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_INTR_ERROR_CRC_Pos (9UL) /*!< ERROR_CRC (Bit 9) */
#define USBCTRL_REGS_INTR_ERROR_CRC_Msk (0x200UL) /*!< ERROR_CRC (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_INTR_ERROR_BIT_STUFF_Pos (8UL) /*!< ERROR_BIT_STUFF (Bit 8) */
#define USBCTRL_REGS_INTR_ERROR_BIT_STUFF_Msk (0x100UL) /*!< ERROR_BIT_STUFF (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_INTR_ERROR_RX_OVERFLOW_Pos (7UL) /*!< ERROR_RX_OVERFLOW (Bit 7) */
#define USBCTRL_REGS_INTR_ERROR_RX_OVERFLOW_Msk (0x80UL) /*!< ERROR_RX_OVERFLOW (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_INTR_ERROR_RX_TIMEOUT_Pos (6UL) /*!< ERROR_RX_TIMEOUT (Bit 6) */
#define USBCTRL_REGS_INTR_ERROR_RX_TIMEOUT_Msk (0x40UL) /*!< ERROR_RX_TIMEOUT (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_INTR_ERROR_DATA_SEQ_Pos (5UL) /*!< ERROR_DATA_SEQ (Bit 5) */
#define USBCTRL_REGS_INTR_ERROR_DATA_SEQ_Msk (0x20UL) /*!< ERROR_DATA_SEQ (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_INTR_BUFF_STATUS_Pos (4UL) /*!< BUFF_STATUS (Bit 4) */
#define USBCTRL_REGS_INTR_BUFF_STATUS_Msk (0x10UL) /*!< BUFF_STATUS (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_INTR_TRANS_COMPLETE_Pos (3UL) /*!< TRANS_COMPLETE (Bit 3) */
#define USBCTRL_REGS_INTR_TRANS_COMPLETE_Msk (0x8UL) /*!< TRANS_COMPLETE (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_INTR_HOST_SOF_Pos (2UL) /*!< HOST_SOF (Bit 2) */
#define USBCTRL_REGS_INTR_HOST_SOF_Msk (0x4UL) /*!< HOST_SOF (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_INTR_HOST_RESUME_Pos (1UL) /*!< HOST_RESUME (Bit 1) */
#define USBCTRL_REGS_INTR_HOST_RESUME_Msk (0x2UL) /*!< HOST_RESUME (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_INTR_HOST_CONN_DIS_Pos (0UL) /*!< HOST_CONN_DIS (Bit 0) */
#define USBCTRL_REGS_INTR_HOST_CONN_DIS_Msk (0x1UL) /*!< HOST_CONN_DIS (Bitfield-Mask: 0x01) */
/* ========================================================= INTE ========================================================== */
#define USBCTRL_REGS_INTE_EP_STALL_NAK_Pos (19UL) /*!< EP_STALL_NAK (Bit 19) */
#define USBCTRL_REGS_INTE_EP_STALL_NAK_Msk (0x80000UL) /*!< EP_STALL_NAK (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_INTE_ABORT_DONE_Pos (18UL) /*!< ABORT_DONE (Bit 18) */
#define USBCTRL_REGS_INTE_ABORT_DONE_Msk (0x40000UL) /*!< ABORT_DONE (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_INTE_DEV_SOF_Pos (17UL) /*!< DEV_SOF (Bit 17) */
#define USBCTRL_REGS_INTE_DEV_SOF_Msk (0x20000UL) /*!< DEV_SOF (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_INTE_SETUP_REQ_Pos (16UL) /*!< SETUP_REQ (Bit 16) */
#define USBCTRL_REGS_INTE_SETUP_REQ_Msk (0x10000UL) /*!< SETUP_REQ (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_INTE_DEV_RESUME_FROM_HOST_Pos (15UL) /*!< DEV_RESUME_FROM_HOST (Bit 15) */
#define USBCTRL_REGS_INTE_DEV_RESUME_FROM_HOST_Msk (0x8000UL) /*!< DEV_RESUME_FROM_HOST (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_INTE_DEV_SUSPEND_Pos (14UL) /*!< DEV_SUSPEND (Bit 14) */
#define USBCTRL_REGS_INTE_DEV_SUSPEND_Msk (0x4000UL) /*!< DEV_SUSPEND (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_INTE_DEV_CONN_DIS_Pos (13UL) /*!< DEV_CONN_DIS (Bit 13) */
#define USBCTRL_REGS_INTE_DEV_CONN_DIS_Msk (0x2000UL) /*!< DEV_CONN_DIS (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_INTE_BUS_RESET_Pos (12UL) /*!< BUS_RESET (Bit 12) */
#define USBCTRL_REGS_INTE_BUS_RESET_Msk (0x1000UL) /*!< BUS_RESET (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_INTE_VBUS_DETECT_Pos (11UL) /*!< VBUS_DETECT (Bit 11) */
#define USBCTRL_REGS_INTE_VBUS_DETECT_Msk (0x800UL) /*!< VBUS_DETECT (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_INTE_STALL_Pos (10UL) /*!< STALL (Bit 10) */
#define USBCTRL_REGS_INTE_STALL_Msk (0x400UL) /*!< STALL (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_INTE_ERROR_CRC_Pos (9UL) /*!< ERROR_CRC (Bit 9) */
#define USBCTRL_REGS_INTE_ERROR_CRC_Msk (0x200UL) /*!< ERROR_CRC (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_INTE_ERROR_BIT_STUFF_Pos (8UL) /*!< ERROR_BIT_STUFF (Bit 8) */
#define USBCTRL_REGS_INTE_ERROR_BIT_STUFF_Msk (0x100UL) /*!< ERROR_BIT_STUFF (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_INTE_ERROR_RX_OVERFLOW_Pos (7UL) /*!< ERROR_RX_OVERFLOW (Bit 7) */
#define USBCTRL_REGS_INTE_ERROR_RX_OVERFLOW_Msk (0x80UL) /*!< ERROR_RX_OVERFLOW (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_INTE_ERROR_RX_TIMEOUT_Pos (6UL) /*!< ERROR_RX_TIMEOUT (Bit 6) */
#define USBCTRL_REGS_INTE_ERROR_RX_TIMEOUT_Msk (0x40UL) /*!< ERROR_RX_TIMEOUT (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_INTE_ERROR_DATA_SEQ_Pos (5UL) /*!< ERROR_DATA_SEQ (Bit 5) */
#define USBCTRL_REGS_INTE_ERROR_DATA_SEQ_Msk (0x20UL) /*!< ERROR_DATA_SEQ (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_INTE_BUFF_STATUS_Pos (4UL) /*!< BUFF_STATUS (Bit 4) */
#define USBCTRL_REGS_INTE_BUFF_STATUS_Msk (0x10UL) /*!< BUFF_STATUS (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_INTE_TRANS_COMPLETE_Pos (3UL) /*!< TRANS_COMPLETE (Bit 3) */
#define USBCTRL_REGS_INTE_TRANS_COMPLETE_Msk (0x8UL) /*!< TRANS_COMPLETE (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_INTE_HOST_SOF_Pos (2UL) /*!< HOST_SOF (Bit 2) */
#define USBCTRL_REGS_INTE_HOST_SOF_Msk (0x4UL) /*!< HOST_SOF (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_INTE_HOST_RESUME_Pos (1UL) /*!< HOST_RESUME (Bit 1) */
#define USBCTRL_REGS_INTE_HOST_RESUME_Msk (0x2UL) /*!< HOST_RESUME (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_INTE_HOST_CONN_DIS_Pos (0UL) /*!< HOST_CONN_DIS (Bit 0) */
#define USBCTRL_REGS_INTE_HOST_CONN_DIS_Msk (0x1UL) /*!< HOST_CONN_DIS (Bitfield-Mask: 0x01) */
/* ========================================================= INTF ========================================================== */
#define USBCTRL_REGS_INTF_EP_STALL_NAK_Pos (19UL) /*!< EP_STALL_NAK (Bit 19) */
#define USBCTRL_REGS_INTF_EP_STALL_NAK_Msk (0x80000UL) /*!< EP_STALL_NAK (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_INTF_ABORT_DONE_Pos (18UL) /*!< ABORT_DONE (Bit 18) */
#define USBCTRL_REGS_INTF_ABORT_DONE_Msk (0x40000UL) /*!< ABORT_DONE (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_INTF_DEV_SOF_Pos (17UL) /*!< DEV_SOF (Bit 17) */
#define USBCTRL_REGS_INTF_DEV_SOF_Msk (0x20000UL) /*!< DEV_SOF (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_INTF_SETUP_REQ_Pos (16UL) /*!< SETUP_REQ (Bit 16) */
#define USBCTRL_REGS_INTF_SETUP_REQ_Msk (0x10000UL) /*!< SETUP_REQ (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_INTF_DEV_RESUME_FROM_HOST_Pos (15UL) /*!< DEV_RESUME_FROM_HOST (Bit 15) */
#define USBCTRL_REGS_INTF_DEV_RESUME_FROM_HOST_Msk (0x8000UL) /*!< DEV_RESUME_FROM_HOST (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_INTF_DEV_SUSPEND_Pos (14UL) /*!< DEV_SUSPEND (Bit 14) */
#define USBCTRL_REGS_INTF_DEV_SUSPEND_Msk (0x4000UL) /*!< DEV_SUSPEND (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_INTF_DEV_CONN_DIS_Pos (13UL) /*!< DEV_CONN_DIS (Bit 13) */
#define USBCTRL_REGS_INTF_DEV_CONN_DIS_Msk (0x2000UL) /*!< DEV_CONN_DIS (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_INTF_BUS_RESET_Pos (12UL) /*!< BUS_RESET (Bit 12) */
#define USBCTRL_REGS_INTF_BUS_RESET_Msk (0x1000UL) /*!< BUS_RESET (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_INTF_VBUS_DETECT_Pos (11UL) /*!< VBUS_DETECT (Bit 11) */
#define USBCTRL_REGS_INTF_VBUS_DETECT_Msk (0x800UL) /*!< VBUS_DETECT (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_INTF_STALL_Pos (10UL) /*!< STALL (Bit 10) */
#define USBCTRL_REGS_INTF_STALL_Msk (0x400UL) /*!< STALL (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_INTF_ERROR_CRC_Pos (9UL) /*!< ERROR_CRC (Bit 9) */
#define USBCTRL_REGS_INTF_ERROR_CRC_Msk (0x200UL) /*!< ERROR_CRC (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_INTF_ERROR_BIT_STUFF_Pos (8UL) /*!< ERROR_BIT_STUFF (Bit 8) */
#define USBCTRL_REGS_INTF_ERROR_BIT_STUFF_Msk (0x100UL) /*!< ERROR_BIT_STUFF (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_INTF_ERROR_RX_OVERFLOW_Pos (7UL) /*!< ERROR_RX_OVERFLOW (Bit 7) */
#define USBCTRL_REGS_INTF_ERROR_RX_OVERFLOW_Msk (0x80UL) /*!< ERROR_RX_OVERFLOW (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_INTF_ERROR_RX_TIMEOUT_Pos (6UL) /*!< ERROR_RX_TIMEOUT (Bit 6) */
#define USBCTRL_REGS_INTF_ERROR_RX_TIMEOUT_Msk (0x40UL) /*!< ERROR_RX_TIMEOUT (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_INTF_ERROR_DATA_SEQ_Pos (5UL) /*!< ERROR_DATA_SEQ (Bit 5) */
#define USBCTRL_REGS_INTF_ERROR_DATA_SEQ_Msk (0x20UL) /*!< ERROR_DATA_SEQ (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_INTF_BUFF_STATUS_Pos (4UL) /*!< BUFF_STATUS (Bit 4) */
#define USBCTRL_REGS_INTF_BUFF_STATUS_Msk (0x10UL) /*!< BUFF_STATUS (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_INTF_TRANS_COMPLETE_Pos (3UL) /*!< TRANS_COMPLETE (Bit 3) */
#define USBCTRL_REGS_INTF_TRANS_COMPLETE_Msk (0x8UL) /*!< TRANS_COMPLETE (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_INTF_HOST_SOF_Pos (2UL) /*!< HOST_SOF (Bit 2) */
#define USBCTRL_REGS_INTF_HOST_SOF_Msk (0x4UL) /*!< HOST_SOF (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_INTF_HOST_RESUME_Pos (1UL) /*!< HOST_RESUME (Bit 1) */
#define USBCTRL_REGS_INTF_HOST_RESUME_Msk (0x2UL) /*!< HOST_RESUME (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_INTF_HOST_CONN_DIS_Pos (0UL) /*!< HOST_CONN_DIS (Bit 0) */
#define USBCTRL_REGS_INTF_HOST_CONN_DIS_Msk (0x1UL) /*!< HOST_CONN_DIS (Bitfield-Mask: 0x01) */
/* ========================================================= INTS ========================================================== */
#define USBCTRL_REGS_INTS_EP_STALL_NAK_Pos (19UL) /*!< EP_STALL_NAK (Bit 19) */
#define USBCTRL_REGS_INTS_EP_STALL_NAK_Msk (0x80000UL) /*!< EP_STALL_NAK (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_INTS_ABORT_DONE_Pos (18UL) /*!< ABORT_DONE (Bit 18) */
#define USBCTRL_REGS_INTS_ABORT_DONE_Msk (0x40000UL) /*!< ABORT_DONE (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_INTS_DEV_SOF_Pos (17UL) /*!< DEV_SOF (Bit 17) */
#define USBCTRL_REGS_INTS_DEV_SOF_Msk (0x20000UL) /*!< DEV_SOF (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_INTS_SETUP_REQ_Pos (16UL) /*!< SETUP_REQ (Bit 16) */
#define USBCTRL_REGS_INTS_SETUP_REQ_Msk (0x10000UL) /*!< SETUP_REQ (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_INTS_DEV_RESUME_FROM_HOST_Pos (15UL) /*!< DEV_RESUME_FROM_HOST (Bit 15) */
#define USBCTRL_REGS_INTS_DEV_RESUME_FROM_HOST_Msk (0x8000UL) /*!< DEV_RESUME_FROM_HOST (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_INTS_DEV_SUSPEND_Pos (14UL) /*!< DEV_SUSPEND (Bit 14) */
#define USBCTRL_REGS_INTS_DEV_SUSPEND_Msk (0x4000UL) /*!< DEV_SUSPEND (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_INTS_DEV_CONN_DIS_Pos (13UL) /*!< DEV_CONN_DIS (Bit 13) */
#define USBCTRL_REGS_INTS_DEV_CONN_DIS_Msk (0x2000UL) /*!< DEV_CONN_DIS (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_INTS_BUS_RESET_Pos (12UL) /*!< BUS_RESET (Bit 12) */
#define USBCTRL_REGS_INTS_BUS_RESET_Msk (0x1000UL) /*!< BUS_RESET (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_INTS_VBUS_DETECT_Pos (11UL) /*!< VBUS_DETECT (Bit 11) */
#define USBCTRL_REGS_INTS_VBUS_DETECT_Msk (0x800UL) /*!< VBUS_DETECT (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_INTS_STALL_Pos (10UL) /*!< STALL (Bit 10) */
#define USBCTRL_REGS_INTS_STALL_Msk (0x400UL) /*!< STALL (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_INTS_ERROR_CRC_Pos (9UL) /*!< ERROR_CRC (Bit 9) */
#define USBCTRL_REGS_INTS_ERROR_CRC_Msk (0x200UL) /*!< ERROR_CRC (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_INTS_ERROR_BIT_STUFF_Pos (8UL) /*!< ERROR_BIT_STUFF (Bit 8) */
#define USBCTRL_REGS_INTS_ERROR_BIT_STUFF_Msk (0x100UL) /*!< ERROR_BIT_STUFF (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_INTS_ERROR_RX_OVERFLOW_Pos (7UL) /*!< ERROR_RX_OVERFLOW (Bit 7) */
#define USBCTRL_REGS_INTS_ERROR_RX_OVERFLOW_Msk (0x80UL) /*!< ERROR_RX_OVERFLOW (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_INTS_ERROR_RX_TIMEOUT_Pos (6UL) /*!< ERROR_RX_TIMEOUT (Bit 6) */
#define USBCTRL_REGS_INTS_ERROR_RX_TIMEOUT_Msk (0x40UL) /*!< ERROR_RX_TIMEOUT (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_INTS_ERROR_DATA_SEQ_Pos (5UL) /*!< ERROR_DATA_SEQ (Bit 5) */
#define USBCTRL_REGS_INTS_ERROR_DATA_SEQ_Msk (0x20UL) /*!< ERROR_DATA_SEQ (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_INTS_BUFF_STATUS_Pos (4UL) /*!< BUFF_STATUS (Bit 4) */
#define USBCTRL_REGS_INTS_BUFF_STATUS_Msk (0x10UL) /*!< BUFF_STATUS (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_INTS_TRANS_COMPLETE_Pos (3UL) /*!< TRANS_COMPLETE (Bit 3) */
#define USBCTRL_REGS_INTS_TRANS_COMPLETE_Msk (0x8UL) /*!< TRANS_COMPLETE (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_INTS_HOST_SOF_Pos (2UL) /*!< HOST_SOF (Bit 2) */
#define USBCTRL_REGS_INTS_HOST_SOF_Msk (0x4UL) /*!< HOST_SOF (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_INTS_HOST_RESUME_Pos (1UL) /*!< HOST_RESUME (Bit 1) */
#define USBCTRL_REGS_INTS_HOST_RESUME_Msk (0x2UL) /*!< HOST_RESUME (Bitfield-Mask: 0x01) */
#define USBCTRL_REGS_INTS_HOST_CONN_DIS_Pos (0UL) /*!< HOST_CONN_DIS (Bit 0) */
#define USBCTRL_REGS_INTS_HOST_CONN_DIS_Msk (0x1UL) /*!< HOST_CONN_DIS (Bitfield-Mask: 0x01) */
/* =========================================================================================================================== */
/* ================ PIO0 ================ */
/* =========================================================================================================================== */
/* ========================================================= CTRL ========================================================== */
#define PIO0_CTRL_CLKDIV_RESTART_Pos (8UL) /*!< CLKDIV_RESTART (Bit 8) */
#define PIO0_CTRL_CLKDIV_RESTART_Msk (0xf00UL) /*!< CLKDIV_RESTART (Bitfield-Mask: 0x0f) */
#define PIO0_CTRL_SM_RESTART_Pos (4UL) /*!< SM_RESTART (Bit 4) */
#define PIO0_CTRL_SM_RESTART_Msk (0xf0UL) /*!< SM_RESTART (Bitfield-Mask: 0x0f) */
#define PIO0_CTRL_SM_ENABLE_Pos (0UL) /*!< SM_ENABLE (Bit 0) */
#define PIO0_CTRL_SM_ENABLE_Msk (0xfUL) /*!< SM_ENABLE (Bitfield-Mask: 0x0f) */
/* ========================================================= FSTAT ========================================================= */
#define PIO0_FSTAT_TXEMPTY_Pos (24UL) /*!< TXEMPTY (Bit 24) */
#define PIO0_FSTAT_TXEMPTY_Msk (0xf000000UL) /*!< TXEMPTY (Bitfield-Mask: 0x0f) */
#define PIO0_FSTAT_TXFULL_Pos (16UL) /*!< TXFULL (Bit 16) */
#define PIO0_FSTAT_TXFULL_Msk (0xf0000UL) /*!< TXFULL (Bitfield-Mask: 0x0f) */
#define PIO0_FSTAT_RXEMPTY_Pos (8UL) /*!< RXEMPTY (Bit 8) */
#define PIO0_FSTAT_RXEMPTY_Msk (0xf00UL) /*!< RXEMPTY (Bitfield-Mask: 0x0f) */
#define PIO0_FSTAT_RXFULL_Pos (0UL) /*!< RXFULL (Bit 0) */
#define PIO0_FSTAT_RXFULL_Msk (0xfUL) /*!< RXFULL (Bitfield-Mask: 0x0f) */
/* ======================================================== FDEBUG ========================================================= */
#define PIO0_FDEBUG_TXSTALL_Pos (24UL) /*!< TXSTALL (Bit 24) */
#define PIO0_FDEBUG_TXSTALL_Msk (0xf000000UL) /*!< TXSTALL (Bitfield-Mask: 0x0f) */
#define PIO0_FDEBUG_TXOVER_Pos (16UL) /*!< TXOVER (Bit 16) */
#define PIO0_FDEBUG_TXOVER_Msk (0xf0000UL) /*!< TXOVER (Bitfield-Mask: 0x0f) */
#define PIO0_FDEBUG_RXUNDER_Pos (8UL) /*!< RXUNDER (Bit 8) */
#define PIO0_FDEBUG_RXUNDER_Msk (0xf00UL) /*!< RXUNDER (Bitfield-Mask: 0x0f) */
#define PIO0_FDEBUG_RXSTALL_Pos (0UL) /*!< RXSTALL (Bit 0) */
#define PIO0_FDEBUG_RXSTALL_Msk (0xfUL) /*!< RXSTALL (Bitfield-Mask: 0x0f) */
/* ======================================================== FLEVEL ========================================================= */
#define PIO0_FLEVEL_RX3_Pos (28UL) /*!< RX3 (Bit 28) */
#define PIO0_FLEVEL_RX3_Msk (0xf0000000UL) /*!< RX3 (Bitfield-Mask: 0x0f) */
#define PIO0_FLEVEL_TX3_Pos (24UL) /*!< TX3 (Bit 24) */
#define PIO0_FLEVEL_TX3_Msk (0xf000000UL) /*!< TX3 (Bitfield-Mask: 0x0f) */
#define PIO0_FLEVEL_RX2_Pos (20UL) /*!< RX2 (Bit 20) */
#define PIO0_FLEVEL_RX2_Msk (0xf00000UL) /*!< RX2 (Bitfield-Mask: 0x0f) */
#define PIO0_FLEVEL_TX2_Pos (16UL) /*!< TX2 (Bit 16) */
#define PIO0_FLEVEL_TX2_Msk (0xf0000UL) /*!< TX2 (Bitfield-Mask: 0x0f) */
#define PIO0_FLEVEL_RX1_Pos (12UL) /*!< RX1 (Bit 12) */
#define PIO0_FLEVEL_RX1_Msk (0xf000UL) /*!< RX1 (Bitfield-Mask: 0x0f) */
#define PIO0_FLEVEL_TX1_Pos (8UL) /*!< TX1 (Bit 8) */
#define PIO0_FLEVEL_TX1_Msk (0xf00UL) /*!< TX1 (Bitfield-Mask: 0x0f) */
#define PIO0_FLEVEL_RX0_Pos (4UL) /*!< RX0 (Bit 4) */
#define PIO0_FLEVEL_RX0_Msk (0xf0UL) /*!< RX0 (Bitfield-Mask: 0x0f) */
#define PIO0_FLEVEL_TX0_Pos (0UL) /*!< TX0 (Bit 0) */
#define PIO0_FLEVEL_TX0_Msk (0xfUL) /*!< TX0 (Bitfield-Mask: 0x0f) */
/* ========================================================= TXF0 ========================================================== */
/* ========================================================= TXF1 ========================================================== */
/* ========================================================= TXF2 ========================================================== */
/* ========================================================= TXF3 ========================================================== */
/* ========================================================= RXF0 ========================================================== */
/* ========================================================= RXF1 ========================================================== */
/* ========================================================= RXF2 ========================================================== */
/* ========================================================= RXF3 ========================================================== */
/* ========================================================== IRQ ========================================================== */
#define PIO0_IRQ_IRQ_Pos (0UL) /*!< IRQ (Bit 0) */
#define PIO0_IRQ_IRQ_Msk (0xffUL) /*!< IRQ (Bitfield-Mask: 0xff) */
/* ======================================================= IRQ_FORCE ======================================================= */
#define PIO0_IRQ_FORCE_IRQ_FORCE_Pos (0UL) /*!< IRQ_FORCE (Bit 0) */
#define PIO0_IRQ_FORCE_IRQ_FORCE_Msk (0xffUL) /*!< IRQ_FORCE (Bitfield-Mask: 0xff) */
/* =================================================== INPUT_SYNC_BYPASS =================================================== */
/* ====================================================== DBG_PADOUT ======================================================= */
/* ======================================================= DBG_PADOE ======================================================= */
/* ====================================================== DBG_CFGINFO ====================================================== */
#define PIO0_DBG_CFGINFO_IMEM_SIZE_Pos (16UL) /*!< IMEM_SIZE (Bit 16) */
#define PIO0_DBG_CFGINFO_IMEM_SIZE_Msk (0x3f0000UL) /*!< IMEM_SIZE (Bitfield-Mask: 0x3f) */
#define PIO0_DBG_CFGINFO_SM_COUNT_Pos (8UL) /*!< SM_COUNT (Bit 8) */
#define PIO0_DBG_CFGINFO_SM_COUNT_Msk (0xf00UL) /*!< SM_COUNT (Bitfield-Mask: 0x0f) */
#define PIO0_DBG_CFGINFO_FIFO_DEPTH_Pos (0UL) /*!< FIFO_DEPTH (Bit 0) */
#define PIO0_DBG_CFGINFO_FIFO_DEPTH_Msk (0x3fUL) /*!< FIFO_DEPTH (Bitfield-Mask: 0x3f) */
/* ====================================================== INSTR_MEM0 ======================================================= */
#define PIO0_INSTR_MEM0_INSTR_MEM0_Pos (0UL) /*!< INSTR_MEM0 (Bit 0) */
#define PIO0_INSTR_MEM0_INSTR_MEM0_Msk (0xffffUL) /*!< INSTR_MEM0 (Bitfield-Mask: 0xffff) */
/* ====================================================== INSTR_MEM1 ======================================================= */
#define PIO0_INSTR_MEM1_INSTR_MEM1_Pos (0UL) /*!< INSTR_MEM1 (Bit 0) */
#define PIO0_INSTR_MEM1_INSTR_MEM1_Msk (0xffffUL) /*!< INSTR_MEM1 (Bitfield-Mask: 0xffff) */
/* ====================================================== INSTR_MEM2 ======================================================= */
#define PIO0_INSTR_MEM2_INSTR_MEM2_Pos (0UL) /*!< INSTR_MEM2 (Bit 0) */
#define PIO0_INSTR_MEM2_INSTR_MEM2_Msk (0xffffUL) /*!< INSTR_MEM2 (Bitfield-Mask: 0xffff) */
/* ====================================================== INSTR_MEM3 ======================================================= */
#define PIO0_INSTR_MEM3_INSTR_MEM3_Pos (0UL) /*!< INSTR_MEM3 (Bit 0) */
#define PIO0_INSTR_MEM3_INSTR_MEM3_Msk (0xffffUL) /*!< INSTR_MEM3 (Bitfield-Mask: 0xffff) */
/* ====================================================== INSTR_MEM4 ======================================================= */
#define PIO0_INSTR_MEM4_INSTR_MEM4_Pos (0UL) /*!< INSTR_MEM4 (Bit 0) */
#define PIO0_INSTR_MEM4_INSTR_MEM4_Msk (0xffffUL) /*!< INSTR_MEM4 (Bitfield-Mask: 0xffff) */
/* ====================================================== INSTR_MEM5 ======================================================= */
#define PIO0_INSTR_MEM5_INSTR_MEM5_Pos (0UL) /*!< INSTR_MEM5 (Bit 0) */
#define PIO0_INSTR_MEM5_INSTR_MEM5_Msk (0xffffUL) /*!< INSTR_MEM5 (Bitfield-Mask: 0xffff) */
/* ====================================================== INSTR_MEM6 ======================================================= */
#define PIO0_INSTR_MEM6_INSTR_MEM6_Pos (0UL) /*!< INSTR_MEM6 (Bit 0) */
#define PIO0_INSTR_MEM6_INSTR_MEM6_Msk (0xffffUL) /*!< INSTR_MEM6 (Bitfield-Mask: 0xffff) */
/* ====================================================== INSTR_MEM7 ======================================================= */
#define PIO0_INSTR_MEM7_INSTR_MEM7_Pos (0UL) /*!< INSTR_MEM7 (Bit 0) */
#define PIO0_INSTR_MEM7_INSTR_MEM7_Msk (0xffffUL) /*!< INSTR_MEM7 (Bitfield-Mask: 0xffff) */
/* ====================================================== INSTR_MEM8 ======================================================= */
#define PIO0_INSTR_MEM8_INSTR_MEM8_Pos (0UL) /*!< INSTR_MEM8 (Bit 0) */
#define PIO0_INSTR_MEM8_INSTR_MEM8_Msk (0xffffUL) /*!< INSTR_MEM8 (Bitfield-Mask: 0xffff) */
/* ====================================================== INSTR_MEM9 ======================================================= */
#define PIO0_INSTR_MEM9_INSTR_MEM9_Pos (0UL) /*!< INSTR_MEM9 (Bit 0) */
#define PIO0_INSTR_MEM9_INSTR_MEM9_Msk (0xffffUL) /*!< INSTR_MEM9 (Bitfield-Mask: 0xffff) */
/* ====================================================== INSTR_MEM10 ====================================================== */
#define PIO0_INSTR_MEM10_INSTR_MEM10_Pos (0UL) /*!< INSTR_MEM10 (Bit 0) */
#define PIO0_INSTR_MEM10_INSTR_MEM10_Msk (0xffffUL) /*!< INSTR_MEM10 (Bitfield-Mask: 0xffff) */
/* ====================================================== INSTR_MEM11 ====================================================== */
#define PIO0_INSTR_MEM11_INSTR_MEM11_Pos (0UL) /*!< INSTR_MEM11 (Bit 0) */
#define PIO0_INSTR_MEM11_INSTR_MEM11_Msk (0xffffUL) /*!< INSTR_MEM11 (Bitfield-Mask: 0xffff) */
/* ====================================================== INSTR_MEM12 ====================================================== */
#define PIO0_INSTR_MEM12_INSTR_MEM12_Pos (0UL) /*!< INSTR_MEM12 (Bit 0) */
#define PIO0_INSTR_MEM12_INSTR_MEM12_Msk (0xffffUL) /*!< INSTR_MEM12 (Bitfield-Mask: 0xffff) */
/* ====================================================== INSTR_MEM13 ====================================================== */
#define PIO0_INSTR_MEM13_INSTR_MEM13_Pos (0UL) /*!< INSTR_MEM13 (Bit 0) */
#define PIO0_INSTR_MEM13_INSTR_MEM13_Msk (0xffffUL) /*!< INSTR_MEM13 (Bitfield-Mask: 0xffff) */
/* ====================================================== INSTR_MEM14 ====================================================== */
#define PIO0_INSTR_MEM14_INSTR_MEM14_Pos (0UL) /*!< INSTR_MEM14 (Bit 0) */
#define PIO0_INSTR_MEM14_INSTR_MEM14_Msk (0xffffUL) /*!< INSTR_MEM14 (Bitfield-Mask: 0xffff) */
/* ====================================================== INSTR_MEM15 ====================================================== */
#define PIO0_INSTR_MEM15_INSTR_MEM15_Pos (0UL) /*!< INSTR_MEM15 (Bit 0) */
#define PIO0_INSTR_MEM15_INSTR_MEM15_Msk (0xffffUL) /*!< INSTR_MEM15 (Bitfield-Mask: 0xffff) */
/* ====================================================== INSTR_MEM16 ====================================================== */
#define PIO0_INSTR_MEM16_INSTR_MEM16_Pos (0UL) /*!< INSTR_MEM16 (Bit 0) */
#define PIO0_INSTR_MEM16_INSTR_MEM16_Msk (0xffffUL) /*!< INSTR_MEM16 (Bitfield-Mask: 0xffff) */
/* ====================================================== INSTR_MEM17 ====================================================== */
#define PIO0_INSTR_MEM17_INSTR_MEM17_Pos (0UL) /*!< INSTR_MEM17 (Bit 0) */
#define PIO0_INSTR_MEM17_INSTR_MEM17_Msk (0xffffUL) /*!< INSTR_MEM17 (Bitfield-Mask: 0xffff) */
/* ====================================================== INSTR_MEM18 ====================================================== */
#define PIO0_INSTR_MEM18_INSTR_MEM18_Pos (0UL) /*!< INSTR_MEM18 (Bit 0) */
#define PIO0_INSTR_MEM18_INSTR_MEM18_Msk (0xffffUL) /*!< INSTR_MEM18 (Bitfield-Mask: 0xffff) */
/* ====================================================== INSTR_MEM19 ====================================================== */
#define PIO0_INSTR_MEM19_INSTR_MEM19_Pos (0UL) /*!< INSTR_MEM19 (Bit 0) */
#define PIO0_INSTR_MEM19_INSTR_MEM19_Msk (0xffffUL) /*!< INSTR_MEM19 (Bitfield-Mask: 0xffff) */
/* ====================================================== INSTR_MEM20 ====================================================== */
#define PIO0_INSTR_MEM20_INSTR_MEM20_Pos (0UL) /*!< INSTR_MEM20 (Bit 0) */
#define PIO0_INSTR_MEM20_INSTR_MEM20_Msk (0xffffUL) /*!< INSTR_MEM20 (Bitfield-Mask: 0xffff) */
/* ====================================================== INSTR_MEM21 ====================================================== */
#define PIO0_INSTR_MEM21_INSTR_MEM21_Pos (0UL) /*!< INSTR_MEM21 (Bit 0) */
#define PIO0_INSTR_MEM21_INSTR_MEM21_Msk (0xffffUL) /*!< INSTR_MEM21 (Bitfield-Mask: 0xffff) */
/* ====================================================== INSTR_MEM22 ====================================================== */
#define PIO0_INSTR_MEM22_INSTR_MEM22_Pos (0UL) /*!< INSTR_MEM22 (Bit 0) */
#define PIO0_INSTR_MEM22_INSTR_MEM22_Msk (0xffffUL) /*!< INSTR_MEM22 (Bitfield-Mask: 0xffff) */
/* ====================================================== INSTR_MEM23 ====================================================== */
#define PIO0_INSTR_MEM23_INSTR_MEM23_Pos (0UL) /*!< INSTR_MEM23 (Bit 0) */
#define PIO0_INSTR_MEM23_INSTR_MEM23_Msk (0xffffUL) /*!< INSTR_MEM23 (Bitfield-Mask: 0xffff) */
/* ====================================================== INSTR_MEM24 ====================================================== */
#define PIO0_INSTR_MEM24_INSTR_MEM24_Pos (0UL) /*!< INSTR_MEM24 (Bit 0) */
#define PIO0_INSTR_MEM24_INSTR_MEM24_Msk (0xffffUL) /*!< INSTR_MEM24 (Bitfield-Mask: 0xffff) */
/* ====================================================== INSTR_MEM25 ====================================================== */
#define PIO0_INSTR_MEM25_INSTR_MEM25_Pos (0UL) /*!< INSTR_MEM25 (Bit 0) */
#define PIO0_INSTR_MEM25_INSTR_MEM25_Msk (0xffffUL) /*!< INSTR_MEM25 (Bitfield-Mask: 0xffff) */
/* ====================================================== INSTR_MEM26 ====================================================== */
#define PIO0_INSTR_MEM26_INSTR_MEM26_Pos (0UL) /*!< INSTR_MEM26 (Bit 0) */
#define PIO0_INSTR_MEM26_INSTR_MEM26_Msk (0xffffUL) /*!< INSTR_MEM26 (Bitfield-Mask: 0xffff) */
/* ====================================================== INSTR_MEM27 ====================================================== */
#define PIO0_INSTR_MEM27_INSTR_MEM27_Pos (0UL) /*!< INSTR_MEM27 (Bit 0) */
#define PIO0_INSTR_MEM27_INSTR_MEM27_Msk (0xffffUL) /*!< INSTR_MEM27 (Bitfield-Mask: 0xffff) */
/* ====================================================== INSTR_MEM28 ====================================================== */
#define PIO0_INSTR_MEM28_INSTR_MEM28_Pos (0UL) /*!< INSTR_MEM28 (Bit 0) */
#define PIO0_INSTR_MEM28_INSTR_MEM28_Msk (0xffffUL) /*!< INSTR_MEM28 (Bitfield-Mask: 0xffff) */
/* ====================================================== INSTR_MEM29 ====================================================== */
#define PIO0_INSTR_MEM29_INSTR_MEM29_Pos (0UL) /*!< INSTR_MEM29 (Bit 0) */
#define PIO0_INSTR_MEM29_INSTR_MEM29_Msk (0xffffUL) /*!< INSTR_MEM29 (Bitfield-Mask: 0xffff) */
/* ====================================================== INSTR_MEM30 ====================================================== */
#define PIO0_INSTR_MEM30_INSTR_MEM30_Pos (0UL) /*!< INSTR_MEM30 (Bit 0) */
#define PIO0_INSTR_MEM30_INSTR_MEM30_Msk (0xffffUL) /*!< INSTR_MEM30 (Bitfield-Mask: 0xffff) */
/* ====================================================== INSTR_MEM31 ====================================================== */
#define PIO0_INSTR_MEM31_INSTR_MEM31_Pos (0UL) /*!< INSTR_MEM31 (Bit 0) */
#define PIO0_INSTR_MEM31_INSTR_MEM31_Msk (0xffffUL) /*!< INSTR_MEM31 (Bitfield-Mask: 0xffff) */
/* ====================================================== SM0_CLKDIV ======================================================= */
#define PIO0_SM0_CLKDIV_INT_Pos (16UL) /*!< INT (Bit 16) */
#define PIO0_SM0_CLKDIV_INT_Msk (0xffff0000UL) /*!< INT (Bitfield-Mask: 0xffff) */
#define PIO0_SM0_CLKDIV_FRAC_Pos (8UL) /*!< FRAC (Bit 8) */
#define PIO0_SM0_CLKDIV_FRAC_Msk (0xff00UL) /*!< FRAC (Bitfield-Mask: 0xff) */
/* ===================================================== SM0_EXECCTRL ====================================================== */
#define PIO0_SM0_EXECCTRL_EXEC_STALLED_Pos (31UL) /*!< EXEC_STALLED (Bit 31) */
#define PIO0_SM0_EXECCTRL_EXEC_STALLED_Msk (0x80000000UL) /*!< EXEC_STALLED (Bitfield-Mask: 0x01) */
#define PIO0_SM0_EXECCTRL_SIDE_EN_Pos (30UL) /*!< SIDE_EN (Bit 30) */
#define PIO0_SM0_EXECCTRL_SIDE_EN_Msk (0x40000000UL) /*!< SIDE_EN (Bitfield-Mask: 0x01) */
#define PIO0_SM0_EXECCTRL_SIDE_PINDIR_Pos (29UL) /*!< SIDE_PINDIR (Bit 29) */
#define PIO0_SM0_EXECCTRL_SIDE_PINDIR_Msk (0x20000000UL) /*!< SIDE_PINDIR (Bitfield-Mask: 0x01) */
#define PIO0_SM0_EXECCTRL_JMP_PIN_Pos (24UL) /*!< JMP_PIN (Bit 24) */
#define PIO0_SM0_EXECCTRL_JMP_PIN_Msk (0x1f000000UL) /*!< JMP_PIN (Bitfield-Mask: 0x1f) */
#define PIO0_SM0_EXECCTRL_OUT_EN_SEL_Pos (19UL) /*!< OUT_EN_SEL (Bit 19) */
#define PIO0_SM0_EXECCTRL_OUT_EN_SEL_Msk (0xf80000UL) /*!< OUT_EN_SEL (Bitfield-Mask: 0x1f) */
#define PIO0_SM0_EXECCTRL_INLINE_OUT_EN_Pos (18UL) /*!< INLINE_OUT_EN (Bit 18) */
#define PIO0_SM0_EXECCTRL_INLINE_OUT_EN_Msk (0x40000UL) /*!< INLINE_OUT_EN (Bitfield-Mask: 0x01) */
#define PIO0_SM0_EXECCTRL_OUT_STICKY_Pos (17UL) /*!< OUT_STICKY (Bit 17) */
#define PIO0_SM0_EXECCTRL_OUT_STICKY_Msk (0x20000UL) /*!< OUT_STICKY (Bitfield-Mask: 0x01) */
#define PIO0_SM0_EXECCTRL_WRAP_TOP_Pos (12UL) /*!< WRAP_TOP (Bit 12) */
#define PIO0_SM0_EXECCTRL_WRAP_TOP_Msk (0x1f000UL) /*!< WRAP_TOP (Bitfield-Mask: 0x1f) */
#define PIO0_SM0_EXECCTRL_WRAP_BOTTOM_Pos (7UL) /*!< WRAP_BOTTOM (Bit 7) */
#define PIO0_SM0_EXECCTRL_WRAP_BOTTOM_Msk (0xf80UL) /*!< WRAP_BOTTOM (Bitfield-Mask: 0x1f) */
#define PIO0_SM0_EXECCTRL_STATUS_SEL_Pos (4UL) /*!< STATUS_SEL (Bit 4) */
#define PIO0_SM0_EXECCTRL_STATUS_SEL_Msk (0x10UL) /*!< STATUS_SEL (Bitfield-Mask: 0x01) */
#define PIO0_SM0_EXECCTRL_STATUS_N_Pos (0UL) /*!< STATUS_N (Bit 0) */
#define PIO0_SM0_EXECCTRL_STATUS_N_Msk (0xfUL) /*!< STATUS_N (Bitfield-Mask: 0x0f) */
/* ===================================================== SM0_SHIFTCTRL ===================================================== */
#define PIO0_SM0_SHIFTCTRL_FJOIN_RX_Pos (31UL) /*!< FJOIN_RX (Bit 31) */
#define PIO0_SM0_SHIFTCTRL_FJOIN_RX_Msk (0x80000000UL) /*!< FJOIN_RX (Bitfield-Mask: 0x01) */
#define PIO0_SM0_SHIFTCTRL_FJOIN_TX_Pos (30UL) /*!< FJOIN_TX (Bit 30) */
#define PIO0_SM0_SHIFTCTRL_FJOIN_TX_Msk (0x40000000UL) /*!< FJOIN_TX (Bitfield-Mask: 0x01) */
#define PIO0_SM0_SHIFTCTRL_PULL_THRESH_Pos (25UL) /*!< PULL_THRESH (Bit 25) */
#define PIO0_SM0_SHIFTCTRL_PULL_THRESH_Msk (0x3e000000UL) /*!< PULL_THRESH (Bitfield-Mask: 0x1f) */
#define PIO0_SM0_SHIFTCTRL_PUSH_THRESH_Pos (20UL) /*!< PUSH_THRESH (Bit 20) */
#define PIO0_SM0_SHIFTCTRL_PUSH_THRESH_Msk (0x1f00000UL) /*!< PUSH_THRESH (Bitfield-Mask: 0x1f) */
#define PIO0_SM0_SHIFTCTRL_OUT_SHIFTDIR_Pos (19UL) /*!< OUT_SHIFTDIR (Bit 19) */
#define PIO0_SM0_SHIFTCTRL_OUT_SHIFTDIR_Msk (0x80000UL) /*!< OUT_SHIFTDIR (Bitfield-Mask: 0x01) */
#define PIO0_SM0_SHIFTCTRL_IN_SHIFTDIR_Pos (18UL) /*!< IN_SHIFTDIR (Bit 18) */
#define PIO0_SM0_SHIFTCTRL_IN_SHIFTDIR_Msk (0x40000UL) /*!< IN_SHIFTDIR (Bitfield-Mask: 0x01) */
#define PIO0_SM0_SHIFTCTRL_AUTOPULL_Pos (17UL) /*!< AUTOPULL (Bit 17) */
#define PIO0_SM0_SHIFTCTRL_AUTOPULL_Msk (0x20000UL) /*!< AUTOPULL (Bitfield-Mask: 0x01) */
#define PIO0_SM0_SHIFTCTRL_AUTOPUSH_Pos (16UL) /*!< AUTOPUSH (Bit 16) */
#define PIO0_SM0_SHIFTCTRL_AUTOPUSH_Msk (0x10000UL) /*!< AUTOPUSH (Bitfield-Mask: 0x01) */
/* ======================================================= SM0_ADDR ======================================================== */
#define PIO0_SM0_ADDR_SM0_ADDR_Pos (0UL) /*!< SM0_ADDR (Bit 0) */
#define PIO0_SM0_ADDR_SM0_ADDR_Msk (0x1fUL) /*!< SM0_ADDR (Bitfield-Mask: 0x1f) */
/* ======================================================= SM0_INSTR ======================================================= */
#define PIO0_SM0_INSTR_SM0_INSTR_Pos (0UL) /*!< SM0_INSTR (Bit 0) */
#define PIO0_SM0_INSTR_SM0_INSTR_Msk (0xffffUL) /*!< SM0_INSTR (Bitfield-Mask: 0xffff) */
/* ====================================================== SM0_PINCTRL ====================================================== */
#define PIO0_SM0_PINCTRL_SIDESET_COUNT_Pos (29UL) /*!< SIDESET_COUNT (Bit 29) */
#define PIO0_SM0_PINCTRL_SIDESET_COUNT_Msk (0xe0000000UL) /*!< SIDESET_COUNT (Bitfield-Mask: 0x07) */
#define PIO0_SM0_PINCTRL_SET_COUNT_Pos (26UL) /*!< SET_COUNT (Bit 26) */
#define PIO0_SM0_PINCTRL_SET_COUNT_Msk (0x1c000000UL) /*!< SET_COUNT (Bitfield-Mask: 0x07) */
#define PIO0_SM0_PINCTRL_OUT_COUNT_Pos (20UL) /*!< OUT_COUNT (Bit 20) */
#define PIO0_SM0_PINCTRL_OUT_COUNT_Msk (0x3f00000UL) /*!< OUT_COUNT (Bitfield-Mask: 0x3f) */
#define PIO0_SM0_PINCTRL_IN_BASE_Pos (15UL) /*!< IN_BASE (Bit 15) */
#define PIO0_SM0_PINCTRL_IN_BASE_Msk (0xf8000UL) /*!< IN_BASE (Bitfield-Mask: 0x1f) */
#define PIO0_SM0_PINCTRL_SIDESET_BASE_Pos (10UL) /*!< SIDESET_BASE (Bit 10) */
#define PIO0_SM0_PINCTRL_SIDESET_BASE_Msk (0x7c00UL) /*!< SIDESET_BASE (Bitfield-Mask: 0x1f) */
#define PIO0_SM0_PINCTRL_SET_BASE_Pos (5UL) /*!< SET_BASE (Bit 5) */
#define PIO0_SM0_PINCTRL_SET_BASE_Msk (0x3e0UL) /*!< SET_BASE (Bitfield-Mask: 0x1f) */
#define PIO0_SM0_PINCTRL_OUT_BASE_Pos (0UL) /*!< OUT_BASE (Bit 0) */
#define PIO0_SM0_PINCTRL_OUT_BASE_Msk (0x1fUL) /*!< OUT_BASE (Bitfield-Mask: 0x1f) */
/* ====================================================== SM1_CLKDIV ======================================================= */
#define PIO0_SM1_CLKDIV_INT_Pos (16UL) /*!< INT (Bit 16) */
#define PIO0_SM1_CLKDIV_INT_Msk (0xffff0000UL) /*!< INT (Bitfield-Mask: 0xffff) */
#define PIO0_SM1_CLKDIV_FRAC_Pos (8UL) /*!< FRAC (Bit 8) */
#define PIO0_SM1_CLKDIV_FRAC_Msk (0xff00UL) /*!< FRAC (Bitfield-Mask: 0xff) */
/* ===================================================== SM1_EXECCTRL ====================================================== */
#define PIO0_SM1_EXECCTRL_EXEC_STALLED_Pos (31UL) /*!< EXEC_STALLED (Bit 31) */
#define PIO0_SM1_EXECCTRL_EXEC_STALLED_Msk (0x80000000UL) /*!< EXEC_STALLED (Bitfield-Mask: 0x01) */
#define PIO0_SM1_EXECCTRL_SIDE_EN_Pos (30UL) /*!< SIDE_EN (Bit 30) */
#define PIO0_SM1_EXECCTRL_SIDE_EN_Msk (0x40000000UL) /*!< SIDE_EN (Bitfield-Mask: 0x01) */
#define PIO0_SM1_EXECCTRL_SIDE_PINDIR_Pos (29UL) /*!< SIDE_PINDIR (Bit 29) */
#define PIO0_SM1_EXECCTRL_SIDE_PINDIR_Msk (0x20000000UL) /*!< SIDE_PINDIR (Bitfield-Mask: 0x01) */
#define PIO0_SM1_EXECCTRL_JMP_PIN_Pos (24UL) /*!< JMP_PIN (Bit 24) */
#define PIO0_SM1_EXECCTRL_JMP_PIN_Msk (0x1f000000UL) /*!< JMP_PIN (Bitfield-Mask: 0x1f) */
#define PIO0_SM1_EXECCTRL_OUT_EN_SEL_Pos (19UL) /*!< OUT_EN_SEL (Bit 19) */
#define PIO0_SM1_EXECCTRL_OUT_EN_SEL_Msk (0xf80000UL) /*!< OUT_EN_SEL (Bitfield-Mask: 0x1f) */
#define PIO0_SM1_EXECCTRL_INLINE_OUT_EN_Pos (18UL) /*!< INLINE_OUT_EN (Bit 18) */
#define PIO0_SM1_EXECCTRL_INLINE_OUT_EN_Msk (0x40000UL) /*!< INLINE_OUT_EN (Bitfield-Mask: 0x01) */
#define PIO0_SM1_EXECCTRL_OUT_STICKY_Pos (17UL) /*!< OUT_STICKY (Bit 17) */
#define PIO0_SM1_EXECCTRL_OUT_STICKY_Msk (0x20000UL) /*!< OUT_STICKY (Bitfield-Mask: 0x01) */
#define PIO0_SM1_EXECCTRL_WRAP_TOP_Pos (12UL) /*!< WRAP_TOP (Bit 12) */
#define PIO0_SM1_EXECCTRL_WRAP_TOP_Msk (0x1f000UL) /*!< WRAP_TOP (Bitfield-Mask: 0x1f) */
#define PIO0_SM1_EXECCTRL_WRAP_BOTTOM_Pos (7UL) /*!< WRAP_BOTTOM (Bit 7) */
#define PIO0_SM1_EXECCTRL_WRAP_BOTTOM_Msk (0xf80UL) /*!< WRAP_BOTTOM (Bitfield-Mask: 0x1f) */
#define PIO0_SM1_EXECCTRL_STATUS_SEL_Pos (4UL) /*!< STATUS_SEL (Bit 4) */
#define PIO0_SM1_EXECCTRL_STATUS_SEL_Msk (0x10UL) /*!< STATUS_SEL (Bitfield-Mask: 0x01) */
#define PIO0_SM1_EXECCTRL_STATUS_N_Pos (0UL) /*!< STATUS_N (Bit 0) */
#define PIO0_SM1_EXECCTRL_STATUS_N_Msk (0xfUL) /*!< STATUS_N (Bitfield-Mask: 0x0f) */
/* ===================================================== SM1_SHIFTCTRL ===================================================== */
#define PIO0_SM1_SHIFTCTRL_FJOIN_RX_Pos (31UL) /*!< FJOIN_RX (Bit 31) */
#define PIO0_SM1_SHIFTCTRL_FJOIN_RX_Msk (0x80000000UL) /*!< FJOIN_RX (Bitfield-Mask: 0x01) */
#define PIO0_SM1_SHIFTCTRL_FJOIN_TX_Pos (30UL) /*!< FJOIN_TX (Bit 30) */
#define PIO0_SM1_SHIFTCTRL_FJOIN_TX_Msk (0x40000000UL) /*!< FJOIN_TX (Bitfield-Mask: 0x01) */
#define PIO0_SM1_SHIFTCTRL_PULL_THRESH_Pos (25UL) /*!< PULL_THRESH (Bit 25) */
#define PIO0_SM1_SHIFTCTRL_PULL_THRESH_Msk (0x3e000000UL) /*!< PULL_THRESH (Bitfield-Mask: 0x1f) */
#define PIO0_SM1_SHIFTCTRL_PUSH_THRESH_Pos (20UL) /*!< PUSH_THRESH (Bit 20) */
#define PIO0_SM1_SHIFTCTRL_PUSH_THRESH_Msk (0x1f00000UL) /*!< PUSH_THRESH (Bitfield-Mask: 0x1f) */
#define PIO0_SM1_SHIFTCTRL_OUT_SHIFTDIR_Pos (19UL) /*!< OUT_SHIFTDIR (Bit 19) */
#define PIO0_SM1_SHIFTCTRL_OUT_SHIFTDIR_Msk (0x80000UL) /*!< OUT_SHIFTDIR (Bitfield-Mask: 0x01) */
#define PIO0_SM1_SHIFTCTRL_IN_SHIFTDIR_Pos (18UL) /*!< IN_SHIFTDIR (Bit 18) */
#define PIO0_SM1_SHIFTCTRL_IN_SHIFTDIR_Msk (0x40000UL) /*!< IN_SHIFTDIR (Bitfield-Mask: 0x01) */
#define PIO0_SM1_SHIFTCTRL_AUTOPULL_Pos (17UL) /*!< AUTOPULL (Bit 17) */
#define PIO0_SM1_SHIFTCTRL_AUTOPULL_Msk (0x20000UL) /*!< AUTOPULL (Bitfield-Mask: 0x01) */
#define PIO0_SM1_SHIFTCTRL_AUTOPUSH_Pos (16UL) /*!< AUTOPUSH (Bit 16) */
#define PIO0_SM1_SHIFTCTRL_AUTOPUSH_Msk (0x10000UL) /*!< AUTOPUSH (Bitfield-Mask: 0x01) */
/* ======================================================= SM1_ADDR ======================================================== */
#define PIO0_SM1_ADDR_SM1_ADDR_Pos (0UL) /*!< SM1_ADDR (Bit 0) */
#define PIO0_SM1_ADDR_SM1_ADDR_Msk (0x1fUL) /*!< SM1_ADDR (Bitfield-Mask: 0x1f) */
/* ======================================================= SM1_INSTR ======================================================= */
#define PIO0_SM1_INSTR_SM1_INSTR_Pos (0UL) /*!< SM1_INSTR (Bit 0) */
#define PIO0_SM1_INSTR_SM1_INSTR_Msk (0xffffUL) /*!< SM1_INSTR (Bitfield-Mask: 0xffff) */
/* ====================================================== SM1_PINCTRL ====================================================== */
#define PIO0_SM1_PINCTRL_SIDESET_COUNT_Pos (29UL) /*!< SIDESET_COUNT (Bit 29) */
#define PIO0_SM1_PINCTRL_SIDESET_COUNT_Msk (0xe0000000UL) /*!< SIDESET_COUNT (Bitfield-Mask: 0x07) */
#define PIO0_SM1_PINCTRL_SET_COUNT_Pos (26UL) /*!< SET_COUNT (Bit 26) */
#define PIO0_SM1_PINCTRL_SET_COUNT_Msk (0x1c000000UL) /*!< SET_COUNT (Bitfield-Mask: 0x07) */
#define PIO0_SM1_PINCTRL_OUT_COUNT_Pos (20UL) /*!< OUT_COUNT (Bit 20) */
#define PIO0_SM1_PINCTRL_OUT_COUNT_Msk (0x3f00000UL) /*!< OUT_COUNT (Bitfield-Mask: 0x3f) */
#define PIO0_SM1_PINCTRL_IN_BASE_Pos (15UL) /*!< IN_BASE (Bit 15) */
#define PIO0_SM1_PINCTRL_IN_BASE_Msk (0xf8000UL) /*!< IN_BASE (Bitfield-Mask: 0x1f) */
#define PIO0_SM1_PINCTRL_SIDESET_BASE_Pos (10UL) /*!< SIDESET_BASE (Bit 10) */
#define PIO0_SM1_PINCTRL_SIDESET_BASE_Msk (0x7c00UL) /*!< SIDESET_BASE (Bitfield-Mask: 0x1f) */
#define PIO0_SM1_PINCTRL_SET_BASE_Pos (5UL) /*!< SET_BASE (Bit 5) */
#define PIO0_SM1_PINCTRL_SET_BASE_Msk (0x3e0UL) /*!< SET_BASE (Bitfield-Mask: 0x1f) */
#define PIO0_SM1_PINCTRL_OUT_BASE_Pos (0UL) /*!< OUT_BASE (Bit 0) */
#define PIO0_SM1_PINCTRL_OUT_BASE_Msk (0x1fUL) /*!< OUT_BASE (Bitfield-Mask: 0x1f) */
/* ====================================================== SM2_CLKDIV ======================================================= */
#define PIO0_SM2_CLKDIV_INT_Pos (16UL) /*!< INT (Bit 16) */
#define PIO0_SM2_CLKDIV_INT_Msk (0xffff0000UL) /*!< INT (Bitfield-Mask: 0xffff) */
#define PIO0_SM2_CLKDIV_FRAC_Pos (8UL) /*!< FRAC (Bit 8) */
#define PIO0_SM2_CLKDIV_FRAC_Msk (0xff00UL) /*!< FRAC (Bitfield-Mask: 0xff) */
/* ===================================================== SM2_EXECCTRL ====================================================== */
#define PIO0_SM2_EXECCTRL_EXEC_STALLED_Pos (31UL) /*!< EXEC_STALLED (Bit 31) */
#define PIO0_SM2_EXECCTRL_EXEC_STALLED_Msk (0x80000000UL) /*!< EXEC_STALLED (Bitfield-Mask: 0x01) */
#define PIO0_SM2_EXECCTRL_SIDE_EN_Pos (30UL) /*!< SIDE_EN (Bit 30) */
#define PIO0_SM2_EXECCTRL_SIDE_EN_Msk (0x40000000UL) /*!< SIDE_EN (Bitfield-Mask: 0x01) */
#define PIO0_SM2_EXECCTRL_SIDE_PINDIR_Pos (29UL) /*!< SIDE_PINDIR (Bit 29) */
#define PIO0_SM2_EXECCTRL_SIDE_PINDIR_Msk (0x20000000UL) /*!< SIDE_PINDIR (Bitfield-Mask: 0x01) */
#define PIO0_SM2_EXECCTRL_JMP_PIN_Pos (24UL) /*!< JMP_PIN (Bit 24) */
#define PIO0_SM2_EXECCTRL_JMP_PIN_Msk (0x1f000000UL) /*!< JMP_PIN (Bitfield-Mask: 0x1f) */
#define PIO0_SM2_EXECCTRL_OUT_EN_SEL_Pos (19UL) /*!< OUT_EN_SEL (Bit 19) */
#define PIO0_SM2_EXECCTRL_OUT_EN_SEL_Msk (0xf80000UL) /*!< OUT_EN_SEL (Bitfield-Mask: 0x1f) */
#define PIO0_SM2_EXECCTRL_INLINE_OUT_EN_Pos (18UL) /*!< INLINE_OUT_EN (Bit 18) */
#define PIO0_SM2_EXECCTRL_INLINE_OUT_EN_Msk (0x40000UL) /*!< INLINE_OUT_EN (Bitfield-Mask: 0x01) */
#define PIO0_SM2_EXECCTRL_OUT_STICKY_Pos (17UL) /*!< OUT_STICKY (Bit 17) */
#define PIO0_SM2_EXECCTRL_OUT_STICKY_Msk (0x20000UL) /*!< OUT_STICKY (Bitfield-Mask: 0x01) */
#define PIO0_SM2_EXECCTRL_WRAP_TOP_Pos (12UL) /*!< WRAP_TOP (Bit 12) */
#define PIO0_SM2_EXECCTRL_WRAP_TOP_Msk (0x1f000UL) /*!< WRAP_TOP (Bitfield-Mask: 0x1f) */
#define PIO0_SM2_EXECCTRL_WRAP_BOTTOM_Pos (7UL) /*!< WRAP_BOTTOM (Bit 7) */
#define PIO0_SM2_EXECCTRL_WRAP_BOTTOM_Msk (0xf80UL) /*!< WRAP_BOTTOM (Bitfield-Mask: 0x1f) */
#define PIO0_SM2_EXECCTRL_STATUS_SEL_Pos (4UL) /*!< STATUS_SEL (Bit 4) */
#define PIO0_SM2_EXECCTRL_STATUS_SEL_Msk (0x10UL) /*!< STATUS_SEL (Bitfield-Mask: 0x01) */
#define PIO0_SM2_EXECCTRL_STATUS_N_Pos (0UL) /*!< STATUS_N (Bit 0) */
#define PIO0_SM2_EXECCTRL_STATUS_N_Msk (0xfUL) /*!< STATUS_N (Bitfield-Mask: 0x0f) */
/* ===================================================== SM2_SHIFTCTRL ===================================================== */
#define PIO0_SM2_SHIFTCTRL_FJOIN_RX_Pos (31UL) /*!< FJOIN_RX (Bit 31) */
#define PIO0_SM2_SHIFTCTRL_FJOIN_RX_Msk (0x80000000UL) /*!< FJOIN_RX (Bitfield-Mask: 0x01) */
#define PIO0_SM2_SHIFTCTRL_FJOIN_TX_Pos (30UL) /*!< FJOIN_TX (Bit 30) */
#define PIO0_SM2_SHIFTCTRL_FJOIN_TX_Msk (0x40000000UL) /*!< FJOIN_TX (Bitfield-Mask: 0x01) */
#define PIO0_SM2_SHIFTCTRL_PULL_THRESH_Pos (25UL) /*!< PULL_THRESH (Bit 25) */
#define PIO0_SM2_SHIFTCTRL_PULL_THRESH_Msk (0x3e000000UL) /*!< PULL_THRESH (Bitfield-Mask: 0x1f) */
#define PIO0_SM2_SHIFTCTRL_PUSH_THRESH_Pos (20UL) /*!< PUSH_THRESH (Bit 20) */
#define PIO0_SM2_SHIFTCTRL_PUSH_THRESH_Msk (0x1f00000UL) /*!< PUSH_THRESH (Bitfield-Mask: 0x1f) */
#define PIO0_SM2_SHIFTCTRL_OUT_SHIFTDIR_Pos (19UL) /*!< OUT_SHIFTDIR (Bit 19) */
#define PIO0_SM2_SHIFTCTRL_OUT_SHIFTDIR_Msk (0x80000UL) /*!< OUT_SHIFTDIR (Bitfield-Mask: 0x01) */
#define PIO0_SM2_SHIFTCTRL_IN_SHIFTDIR_Pos (18UL) /*!< IN_SHIFTDIR (Bit 18) */
#define PIO0_SM2_SHIFTCTRL_IN_SHIFTDIR_Msk (0x40000UL) /*!< IN_SHIFTDIR (Bitfield-Mask: 0x01) */
#define PIO0_SM2_SHIFTCTRL_AUTOPULL_Pos (17UL) /*!< AUTOPULL (Bit 17) */
#define PIO0_SM2_SHIFTCTRL_AUTOPULL_Msk (0x20000UL) /*!< AUTOPULL (Bitfield-Mask: 0x01) */
#define PIO0_SM2_SHIFTCTRL_AUTOPUSH_Pos (16UL) /*!< AUTOPUSH (Bit 16) */
#define PIO0_SM2_SHIFTCTRL_AUTOPUSH_Msk (0x10000UL) /*!< AUTOPUSH (Bitfield-Mask: 0x01) */
/* ======================================================= SM2_ADDR ======================================================== */
#define PIO0_SM2_ADDR_SM2_ADDR_Pos (0UL) /*!< SM2_ADDR (Bit 0) */
#define PIO0_SM2_ADDR_SM2_ADDR_Msk (0x1fUL) /*!< SM2_ADDR (Bitfield-Mask: 0x1f) */
/* ======================================================= SM2_INSTR ======================================================= */
#define PIO0_SM2_INSTR_SM2_INSTR_Pos (0UL) /*!< SM2_INSTR (Bit 0) */
#define PIO0_SM2_INSTR_SM2_INSTR_Msk (0xffffUL) /*!< SM2_INSTR (Bitfield-Mask: 0xffff) */
/* ====================================================== SM2_PINCTRL ====================================================== */
#define PIO0_SM2_PINCTRL_SIDESET_COUNT_Pos (29UL) /*!< SIDESET_COUNT (Bit 29) */
#define PIO0_SM2_PINCTRL_SIDESET_COUNT_Msk (0xe0000000UL) /*!< SIDESET_COUNT (Bitfield-Mask: 0x07) */
#define PIO0_SM2_PINCTRL_SET_COUNT_Pos (26UL) /*!< SET_COUNT (Bit 26) */
#define PIO0_SM2_PINCTRL_SET_COUNT_Msk (0x1c000000UL) /*!< SET_COUNT (Bitfield-Mask: 0x07) */
#define PIO0_SM2_PINCTRL_OUT_COUNT_Pos (20UL) /*!< OUT_COUNT (Bit 20) */
#define PIO0_SM2_PINCTRL_OUT_COUNT_Msk (0x3f00000UL) /*!< OUT_COUNT (Bitfield-Mask: 0x3f) */
#define PIO0_SM2_PINCTRL_IN_BASE_Pos (15UL) /*!< IN_BASE (Bit 15) */
#define PIO0_SM2_PINCTRL_IN_BASE_Msk (0xf8000UL) /*!< IN_BASE (Bitfield-Mask: 0x1f) */
#define PIO0_SM2_PINCTRL_SIDESET_BASE_Pos (10UL) /*!< SIDESET_BASE (Bit 10) */
#define PIO0_SM2_PINCTRL_SIDESET_BASE_Msk (0x7c00UL) /*!< SIDESET_BASE (Bitfield-Mask: 0x1f) */
#define PIO0_SM2_PINCTRL_SET_BASE_Pos (5UL) /*!< SET_BASE (Bit 5) */
#define PIO0_SM2_PINCTRL_SET_BASE_Msk (0x3e0UL) /*!< SET_BASE (Bitfield-Mask: 0x1f) */
#define PIO0_SM2_PINCTRL_OUT_BASE_Pos (0UL) /*!< OUT_BASE (Bit 0) */
#define PIO0_SM2_PINCTRL_OUT_BASE_Msk (0x1fUL) /*!< OUT_BASE (Bitfield-Mask: 0x1f) */
/* ====================================================== SM3_CLKDIV ======================================================= */
#define PIO0_SM3_CLKDIV_INT_Pos (16UL) /*!< INT (Bit 16) */
#define PIO0_SM3_CLKDIV_INT_Msk (0xffff0000UL) /*!< INT (Bitfield-Mask: 0xffff) */
#define PIO0_SM3_CLKDIV_FRAC_Pos (8UL) /*!< FRAC (Bit 8) */
#define PIO0_SM3_CLKDIV_FRAC_Msk (0xff00UL) /*!< FRAC (Bitfield-Mask: 0xff) */
/* ===================================================== SM3_EXECCTRL ====================================================== */
#define PIO0_SM3_EXECCTRL_EXEC_STALLED_Pos (31UL) /*!< EXEC_STALLED (Bit 31) */
#define PIO0_SM3_EXECCTRL_EXEC_STALLED_Msk (0x80000000UL) /*!< EXEC_STALLED (Bitfield-Mask: 0x01) */
#define PIO0_SM3_EXECCTRL_SIDE_EN_Pos (30UL) /*!< SIDE_EN (Bit 30) */
#define PIO0_SM3_EXECCTRL_SIDE_EN_Msk (0x40000000UL) /*!< SIDE_EN (Bitfield-Mask: 0x01) */
#define PIO0_SM3_EXECCTRL_SIDE_PINDIR_Pos (29UL) /*!< SIDE_PINDIR (Bit 29) */
#define PIO0_SM3_EXECCTRL_SIDE_PINDIR_Msk (0x20000000UL) /*!< SIDE_PINDIR (Bitfield-Mask: 0x01) */
#define PIO0_SM3_EXECCTRL_JMP_PIN_Pos (24UL) /*!< JMP_PIN (Bit 24) */
#define PIO0_SM3_EXECCTRL_JMP_PIN_Msk (0x1f000000UL) /*!< JMP_PIN (Bitfield-Mask: 0x1f) */
#define PIO0_SM3_EXECCTRL_OUT_EN_SEL_Pos (19UL) /*!< OUT_EN_SEL (Bit 19) */
#define PIO0_SM3_EXECCTRL_OUT_EN_SEL_Msk (0xf80000UL) /*!< OUT_EN_SEL (Bitfield-Mask: 0x1f) */
#define PIO0_SM3_EXECCTRL_INLINE_OUT_EN_Pos (18UL) /*!< INLINE_OUT_EN (Bit 18) */
#define PIO0_SM3_EXECCTRL_INLINE_OUT_EN_Msk (0x40000UL) /*!< INLINE_OUT_EN (Bitfield-Mask: 0x01) */
#define PIO0_SM3_EXECCTRL_OUT_STICKY_Pos (17UL) /*!< OUT_STICKY (Bit 17) */
#define PIO0_SM3_EXECCTRL_OUT_STICKY_Msk (0x20000UL) /*!< OUT_STICKY (Bitfield-Mask: 0x01) */
#define PIO0_SM3_EXECCTRL_WRAP_TOP_Pos (12UL) /*!< WRAP_TOP (Bit 12) */
#define PIO0_SM3_EXECCTRL_WRAP_TOP_Msk (0x1f000UL) /*!< WRAP_TOP (Bitfield-Mask: 0x1f) */
#define PIO0_SM3_EXECCTRL_WRAP_BOTTOM_Pos (7UL) /*!< WRAP_BOTTOM (Bit 7) */
#define PIO0_SM3_EXECCTRL_WRAP_BOTTOM_Msk (0xf80UL) /*!< WRAP_BOTTOM (Bitfield-Mask: 0x1f) */
#define PIO0_SM3_EXECCTRL_STATUS_SEL_Pos (4UL) /*!< STATUS_SEL (Bit 4) */
#define PIO0_SM3_EXECCTRL_STATUS_SEL_Msk (0x10UL) /*!< STATUS_SEL (Bitfield-Mask: 0x01) */
#define PIO0_SM3_EXECCTRL_STATUS_N_Pos (0UL) /*!< STATUS_N (Bit 0) */
#define PIO0_SM3_EXECCTRL_STATUS_N_Msk (0xfUL) /*!< STATUS_N (Bitfield-Mask: 0x0f) */
/* ===================================================== SM3_SHIFTCTRL ===================================================== */
#define PIO0_SM3_SHIFTCTRL_FJOIN_RX_Pos (31UL) /*!< FJOIN_RX (Bit 31) */
#define PIO0_SM3_SHIFTCTRL_FJOIN_RX_Msk (0x80000000UL) /*!< FJOIN_RX (Bitfield-Mask: 0x01) */
#define PIO0_SM3_SHIFTCTRL_FJOIN_TX_Pos (30UL) /*!< FJOIN_TX (Bit 30) */
#define PIO0_SM3_SHIFTCTRL_FJOIN_TX_Msk (0x40000000UL) /*!< FJOIN_TX (Bitfield-Mask: 0x01) */
#define PIO0_SM3_SHIFTCTRL_PULL_THRESH_Pos (25UL) /*!< PULL_THRESH (Bit 25) */
#define PIO0_SM3_SHIFTCTRL_PULL_THRESH_Msk (0x3e000000UL) /*!< PULL_THRESH (Bitfield-Mask: 0x1f) */
#define PIO0_SM3_SHIFTCTRL_PUSH_THRESH_Pos (20UL) /*!< PUSH_THRESH (Bit 20) */
#define PIO0_SM3_SHIFTCTRL_PUSH_THRESH_Msk (0x1f00000UL) /*!< PUSH_THRESH (Bitfield-Mask: 0x1f) */
#define PIO0_SM3_SHIFTCTRL_OUT_SHIFTDIR_Pos (19UL) /*!< OUT_SHIFTDIR (Bit 19) */
#define PIO0_SM3_SHIFTCTRL_OUT_SHIFTDIR_Msk (0x80000UL) /*!< OUT_SHIFTDIR (Bitfield-Mask: 0x01) */
#define PIO0_SM3_SHIFTCTRL_IN_SHIFTDIR_Pos (18UL) /*!< IN_SHIFTDIR (Bit 18) */
#define PIO0_SM3_SHIFTCTRL_IN_SHIFTDIR_Msk (0x40000UL) /*!< IN_SHIFTDIR (Bitfield-Mask: 0x01) */
#define PIO0_SM3_SHIFTCTRL_AUTOPULL_Pos (17UL) /*!< AUTOPULL (Bit 17) */
#define PIO0_SM3_SHIFTCTRL_AUTOPULL_Msk (0x20000UL) /*!< AUTOPULL (Bitfield-Mask: 0x01) */
#define PIO0_SM3_SHIFTCTRL_AUTOPUSH_Pos (16UL) /*!< AUTOPUSH (Bit 16) */
#define PIO0_SM3_SHIFTCTRL_AUTOPUSH_Msk (0x10000UL) /*!< AUTOPUSH (Bitfield-Mask: 0x01) */
/* ======================================================= SM3_ADDR ======================================================== */
#define PIO0_SM3_ADDR_SM3_ADDR_Pos (0UL) /*!< SM3_ADDR (Bit 0) */
#define PIO0_SM3_ADDR_SM3_ADDR_Msk (0x1fUL) /*!< SM3_ADDR (Bitfield-Mask: 0x1f) */
/* ======================================================= SM3_INSTR ======================================================= */
#define PIO0_SM3_INSTR_SM3_INSTR_Pos (0UL) /*!< SM3_INSTR (Bit 0) */
#define PIO0_SM3_INSTR_SM3_INSTR_Msk (0xffffUL) /*!< SM3_INSTR (Bitfield-Mask: 0xffff) */
/* ====================================================== SM3_PINCTRL ====================================================== */
#define PIO0_SM3_PINCTRL_SIDESET_COUNT_Pos (29UL) /*!< SIDESET_COUNT (Bit 29) */
#define PIO0_SM3_PINCTRL_SIDESET_COUNT_Msk (0xe0000000UL) /*!< SIDESET_COUNT (Bitfield-Mask: 0x07) */
#define PIO0_SM3_PINCTRL_SET_COUNT_Pos (26UL) /*!< SET_COUNT (Bit 26) */
#define PIO0_SM3_PINCTRL_SET_COUNT_Msk (0x1c000000UL) /*!< SET_COUNT (Bitfield-Mask: 0x07) */
#define PIO0_SM3_PINCTRL_OUT_COUNT_Pos (20UL) /*!< OUT_COUNT (Bit 20) */
#define PIO0_SM3_PINCTRL_OUT_COUNT_Msk (0x3f00000UL) /*!< OUT_COUNT (Bitfield-Mask: 0x3f) */
#define PIO0_SM3_PINCTRL_IN_BASE_Pos (15UL) /*!< IN_BASE (Bit 15) */
#define PIO0_SM3_PINCTRL_IN_BASE_Msk (0xf8000UL) /*!< IN_BASE (Bitfield-Mask: 0x1f) */
#define PIO0_SM3_PINCTRL_SIDESET_BASE_Pos (10UL) /*!< SIDESET_BASE (Bit 10) */
#define PIO0_SM3_PINCTRL_SIDESET_BASE_Msk (0x7c00UL) /*!< SIDESET_BASE (Bitfield-Mask: 0x1f) */
#define PIO0_SM3_PINCTRL_SET_BASE_Pos (5UL) /*!< SET_BASE (Bit 5) */
#define PIO0_SM3_PINCTRL_SET_BASE_Msk (0x3e0UL) /*!< SET_BASE (Bitfield-Mask: 0x1f) */
#define PIO0_SM3_PINCTRL_OUT_BASE_Pos (0UL) /*!< OUT_BASE (Bit 0) */
#define PIO0_SM3_PINCTRL_OUT_BASE_Msk (0x1fUL) /*!< OUT_BASE (Bitfield-Mask: 0x1f) */
/* ========================================================= INTR ========================================================== */
#define PIO0_INTR_SM3_Pos (11UL) /*!< SM3 (Bit 11) */
#define PIO0_INTR_SM3_Msk (0x800UL) /*!< SM3 (Bitfield-Mask: 0x01) */
#define PIO0_INTR_SM2_Pos (10UL) /*!< SM2 (Bit 10) */
#define PIO0_INTR_SM2_Msk (0x400UL) /*!< SM2 (Bitfield-Mask: 0x01) */
#define PIO0_INTR_SM1_Pos (9UL) /*!< SM1 (Bit 9) */
#define PIO0_INTR_SM1_Msk (0x200UL) /*!< SM1 (Bitfield-Mask: 0x01) */
#define PIO0_INTR_SM0_Pos (8UL) /*!< SM0 (Bit 8) */
#define PIO0_INTR_SM0_Msk (0x100UL) /*!< SM0 (Bitfield-Mask: 0x01) */
#define PIO0_INTR_SM3_TXNFULL_Pos (7UL) /*!< SM3_TXNFULL (Bit 7) */
#define PIO0_INTR_SM3_TXNFULL_Msk (0x80UL) /*!< SM3_TXNFULL (Bitfield-Mask: 0x01) */
#define PIO0_INTR_SM2_TXNFULL_Pos (6UL) /*!< SM2_TXNFULL (Bit 6) */
#define PIO0_INTR_SM2_TXNFULL_Msk (0x40UL) /*!< SM2_TXNFULL (Bitfield-Mask: 0x01) */
#define PIO0_INTR_SM1_TXNFULL_Pos (5UL) /*!< SM1_TXNFULL (Bit 5) */
#define PIO0_INTR_SM1_TXNFULL_Msk (0x20UL) /*!< SM1_TXNFULL (Bitfield-Mask: 0x01) */
#define PIO0_INTR_SM0_TXNFULL_Pos (4UL) /*!< SM0_TXNFULL (Bit 4) */
#define PIO0_INTR_SM0_TXNFULL_Msk (0x10UL) /*!< SM0_TXNFULL (Bitfield-Mask: 0x01) */
#define PIO0_INTR_SM3_RXNEMPTY_Pos (3UL) /*!< SM3_RXNEMPTY (Bit 3) */
#define PIO0_INTR_SM3_RXNEMPTY_Msk (0x8UL) /*!< SM3_RXNEMPTY (Bitfield-Mask: 0x01) */
#define PIO0_INTR_SM2_RXNEMPTY_Pos (2UL) /*!< SM2_RXNEMPTY (Bit 2) */
#define PIO0_INTR_SM2_RXNEMPTY_Msk (0x4UL) /*!< SM2_RXNEMPTY (Bitfield-Mask: 0x01) */
#define PIO0_INTR_SM1_RXNEMPTY_Pos (1UL) /*!< SM1_RXNEMPTY (Bit 1) */
#define PIO0_INTR_SM1_RXNEMPTY_Msk (0x2UL) /*!< SM1_RXNEMPTY (Bitfield-Mask: 0x01) */
#define PIO0_INTR_SM0_RXNEMPTY_Pos (0UL) /*!< SM0_RXNEMPTY (Bit 0) */
#define PIO0_INTR_SM0_RXNEMPTY_Msk (0x1UL) /*!< SM0_RXNEMPTY (Bitfield-Mask: 0x01) */
/* ======================================================= IRQ0_INTE ======================================================= */
#define PIO0_IRQ0_INTE_SM3_Pos (11UL) /*!< SM3 (Bit 11) */
#define PIO0_IRQ0_INTE_SM3_Msk (0x800UL) /*!< SM3 (Bitfield-Mask: 0x01) */
#define PIO0_IRQ0_INTE_SM2_Pos (10UL) /*!< SM2 (Bit 10) */
#define PIO0_IRQ0_INTE_SM2_Msk (0x400UL) /*!< SM2 (Bitfield-Mask: 0x01) */
#define PIO0_IRQ0_INTE_SM1_Pos (9UL) /*!< SM1 (Bit 9) */
#define PIO0_IRQ0_INTE_SM1_Msk (0x200UL) /*!< SM1 (Bitfield-Mask: 0x01) */
#define PIO0_IRQ0_INTE_SM0_Pos (8UL) /*!< SM0 (Bit 8) */
#define PIO0_IRQ0_INTE_SM0_Msk (0x100UL) /*!< SM0 (Bitfield-Mask: 0x01) */
#define PIO0_IRQ0_INTE_SM3_TXNFULL_Pos (7UL) /*!< SM3_TXNFULL (Bit 7) */
#define PIO0_IRQ0_INTE_SM3_TXNFULL_Msk (0x80UL) /*!< SM3_TXNFULL (Bitfield-Mask: 0x01) */
#define PIO0_IRQ0_INTE_SM2_TXNFULL_Pos (6UL) /*!< SM2_TXNFULL (Bit 6) */
#define PIO0_IRQ0_INTE_SM2_TXNFULL_Msk (0x40UL) /*!< SM2_TXNFULL (Bitfield-Mask: 0x01) */
#define PIO0_IRQ0_INTE_SM1_TXNFULL_Pos (5UL) /*!< SM1_TXNFULL (Bit 5) */
#define PIO0_IRQ0_INTE_SM1_TXNFULL_Msk (0x20UL) /*!< SM1_TXNFULL (Bitfield-Mask: 0x01) */
#define PIO0_IRQ0_INTE_SM0_TXNFULL_Pos (4UL) /*!< SM0_TXNFULL (Bit 4) */
#define PIO0_IRQ0_INTE_SM0_TXNFULL_Msk (0x10UL) /*!< SM0_TXNFULL (Bitfield-Mask: 0x01) */
#define PIO0_IRQ0_INTE_SM3_RXNEMPTY_Pos (3UL) /*!< SM3_RXNEMPTY (Bit 3) */
#define PIO0_IRQ0_INTE_SM3_RXNEMPTY_Msk (0x8UL) /*!< SM3_RXNEMPTY (Bitfield-Mask: 0x01) */
#define PIO0_IRQ0_INTE_SM2_RXNEMPTY_Pos (2UL) /*!< SM2_RXNEMPTY (Bit 2) */
#define PIO0_IRQ0_INTE_SM2_RXNEMPTY_Msk (0x4UL) /*!< SM2_RXNEMPTY (Bitfield-Mask: 0x01) */
#define PIO0_IRQ0_INTE_SM1_RXNEMPTY_Pos (1UL) /*!< SM1_RXNEMPTY (Bit 1) */
#define PIO0_IRQ0_INTE_SM1_RXNEMPTY_Msk (0x2UL) /*!< SM1_RXNEMPTY (Bitfield-Mask: 0x01) */
#define PIO0_IRQ0_INTE_SM0_RXNEMPTY_Pos (0UL) /*!< SM0_RXNEMPTY (Bit 0) */
#define PIO0_IRQ0_INTE_SM0_RXNEMPTY_Msk (0x1UL) /*!< SM0_RXNEMPTY (Bitfield-Mask: 0x01) */
/* ======================================================= IRQ0_INTF ======================================================= */
#define PIO0_IRQ0_INTF_SM3_Pos (11UL) /*!< SM3 (Bit 11) */
#define PIO0_IRQ0_INTF_SM3_Msk (0x800UL) /*!< SM3 (Bitfield-Mask: 0x01) */
#define PIO0_IRQ0_INTF_SM2_Pos (10UL) /*!< SM2 (Bit 10) */
#define PIO0_IRQ0_INTF_SM2_Msk (0x400UL) /*!< SM2 (Bitfield-Mask: 0x01) */
#define PIO0_IRQ0_INTF_SM1_Pos (9UL) /*!< SM1 (Bit 9) */
#define PIO0_IRQ0_INTF_SM1_Msk (0x200UL) /*!< SM1 (Bitfield-Mask: 0x01) */
#define PIO0_IRQ0_INTF_SM0_Pos (8UL) /*!< SM0 (Bit 8) */
#define PIO0_IRQ0_INTF_SM0_Msk (0x100UL) /*!< SM0 (Bitfield-Mask: 0x01) */
#define PIO0_IRQ0_INTF_SM3_TXNFULL_Pos (7UL) /*!< SM3_TXNFULL (Bit 7) */
#define PIO0_IRQ0_INTF_SM3_TXNFULL_Msk (0x80UL) /*!< SM3_TXNFULL (Bitfield-Mask: 0x01) */
#define PIO0_IRQ0_INTF_SM2_TXNFULL_Pos (6UL) /*!< SM2_TXNFULL (Bit 6) */
#define PIO0_IRQ0_INTF_SM2_TXNFULL_Msk (0x40UL) /*!< SM2_TXNFULL (Bitfield-Mask: 0x01) */
#define PIO0_IRQ0_INTF_SM1_TXNFULL_Pos (5UL) /*!< SM1_TXNFULL (Bit 5) */
#define PIO0_IRQ0_INTF_SM1_TXNFULL_Msk (0x20UL) /*!< SM1_TXNFULL (Bitfield-Mask: 0x01) */
#define PIO0_IRQ0_INTF_SM0_TXNFULL_Pos (4UL) /*!< SM0_TXNFULL (Bit 4) */
#define PIO0_IRQ0_INTF_SM0_TXNFULL_Msk (0x10UL) /*!< SM0_TXNFULL (Bitfield-Mask: 0x01) */
#define PIO0_IRQ0_INTF_SM3_RXNEMPTY_Pos (3UL) /*!< SM3_RXNEMPTY (Bit 3) */
#define PIO0_IRQ0_INTF_SM3_RXNEMPTY_Msk (0x8UL) /*!< SM3_RXNEMPTY (Bitfield-Mask: 0x01) */
#define PIO0_IRQ0_INTF_SM2_RXNEMPTY_Pos (2UL) /*!< SM2_RXNEMPTY (Bit 2) */
#define PIO0_IRQ0_INTF_SM2_RXNEMPTY_Msk (0x4UL) /*!< SM2_RXNEMPTY (Bitfield-Mask: 0x01) */
#define PIO0_IRQ0_INTF_SM1_RXNEMPTY_Pos (1UL) /*!< SM1_RXNEMPTY (Bit 1) */
#define PIO0_IRQ0_INTF_SM1_RXNEMPTY_Msk (0x2UL) /*!< SM1_RXNEMPTY (Bitfield-Mask: 0x01) */
#define PIO0_IRQ0_INTF_SM0_RXNEMPTY_Pos (0UL) /*!< SM0_RXNEMPTY (Bit 0) */
#define PIO0_IRQ0_INTF_SM0_RXNEMPTY_Msk (0x1UL) /*!< SM0_RXNEMPTY (Bitfield-Mask: 0x01) */
/* ======================================================= IRQ0_INTS ======================================================= */
#define PIO0_IRQ0_INTS_SM3_Pos (11UL) /*!< SM3 (Bit 11) */
#define PIO0_IRQ0_INTS_SM3_Msk (0x800UL) /*!< SM3 (Bitfield-Mask: 0x01) */
#define PIO0_IRQ0_INTS_SM2_Pos (10UL) /*!< SM2 (Bit 10) */
#define PIO0_IRQ0_INTS_SM2_Msk (0x400UL) /*!< SM2 (Bitfield-Mask: 0x01) */
#define PIO0_IRQ0_INTS_SM1_Pos (9UL) /*!< SM1 (Bit 9) */
#define PIO0_IRQ0_INTS_SM1_Msk (0x200UL) /*!< SM1 (Bitfield-Mask: 0x01) */
#define PIO0_IRQ0_INTS_SM0_Pos (8UL) /*!< SM0 (Bit 8) */
#define PIO0_IRQ0_INTS_SM0_Msk (0x100UL) /*!< SM0 (Bitfield-Mask: 0x01) */
#define PIO0_IRQ0_INTS_SM3_TXNFULL_Pos (7UL) /*!< SM3_TXNFULL (Bit 7) */
#define PIO0_IRQ0_INTS_SM3_TXNFULL_Msk (0x80UL) /*!< SM3_TXNFULL (Bitfield-Mask: 0x01) */
#define PIO0_IRQ0_INTS_SM2_TXNFULL_Pos (6UL) /*!< SM2_TXNFULL (Bit 6) */
#define PIO0_IRQ0_INTS_SM2_TXNFULL_Msk (0x40UL) /*!< SM2_TXNFULL (Bitfield-Mask: 0x01) */
#define PIO0_IRQ0_INTS_SM1_TXNFULL_Pos (5UL) /*!< SM1_TXNFULL (Bit 5) */
#define PIO0_IRQ0_INTS_SM1_TXNFULL_Msk (0x20UL) /*!< SM1_TXNFULL (Bitfield-Mask: 0x01) */
#define PIO0_IRQ0_INTS_SM0_TXNFULL_Pos (4UL) /*!< SM0_TXNFULL (Bit 4) */
#define PIO0_IRQ0_INTS_SM0_TXNFULL_Msk (0x10UL) /*!< SM0_TXNFULL (Bitfield-Mask: 0x01) */
#define PIO0_IRQ0_INTS_SM3_RXNEMPTY_Pos (3UL) /*!< SM3_RXNEMPTY (Bit 3) */
#define PIO0_IRQ0_INTS_SM3_RXNEMPTY_Msk (0x8UL) /*!< SM3_RXNEMPTY (Bitfield-Mask: 0x01) */
#define PIO0_IRQ0_INTS_SM2_RXNEMPTY_Pos (2UL) /*!< SM2_RXNEMPTY (Bit 2) */
#define PIO0_IRQ0_INTS_SM2_RXNEMPTY_Msk (0x4UL) /*!< SM2_RXNEMPTY (Bitfield-Mask: 0x01) */
#define PIO0_IRQ0_INTS_SM1_RXNEMPTY_Pos (1UL) /*!< SM1_RXNEMPTY (Bit 1) */
#define PIO0_IRQ0_INTS_SM1_RXNEMPTY_Msk (0x2UL) /*!< SM1_RXNEMPTY (Bitfield-Mask: 0x01) */
#define PIO0_IRQ0_INTS_SM0_RXNEMPTY_Pos (0UL) /*!< SM0_RXNEMPTY (Bit 0) */
#define PIO0_IRQ0_INTS_SM0_RXNEMPTY_Msk (0x1UL) /*!< SM0_RXNEMPTY (Bitfield-Mask: 0x01) */
/* ======================================================= IRQ1_INTE ======================================================= */
#define PIO0_IRQ1_INTE_SM3_Pos (11UL) /*!< SM3 (Bit 11) */
#define PIO0_IRQ1_INTE_SM3_Msk (0x800UL) /*!< SM3 (Bitfield-Mask: 0x01) */
#define PIO0_IRQ1_INTE_SM2_Pos (10UL) /*!< SM2 (Bit 10) */
#define PIO0_IRQ1_INTE_SM2_Msk (0x400UL) /*!< SM2 (Bitfield-Mask: 0x01) */
#define PIO0_IRQ1_INTE_SM1_Pos (9UL) /*!< SM1 (Bit 9) */
#define PIO0_IRQ1_INTE_SM1_Msk (0x200UL) /*!< SM1 (Bitfield-Mask: 0x01) */
#define PIO0_IRQ1_INTE_SM0_Pos (8UL) /*!< SM0 (Bit 8) */
#define PIO0_IRQ1_INTE_SM0_Msk (0x100UL) /*!< SM0 (Bitfield-Mask: 0x01) */
#define PIO0_IRQ1_INTE_SM3_TXNFULL_Pos (7UL) /*!< SM3_TXNFULL (Bit 7) */
#define PIO0_IRQ1_INTE_SM3_TXNFULL_Msk (0x80UL) /*!< SM3_TXNFULL (Bitfield-Mask: 0x01) */
#define PIO0_IRQ1_INTE_SM2_TXNFULL_Pos (6UL) /*!< SM2_TXNFULL (Bit 6) */
#define PIO0_IRQ1_INTE_SM2_TXNFULL_Msk (0x40UL) /*!< SM2_TXNFULL (Bitfield-Mask: 0x01) */
#define PIO0_IRQ1_INTE_SM1_TXNFULL_Pos (5UL) /*!< SM1_TXNFULL (Bit 5) */
#define PIO0_IRQ1_INTE_SM1_TXNFULL_Msk (0x20UL) /*!< SM1_TXNFULL (Bitfield-Mask: 0x01) */
#define PIO0_IRQ1_INTE_SM0_TXNFULL_Pos (4UL) /*!< SM0_TXNFULL (Bit 4) */
#define PIO0_IRQ1_INTE_SM0_TXNFULL_Msk (0x10UL) /*!< SM0_TXNFULL (Bitfield-Mask: 0x01) */
#define PIO0_IRQ1_INTE_SM3_RXNEMPTY_Pos (3UL) /*!< SM3_RXNEMPTY (Bit 3) */
#define PIO0_IRQ1_INTE_SM3_RXNEMPTY_Msk (0x8UL) /*!< SM3_RXNEMPTY (Bitfield-Mask: 0x01) */
#define PIO0_IRQ1_INTE_SM2_RXNEMPTY_Pos (2UL) /*!< SM2_RXNEMPTY (Bit 2) */
#define PIO0_IRQ1_INTE_SM2_RXNEMPTY_Msk (0x4UL) /*!< SM2_RXNEMPTY (Bitfield-Mask: 0x01) */
#define PIO0_IRQ1_INTE_SM1_RXNEMPTY_Pos (1UL) /*!< SM1_RXNEMPTY (Bit 1) */
#define PIO0_IRQ1_INTE_SM1_RXNEMPTY_Msk (0x2UL) /*!< SM1_RXNEMPTY (Bitfield-Mask: 0x01) */
#define PIO0_IRQ1_INTE_SM0_RXNEMPTY_Pos (0UL) /*!< SM0_RXNEMPTY (Bit 0) */
#define PIO0_IRQ1_INTE_SM0_RXNEMPTY_Msk (0x1UL) /*!< SM0_RXNEMPTY (Bitfield-Mask: 0x01) */
/* ======================================================= IRQ1_INTF ======================================================= */
#define PIO0_IRQ1_INTF_SM3_Pos (11UL) /*!< SM3 (Bit 11) */
#define PIO0_IRQ1_INTF_SM3_Msk (0x800UL) /*!< SM3 (Bitfield-Mask: 0x01) */
#define PIO0_IRQ1_INTF_SM2_Pos (10UL) /*!< SM2 (Bit 10) */
#define PIO0_IRQ1_INTF_SM2_Msk (0x400UL) /*!< SM2 (Bitfield-Mask: 0x01) */
#define PIO0_IRQ1_INTF_SM1_Pos (9UL) /*!< SM1 (Bit 9) */
#define PIO0_IRQ1_INTF_SM1_Msk (0x200UL) /*!< SM1 (Bitfield-Mask: 0x01) */
#define PIO0_IRQ1_INTF_SM0_Pos (8UL) /*!< SM0 (Bit 8) */
#define PIO0_IRQ1_INTF_SM0_Msk (0x100UL) /*!< SM0 (Bitfield-Mask: 0x01) */
#define PIO0_IRQ1_INTF_SM3_TXNFULL_Pos (7UL) /*!< SM3_TXNFULL (Bit 7) */
#define PIO0_IRQ1_INTF_SM3_TXNFULL_Msk (0x80UL) /*!< SM3_TXNFULL (Bitfield-Mask: 0x01) */
#define PIO0_IRQ1_INTF_SM2_TXNFULL_Pos (6UL) /*!< SM2_TXNFULL (Bit 6) */
#define PIO0_IRQ1_INTF_SM2_TXNFULL_Msk (0x40UL) /*!< SM2_TXNFULL (Bitfield-Mask: 0x01) */
#define PIO0_IRQ1_INTF_SM1_TXNFULL_Pos (5UL) /*!< SM1_TXNFULL (Bit 5) */
#define PIO0_IRQ1_INTF_SM1_TXNFULL_Msk (0x20UL) /*!< SM1_TXNFULL (Bitfield-Mask: 0x01) */
#define PIO0_IRQ1_INTF_SM0_TXNFULL_Pos (4UL) /*!< SM0_TXNFULL (Bit 4) */
#define PIO0_IRQ1_INTF_SM0_TXNFULL_Msk (0x10UL) /*!< SM0_TXNFULL (Bitfield-Mask: 0x01) */
#define PIO0_IRQ1_INTF_SM3_RXNEMPTY_Pos (3UL) /*!< SM3_RXNEMPTY (Bit 3) */
#define PIO0_IRQ1_INTF_SM3_RXNEMPTY_Msk (0x8UL) /*!< SM3_RXNEMPTY (Bitfield-Mask: 0x01) */
#define PIO0_IRQ1_INTF_SM2_RXNEMPTY_Pos (2UL) /*!< SM2_RXNEMPTY (Bit 2) */
#define PIO0_IRQ1_INTF_SM2_RXNEMPTY_Msk (0x4UL) /*!< SM2_RXNEMPTY (Bitfield-Mask: 0x01) */
#define PIO0_IRQ1_INTF_SM1_RXNEMPTY_Pos (1UL) /*!< SM1_RXNEMPTY (Bit 1) */
#define PIO0_IRQ1_INTF_SM1_RXNEMPTY_Msk (0x2UL) /*!< SM1_RXNEMPTY (Bitfield-Mask: 0x01) */
#define PIO0_IRQ1_INTF_SM0_RXNEMPTY_Pos (0UL) /*!< SM0_RXNEMPTY (Bit 0) */
#define PIO0_IRQ1_INTF_SM0_RXNEMPTY_Msk (0x1UL) /*!< SM0_RXNEMPTY (Bitfield-Mask: 0x01) */
/* ======================================================= IRQ1_INTS ======================================================= */
#define PIO0_IRQ1_INTS_SM3_Pos (11UL) /*!< SM3 (Bit 11) */
#define PIO0_IRQ1_INTS_SM3_Msk (0x800UL) /*!< SM3 (Bitfield-Mask: 0x01) */
#define PIO0_IRQ1_INTS_SM2_Pos (10UL) /*!< SM2 (Bit 10) */
#define PIO0_IRQ1_INTS_SM2_Msk (0x400UL) /*!< SM2 (Bitfield-Mask: 0x01) */
#define PIO0_IRQ1_INTS_SM1_Pos (9UL) /*!< SM1 (Bit 9) */
#define PIO0_IRQ1_INTS_SM1_Msk (0x200UL) /*!< SM1 (Bitfield-Mask: 0x01) */
#define PIO0_IRQ1_INTS_SM0_Pos (8UL) /*!< SM0 (Bit 8) */
#define PIO0_IRQ1_INTS_SM0_Msk (0x100UL) /*!< SM0 (Bitfield-Mask: 0x01) */
#define PIO0_IRQ1_INTS_SM3_TXNFULL_Pos (7UL) /*!< SM3_TXNFULL (Bit 7) */
#define PIO0_IRQ1_INTS_SM3_TXNFULL_Msk (0x80UL) /*!< SM3_TXNFULL (Bitfield-Mask: 0x01) */
#define PIO0_IRQ1_INTS_SM2_TXNFULL_Pos (6UL) /*!< SM2_TXNFULL (Bit 6) */
#define PIO0_IRQ1_INTS_SM2_TXNFULL_Msk (0x40UL) /*!< SM2_TXNFULL (Bitfield-Mask: 0x01) */
#define PIO0_IRQ1_INTS_SM1_TXNFULL_Pos (5UL) /*!< SM1_TXNFULL (Bit 5) */
#define PIO0_IRQ1_INTS_SM1_TXNFULL_Msk (0x20UL) /*!< SM1_TXNFULL (Bitfield-Mask: 0x01) */
#define PIO0_IRQ1_INTS_SM0_TXNFULL_Pos (4UL) /*!< SM0_TXNFULL (Bit 4) */
#define PIO0_IRQ1_INTS_SM0_TXNFULL_Msk (0x10UL) /*!< SM0_TXNFULL (Bitfield-Mask: 0x01) */
#define PIO0_IRQ1_INTS_SM3_RXNEMPTY_Pos (3UL) /*!< SM3_RXNEMPTY (Bit 3) */
#define PIO0_IRQ1_INTS_SM3_RXNEMPTY_Msk (0x8UL) /*!< SM3_RXNEMPTY (Bitfield-Mask: 0x01) */
#define PIO0_IRQ1_INTS_SM2_RXNEMPTY_Pos (2UL) /*!< SM2_RXNEMPTY (Bit 2) */
#define PIO0_IRQ1_INTS_SM2_RXNEMPTY_Msk (0x4UL) /*!< SM2_RXNEMPTY (Bitfield-Mask: 0x01) */
#define PIO0_IRQ1_INTS_SM1_RXNEMPTY_Pos (1UL) /*!< SM1_RXNEMPTY (Bit 1) */
#define PIO0_IRQ1_INTS_SM1_RXNEMPTY_Msk (0x2UL) /*!< SM1_RXNEMPTY (Bitfield-Mask: 0x01) */
#define PIO0_IRQ1_INTS_SM0_RXNEMPTY_Pos (0UL) /*!< SM0_RXNEMPTY (Bit 0) */
#define PIO0_IRQ1_INTS_SM0_RXNEMPTY_Msk (0x1UL) /*!< SM0_RXNEMPTY (Bitfield-Mask: 0x01) */
/* =========================================================================================================================== */
/* ================ SIO ================ */
/* =========================================================================================================================== */
/* ========================================================= CPUID ========================================================= */
/* ======================================================== GPIO_IN ======================================================== */
#define SIO_GPIO_IN_GPIO_IN_Pos (0UL) /*!< GPIO_IN (Bit 0) */
#define SIO_GPIO_IN_GPIO_IN_Msk (0x3fffffffUL) /*!< GPIO_IN (Bitfield-Mask: 0x3fffffff) */
/* ====================================================== GPIO_HI_IN ======================================================= */
#define SIO_GPIO_HI_IN_GPIO_HI_IN_Pos (0UL) /*!< GPIO_HI_IN (Bit 0) */
#define SIO_GPIO_HI_IN_GPIO_HI_IN_Msk (0x3fUL) /*!< GPIO_HI_IN (Bitfield-Mask: 0x3f) */
/* ======================================================= GPIO_OUT ======================================================== */
#define SIO_GPIO_OUT_GPIO_OUT_Pos (0UL) /*!< GPIO_OUT (Bit 0) */
#define SIO_GPIO_OUT_GPIO_OUT_Msk (0x3fffffffUL) /*!< GPIO_OUT (Bitfield-Mask: 0x3fffffff) */
/* ===================================================== GPIO_OUT_SET ====================================================== */
#define SIO_GPIO_OUT_SET_GPIO_OUT_SET_Pos (0UL) /*!< GPIO_OUT_SET (Bit 0) */
#define SIO_GPIO_OUT_SET_GPIO_OUT_SET_Msk (0x3fffffffUL) /*!< GPIO_OUT_SET (Bitfield-Mask: 0x3fffffff) */
/* ===================================================== GPIO_OUT_CLR ====================================================== */
#define SIO_GPIO_OUT_CLR_GPIO_OUT_CLR_Pos (0UL) /*!< GPIO_OUT_CLR (Bit 0) */
#define SIO_GPIO_OUT_CLR_GPIO_OUT_CLR_Msk (0x3fffffffUL) /*!< GPIO_OUT_CLR (Bitfield-Mask: 0x3fffffff) */
/* ===================================================== GPIO_OUT_XOR ====================================================== */
#define SIO_GPIO_OUT_XOR_GPIO_OUT_XOR_Pos (0UL) /*!< GPIO_OUT_XOR (Bit 0) */
#define SIO_GPIO_OUT_XOR_GPIO_OUT_XOR_Msk (0x3fffffffUL) /*!< GPIO_OUT_XOR (Bitfield-Mask: 0x3fffffff) */
/* ======================================================== GPIO_OE ======================================================== */
#define SIO_GPIO_OE_GPIO_OE_Pos (0UL) /*!< GPIO_OE (Bit 0) */
#define SIO_GPIO_OE_GPIO_OE_Msk (0x3fffffffUL) /*!< GPIO_OE (Bitfield-Mask: 0x3fffffff) */
/* ====================================================== GPIO_OE_SET ====================================================== */
#define SIO_GPIO_OE_SET_GPIO_OE_SET_Pos (0UL) /*!< GPIO_OE_SET (Bit 0) */
#define SIO_GPIO_OE_SET_GPIO_OE_SET_Msk (0x3fffffffUL) /*!< GPIO_OE_SET (Bitfield-Mask: 0x3fffffff) */
/* ====================================================== GPIO_OE_CLR ====================================================== */
#define SIO_GPIO_OE_CLR_GPIO_OE_CLR_Pos (0UL) /*!< GPIO_OE_CLR (Bit 0) */
#define SIO_GPIO_OE_CLR_GPIO_OE_CLR_Msk (0x3fffffffUL) /*!< GPIO_OE_CLR (Bitfield-Mask: 0x3fffffff) */
/* ====================================================== GPIO_OE_XOR ====================================================== */
#define SIO_GPIO_OE_XOR_GPIO_OE_XOR_Pos (0UL) /*!< GPIO_OE_XOR (Bit 0) */
#define SIO_GPIO_OE_XOR_GPIO_OE_XOR_Msk (0x3fffffffUL) /*!< GPIO_OE_XOR (Bitfield-Mask: 0x3fffffff) */
/* ====================================================== GPIO_HI_OUT ====================================================== */
#define SIO_GPIO_HI_OUT_GPIO_HI_OUT_Pos (0UL) /*!< GPIO_HI_OUT (Bit 0) */
#define SIO_GPIO_HI_OUT_GPIO_HI_OUT_Msk (0x3fUL) /*!< GPIO_HI_OUT (Bitfield-Mask: 0x3f) */
/* ==================================================== GPIO_HI_OUT_SET ==================================================== */
#define SIO_GPIO_HI_OUT_SET_GPIO_HI_OUT_SET_Pos (0UL) /*!< GPIO_HI_OUT_SET (Bit 0) */
#define SIO_GPIO_HI_OUT_SET_GPIO_HI_OUT_SET_Msk (0x3fUL) /*!< GPIO_HI_OUT_SET (Bitfield-Mask: 0x3f) */
/* ==================================================== GPIO_HI_OUT_CLR ==================================================== */
#define SIO_GPIO_HI_OUT_CLR_GPIO_HI_OUT_CLR_Pos (0UL) /*!< GPIO_HI_OUT_CLR (Bit 0) */
#define SIO_GPIO_HI_OUT_CLR_GPIO_HI_OUT_CLR_Msk (0x3fUL) /*!< GPIO_HI_OUT_CLR (Bitfield-Mask: 0x3f) */
/* ==================================================== GPIO_HI_OUT_XOR ==================================================== */
#define SIO_GPIO_HI_OUT_XOR_GPIO_HI_OUT_XOR_Pos (0UL) /*!< GPIO_HI_OUT_XOR (Bit 0) */
#define SIO_GPIO_HI_OUT_XOR_GPIO_HI_OUT_XOR_Msk (0x3fUL) /*!< GPIO_HI_OUT_XOR (Bitfield-Mask: 0x3f) */
/* ====================================================== GPIO_HI_OE ======================================================= */
#define SIO_GPIO_HI_OE_GPIO_HI_OE_Pos (0UL) /*!< GPIO_HI_OE (Bit 0) */
#define SIO_GPIO_HI_OE_GPIO_HI_OE_Msk (0x3fUL) /*!< GPIO_HI_OE (Bitfield-Mask: 0x3f) */
/* ==================================================== GPIO_HI_OE_SET ===================================================== */
#define SIO_GPIO_HI_OE_SET_GPIO_HI_OE_SET_Pos (0UL) /*!< GPIO_HI_OE_SET (Bit 0) */
#define SIO_GPIO_HI_OE_SET_GPIO_HI_OE_SET_Msk (0x3fUL) /*!< GPIO_HI_OE_SET (Bitfield-Mask: 0x3f) */
/* ==================================================== GPIO_HI_OE_CLR ===================================================== */
#define SIO_GPIO_HI_OE_CLR_GPIO_HI_OE_CLR_Pos (0UL) /*!< GPIO_HI_OE_CLR (Bit 0) */
#define SIO_GPIO_HI_OE_CLR_GPIO_HI_OE_CLR_Msk (0x3fUL) /*!< GPIO_HI_OE_CLR (Bitfield-Mask: 0x3f) */
/* ==================================================== GPIO_HI_OE_XOR ===================================================== */
#define SIO_GPIO_HI_OE_XOR_GPIO_HI_OE_XOR_Pos (0UL) /*!< GPIO_HI_OE_XOR (Bit 0) */
#define SIO_GPIO_HI_OE_XOR_GPIO_HI_OE_XOR_Msk (0x3fUL) /*!< GPIO_HI_OE_XOR (Bitfield-Mask: 0x3f) */
/* ======================================================== FIFO_ST ======================================================== */
#define SIO_FIFO_ST_ROE_Pos (3UL) /*!< ROE (Bit 3) */
#define SIO_FIFO_ST_ROE_Msk (0x8UL) /*!< ROE (Bitfield-Mask: 0x01) */
#define SIO_FIFO_ST_WOF_Pos (2UL) /*!< WOF (Bit 2) */
#define SIO_FIFO_ST_WOF_Msk (0x4UL) /*!< WOF (Bitfield-Mask: 0x01) */
#define SIO_FIFO_ST_RDY_Pos (1UL) /*!< RDY (Bit 1) */
#define SIO_FIFO_ST_RDY_Msk (0x2UL) /*!< RDY (Bitfield-Mask: 0x01) */
#define SIO_FIFO_ST_VLD_Pos (0UL) /*!< VLD (Bit 0) */
#define SIO_FIFO_ST_VLD_Msk (0x1UL) /*!< VLD (Bitfield-Mask: 0x01) */
/* ======================================================== FIFO_WR ======================================================== */
/* ======================================================== FIFO_RD ======================================================== */
/* ====================================================== SPINLOCK_ST ====================================================== */
/* ===================================================== DIV_UDIVIDEND ===================================================== */
/* ===================================================== DIV_UDIVISOR ====================================================== */
/* ===================================================== DIV_SDIVIDEND ===================================================== */
/* ===================================================== DIV_SDIVISOR ====================================================== */
/* ===================================================== DIV_QUOTIENT ====================================================== */
/* ===================================================== DIV_REMAINDER ===================================================== */
/* ======================================================== DIV_CSR ======================================================== */
#define SIO_DIV_CSR_DIRTY_Pos (1UL) /*!< DIRTY (Bit 1) */
#define SIO_DIV_CSR_DIRTY_Msk (0x2UL) /*!< DIRTY (Bitfield-Mask: 0x01) */
#define SIO_DIV_CSR_READY_Pos (0UL) /*!< READY (Bit 0) */
#define SIO_DIV_CSR_READY_Msk (0x1UL) /*!< READY (Bitfield-Mask: 0x01) */
/* ==================================================== INTERP0_ACCUM0 ===================================================== */
/* ==================================================== INTERP0_ACCUM1 ===================================================== */
/* ===================================================== INTERP0_BASE0 ===================================================== */
/* ===================================================== INTERP0_BASE1 ===================================================== */
/* ===================================================== INTERP0_BASE2 ===================================================== */
/* =================================================== INTERP0_POP_LANE0 =================================================== */
/* =================================================== INTERP0_POP_LANE1 =================================================== */
/* =================================================== INTERP0_POP_FULL ==================================================== */
/* ================================================== INTERP0_PEEK_LANE0 =================================================== */
/* ================================================== INTERP0_PEEK_LANE1 =================================================== */
/* =================================================== INTERP0_PEEK_FULL =================================================== */
/* ================================================== INTERP0_CTRL_LANE0 =================================================== */
#define SIO_INTERP0_CTRL_LANE0_OVERF_Pos (25UL) /*!< OVERF (Bit 25) */
#define SIO_INTERP0_CTRL_LANE0_OVERF_Msk (0x2000000UL) /*!< OVERF (Bitfield-Mask: 0x01) */
#define SIO_INTERP0_CTRL_LANE0_OVERF1_Pos (24UL) /*!< OVERF1 (Bit 24) */
#define SIO_INTERP0_CTRL_LANE0_OVERF1_Msk (0x1000000UL) /*!< OVERF1 (Bitfield-Mask: 0x01) */
#define SIO_INTERP0_CTRL_LANE0_OVERF0_Pos (23UL) /*!< OVERF0 (Bit 23) */
#define SIO_INTERP0_CTRL_LANE0_OVERF0_Msk (0x800000UL) /*!< OVERF0 (Bitfield-Mask: 0x01) */
#define SIO_INTERP0_CTRL_LANE0_BLEND_Pos (21UL) /*!< BLEND (Bit 21) */
#define SIO_INTERP0_CTRL_LANE0_BLEND_Msk (0x200000UL) /*!< BLEND (Bitfield-Mask: 0x01) */
#define SIO_INTERP0_CTRL_LANE0_FORCE_MSB_Pos (19UL) /*!< FORCE_MSB (Bit 19) */
#define SIO_INTERP0_CTRL_LANE0_FORCE_MSB_Msk (0x180000UL) /*!< FORCE_MSB (Bitfield-Mask: 0x03) */
#define SIO_INTERP0_CTRL_LANE0_ADD_RAW_Pos (18UL) /*!< ADD_RAW (Bit 18) */
#define SIO_INTERP0_CTRL_LANE0_ADD_RAW_Msk (0x40000UL) /*!< ADD_RAW (Bitfield-Mask: 0x01) */
#define SIO_INTERP0_CTRL_LANE0_CROSS_RESULT_Pos (17UL) /*!< CROSS_RESULT (Bit 17) */
#define SIO_INTERP0_CTRL_LANE0_CROSS_RESULT_Msk (0x20000UL) /*!< CROSS_RESULT (Bitfield-Mask: 0x01) */
#define SIO_INTERP0_CTRL_LANE0_CROSS_INPUT_Pos (16UL) /*!< CROSS_INPUT (Bit 16) */
#define SIO_INTERP0_CTRL_LANE0_CROSS_INPUT_Msk (0x10000UL) /*!< CROSS_INPUT (Bitfield-Mask: 0x01) */
#define SIO_INTERP0_CTRL_LANE0_SIGNED_Pos (15UL) /*!< SIGNED (Bit 15) */
#define SIO_INTERP0_CTRL_LANE0_SIGNED_Msk (0x8000UL) /*!< SIGNED (Bitfield-Mask: 0x01) */
#define SIO_INTERP0_CTRL_LANE0_MASK_MSB_Pos (10UL) /*!< MASK_MSB (Bit 10) */
#define SIO_INTERP0_CTRL_LANE0_MASK_MSB_Msk (0x7c00UL) /*!< MASK_MSB (Bitfield-Mask: 0x1f) */
#define SIO_INTERP0_CTRL_LANE0_MASK_LSB_Pos (5UL) /*!< MASK_LSB (Bit 5) */
#define SIO_INTERP0_CTRL_LANE0_MASK_LSB_Msk (0x3e0UL) /*!< MASK_LSB (Bitfield-Mask: 0x1f) */
#define SIO_INTERP0_CTRL_LANE0_SHIFT_Pos (0UL) /*!< SHIFT (Bit 0) */
#define SIO_INTERP0_CTRL_LANE0_SHIFT_Msk (0x1fUL) /*!< SHIFT (Bitfield-Mask: 0x1f) */
/* ================================================== INTERP0_CTRL_LANE1 =================================================== */
#define SIO_INTERP0_CTRL_LANE1_FORCE_MSB_Pos (19UL) /*!< FORCE_MSB (Bit 19) */
#define SIO_INTERP0_CTRL_LANE1_FORCE_MSB_Msk (0x180000UL) /*!< FORCE_MSB (Bitfield-Mask: 0x03) */
#define SIO_INTERP0_CTRL_LANE1_ADD_RAW_Pos (18UL) /*!< ADD_RAW (Bit 18) */
#define SIO_INTERP0_CTRL_LANE1_ADD_RAW_Msk (0x40000UL) /*!< ADD_RAW (Bitfield-Mask: 0x01) */
#define SIO_INTERP0_CTRL_LANE1_CROSS_RESULT_Pos (17UL) /*!< CROSS_RESULT (Bit 17) */
#define SIO_INTERP0_CTRL_LANE1_CROSS_RESULT_Msk (0x20000UL) /*!< CROSS_RESULT (Bitfield-Mask: 0x01) */
#define SIO_INTERP0_CTRL_LANE1_CROSS_INPUT_Pos (16UL) /*!< CROSS_INPUT (Bit 16) */
#define SIO_INTERP0_CTRL_LANE1_CROSS_INPUT_Msk (0x10000UL) /*!< CROSS_INPUT (Bitfield-Mask: 0x01) */
#define SIO_INTERP0_CTRL_LANE1_SIGNED_Pos (15UL) /*!< SIGNED (Bit 15) */
#define SIO_INTERP0_CTRL_LANE1_SIGNED_Msk (0x8000UL) /*!< SIGNED (Bitfield-Mask: 0x01) */
#define SIO_INTERP0_CTRL_LANE1_MASK_MSB_Pos (10UL) /*!< MASK_MSB (Bit 10) */
#define SIO_INTERP0_CTRL_LANE1_MASK_MSB_Msk (0x7c00UL) /*!< MASK_MSB (Bitfield-Mask: 0x1f) */
#define SIO_INTERP0_CTRL_LANE1_MASK_LSB_Pos (5UL) /*!< MASK_LSB (Bit 5) */
#define SIO_INTERP0_CTRL_LANE1_MASK_LSB_Msk (0x3e0UL) /*!< MASK_LSB (Bitfield-Mask: 0x1f) */
#define SIO_INTERP0_CTRL_LANE1_SHIFT_Pos (0UL) /*!< SHIFT (Bit 0) */
#define SIO_INTERP0_CTRL_LANE1_SHIFT_Msk (0x1fUL) /*!< SHIFT (Bitfield-Mask: 0x1f) */
/* ================================================== INTERP0_ACCUM0_ADD =================================================== */
#define SIO_INTERP0_ACCUM0_ADD_INTERP0_ACCUM0_ADD_Pos (0UL) /*!< INTERP0_ACCUM0_ADD (Bit 0) */
#define SIO_INTERP0_ACCUM0_ADD_INTERP0_ACCUM0_ADD_Msk (0xffffffUL) /*!< INTERP0_ACCUM0_ADD (Bitfield-Mask: 0xffffff) */
/* ================================================== INTERP0_ACCUM1_ADD =================================================== */
#define SIO_INTERP0_ACCUM1_ADD_INTERP0_ACCUM1_ADD_Pos (0UL) /*!< INTERP0_ACCUM1_ADD (Bit 0) */
#define SIO_INTERP0_ACCUM1_ADD_INTERP0_ACCUM1_ADD_Msk (0xffffffUL) /*!< INTERP0_ACCUM1_ADD (Bitfield-Mask: 0xffffff) */
/* ================================================== INTERP0_BASE_1AND0 =================================================== */
/* ==================================================== INTERP1_ACCUM0 ===================================================== */
/* ==================================================== INTERP1_ACCUM1 ===================================================== */
/* ===================================================== INTERP1_BASE0 ===================================================== */
/* ===================================================== INTERP1_BASE1 ===================================================== */
/* ===================================================== INTERP1_BASE2 ===================================================== */
/* =================================================== INTERP1_POP_LANE0 =================================================== */
/* =================================================== INTERP1_POP_LANE1 =================================================== */
/* =================================================== INTERP1_POP_FULL ==================================================== */
/* ================================================== INTERP1_PEEK_LANE0 =================================================== */
/* ================================================== INTERP1_PEEK_LANE1 =================================================== */
/* =================================================== INTERP1_PEEK_FULL =================================================== */
/* ================================================== INTERP1_CTRL_LANE0 =================================================== */
#define SIO_INTERP1_CTRL_LANE0_OVERF_Pos (25UL) /*!< OVERF (Bit 25) */
#define SIO_INTERP1_CTRL_LANE0_OVERF_Msk (0x2000000UL) /*!< OVERF (Bitfield-Mask: 0x01) */
#define SIO_INTERP1_CTRL_LANE0_OVERF1_Pos (24UL) /*!< OVERF1 (Bit 24) */
#define SIO_INTERP1_CTRL_LANE0_OVERF1_Msk (0x1000000UL) /*!< OVERF1 (Bitfield-Mask: 0x01) */
#define SIO_INTERP1_CTRL_LANE0_OVERF0_Pos (23UL) /*!< OVERF0 (Bit 23) */
#define SIO_INTERP1_CTRL_LANE0_OVERF0_Msk (0x800000UL) /*!< OVERF0 (Bitfield-Mask: 0x01) */
#define SIO_INTERP1_CTRL_LANE0_CLAMP_Pos (22UL) /*!< CLAMP (Bit 22) */
#define SIO_INTERP1_CTRL_LANE0_CLAMP_Msk (0x400000UL) /*!< CLAMP (Bitfield-Mask: 0x01) */
#define SIO_INTERP1_CTRL_LANE0_FORCE_MSB_Pos (19UL) /*!< FORCE_MSB (Bit 19) */
#define SIO_INTERP1_CTRL_LANE0_FORCE_MSB_Msk (0x180000UL) /*!< FORCE_MSB (Bitfield-Mask: 0x03) */
#define SIO_INTERP1_CTRL_LANE0_ADD_RAW_Pos (18UL) /*!< ADD_RAW (Bit 18) */
#define SIO_INTERP1_CTRL_LANE0_ADD_RAW_Msk (0x40000UL) /*!< ADD_RAW (Bitfield-Mask: 0x01) */
#define SIO_INTERP1_CTRL_LANE0_CROSS_RESULT_Pos (17UL) /*!< CROSS_RESULT (Bit 17) */
#define SIO_INTERP1_CTRL_LANE0_CROSS_RESULT_Msk (0x20000UL) /*!< CROSS_RESULT (Bitfield-Mask: 0x01) */
#define SIO_INTERP1_CTRL_LANE0_CROSS_INPUT_Pos (16UL) /*!< CROSS_INPUT (Bit 16) */
#define SIO_INTERP1_CTRL_LANE0_CROSS_INPUT_Msk (0x10000UL) /*!< CROSS_INPUT (Bitfield-Mask: 0x01) */
#define SIO_INTERP1_CTRL_LANE0_SIGNED_Pos (15UL) /*!< SIGNED (Bit 15) */
#define SIO_INTERP1_CTRL_LANE0_SIGNED_Msk (0x8000UL) /*!< SIGNED (Bitfield-Mask: 0x01) */
#define SIO_INTERP1_CTRL_LANE0_MASK_MSB_Pos (10UL) /*!< MASK_MSB (Bit 10) */
#define SIO_INTERP1_CTRL_LANE0_MASK_MSB_Msk (0x7c00UL) /*!< MASK_MSB (Bitfield-Mask: 0x1f) */
#define SIO_INTERP1_CTRL_LANE0_MASK_LSB_Pos (5UL) /*!< MASK_LSB (Bit 5) */
#define SIO_INTERP1_CTRL_LANE0_MASK_LSB_Msk (0x3e0UL) /*!< MASK_LSB (Bitfield-Mask: 0x1f) */
#define SIO_INTERP1_CTRL_LANE0_SHIFT_Pos (0UL) /*!< SHIFT (Bit 0) */
#define SIO_INTERP1_CTRL_LANE0_SHIFT_Msk (0x1fUL) /*!< SHIFT (Bitfield-Mask: 0x1f) */
/* ================================================== INTERP1_CTRL_LANE1 =================================================== */
#define SIO_INTERP1_CTRL_LANE1_FORCE_MSB_Pos (19UL) /*!< FORCE_MSB (Bit 19) */
#define SIO_INTERP1_CTRL_LANE1_FORCE_MSB_Msk (0x180000UL) /*!< FORCE_MSB (Bitfield-Mask: 0x03) */
#define SIO_INTERP1_CTRL_LANE1_ADD_RAW_Pos (18UL) /*!< ADD_RAW (Bit 18) */
#define SIO_INTERP1_CTRL_LANE1_ADD_RAW_Msk (0x40000UL) /*!< ADD_RAW (Bitfield-Mask: 0x01) */
#define SIO_INTERP1_CTRL_LANE1_CROSS_RESULT_Pos (17UL) /*!< CROSS_RESULT (Bit 17) */
#define SIO_INTERP1_CTRL_LANE1_CROSS_RESULT_Msk (0x20000UL) /*!< CROSS_RESULT (Bitfield-Mask: 0x01) */
#define SIO_INTERP1_CTRL_LANE1_CROSS_INPUT_Pos (16UL) /*!< CROSS_INPUT (Bit 16) */
#define SIO_INTERP1_CTRL_LANE1_CROSS_INPUT_Msk (0x10000UL) /*!< CROSS_INPUT (Bitfield-Mask: 0x01) */
#define SIO_INTERP1_CTRL_LANE1_SIGNED_Pos (15UL) /*!< SIGNED (Bit 15) */
#define SIO_INTERP1_CTRL_LANE1_SIGNED_Msk (0x8000UL) /*!< SIGNED (Bitfield-Mask: 0x01) */
#define SIO_INTERP1_CTRL_LANE1_MASK_MSB_Pos (10UL) /*!< MASK_MSB (Bit 10) */
#define SIO_INTERP1_CTRL_LANE1_MASK_MSB_Msk (0x7c00UL) /*!< MASK_MSB (Bitfield-Mask: 0x1f) */
#define SIO_INTERP1_CTRL_LANE1_MASK_LSB_Pos (5UL) /*!< MASK_LSB (Bit 5) */
#define SIO_INTERP1_CTRL_LANE1_MASK_LSB_Msk (0x3e0UL) /*!< MASK_LSB (Bitfield-Mask: 0x1f) */
#define SIO_INTERP1_CTRL_LANE1_SHIFT_Pos (0UL) /*!< SHIFT (Bit 0) */
#define SIO_INTERP1_CTRL_LANE1_SHIFT_Msk (0x1fUL) /*!< SHIFT (Bitfield-Mask: 0x1f) */
/* ================================================== INTERP1_ACCUM0_ADD =================================================== */
#define SIO_INTERP1_ACCUM0_ADD_INTERP1_ACCUM0_ADD_Pos (0UL) /*!< INTERP1_ACCUM0_ADD (Bit 0) */
#define SIO_INTERP1_ACCUM0_ADD_INTERP1_ACCUM0_ADD_Msk (0xffffffUL) /*!< INTERP1_ACCUM0_ADD (Bitfield-Mask: 0xffffff) */
/* ================================================== INTERP1_ACCUM1_ADD =================================================== */
#define SIO_INTERP1_ACCUM1_ADD_INTERP1_ACCUM1_ADD_Pos (0UL) /*!< INTERP1_ACCUM1_ADD (Bit 0) */
#define SIO_INTERP1_ACCUM1_ADD_INTERP1_ACCUM1_ADD_Msk (0xffffffUL) /*!< INTERP1_ACCUM1_ADD (Bitfield-Mask: 0xffffff) */
/* ================================================== INTERP1_BASE_1AND0 =================================================== */
/* ======================================================= SPINLOCK0 ======================================================= */
/* ======================================================= SPINLOCK1 ======================================================= */
/* ======================================================= SPINLOCK2 ======================================================= */
/* ======================================================= SPINLOCK3 ======================================================= */
/* ======================================================= SPINLOCK4 ======================================================= */
/* ======================================================= SPINLOCK5 ======================================================= */
/* ======================================================= SPINLOCK6 ======================================================= */
/* ======================================================= SPINLOCK7 ======================================================= */
/* ======================================================= SPINLOCK8 ======================================================= */
/* ======================================================= SPINLOCK9 ======================================================= */
/* ====================================================== SPINLOCK10 ======================================================= */
/* ====================================================== SPINLOCK11 ======================================================= */
/* ====================================================== SPINLOCK12 ======================================================= */
/* ====================================================== SPINLOCK13 ======================================================= */
/* ====================================================== SPINLOCK14 ======================================================= */
/* ====================================================== SPINLOCK15 ======================================================= */
/* ====================================================== SPINLOCK16 ======================================================= */
/* ====================================================== SPINLOCK17 ======================================================= */
/* ====================================================== SPINLOCK18 ======================================================= */
/* ====================================================== SPINLOCK19 ======================================================= */
/* ====================================================== SPINLOCK20 ======================================================= */
/* ====================================================== SPINLOCK21 ======================================================= */
/* ====================================================== SPINLOCK22 ======================================================= */
/* ====================================================== SPINLOCK23 ======================================================= */
/* ====================================================== SPINLOCK24 ======================================================= */
/* ====================================================== SPINLOCK25 ======================================================= */
/* ====================================================== SPINLOCK26 ======================================================= */
/* ====================================================== SPINLOCK27 ======================================================= */
/* ====================================================== SPINLOCK28 ======================================================= */
/* ====================================================== SPINLOCK29 ======================================================= */
/* ====================================================== SPINLOCK30 ======================================================= */
/* ====================================================== SPINLOCK31 ======================================================= */
/* =========================================================================================================================== */
/* ================ PPB ================ */
/* =========================================================================================================================== */
/* ======================================================= SYST_CSR ======================================================== */
#define PPB_SYST_CSR_COUNTFLAG_Pos (16UL) /*!< COUNTFLAG (Bit 16) */
#define PPB_SYST_CSR_COUNTFLAG_Msk (0x10000UL) /*!< COUNTFLAG (Bitfield-Mask: 0x01) */
#define PPB_SYST_CSR_CLKSOURCE_Pos (2UL) /*!< CLKSOURCE (Bit 2) */
#define PPB_SYST_CSR_CLKSOURCE_Msk (0x4UL) /*!< CLKSOURCE (Bitfield-Mask: 0x01) */
#define PPB_SYST_CSR_TICKINT_Pos (1UL) /*!< TICKINT (Bit 1) */
#define PPB_SYST_CSR_TICKINT_Msk (0x2UL) /*!< TICKINT (Bitfield-Mask: 0x01) */
#define PPB_SYST_CSR_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */
#define PPB_SYST_CSR_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */
/* ======================================================= SYST_RVR ======================================================== */
#define PPB_SYST_RVR_RELOAD_Pos (0UL) /*!< RELOAD (Bit 0) */
#define PPB_SYST_RVR_RELOAD_Msk (0xffffffUL) /*!< RELOAD (Bitfield-Mask: 0xffffff) */
/* ======================================================= SYST_CVR ======================================================== */
#define PPB_SYST_CVR_CURRENT_Pos (0UL) /*!< CURRENT (Bit 0) */
#define PPB_SYST_CVR_CURRENT_Msk (0xffffffUL) /*!< CURRENT (Bitfield-Mask: 0xffffff) */
/* ====================================================== SYST_CALIB ======================================================= */
#define PPB_SYST_CALIB_NOREF_Pos (31UL) /*!< NOREF (Bit 31) */
#define PPB_SYST_CALIB_NOREF_Msk (0x80000000UL) /*!< NOREF (Bitfield-Mask: 0x01) */
#define PPB_SYST_CALIB_SKEW_Pos (30UL) /*!< SKEW (Bit 30) */
#define PPB_SYST_CALIB_SKEW_Msk (0x40000000UL) /*!< SKEW (Bitfield-Mask: 0x01) */
#define PPB_SYST_CALIB_TENMS_Pos (0UL) /*!< TENMS (Bit 0) */
#define PPB_SYST_CALIB_TENMS_Msk (0xffffffUL) /*!< TENMS (Bitfield-Mask: 0xffffff) */
/* ======================================================= NVIC_ISER ======================================================= */
#define PPB_NVIC_ISER_SETENA_Pos (0UL) /*!< SETENA (Bit 0) */
#define PPB_NVIC_ISER_SETENA_Msk (0xffffffffUL) /*!< SETENA (Bitfield-Mask: 0xffffffff) */
/* ======================================================= NVIC_ICER ======================================================= */
#define PPB_NVIC_ICER_CLRENA_Pos (0UL) /*!< CLRENA (Bit 0) */
#define PPB_NVIC_ICER_CLRENA_Msk (0xffffffffUL) /*!< CLRENA (Bitfield-Mask: 0xffffffff) */
/* ======================================================= NVIC_ISPR ======================================================= */
#define PPB_NVIC_ISPR_SETPEND_Pos (0UL) /*!< SETPEND (Bit 0) */
#define PPB_NVIC_ISPR_SETPEND_Msk (0xffffffffUL) /*!< SETPEND (Bitfield-Mask: 0xffffffff) */
/* ======================================================= NVIC_ICPR ======================================================= */
#define PPB_NVIC_ICPR_CLRPEND_Pos (0UL) /*!< CLRPEND (Bit 0) */
#define PPB_NVIC_ICPR_CLRPEND_Msk (0xffffffffUL) /*!< CLRPEND (Bitfield-Mask: 0xffffffff) */
/* ======================================================= NVIC_IPR0 ======================================================= */
#define PPB_NVIC_IPR0_IP_3_Pos (30UL) /*!< IP_3 (Bit 30) */
#define PPB_NVIC_IPR0_IP_3_Msk (0xc0000000UL) /*!< IP_3 (Bitfield-Mask: 0x03) */
#define PPB_NVIC_IPR0_IP_2_Pos (22UL) /*!< IP_2 (Bit 22) */
#define PPB_NVIC_IPR0_IP_2_Msk (0xc00000UL) /*!< IP_2 (Bitfield-Mask: 0x03) */
#define PPB_NVIC_IPR0_IP_1_Pos (14UL) /*!< IP_1 (Bit 14) */
#define PPB_NVIC_IPR0_IP_1_Msk (0xc000UL) /*!< IP_1 (Bitfield-Mask: 0x03) */
#define PPB_NVIC_IPR0_IP_0_Pos (6UL) /*!< IP_0 (Bit 6) */
#define PPB_NVIC_IPR0_IP_0_Msk (0xc0UL) /*!< IP_0 (Bitfield-Mask: 0x03) */
/* ======================================================= NVIC_IPR1 ======================================================= */
#define PPB_NVIC_IPR1_IP_7_Pos (30UL) /*!< IP_7 (Bit 30) */
#define PPB_NVIC_IPR1_IP_7_Msk (0xc0000000UL) /*!< IP_7 (Bitfield-Mask: 0x03) */
#define PPB_NVIC_IPR1_IP_6_Pos (22UL) /*!< IP_6 (Bit 22) */
#define PPB_NVIC_IPR1_IP_6_Msk (0xc00000UL) /*!< IP_6 (Bitfield-Mask: 0x03) */
#define PPB_NVIC_IPR1_IP_5_Pos (14UL) /*!< IP_5 (Bit 14) */
#define PPB_NVIC_IPR1_IP_5_Msk (0xc000UL) /*!< IP_5 (Bitfield-Mask: 0x03) */
#define PPB_NVIC_IPR1_IP_4_Pos (6UL) /*!< IP_4 (Bit 6) */
#define PPB_NVIC_IPR1_IP_4_Msk (0xc0UL) /*!< IP_4 (Bitfield-Mask: 0x03) */
/* ======================================================= NVIC_IPR2 ======================================================= */
#define PPB_NVIC_IPR2_IP_11_Pos (30UL) /*!< IP_11 (Bit 30) */
#define PPB_NVIC_IPR2_IP_11_Msk (0xc0000000UL) /*!< IP_11 (Bitfield-Mask: 0x03) */
#define PPB_NVIC_IPR2_IP_10_Pos (22UL) /*!< IP_10 (Bit 22) */
#define PPB_NVIC_IPR2_IP_10_Msk (0xc00000UL) /*!< IP_10 (Bitfield-Mask: 0x03) */
#define PPB_NVIC_IPR2_IP_9_Pos (14UL) /*!< IP_9 (Bit 14) */
#define PPB_NVIC_IPR2_IP_9_Msk (0xc000UL) /*!< IP_9 (Bitfield-Mask: 0x03) */
#define PPB_NVIC_IPR2_IP_8_Pos (6UL) /*!< IP_8 (Bit 6) */
#define PPB_NVIC_IPR2_IP_8_Msk (0xc0UL) /*!< IP_8 (Bitfield-Mask: 0x03) */
/* ======================================================= NVIC_IPR3 ======================================================= */
#define PPB_NVIC_IPR3_IP_15_Pos (30UL) /*!< IP_15 (Bit 30) */
#define PPB_NVIC_IPR3_IP_15_Msk (0xc0000000UL) /*!< IP_15 (Bitfield-Mask: 0x03) */
#define PPB_NVIC_IPR3_IP_14_Pos (22UL) /*!< IP_14 (Bit 22) */
#define PPB_NVIC_IPR3_IP_14_Msk (0xc00000UL) /*!< IP_14 (Bitfield-Mask: 0x03) */
#define PPB_NVIC_IPR3_IP_13_Pos (14UL) /*!< IP_13 (Bit 14) */
#define PPB_NVIC_IPR3_IP_13_Msk (0xc000UL) /*!< IP_13 (Bitfield-Mask: 0x03) */
#define PPB_NVIC_IPR3_IP_12_Pos (6UL) /*!< IP_12 (Bit 6) */
#define PPB_NVIC_IPR3_IP_12_Msk (0xc0UL) /*!< IP_12 (Bitfield-Mask: 0x03) */
/* ======================================================= NVIC_IPR4 ======================================================= */
#define PPB_NVIC_IPR4_IP_19_Pos (30UL) /*!< IP_19 (Bit 30) */
#define PPB_NVIC_IPR4_IP_19_Msk (0xc0000000UL) /*!< IP_19 (Bitfield-Mask: 0x03) */
#define PPB_NVIC_IPR4_IP_18_Pos (22UL) /*!< IP_18 (Bit 22) */
#define PPB_NVIC_IPR4_IP_18_Msk (0xc00000UL) /*!< IP_18 (Bitfield-Mask: 0x03) */
#define PPB_NVIC_IPR4_IP_17_Pos (14UL) /*!< IP_17 (Bit 14) */
#define PPB_NVIC_IPR4_IP_17_Msk (0xc000UL) /*!< IP_17 (Bitfield-Mask: 0x03) */
#define PPB_NVIC_IPR4_IP_16_Pos (6UL) /*!< IP_16 (Bit 6) */
#define PPB_NVIC_IPR4_IP_16_Msk (0xc0UL) /*!< IP_16 (Bitfield-Mask: 0x03) */
/* ======================================================= NVIC_IPR5 ======================================================= */
#define PPB_NVIC_IPR5_IP_23_Pos (30UL) /*!< IP_23 (Bit 30) */
#define PPB_NVIC_IPR5_IP_23_Msk (0xc0000000UL) /*!< IP_23 (Bitfield-Mask: 0x03) */
#define PPB_NVIC_IPR5_IP_22_Pos (22UL) /*!< IP_22 (Bit 22) */
#define PPB_NVIC_IPR5_IP_22_Msk (0xc00000UL) /*!< IP_22 (Bitfield-Mask: 0x03) */
#define PPB_NVIC_IPR5_IP_21_Pos (14UL) /*!< IP_21 (Bit 14) */
#define PPB_NVIC_IPR5_IP_21_Msk (0xc000UL) /*!< IP_21 (Bitfield-Mask: 0x03) */
#define PPB_NVIC_IPR5_IP_20_Pos (6UL) /*!< IP_20 (Bit 6) */
#define PPB_NVIC_IPR5_IP_20_Msk (0xc0UL) /*!< IP_20 (Bitfield-Mask: 0x03) */
/* ======================================================= NVIC_IPR6 ======================================================= */
#define PPB_NVIC_IPR6_IP_27_Pos (30UL) /*!< IP_27 (Bit 30) */
#define PPB_NVIC_IPR6_IP_27_Msk (0xc0000000UL) /*!< IP_27 (Bitfield-Mask: 0x03) */
#define PPB_NVIC_IPR6_IP_26_Pos (22UL) /*!< IP_26 (Bit 22) */
#define PPB_NVIC_IPR6_IP_26_Msk (0xc00000UL) /*!< IP_26 (Bitfield-Mask: 0x03) */
#define PPB_NVIC_IPR6_IP_25_Pos (14UL) /*!< IP_25 (Bit 14) */
#define PPB_NVIC_IPR6_IP_25_Msk (0xc000UL) /*!< IP_25 (Bitfield-Mask: 0x03) */
#define PPB_NVIC_IPR6_IP_24_Pos (6UL) /*!< IP_24 (Bit 6) */
#define PPB_NVIC_IPR6_IP_24_Msk (0xc0UL) /*!< IP_24 (Bitfield-Mask: 0x03) */
/* ======================================================= NVIC_IPR7 ======================================================= */
#define PPB_NVIC_IPR7_IP_31_Pos (30UL) /*!< IP_31 (Bit 30) */
#define PPB_NVIC_IPR7_IP_31_Msk (0xc0000000UL) /*!< IP_31 (Bitfield-Mask: 0x03) */
#define PPB_NVIC_IPR7_IP_30_Pos (22UL) /*!< IP_30 (Bit 22) */
#define PPB_NVIC_IPR7_IP_30_Msk (0xc00000UL) /*!< IP_30 (Bitfield-Mask: 0x03) */
#define PPB_NVIC_IPR7_IP_29_Pos (14UL) /*!< IP_29 (Bit 14) */
#define PPB_NVIC_IPR7_IP_29_Msk (0xc000UL) /*!< IP_29 (Bitfield-Mask: 0x03) */
#define PPB_NVIC_IPR7_IP_28_Pos (6UL) /*!< IP_28 (Bit 6) */
#define PPB_NVIC_IPR7_IP_28_Msk (0xc0UL) /*!< IP_28 (Bitfield-Mask: 0x03) */
/* ========================================================= CPUID ========================================================= */
#define PPB_CPUID_IMPLEMENTER_Pos (24UL) /*!< IMPLEMENTER (Bit 24) */
#define PPB_CPUID_IMPLEMENTER_Msk (0xff000000UL) /*!< IMPLEMENTER (Bitfield-Mask: 0xff) */
#define PPB_CPUID_VARIANT_Pos (20UL) /*!< VARIANT (Bit 20) */
#define PPB_CPUID_VARIANT_Msk (0xf00000UL) /*!< VARIANT (Bitfield-Mask: 0x0f) */
#define PPB_CPUID_ARCHITECTURE_Pos (16UL) /*!< ARCHITECTURE (Bit 16) */
#define PPB_CPUID_ARCHITECTURE_Msk (0xf0000UL) /*!< ARCHITECTURE (Bitfield-Mask: 0x0f) */
#define PPB_CPUID_PARTNO_Pos (4UL) /*!< PARTNO (Bit 4) */
#define PPB_CPUID_PARTNO_Msk (0xfff0UL) /*!< PARTNO (Bitfield-Mask: 0xfff) */
#define PPB_CPUID_REVISION_Pos (0UL) /*!< REVISION (Bit 0) */
#define PPB_CPUID_REVISION_Msk (0xfUL) /*!< REVISION (Bitfield-Mask: 0x0f) */
/* ========================================================= ICSR ========================================================== */
#define PPB_ICSR_NMIPENDSET_Pos (31UL) /*!< NMIPENDSET (Bit 31) */
#define PPB_ICSR_NMIPENDSET_Msk (0x80000000UL) /*!< NMIPENDSET (Bitfield-Mask: 0x01) */
#define PPB_ICSR_PENDSVSET_Pos (28UL) /*!< PENDSVSET (Bit 28) */
#define PPB_ICSR_PENDSVSET_Msk (0x10000000UL) /*!< PENDSVSET (Bitfield-Mask: 0x01) */
#define PPB_ICSR_PENDSVCLR_Pos (27UL) /*!< PENDSVCLR (Bit 27) */
#define PPB_ICSR_PENDSVCLR_Msk (0x8000000UL) /*!< PENDSVCLR (Bitfield-Mask: 0x01) */
#define PPB_ICSR_PENDSTSET_Pos (26UL) /*!< PENDSTSET (Bit 26) */
#define PPB_ICSR_PENDSTSET_Msk (0x4000000UL) /*!< PENDSTSET (Bitfield-Mask: 0x01) */
#define PPB_ICSR_PENDSTCLR_Pos (25UL) /*!< PENDSTCLR (Bit 25) */
#define PPB_ICSR_PENDSTCLR_Msk (0x2000000UL) /*!< PENDSTCLR (Bitfield-Mask: 0x01) */
#define PPB_ICSR_ISRPREEMPT_Pos (23UL) /*!< ISRPREEMPT (Bit 23) */
#define PPB_ICSR_ISRPREEMPT_Msk (0x800000UL) /*!< ISRPREEMPT (Bitfield-Mask: 0x01) */
#define PPB_ICSR_ISRPENDING_Pos (22UL) /*!< ISRPENDING (Bit 22) */
#define PPB_ICSR_ISRPENDING_Msk (0x400000UL) /*!< ISRPENDING (Bitfield-Mask: 0x01) */
#define PPB_ICSR_VECTPENDING_Pos (12UL) /*!< VECTPENDING (Bit 12) */
#define PPB_ICSR_VECTPENDING_Msk (0x1ff000UL) /*!< VECTPENDING (Bitfield-Mask: 0x1ff) */
#define PPB_ICSR_VECTACTIVE_Pos (0UL) /*!< VECTACTIVE (Bit 0) */
#define PPB_ICSR_VECTACTIVE_Msk (0x1ffUL) /*!< VECTACTIVE (Bitfield-Mask: 0x1ff) */
/* ========================================================= VTOR ========================================================== */
#define PPB_VTOR_TBLOFF_Pos (8UL) /*!< TBLOFF (Bit 8) */
#define PPB_VTOR_TBLOFF_Msk (0xffffff00UL) /*!< TBLOFF (Bitfield-Mask: 0xffffff) */
/* ========================================================= AIRCR ========================================================= */
#define PPB_AIRCR_VECTKEY_Pos (16UL) /*!< VECTKEY (Bit 16) */
#define PPB_AIRCR_VECTKEY_Msk (0xffff0000UL) /*!< VECTKEY (Bitfield-Mask: 0xffff) */
#define PPB_AIRCR_ENDIANESS_Pos (15UL) /*!< ENDIANESS (Bit 15) */
#define PPB_AIRCR_ENDIANESS_Msk (0x8000UL) /*!< ENDIANESS (Bitfield-Mask: 0x01) */
#define PPB_AIRCR_SYSRESETREQ_Pos (2UL) /*!< SYSRESETREQ (Bit 2) */
#define PPB_AIRCR_SYSRESETREQ_Msk (0x4UL) /*!< SYSRESETREQ (Bitfield-Mask: 0x01) */
#define PPB_AIRCR_VECTCLRACTIVE_Pos (1UL) /*!< VECTCLRACTIVE (Bit 1) */
#define PPB_AIRCR_VECTCLRACTIVE_Msk (0x2UL) /*!< VECTCLRACTIVE (Bitfield-Mask: 0x01) */
/* ========================================================== SCR ========================================================== */
#define PPB_SCR_SEVONPEND_Pos (4UL) /*!< SEVONPEND (Bit 4) */
#define PPB_SCR_SEVONPEND_Msk (0x10UL) /*!< SEVONPEND (Bitfield-Mask: 0x01) */
#define PPB_SCR_SLEEPDEEP_Pos (2UL) /*!< SLEEPDEEP (Bit 2) */
#define PPB_SCR_SLEEPDEEP_Msk (0x4UL) /*!< SLEEPDEEP (Bitfield-Mask: 0x01) */
#define PPB_SCR_SLEEPONEXIT_Pos (1UL) /*!< SLEEPONEXIT (Bit 1) */
#define PPB_SCR_SLEEPONEXIT_Msk (0x2UL) /*!< SLEEPONEXIT (Bitfield-Mask: 0x01) */
/* ========================================================== CCR ========================================================== */
#define PPB_CCR_STKALIGN_Pos (9UL) /*!< STKALIGN (Bit 9) */
#define PPB_CCR_STKALIGN_Msk (0x200UL) /*!< STKALIGN (Bitfield-Mask: 0x01) */
#define PPB_CCR_UNALIGN_TRP_Pos (3UL) /*!< UNALIGN_TRP (Bit 3) */
#define PPB_CCR_UNALIGN_TRP_Msk (0x8UL) /*!< UNALIGN_TRP (Bitfield-Mask: 0x01) */
/* ========================================================= SHPR2 ========================================================= */
#define PPB_SHPR2_PRI_11_Pos (30UL) /*!< PRI_11 (Bit 30) */
#define PPB_SHPR2_PRI_11_Msk (0xc0000000UL) /*!< PRI_11 (Bitfield-Mask: 0x03) */
/* ========================================================= SHPR3 ========================================================= */
#define PPB_SHPR3_PRI_15_Pos (30UL) /*!< PRI_15 (Bit 30) */
#define PPB_SHPR3_PRI_15_Msk (0xc0000000UL) /*!< PRI_15 (Bitfield-Mask: 0x03) */
#define PPB_SHPR3_PRI_14_Pos (22UL) /*!< PRI_14 (Bit 22) */
#define PPB_SHPR3_PRI_14_Msk (0xc00000UL) /*!< PRI_14 (Bitfield-Mask: 0x03) */
/* ========================================================= SHCSR ========================================================= */
#define PPB_SHCSR_SVCALLPENDED_Pos (15UL) /*!< SVCALLPENDED (Bit 15) */
#define PPB_SHCSR_SVCALLPENDED_Msk (0x8000UL) /*!< SVCALLPENDED (Bitfield-Mask: 0x01) */
/* ======================================================= MPU_TYPE ======================================================== */
#define PPB_MPU_TYPE_IREGION_Pos (16UL) /*!< IREGION (Bit 16) */
#define PPB_MPU_TYPE_IREGION_Msk (0xff0000UL) /*!< IREGION (Bitfield-Mask: 0xff) */
#define PPB_MPU_TYPE_DREGION_Pos (8UL) /*!< DREGION (Bit 8) */
#define PPB_MPU_TYPE_DREGION_Msk (0xff00UL) /*!< DREGION (Bitfield-Mask: 0xff) */
#define PPB_MPU_TYPE_SEPARATE_Pos (0UL) /*!< SEPARATE (Bit 0) */
#define PPB_MPU_TYPE_SEPARATE_Msk (0x1UL) /*!< SEPARATE (Bitfield-Mask: 0x01) */
/* ======================================================= MPU_CTRL ======================================================== */
#define PPB_MPU_CTRL_PRIVDEFENA_Pos (2UL) /*!< PRIVDEFENA (Bit 2) */
#define PPB_MPU_CTRL_PRIVDEFENA_Msk (0x4UL) /*!< PRIVDEFENA (Bitfield-Mask: 0x01) */
#define PPB_MPU_CTRL_HFNMIENA_Pos (1UL) /*!< HFNMIENA (Bit 1) */
#define PPB_MPU_CTRL_HFNMIENA_Msk (0x2UL) /*!< HFNMIENA (Bitfield-Mask: 0x01) */
#define PPB_MPU_CTRL_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */
#define PPB_MPU_CTRL_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */
/* ======================================================== MPU_RNR ======================================================== */
#define PPB_MPU_RNR_REGION_Pos (0UL) /*!< REGION (Bit 0) */
#define PPB_MPU_RNR_REGION_Msk (0xfUL) /*!< REGION (Bitfield-Mask: 0x0f) */
/* ======================================================= MPU_RBAR ======================================================== */
#define PPB_MPU_RBAR_ADDR_Pos (8UL) /*!< ADDR (Bit 8) */
#define PPB_MPU_RBAR_ADDR_Msk (0xffffff00UL) /*!< ADDR (Bitfield-Mask: 0xffffff) */
#define PPB_MPU_RBAR_VALID_Pos (4UL) /*!< VALID (Bit 4) */
#define PPB_MPU_RBAR_VALID_Msk (0x10UL) /*!< VALID (Bitfield-Mask: 0x01) */
#define PPB_MPU_RBAR_REGION_Pos (0UL) /*!< REGION (Bit 0) */
#define PPB_MPU_RBAR_REGION_Msk (0xfUL) /*!< REGION (Bitfield-Mask: 0x0f) */
/* ======================================================= MPU_RASR ======================================================== */
#define PPB_MPU_RASR_ATTRS_Pos (16UL) /*!< ATTRS (Bit 16) */
#define PPB_MPU_RASR_ATTRS_Msk (0xffff0000UL) /*!< ATTRS (Bitfield-Mask: 0xffff) */
#define PPB_MPU_RASR_SRD_Pos (8UL) /*!< SRD (Bit 8) */
#define PPB_MPU_RASR_SRD_Msk (0xff00UL) /*!< SRD (Bitfield-Mask: 0xff) */
#define PPB_MPU_RASR_SIZE_Pos (1UL) /*!< SIZE (Bit 1) */
#define PPB_MPU_RASR_SIZE_Msk (0x3eUL) /*!< SIZE (Bitfield-Mask: 0x1f) */
#define PPB_MPU_RASR_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */
#define PPB_MPU_RASR_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */
/** @} */ /* End of group PosMask_peripherals */
/* =========================================================================================================================== */
/* ================ Enumerated Values Peripheral Section ================ */
/* =========================================================================================================================== */
/** @addtogroup EnumValue_peripherals
* @{
*/
/* =========================================================================================================================== */
/* ================ XIP_CTRL ================ */
/* =========================================================================================================================== */
/* ========================================================= CTRL ========================================================== */
/* ========================================================= FLUSH ========================================================= */
/* ========================================================= STAT ========================================================== */
/* ======================================================== CTR_HIT ======================================================== */
/* ======================================================== CTR_ACC ======================================================== */
/* ====================================================== STREAM_ADDR ====================================================== */
/* ====================================================== STREAM_CTR ======================================================= */
/* ====================================================== STREAM_FIFO ====================================================== */
/* =========================================================================================================================== */
/* ================ XIP_SSI ================ */
/* =========================================================================================================================== */
/* ======================================================== CTRLR0 ========================================================= */
/* ============================================ XIP_SSI CTRLR0 SPI_FRF [21..22] ============================================ */
typedef enum { /*!< XIP_SSI_CTRLR0_SPI_FRF */
XIP_SSI_CTRLR0_SPI_FRF_STD = 0, /*!< STD : Standard 1-bit SPI frame format; 1 bit per SCK, full-duplex */
XIP_SSI_CTRLR0_SPI_FRF_DUAL = 1, /*!< DUAL : Dual-SPI frame format; two bits per SCK, half-duplex */
XIP_SSI_CTRLR0_SPI_FRF_QUAD = 2, /*!< QUAD : Quad-SPI frame format; four bits per SCK, half-duplex */
} XIP_SSI_CTRLR0_SPI_FRF_Enum;
/* ============================================== XIP_SSI CTRLR0 TMOD [8..9] =============================================== */
typedef enum { /*!< XIP_SSI_CTRLR0_TMOD */
XIP_SSI_CTRLR0_TMOD_TX_AND_RX = 0, /*!< TX_AND_RX : Both transmit and receive */
XIP_SSI_CTRLR0_TMOD_TX_ONLY = 1, /*!< TX_ONLY : Transmit only (not for FRF == 0, standard SPI mode) */
XIP_SSI_CTRLR0_TMOD_RX_ONLY = 2, /*!< RX_ONLY : Receive only (not for FRF == 0, standard SPI mode) */
XIP_SSI_CTRLR0_TMOD_EEPROM_READ = 3, /*!< EEPROM_READ : EEPROM read mode (TX then RX; RX starts after
control data TX'd) */
} XIP_SSI_CTRLR0_TMOD_Enum;
/* ======================================================== CTRLR1 ========================================================= */
/* ======================================================== SSIENR ========================================================= */
/* ========================================================= MWCR ========================================================== */
/* ========================================================== SER ========================================================== */
/* ========================================================= BAUDR ========================================================= */
/* ======================================================== TXFTLR ========================================================= */
/* ======================================================== RXFTLR ========================================================= */
/* ========================================================= TXFLR ========================================================= */
/* ========================================================= RXFLR ========================================================= */
/* ========================================================== SR =========================================================== */
/* ========================================================== IMR ========================================================== */
/* ========================================================== ISR ========================================================== */
/* ========================================================= RISR ========================================================== */
/* ======================================================== TXOICR ========================================================= */
/* ======================================================== RXOICR ========================================================= */
/* ======================================================== RXUICR ========================================================= */
/* ======================================================== MSTICR ========================================================= */
/* ========================================================== ICR ========================================================== */
/* ========================================================= DMACR ========================================================= */
/* ======================================================== DMATDLR ======================================================== */
/* ======================================================== DMARDLR ======================================================== */
/* ========================================================== IDR ========================================================== */
/* ==================================================== SSI_VERSION_ID ===================================================== */
/* ========================================================== DR0 ========================================================== */
/* ===================================================== RX_SAMPLE_DLY ===================================================== */
/* ====================================================== SPI_CTRLR0 ======================================================= */
/* =========================================== XIP_SSI SPI_CTRLR0 INST_L [8..9] ============================================ */
typedef enum { /*!< XIP_SSI_SPI_CTRLR0_INST_L */
XIP_SSI_SPI_CTRLR0_INST_L_NONE = 0, /*!< NONE : No instruction */
XIP_SSI_SPI_CTRLR0_INST_L_4B = 1, /*!< 4B : 4-bit instruction */
XIP_SSI_SPI_CTRLR0_INST_L_8B = 2, /*!< 8B : 8-bit instruction */
XIP_SSI_SPI_CTRLR0_INST_L_16B = 3, /*!< 16B : 16-bit instruction */
} XIP_SSI_SPI_CTRLR0_INST_L_Enum;
/* ========================================= XIP_SSI SPI_CTRLR0 TRANS_TYPE [0..1] ========================================== */
typedef enum { /*!< XIP_SSI_SPI_CTRLR0_TRANS_TYPE */
XIP_SSI_SPI_CTRLR0_TRANS_TYPE_1C1A = 0, /*!< 1C1A : Command and address both in standard SPI frame format */
XIP_SSI_SPI_CTRLR0_TRANS_TYPE_1C2A = 1, /*!< 1C2A : Command in standard SPI format, address in format specified
by FRF */
XIP_SSI_SPI_CTRLR0_TRANS_TYPE_2C2A = 2, /*!< 2C2A : Command and address both in format specified by FRF (e.g.
Dual-SPI) */
} XIP_SSI_SPI_CTRLR0_TRANS_TYPE_Enum;
/* ==================================================== TXD_DRIVE_EDGE ===================================================== */
/* =========================================================================================================================== */
/* ================ SYSINFO ================ */
/* =========================================================================================================================== */
/* ======================================================== CHIP_ID ======================================================== */
/* ======================================================= PLATFORM ======================================================== */
/* ===================================================== GITREF_RP2040 ===================================================== */
/* =========================================================================================================================== */
/* ================ SYSCFG ================ */
/* =========================================================================================================================== */
/* ==================================================== PROC0_NMI_MASK ===================================================== */
/* ==================================================== PROC1_NMI_MASK ===================================================== */
/* ====================================================== PROC_CONFIG ====================================================== */
/* ================================================== PROC_IN_SYNC_BYPASS ================================================== */
/* ================================================ PROC_IN_SYNC_BYPASS_HI ================================================= */
/* ======================================================= DBGFORCE ======================================================== */
/* ===================================================== MEMPOWERDOWN ====================================================== */
/* =========================================================================================================================== */
/* ================ CLOCKS ================ */
/* =========================================================================================================================== */
/* ==================================================== CLK_GPOUT0_CTRL ==================================================== */
/* ========================================= CLOCKS CLK_GPOUT0_CTRL AUXSRC [5..8] ========================================== */
typedef enum { /*!< CLOCKS_CLK_GPOUT0_CTRL_AUXSRC */
CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_clksrc_pll_sys = 0,/*!< clksrc_pll_sys : clksrc_pll_sys */
CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_clksrc_gpin0 = 1,/*!< clksrc_gpin0 : clksrc_gpin0 */
CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_clksrc_gpin1 = 2,/*!< clksrc_gpin1 : clksrc_gpin1 */
CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_clksrc_pll_usb = 3,/*!< clksrc_pll_usb : clksrc_pll_usb */
CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_rosc_clksrc = 4,/*!< rosc_clksrc : rosc_clksrc */
CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_xosc_clksrc = 5,/*!< xosc_clksrc : xosc_clksrc */
CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_clk_sys = 6, /*!< clk_sys : clk_sys */
CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_clk_usb = 7, /*!< clk_usb : clk_usb */
CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_clk_adc = 8, /*!< clk_adc : clk_adc */
CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_clk_rtc = 9, /*!< clk_rtc : clk_rtc */
CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_clk_ref = 10, /*!< clk_ref : clk_ref */
} CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_Enum;
/* ==================================================== CLK_GPOUT0_DIV ===================================================== */
/* ================================================== CLK_GPOUT0_SELECTED ================================================== */
/* ==================================================== CLK_GPOUT1_CTRL ==================================================== */
/* ========================================= CLOCKS CLK_GPOUT1_CTRL AUXSRC [5..8] ========================================== */
typedef enum { /*!< CLOCKS_CLK_GPOUT1_CTRL_AUXSRC */
CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_clksrc_pll_sys = 0,/*!< clksrc_pll_sys : clksrc_pll_sys */
CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_clksrc_gpin0 = 1,/*!< clksrc_gpin0 : clksrc_gpin0 */
CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_clksrc_gpin1 = 2,/*!< clksrc_gpin1 : clksrc_gpin1 */
CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_clksrc_pll_usb = 3,/*!< clksrc_pll_usb : clksrc_pll_usb */
CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_rosc_clksrc = 4,/*!< rosc_clksrc : rosc_clksrc */
CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_xosc_clksrc = 5,/*!< xosc_clksrc : xosc_clksrc */
CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_clk_sys = 6, /*!< clk_sys : clk_sys */
CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_clk_usb = 7, /*!< clk_usb : clk_usb */
CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_clk_adc = 8, /*!< clk_adc : clk_adc */
CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_clk_rtc = 9, /*!< clk_rtc : clk_rtc */
CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_clk_ref = 10, /*!< clk_ref : clk_ref */
} CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_Enum;
/* ==================================================== CLK_GPOUT1_DIV ===================================================== */
/* ================================================== CLK_GPOUT1_SELECTED ================================================== */
/* ==================================================== CLK_GPOUT2_CTRL ==================================================== */
/* ========================================= CLOCKS CLK_GPOUT2_CTRL AUXSRC [5..8] ========================================== */
typedef enum { /*!< CLOCKS_CLK_GPOUT2_CTRL_AUXSRC */
CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_clksrc_pll_sys = 0,/*!< clksrc_pll_sys : clksrc_pll_sys */
CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_clksrc_gpin0 = 1,/*!< clksrc_gpin0 : clksrc_gpin0 */
CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_clksrc_gpin1 = 2,/*!< clksrc_gpin1 : clksrc_gpin1 */
CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_clksrc_pll_usb = 3,/*!< clksrc_pll_usb : clksrc_pll_usb */
CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_rosc_clksrc_ph = 4,/*!< rosc_clksrc_ph : rosc_clksrc_ph */
CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_xosc_clksrc = 5,/*!< xosc_clksrc : xosc_clksrc */
CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_clk_sys = 6, /*!< clk_sys : clk_sys */
CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_clk_usb = 7, /*!< clk_usb : clk_usb */
CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_clk_adc = 8, /*!< clk_adc : clk_adc */
CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_clk_rtc = 9, /*!< clk_rtc : clk_rtc */
CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_clk_ref = 10, /*!< clk_ref : clk_ref */
} CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_Enum;
/* ==================================================== CLK_GPOUT2_DIV ===================================================== */
/* ================================================== CLK_GPOUT2_SELECTED ================================================== */
/* ==================================================== CLK_GPOUT3_CTRL ==================================================== */
/* ========================================= CLOCKS CLK_GPOUT3_CTRL AUXSRC [5..8] ========================================== */
typedef enum { /*!< CLOCKS_CLK_GPOUT3_CTRL_AUXSRC */
CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_clksrc_pll_sys = 0,/*!< clksrc_pll_sys : clksrc_pll_sys */
CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_clksrc_gpin0 = 1,/*!< clksrc_gpin0 : clksrc_gpin0 */
CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_clksrc_gpin1 = 2,/*!< clksrc_gpin1 : clksrc_gpin1 */
CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_clksrc_pll_usb = 3,/*!< clksrc_pll_usb : clksrc_pll_usb */
CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_rosc_clksrc_ph = 4,/*!< rosc_clksrc_ph : rosc_clksrc_ph */
CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_xosc_clksrc = 5,/*!< xosc_clksrc : xosc_clksrc */
CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_clk_sys = 6, /*!< clk_sys : clk_sys */
CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_clk_usb = 7, /*!< clk_usb : clk_usb */
CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_clk_adc = 8, /*!< clk_adc : clk_adc */
CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_clk_rtc = 9, /*!< clk_rtc : clk_rtc */
CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_clk_ref = 10, /*!< clk_ref : clk_ref */
} CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_Enum;
/* ==================================================== CLK_GPOUT3_DIV ===================================================== */
/* ================================================== CLK_GPOUT3_SELECTED ================================================== */
/* ===================================================== CLK_REF_CTRL ====================================================== */
/* =========================================== CLOCKS CLK_REF_CTRL AUXSRC [5..6] =========================================== */
typedef enum { /*!< CLOCKS_CLK_REF_CTRL_AUXSRC */
CLOCKS_CLK_REF_CTRL_AUXSRC_clksrc_pll_usb = 0,/*!< clksrc_pll_usb : clksrc_pll_usb */
CLOCKS_CLK_REF_CTRL_AUXSRC_clksrc_gpin0 = 1, /*!< clksrc_gpin0 : clksrc_gpin0 */
CLOCKS_CLK_REF_CTRL_AUXSRC_clksrc_gpin1 = 2, /*!< clksrc_gpin1 : clksrc_gpin1 */
} CLOCKS_CLK_REF_CTRL_AUXSRC_Enum;
/* ============================================ CLOCKS CLK_REF_CTRL SRC [0..1] ============================================= */
typedef enum { /*!< CLOCKS_CLK_REF_CTRL_SRC */
CLOCKS_CLK_REF_CTRL_SRC_rosc_clksrc_ph = 0, /*!< rosc_clksrc_ph : rosc_clksrc_ph */
CLOCKS_CLK_REF_CTRL_SRC_clksrc_clk_ref_aux = 1,/*!< clksrc_clk_ref_aux : clksrc_clk_ref_aux */
CLOCKS_CLK_REF_CTRL_SRC_xosc_clksrc = 2, /*!< xosc_clksrc : xosc_clksrc */
} CLOCKS_CLK_REF_CTRL_SRC_Enum;
/* ====================================================== CLK_REF_DIV ====================================================== */
/* =================================================== CLK_REF_SELECTED ==================================================== */
/* ===================================================== CLK_SYS_CTRL ====================================================== */
/* =========================================== CLOCKS CLK_SYS_CTRL AUXSRC [5..7] =========================================== */
typedef enum { /*!< CLOCKS_CLK_SYS_CTRL_AUXSRC */
CLOCKS_CLK_SYS_CTRL_AUXSRC_clksrc_pll_sys = 0,/*!< clksrc_pll_sys : clksrc_pll_sys */
CLOCKS_CLK_SYS_CTRL_AUXSRC_clksrc_pll_usb = 1,/*!< clksrc_pll_usb : clksrc_pll_usb */
CLOCKS_CLK_SYS_CTRL_AUXSRC_rosc_clksrc = 2, /*!< rosc_clksrc : rosc_clksrc */
CLOCKS_CLK_SYS_CTRL_AUXSRC_xosc_clksrc = 3, /*!< xosc_clksrc : xosc_clksrc */
CLOCKS_CLK_SYS_CTRL_AUXSRC_clksrc_gpin0 = 4, /*!< clksrc_gpin0 : clksrc_gpin0 */
CLOCKS_CLK_SYS_CTRL_AUXSRC_clksrc_gpin1 = 5, /*!< clksrc_gpin1 : clksrc_gpin1 */
} CLOCKS_CLK_SYS_CTRL_AUXSRC_Enum;
/* ============================================ CLOCKS CLK_SYS_CTRL SRC [0..0] ============================================= */
typedef enum { /*!< CLOCKS_CLK_SYS_CTRL_SRC */
CLOCKS_CLK_SYS_CTRL_SRC_clk_ref = 0, /*!< clk_ref : clk_ref */
CLOCKS_CLK_SYS_CTRL_SRC_clksrc_clk_sys_aux = 1,/*!< clksrc_clk_sys_aux : clksrc_clk_sys_aux */
} CLOCKS_CLK_SYS_CTRL_SRC_Enum;
/* ====================================================== CLK_SYS_DIV ====================================================== */
/* =================================================== CLK_SYS_SELECTED ==================================================== */
/* ===================================================== CLK_PERI_CTRL ===================================================== */
/* ========================================== CLOCKS CLK_PERI_CTRL AUXSRC [5..7] =========================================== */
typedef enum { /*!< CLOCKS_CLK_PERI_CTRL_AUXSRC */
CLOCKS_CLK_PERI_CTRL_AUXSRC_clk_sys = 0, /*!< clk_sys : clk_sys */
CLOCKS_CLK_PERI_CTRL_AUXSRC_clksrc_pll_sys = 1,/*!< clksrc_pll_sys : clksrc_pll_sys */
CLOCKS_CLK_PERI_CTRL_AUXSRC_clksrc_pll_usb = 2,/*!< clksrc_pll_usb : clksrc_pll_usb */
CLOCKS_CLK_PERI_CTRL_AUXSRC_rosc_clksrc_ph = 3,/*!< rosc_clksrc_ph : rosc_clksrc_ph */
CLOCKS_CLK_PERI_CTRL_AUXSRC_xosc_clksrc = 4, /*!< xosc_clksrc : xosc_clksrc */
CLOCKS_CLK_PERI_CTRL_AUXSRC_clksrc_gpin0 = 5, /*!< clksrc_gpin0 : clksrc_gpin0 */
CLOCKS_CLK_PERI_CTRL_AUXSRC_clksrc_gpin1 = 6, /*!< clksrc_gpin1 : clksrc_gpin1 */
} CLOCKS_CLK_PERI_CTRL_AUXSRC_Enum;
/* =================================================== CLK_PERI_SELECTED =================================================== */
/* ===================================================== CLK_USB_CTRL ====================================================== */
/* =========================================== CLOCKS CLK_USB_CTRL AUXSRC [5..7] =========================================== */
typedef enum { /*!< CLOCKS_CLK_USB_CTRL_AUXSRC */
CLOCKS_CLK_USB_CTRL_AUXSRC_clksrc_pll_usb = 0,/*!< clksrc_pll_usb : clksrc_pll_usb */
CLOCKS_CLK_USB_CTRL_AUXSRC_clksrc_pll_sys = 1,/*!< clksrc_pll_sys : clksrc_pll_sys */
CLOCKS_CLK_USB_CTRL_AUXSRC_rosc_clksrc_ph = 2,/*!< rosc_clksrc_ph : rosc_clksrc_ph */
CLOCKS_CLK_USB_CTRL_AUXSRC_xosc_clksrc = 3, /*!< xosc_clksrc : xosc_clksrc */
CLOCKS_CLK_USB_CTRL_AUXSRC_clksrc_gpin0 = 4, /*!< clksrc_gpin0 : clksrc_gpin0 */
CLOCKS_CLK_USB_CTRL_AUXSRC_clksrc_gpin1 = 5, /*!< clksrc_gpin1 : clksrc_gpin1 */
} CLOCKS_CLK_USB_CTRL_AUXSRC_Enum;
/* ====================================================== CLK_USB_DIV ====================================================== */
/* =================================================== CLK_USB_SELECTED ==================================================== */
/* ===================================================== CLK_ADC_CTRL ====================================================== */
/* =========================================== CLOCKS CLK_ADC_CTRL AUXSRC [5..7] =========================================== */
typedef enum { /*!< CLOCKS_CLK_ADC_CTRL_AUXSRC */
CLOCKS_CLK_ADC_CTRL_AUXSRC_clksrc_pll_usb = 0,/*!< clksrc_pll_usb : clksrc_pll_usb */
CLOCKS_CLK_ADC_CTRL_AUXSRC_clksrc_pll_sys = 1,/*!< clksrc_pll_sys : clksrc_pll_sys */
CLOCKS_CLK_ADC_CTRL_AUXSRC_rosc_clksrc_ph = 2,/*!< rosc_clksrc_ph : rosc_clksrc_ph */
CLOCKS_CLK_ADC_CTRL_AUXSRC_xosc_clksrc = 3, /*!< xosc_clksrc : xosc_clksrc */
CLOCKS_CLK_ADC_CTRL_AUXSRC_clksrc_gpin0 = 4, /*!< clksrc_gpin0 : clksrc_gpin0 */
CLOCKS_CLK_ADC_CTRL_AUXSRC_clksrc_gpin1 = 5, /*!< clksrc_gpin1 : clksrc_gpin1 */
} CLOCKS_CLK_ADC_CTRL_AUXSRC_Enum;
/* ====================================================== CLK_ADC_DIV ====================================================== */
/* =================================================== CLK_ADC_SELECTED ==================================================== */
/* ===================================================== CLK_RTC_CTRL ====================================================== */
/* =========================================== CLOCKS CLK_RTC_CTRL AUXSRC [5..7] =========================================== */
typedef enum { /*!< CLOCKS_CLK_RTC_CTRL_AUXSRC */
CLOCKS_CLK_RTC_CTRL_AUXSRC_clksrc_pll_usb = 0,/*!< clksrc_pll_usb : clksrc_pll_usb */
CLOCKS_CLK_RTC_CTRL_AUXSRC_clksrc_pll_sys = 1,/*!< clksrc_pll_sys : clksrc_pll_sys */
CLOCKS_CLK_RTC_CTRL_AUXSRC_rosc_clksrc_ph = 2,/*!< rosc_clksrc_ph : rosc_clksrc_ph */
CLOCKS_CLK_RTC_CTRL_AUXSRC_xosc_clksrc = 3, /*!< xosc_clksrc : xosc_clksrc */
CLOCKS_CLK_RTC_CTRL_AUXSRC_clksrc_gpin0 = 4, /*!< clksrc_gpin0 : clksrc_gpin0 */
CLOCKS_CLK_RTC_CTRL_AUXSRC_clksrc_gpin1 = 5, /*!< clksrc_gpin1 : clksrc_gpin1 */
} CLOCKS_CLK_RTC_CTRL_AUXSRC_Enum;
/* ====================================================== CLK_RTC_DIV ====================================================== */
/* =================================================== CLK_RTC_SELECTED ==================================================== */
/* ================================================== CLK_SYS_RESUS_CTRL =================================================== */
/* ================================================= CLK_SYS_RESUS_STATUS ================================================== */
/* ====================================================== FC0_REF_KHZ ====================================================== */
/* ====================================================== FC0_MIN_KHZ ====================================================== */
/* ====================================================== FC0_MAX_KHZ ====================================================== */
/* ======================================================= FC0_DELAY ======================================================= */
/* ===================================================== FC0_INTERVAL ====================================================== */
/* ======================================================== FC0_SRC ======================================================== */
/* ============================================= CLOCKS FC0_SRC FC0_SRC [0..7] ============================================= */
typedef enum { /*!< CLOCKS_FC0_SRC_FC0_SRC */
CLOCKS_FC0_SRC_FC0_SRC_NULL = 0, /*!< NULL : NULL */
CLOCKS_FC0_SRC_FC0_SRC_pll_sys_clksrc_primary = 1,/*!< pll_sys_clksrc_primary : pll_sys_clksrc_primary */
CLOCKS_FC0_SRC_FC0_SRC_pll_usb_clksrc_primary = 2,/*!< pll_usb_clksrc_primary : pll_usb_clksrc_primary */
CLOCKS_FC0_SRC_FC0_SRC_rosc_clksrc = 3, /*!< rosc_clksrc : rosc_clksrc */
CLOCKS_FC0_SRC_FC0_SRC_rosc_clksrc_ph = 4, /*!< rosc_clksrc_ph : rosc_clksrc_ph */
CLOCKS_FC0_SRC_FC0_SRC_xosc_clksrc = 5, /*!< xosc_clksrc : xosc_clksrc */
CLOCKS_FC0_SRC_FC0_SRC_clksrc_gpin0 = 6, /*!< clksrc_gpin0 : clksrc_gpin0 */
CLOCKS_FC0_SRC_FC0_SRC_clksrc_gpin1 = 7, /*!< clksrc_gpin1 : clksrc_gpin1 */
CLOCKS_FC0_SRC_FC0_SRC_clk_ref = 8, /*!< clk_ref : clk_ref */
CLOCKS_FC0_SRC_FC0_SRC_clk_sys = 9, /*!< clk_sys : clk_sys */
CLOCKS_FC0_SRC_FC0_SRC_clk_peri = 10, /*!< clk_peri : clk_peri */
CLOCKS_FC0_SRC_FC0_SRC_clk_usb = 11, /*!< clk_usb : clk_usb */
CLOCKS_FC0_SRC_FC0_SRC_clk_adc = 12, /*!< clk_adc : clk_adc */
CLOCKS_FC0_SRC_FC0_SRC_clk_rtc = 13, /*!< clk_rtc : clk_rtc */
} CLOCKS_FC0_SRC_FC0_SRC_Enum;
/* ====================================================== FC0_STATUS ======================================================= */
/* ====================================================== FC0_RESULT ======================================================= */
/* ======================================================= WAKE_EN0 ======================================================== */
/* ======================================================= WAKE_EN1 ======================================================== */
/* ======================================================= SLEEP_EN0 ======================================================= */
/* ======================================================= SLEEP_EN1 ======================================================= */
/* ======================================================= ENABLED0 ======================================================== */
/* ======================================================= ENABLED1 ======================================================== */
/* ========================================================= INTR ========================================================== */
/* ========================================================= INTE ========================================================== */
/* ========================================================= INTF ========================================================== */
/* ========================================================= INTS ========================================================== */
/* =========================================================================================================================== */
/* ================ RESETS ================ */
/* =========================================================================================================================== */
/* ========================================================= RESET ========================================================= */
/* ========================================================= WDSEL ========================================================= */
/* ====================================================== RESET_DONE ======================================================= */
/* =========================================================================================================================== */
/* ================ PSM ================ */
/* =========================================================================================================================== */
/* ======================================================== FRCE_ON ======================================================== */
/* ======================================================= FRCE_OFF ======================================================== */
/* ========================================================= WDSEL ========================================================= */
/* ========================================================= DONE ========================================================== */
/* =========================================================================================================================== */
/* ================ IO_BANK0 ================ */
/* =========================================================================================================================== */
/* ===================================================== GPIO0_STATUS ====================================================== */
/* ====================================================== GPIO0_CTRL ======================================================= */
/* ========================================= IO_BANK0 GPIO0_CTRL IRQOVER [28..29] ========================================== */
typedef enum { /*!< IO_BANK0_GPIO0_CTRL_IRQOVER */
IO_BANK0_GPIO0_CTRL_IRQOVER_NORMAL = 0, /*!< NORMAL : don't invert the interrupt */
IO_BANK0_GPIO0_CTRL_IRQOVER_INVERT = 1, /*!< INVERT : invert the interrupt */
IO_BANK0_GPIO0_CTRL_IRQOVER_LOW = 2, /*!< LOW : drive interrupt low */
IO_BANK0_GPIO0_CTRL_IRQOVER_HIGH = 3, /*!< HIGH : drive interrupt high */
} IO_BANK0_GPIO0_CTRL_IRQOVER_Enum;
/* ========================================== IO_BANK0 GPIO0_CTRL INOVER [16..17] ========================================== */
typedef enum { /*!< IO_BANK0_GPIO0_CTRL_INOVER */
IO_BANK0_GPIO0_CTRL_INOVER_NORMAL = 0, /*!< NORMAL : don't invert the peri input */
IO_BANK0_GPIO0_CTRL_INOVER_INVERT = 1, /*!< INVERT : invert the peri input */
IO_BANK0_GPIO0_CTRL_INOVER_LOW = 2, /*!< LOW : drive peri input low */
IO_BANK0_GPIO0_CTRL_INOVER_HIGH = 3, /*!< HIGH : drive peri input high */
} IO_BANK0_GPIO0_CTRL_INOVER_Enum;
/* ========================================== IO_BANK0 GPIO0_CTRL OEOVER [12..13] ========================================== */
typedef enum { /*!< IO_BANK0_GPIO0_CTRL_OEOVER */
IO_BANK0_GPIO0_CTRL_OEOVER_NORMAL = 0, /*!< NORMAL : drive output enable from peripheral signal selected
by funcsel */
IO_BANK0_GPIO0_CTRL_OEOVER_INVERT = 1, /*!< INVERT : drive output enable from inverse of peripheral signal
selected by funcsel */
IO_BANK0_GPIO0_CTRL_OEOVER_DISABLE = 2, /*!< DISABLE : disable output */
IO_BANK0_GPIO0_CTRL_OEOVER_ENABLE = 3, /*!< ENABLE : enable output */
} IO_BANK0_GPIO0_CTRL_OEOVER_Enum;
/* ========================================== IO_BANK0 GPIO0_CTRL OUTOVER [8..9] =========================================== */
typedef enum { /*!< IO_BANK0_GPIO0_CTRL_OUTOVER */
IO_BANK0_GPIO0_CTRL_OUTOVER_NORMAL = 0, /*!< NORMAL : drive output from peripheral signal selected by funcsel */
IO_BANK0_GPIO0_CTRL_OUTOVER_INVERT = 1, /*!< INVERT : drive output from inverse of peripheral signal selected
by funcsel */
IO_BANK0_GPIO0_CTRL_OUTOVER_LOW = 2, /*!< LOW : drive output low */
IO_BANK0_GPIO0_CTRL_OUTOVER_HIGH = 3, /*!< HIGH : drive output high */
} IO_BANK0_GPIO0_CTRL_OUTOVER_Enum;
/* ========================================== IO_BANK0 GPIO0_CTRL FUNCSEL [0..4] =========================================== */
typedef enum { /*!< IO_BANK0_GPIO0_CTRL_FUNCSEL */
IO_BANK0_GPIO0_CTRL_FUNCSEL_jtag_tck = 0, /*!< jtag_tck : jtag_tck */
IO_BANK0_GPIO0_CTRL_FUNCSEL_spi0_rx = 1, /*!< spi0_rx : spi0_rx */
IO_BANK0_GPIO0_CTRL_FUNCSEL_uart0_tx = 2, /*!< uart0_tx : uart0_tx */
IO_BANK0_GPIO0_CTRL_FUNCSEL_i2c0_sda = 3, /*!< i2c0_sda : i2c0_sda */
IO_BANK0_GPIO0_CTRL_FUNCSEL_pwm_a_0 = 4, /*!< pwm_a_0 : pwm_a_0 */
IO_BANK0_GPIO0_CTRL_FUNCSEL_sio_0 = 5, /*!< sio_0 : sio_0 */
IO_BANK0_GPIO0_CTRL_FUNCSEL_pio0_0 = 6, /*!< pio0_0 : pio0_0 */
IO_BANK0_GPIO0_CTRL_FUNCSEL_pio1_0 = 7, /*!< pio1_0 : pio1_0 */
IO_BANK0_GPIO0_CTRL_FUNCSEL_usb_muxing_overcurr_detect = 9,/*!< usb_muxing_overcurr_detect : usb_muxing_overcurr_detect */
IO_BANK0_GPIO0_CTRL_FUNCSEL_null = 31, /*!< null : null */
} IO_BANK0_GPIO0_CTRL_FUNCSEL_Enum;
/* ===================================================== GPIO1_STATUS ====================================================== */
/* ====================================================== GPIO1_CTRL ======================================================= */
/* ========================================= IO_BANK0 GPIO1_CTRL IRQOVER [28..29] ========================================== */
typedef enum { /*!< IO_BANK0_GPIO1_CTRL_IRQOVER */
IO_BANK0_GPIO1_CTRL_IRQOVER_NORMAL = 0, /*!< NORMAL : don't invert the interrupt */
IO_BANK0_GPIO1_CTRL_IRQOVER_INVERT = 1, /*!< INVERT : invert the interrupt */
IO_BANK0_GPIO1_CTRL_IRQOVER_LOW = 2, /*!< LOW : drive interrupt low */
IO_BANK0_GPIO1_CTRL_IRQOVER_HIGH = 3, /*!< HIGH : drive interrupt high */
} IO_BANK0_GPIO1_CTRL_IRQOVER_Enum;
/* ========================================== IO_BANK0 GPIO1_CTRL INOVER [16..17] ========================================== */
typedef enum { /*!< IO_BANK0_GPIO1_CTRL_INOVER */
IO_BANK0_GPIO1_CTRL_INOVER_NORMAL = 0, /*!< NORMAL : don't invert the peri input */
IO_BANK0_GPIO1_CTRL_INOVER_INVERT = 1, /*!< INVERT : invert the peri input */
IO_BANK0_GPIO1_CTRL_INOVER_LOW = 2, /*!< LOW : drive peri input low */
IO_BANK0_GPIO1_CTRL_INOVER_HIGH = 3, /*!< HIGH : drive peri input high */
} IO_BANK0_GPIO1_CTRL_INOVER_Enum;
/* ========================================== IO_BANK0 GPIO1_CTRL OEOVER [12..13] ========================================== */
typedef enum { /*!< IO_BANK0_GPIO1_CTRL_OEOVER */
IO_BANK0_GPIO1_CTRL_OEOVER_NORMAL = 0, /*!< NORMAL : drive output enable from peripheral signal selected
by funcsel */
IO_BANK0_GPIO1_CTRL_OEOVER_INVERT = 1, /*!< INVERT : drive output enable from inverse of peripheral signal
selected by funcsel */
IO_BANK0_GPIO1_CTRL_OEOVER_DISABLE = 2, /*!< DISABLE : disable output */
IO_BANK0_GPIO1_CTRL_OEOVER_ENABLE = 3, /*!< ENABLE : enable output */
} IO_BANK0_GPIO1_CTRL_OEOVER_Enum;
/* ========================================== IO_BANK0 GPIO1_CTRL OUTOVER [8..9] =========================================== */
typedef enum { /*!< IO_BANK0_GPIO1_CTRL_OUTOVER */
IO_BANK0_GPIO1_CTRL_OUTOVER_NORMAL = 0, /*!< NORMAL : drive output from peripheral signal selected by funcsel */
IO_BANK0_GPIO1_CTRL_OUTOVER_INVERT = 1, /*!< INVERT : drive output from inverse of peripheral signal selected
by funcsel */
IO_BANK0_GPIO1_CTRL_OUTOVER_LOW = 2, /*!< LOW : drive output low */
IO_BANK0_GPIO1_CTRL_OUTOVER_HIGH = 3, /*!< HIGH : drive output high */
} IO_BANK0_GPIO1_CTRL_OUTOVER_Enum;
/* ========================================== IO_BANK0 GPIO1_CTRL FUNCSEL [0..4] =========================================== */
typedef enum { /*!< IO_BANK0_GPIO1_CTRL_FUNCSEL */
IO_BANK0_GPIO1_CTRL_FUNCSEL_jtag_tms = 0, /*!< jtag_tms : jtag_tms */
IO_BANK0_GPIO1_CTRL_FUNCSEL_spi0_ss_n = 1, /*!< spi0_ss_n : spi0_ss_n */
IO_BANK0_GPIO1_CTRL_FUNCSEL_uart0_rx = 2, /*!< uart0_rx : uart0_rx */
IO_BANK0_GPIO1_CTRL_FUNCSEL_i2c0_scl = 3, /*!< i2c0_scl : i2c0_scl */
IO_BANK0_GPIO1_CTRL_FUNCSEL_pwm_b_0 = 4, /*!< pwm_b_0 : pwm_b_0 */
IO_BANK0_GPIO1_CTRL_FUNCSEL_sio_1 = 5, /*!< sio_1 : sio_1 */
IO_BANK0_GPIO1_CTRL_FUNCSEL_pio0_1 = 6, /*!< pio0_1 : pio0_1 */
IO_BANK0_GPIO1_CTRL_FUNCSEL_pio1_1 = 7, /*!< pio1_1 : pio1_1 */
IO_BANK0_GPIO1_CTRL_FUNCSEL_usb_muxing_vbus_detect = 9,/*!< usb_muxing_vbus_detect : usb_muxing_vbus_detect */
IO_BANK0_GPIO1_CTRL_FUNCSEL_null = 31, /*!< null : null */
} IO_BANK0_GPIO1_CTRL_FUNCSEL_Enum;
/* ===================================================== GPIO2_STATUS ====================================================== */
/* ====================================================== GPIO2_CTRL ======================================================= */
/* ========================================= IO_BANK0 GPIO2_CTRL IRQOVER [28..29] ========================================== */
typedef enum { /*!< IO_BANK0_GPIO2_CTRL_IRQOVER */
IO_BANK0_GPIO2_CTRL_IRQOVER_NORMAL = 0, /*!< NORMAL : don't invert the interrupt */
IO_BANK0_GPIO2_CTRL_IRQOVER_INVERT = 1, /*!< INVERT : invert the interrupt */
IO_BANK0_GPIO2_CTRL_IRQOVER_LOW = 2, /*!< LOW : drive interrupt low */
IO_BANK0_GPIO2_CTRL_IRQOVER_HIGH = 3, /*!< HIGH : drive interrupt high */
} IO_BANK0_GPIO2_CTRL_IRQOVER_Enum;
/* ========================================== IO_BANK0 GPIO2_CTRL INOVER [16..17] ========================================== */
typedef enum { /*!< IO_BANK0_GPIO2_CTRL_INOVER */
IO_BANK0_GPIO2_CTRL_INOVER_NORMAL = 0, /*!< NORMAL : don't invert the peri input */
IO_BANK0_GPIO2_CTRL_INOVER_INVERT = 1, /*!< INVERT : invert the peri input */
IO_BANK0_GPIO2_CTRL_INOVER_LOW = 2, /*!< LOW : drive peri input low */
IO_BANK0_GPIO2_CTRL_INOVER_HIGH = 3, /*!< HIGH : drive peri input high */
} IO_BANK0_GPIO2_CTRL_INOVER_Enum;
/* ========================================== IO_BANK0 GPIO2_CTRL OEOVER [12..13] ========================================== */
typedef enum { /*!< IO_BANK0_GPIO2_CTRL_OEOVER */
IO_BANK0_GPIO2_CTRL_OEOVER_NORMAL = 0, /*!< NORMAL : drive output enable from peripheral signal selected
by funcsel */
IO_BANK0_GPIO2_CTRL_OEOVER_INVERT = 1, /*!< INVERT : drive output enable from inverse of peripheral signal
selected by funcsel */
IO_BANK0_GPIO2_CTRL_OEOVER_DISABLE = 2, /*!< DISABLE : disable output */
IO_BANK0_GPIO2_CTRL_OEOVER_ENABLE = 3, /*!< ENABLE : enable output */
} IO_BANK0_GPIO2_CTRL_OEOVER_Enum;
/* ========================================== IO_BANK0 GPIO2_CTRL OUTOVER [8..9] =========================================== */
typedef enum { /*!< IO_BANK0_GPIO2_CTRL_OUTOVER */
IO_BANK0_GPIO2_CTRL_OUTOVER_NORMAL = 0, /*!< NORMAL : drive output from peripheral signal selected by funcsel */
IO_BANK0_GPIO2_CTRL_OUTOVER_INVERT = 1, /*!< INVERT : drive output from inverse of peripheral signal selected
by funcsel */
IO_BANK0_GPIO2_CTRL_OUTOVER_LOW = 2, /*!< LOW : drive output low */
IO_BANK0_GPIO2_CTRL_OUTOVER_HIGH = 3, /*!< HIGH : drive output high */
} IO_BANK0_GPIO2_CTRL_OUTOVER_Enum;
/* ========================================== IO_BANK0 GPIO2_CTRL FUNCSEL [0..4] =========================================== */
typedef enum { /*!< IO_BANK0_GPIO2_CTRL_FUNCSEL */
IO_BANK0_GPIO2_CTRL_FUNCSEL_jtag_tdi = 0, /*!< jtag_tdi : jtag_tdi */
IO_BANK0_GPIO2_CTRL_FUNCSEL_spi0_sclk = 1, /*!< spi0_sclk : spi0_sclk */
IO_BANK0_GPIO2_CTRL_FUNCSEL_uart0_cts = 2, /*!< uart0_cts : uart0_cts */
IO_BANK0_GPIO2_CTRL_FUNCSEL_i2c1_sda = 3, /*!< i2c1_sda : i2c1_sda */
IO_BANK0_GPIO2_CTRL_FUNCSEL_pwm_a_1 = 4, /*!< pwm_a_1 : pwm_a_1 */
IO_BANK0_GPIO2_CTRL_FUNCSEL_sio_2 = 5, /*!< sio_2 : sio_2 */
IO_BANK0_GPIO2_CTRL_FUNCSEL_pio0_2 = 6, /*!< pio0_2 : pio0_2 */
IO_BANK0_GPIO2_CTRL_FUNCSEL_pio1_2 = 7, /*!< pio1_2 : pio1_2 */
IO_BANK0_GPIO2_CTRL_FUNCSEL_usb_muxing_vbus_en = 9,/*!< usb_muxing_vbus_en : usb_muxing_vbus_en */
IO_BANK0_GPIO2_CTRL_FUNCSEL_null = 31, /*!< null : null */
} IO_BANK0_GPIO2_CTRL_FUNCSEL_Enum;
/* ===================================================== GPIO3_STATUS ====================================================== */
/* ====================================================== GPIO3_CTRL ======================================================= */
/* ========================================= IO_BANK0 GPIO3_CTRL IRQOVER [28..29] ========================================== */
typedef enum { /*!< IO_BANK0_GPIO3_CTRL_IRQOVER */
IO_BANK0_GPIO3_CTRL_IRQOVER_NORMAL = 0, /*!< NORMAL : don't invert the interrupt */
IO_BANK0_GPIO3_CTRL_IRQOVER_INVERT = 1, /*!< INVERT : invert the interrupt */
IO_BANK0_GPIO3_CTRL_IRQOVER_LOW = 2, /*!< LOW : drive interrupt low */
IO_BANK0_GPIO3_CTRL_IRQOVER_HIGH = 3, /*!< HIGH : drive interrupt high */
} IO_BANK0_GPIO3_CTRL_IRQOVER_Enum;
/* ========================================== IO_BANK0 GPIO3_CTRL INOVER [16..17] ========================================== */
typedef enum { /*!< IO_BANK0_GPIO3_CTRL_INOVER */
IO_BANK0_GPIO3_CTRL_INOVER_NORMAL = 0, /*!< NORMAL : don't invert the peri input */
IO_BANK0_GPIO3_CTRL_INOVER_INVERT = 1, /*!< INVERT : invert the peri input */
IO_BANK0_GPIO3_CTRL_INOVER_LOW = 2, /*!< LOW : drive peri input low */
IO_BANK0_GPIO3_CTRL_INOVER_HIGH = 3, /*!< HIGH : drive peri input high */
} IO_BANK0_GPIO3_CTRL_INOVER_Enum;
/* ========================================== IO_BANK0 GPIO3_CTRL OEOVER [12..13] ========================================== */
typedef enum { /*!< IO_BANK0_GPIO3_CTRL_OEOVER */
IO_BANK0_GPIO3_CTRL_OEOVER_NORMAL = 0, /*!< NORMAL : drive output enable from peripheral signal selected
by funcsel */
IO_BANK0_GPIO3_CTRL_OEOVER_INVERT = 1, /*!< INVERT : drive output enable from inverse of peripheral signal
selected by funcsel */
IO_BANK0_GPIO3_CTRL_OEOVER_DISABLE = 2, /*!< DISABLE : disable output */
IO_BANK0_GPIO3_CTRL_OEOVER_ENABLE = 3, /*!< ENABLE : enable output */
} IO_BANK0_GPIO3_CTRL_OEOVER_Enum;
/* ========================================== IO_BANK0 GPIO3_CTRL OUTOVER [8..9] =========================================== */
typedef enum { /*!< IO_BANK0_GPIO3_CTRL_OUTOVER */
IO_BANK0_GPIO3_CTRL_OUTOVER_NORMAL = 0, /*!< NORMAL : drive output from peripheral signal selected by funcsel */
IO_BANK0_GPIO3_CTRL_OUTOVER_INVERT = 1, /*!< INVERT : drive output from inverse of peripheral signal selected
by funcsel */
IO_BANK0_GPIO3_CTRL_OUTOVER_LOW = 2, /*!< LOW : drive output low */
IO_BANK0_GPIO3_CTRL_OUTOVER_HIGH = 3, /*!< HIGH : drive output high */
} IO_BANK0_GPIO3_CTRL_OUTOVER_Enum;
/* ========================================== IO_BANK0 GPIO3_CTRL FUNCSEL [0..4] =========================================== */
typedef enum { /*!< IO_BANK0_GPIO3_CTRL_FUNCSEL */
IO_BANK0_GPIO3_CTRL_FUNCSEL_jtag_tdo = 0, /*!< jtag_tdo : jtag_tdo */
IO_BANK0_GPIO3_CTRL_FUNCSEL_spi0_tx = 1, /*!< spi0_tx : spi0_tx */
IO_BANK0_GPIO3_CTRL_FUNCSEL_uart0_rts = 2, /*!< uart0_rts : uart0_rts */
IO_BANK0_GPIO3_CTRL_FUNCSEL_i2c1_scl = 3, /*!< i2c1_scl : i2c1_scl */
IO_BANK0_GPIO3_CTRL_FUNCSEL_pwm_b_1 = 4, /*!< pwm_b_1 : pwm_b_1 */
IO_BANK0_GPIO3_CTRL_FUNCSEL_sio_3 = 5, /*!< sio_3 : sio_3 */
IO_BANK0_GPIO3_CTRL_FUNCSEL_pio0_3 = 6, /*!< pio0_3 : pio0_3 */
IO_BANK0_GPIO3_CTRL_FUNCSEL_pio1_3 = 7, /*!< pio1_3 : pio1_3 */
IO_BANK0_GPIO3_CTRL_FUNCSEL_usb_muxing_overcurr_detect = 9,/*!< usb_muxing_overcurr_detect : usb_muxing_overcurr_detect */
IO_BANK0_GPIO3_CTRL_FUNCSEL_null = 31, /*!< null : null */
} IO_BANK0_GPIO3_CTRL_FUNCSEL_Enum;
/* ===================================================== GPIO4_STATUS ====================================================== */
/* ====================================================== GPIO4_CTRL ======================================================= */
/* ========================================= IO_BANK0 GPIO4_CTRL IRQOVER [28..29] ========================================== */
typedef enum { /*!< IO_BANK0_GPIO4_CTRL_IRQOVER */
IO_BANK0_GPIO4_CTRL_IRQOVER_NORMAL = 0, /*!< NORMAL : don't invert the interrupt */
IO_BANK0_GPIO4_CTRL_IRQOVER_INVERT = 1, /*!< INVERT : invert the interrupt */
IO_BANK0_GPIO4_CTRL_IRQOVER_LOW = 2, /*!< LOW : drive interrupt low */
IO_BANK0_GPIO4_CTRL_IRQOVER_HIGH = 3, /*!< HIGH : drive interrupt high */
} IO_BANK0_GPIO4_CTRL_IRQOVER_Enum;
/* ========================================== IO_BANK0 GPIO4_CTRL INOVER [16..17] ========================================== */
typedef enum { /*!< IO_BANK0_GPIO4_CTRL_INOVER */
IO_BANK0_GPIO4_CTRL_INOVER_NORMAL = 0, /*!< NORMAL : don't invert the peri input */
IO_BANK0_GPIO4_CTRL_INOVER_INVERT = 1, /*!< INVERT : invert the peri input */
IO_BANK0_GPIO4_CTRL_INOVER_LOW = 2, /*!< LOW : drive peri input low */
IO_BANK0_GPIO4_CTRL_INOVER_HIGH = 3, /*!< HIGH : drive peri input high */
} IO_BANK0_GPIO4_CTRL_INOVER_Enum;
/* ========================================== IO_BANK0 GPIO4_CTRL OEOVER [12..13] ========================================== */
typedef enum { /*!< IO_BANK0_GPIO4_CTRL_OEOVER */
IO_BANK0_GPIO4_CTRL_OEOVER_NORMAL = 0, /*!< NORMAL : drive output enable from peripheral signal selected
by funcsel */
IO_BANK0_GPIO4_CTRL_OEOVER_INVERT = 1, /*!< INVERT : drive output enable from inverse of peripheral signal
selected by funcsel */
IO_BANK0_GPIO4_CTRL_OEOVER_DISABLE = 2, /*!< DISABLE : disable output */
IO_BANK0_GPIO4_CTRL_OEOVER_ENABLE = 3, /*!< ENABLE : enable output */
} IO_BANK0_GPIO4_CTRL_OEOVER_Enum;
/* ========================================== IO_BANK0 GPIO4_CTRL OUTOVER [8..9] =========================================== */
typedef enum { /*!< IO_BANK0_GPIO4_CTRL_OUTOVER */
IO_BANK0_GPIO4_CTRL_OUTOVER_NORMAL = 0, /*!< NORMAL : drive output from peripheral signal selected by funcsel */
IO_BANK0_GPIO4_CTRL_OUTOVER_INVERT = 1, /*!< INVERT : drive output from inverse of peripheral signal selected
by funcsel */
IO_BANK0_GPIO4_CTRL_OUTOVER_LOW = 2, /*!< LOW : drive output low */
IO_BANK0_GPIO4_CTRL_OUTOVER_HIGH = 3, /*!< HIGH : drive output high */
} IO_BANK0_GPIO4_CTRL_OUTOVER_Enum;
/* ========================================== IO_BANK0 GPIO4_CTRL FUNCSEL [0..4] =========================================== */
typedef enum { /*!< IO_BANK0_GPIO4_CTRL_FUNCSEL */
IO_BANK0_GPIO4_CTRL_FUNCSEL_spi0_rx = 1, /*!< spi0_rx : spi0_rx */
IO_BANK0_GPIO4_CTRL_FUNCSEL_uart1_tx = 2, /*!< uart1_tx : uart1_tx */
IO_BANK0_GPIO4_CTRL_FUNCSEL_i2c0_sda = 3, /*!< i2c0_sda : i2c0_sda */
IO_BANK0_GPIO4_CTRL_FUNCSEL_pwm_a_2 = 4, /*!< pwm_a_2 : pwm_a_2 */
IO_BANK0_GPIO4_CTRL_FUNCSEL_sio_4 = 5, /*!< sio_4 : sio_4 */
IO_BANK0_GPIO4_CTRL_FUNCSEL_pio0_4 = 6, /*!< pio0_4 : pio0_4 */
IO_BANK0_GPIO4_CTRL_FUNCSEL_pio1_4 = 7, /*!< pio1_4 : pio1_4 */
IO_BANK0_GPIO4_CTRL_FUNCSEL_usb_muxing_vbus_detect = 9,/*!< usb_muxing_vbus_detect : usb_muxing_vbus_detect */
IO_BANK0_GPIO4_CTRL_FUNCSEL_null = 31, /*!< null : null */
} IO_BANK0_GPIO4_CTRL_FUNCSEL_Enum;
/* ===================================================== GPIO5_STATUS ====================================================== */
/* ====================================================== GPIO5_CTRL ======================================================= */
/* ========================================= IO_BANK0 GPIO5_CTRL IRQOVER [28..29] ========================================== */
typedef enum { /*!< IO_BANK0_GPIO5_CTRL_IRQOVER */
IO_BANK0_GPIO5_CTRL_IRQOVER_NORMAL = 0, /*!< NORMAL : don't invert the interrupt */
IO_BANK0_GPIO5_CTRL_IRQOVER_INVERT = 1, /*!< INVERT : invert the interrupt */
IO_BANK0_GPIO5_CTRL_IRQOVER_LOW = 2, /*!< LOW : drive interrupt low */
IO_BANK0_GPIO5_CTRL_IRQOVER_HIGH = 3, /*!< HIGH : drive interrupt high */
} IO_BANK0_GPIO5_CTRL_IRQOVER_Enum;
/* ========================================== IO_BANK0 GPIO5_CTRL INOVER [16..17] ========================================== */
typedef enum { /*!< IO_BANK0_GPIO5_CTRL_INOVER */
IO_BANK0_GPIO5_CTRL_INOVER_NORMAL = 0, /*!< NORMAL : don't invert the peri input */
IO_BANK0_GPIO5_CTRL_INOVER_INVERT = 1, /*!< INVERT : invert the peri input */
IO_BANK0_GPIO5_CTRL_INOVER_LOW = 2, /*!< LOW : drive peri input low */
IO_BANK0_GPIO5_CTRL_INOVER_HIGH = 3, /*!< HIGH : drive peri input high */
} IO_BANK0_GPIO5_CTRL_INOVER_Enum;
/* ========================================== IO_BANK0 GPIO5_CTRL OEOVER [12..13] ========================================== */
typedef enum { /*!< IO_BANK0_GPIO5_CTRL_OEOVER */
IO_BANK0_GPIO5_CTRL_OEOVER_NORMAL = 0, /*!< NORMAL : drive output enable from peripheral signal selected
by funcsel */
IO_BANK0_GPIO5_CTRL_OEOVER_INVERT = 1, /*!< INVERT : drive output enable from inverse of peripheral signal
selected by funcsel */
IO_BANK0_GPIO5_CTRL_OEOVER_DISABLE = 2, /*!< DISABLE : disable output */
IO_BANK0_GPIO5_CTRL_OEOVER_ENABLE = 3, /*!< ENABLE : enable output */
} IO_BANK0_GPIO5_CTRL_OEOVER_Enum;
/* ========================================== IO_BANK0 GPIO5_CTRL OUTOVER [8..9] =========================================== */
typedef enum { /*!< IO_BANK0_GPIO5_CTRL_OUTOVER */
IO_BANK0_GPIO5_CTRL_OUTOVER_NORMAL = 0, /*!< NORMAL : drive output from peripheral signal selected by funcsel */
IO_BANK0_GPIO5_CTRL_OUTOVER_INVERT = 1, /*!< INVERT : drive output from inverse of peripheral signal selected
by funcsel */
IO_BANK0_GPIO5_CTRL_OUTOVER_LOW = 2, /*!< LOW : drive output low */
IO_BANK0_GPIO5_CTRL_OUTOVER_HIGH = 3, /*!< HIGH : drive output high */
} IO_BANK0_GPIO5_CTRL_OUTOVER_Enum;
/* ========================================== IO_BANK0 GPIO5_CTRL FUNCSEL [0..4] =========================================== */
typedef enum { /*!< IO_BANK0_GPIO5_CTRL_FUNCSEL */
IO_BANK0_GPIO5_CTRL_FUNCSEL_spi0_ss_n = 1, /*!< spi0_ss_n : spi0_ss_n */
IO_BANK0_GPIO5_CTRL_FUNCSEL_uart1_rx = 2, /*!< uart1_rx : uart1_rx */
IO_BANK0_GPIO5_CTRL_FUNCSEL_i2c0_scl = 3, /*!< i2c0_scl : i2c0_scl */
IO_BANK0_GPIO5_CTRL_FUNCSEL_pwm_b_2 = 4, /*!< pwm_b_2 : pwm_b_2 */
IO_BANK0_GPIO5_CTRL_FUNCSEL_sio_5 = 5, /*!< sio_5 : sio_5 */
IO_BANK0_GPIO5_CTRL_FUNCSEL_pio0_5 = 6, /*!< pio0_5 : pio0_5 */
IO_BANK0_GPIO5_CTRL_FUNCSEL_pio1_5 = 7, /*!< pio1_5 : pio1_5 */
IO_BANK0_GPIO5_CTRL_FUNCSEL_usb_muxing_vbus_en = 9,/*!< usb_muxing_vbus_en : usb_muxing_vbus_en */
IO_BANK0_GPIO5_CTRL_FUNCSEL_null = 31, /*!< null : null */
} IO_BANK0_GPIO5_CTRL_FUNCSEL_Enum;
/* ===================================================== GPIO6_STATUS ====================================================== */
/* ====================================================== GPIO6_CTRL ======================================================= */
/* ========================================= IO_BANK0 GPIO6_CTRL IRQOVER [28..29] ========================================== */
typedef enum { /*!< IO_BANK0_GPIO6_CTRL_IRQOVER */
IO_BANK0_GPIO6_CTRL_IRQOVER_NORMAL = 0, /*!< NORMAL : don't invert the interrupt */
IO_BANK0_GPIO6_CTRL_IRQOVER_INVERT = 1, /*!< INVERT : invert the interrupt */
IO_BANK0_GPIO6_CTRL_IRQOVER_LOW = 2, /*!< LOW : drive interrupt low */
IO_BANK0_GPIO6_CTRL_IRQOVER_HIGH = 3, /*!< HIGH : drive interrupt high */
} IO_BANK0_GPIO6_CTRL_IRQOVER_Enum;
/* ========================================== IO_BANK0 GPIO6_CTRL INOVER [16..17] ========================================== */
typedef enum { /*!< IO_BANK0_GPIO6_CTRL_INOVER */
IO_BANK0_GPIO6_CTRL_INOVER_NORMAL = 0, /*!< NORMAL : don't invert the peri input */
IO_BANK0_GPIO6_CTRL_INOVER_INVERT = 1, /*!< INVERT : invert the peri input */
IO_BANK0_GPIO6_CTRL_INOVER_LOW = 2, /*!< LOW : drive peri input low */
IO_BANK0_GPIO6_CTRL_INOVER_HIGH = 3, /*!< HIGH : drive peri input high */
} IO_BANK0_GPIO6_CTRL_INOVER_Enum;
/* ========================================== IO_BANK0 GPIO6_CTRL OEOVER [12..13] ========================================== */
typedef enum { /*!< IO_BANK0_GPIO6_CTRL_OEOVER */
IO_BANK0_GPIO6_CTRL_OEOVER_NORMAL = 0, /*!< NORMAL : drive output enable from peripheral signal selected
by funcsel */
IO_BANK0_GPIO6_CTRL_OEOVER_INVERT = 1, /*!< INVERT : drive output enable from inverse of peripheral signal
selected by funcsel */
IO_BANK0_GPIO6_CTRL_OEOVER_DISABLE = 2, /*!< DISABLE : disable output */
IO_BANK0_GPIO6_CTRL_OEOVER_ENABLE = 3, /*!< ENABLE : enable output */
} IO_BANK0_GPIO6_CTRL_OEOVER_Enum;
/* ========================================== IO_BANK0 GPIO6_CTRL OUTOVER [8..9] =========================================== */
typedef enum { /*!< IO_BANK0_GPIO6_CTRL_OUTOVER */
IO_BANK0_GPIO6_CTRL_OUTOVER_NORMAL = 0, /*!< NORMAL : drive output from peripheral signal selected by funcsel */
IO_BANK0_GPIO6_CTRL_OUTOVER_INVERT = 1, /*!< INVERT : drive output from inverse of peripheral signal selected
by funcsel */
IO_BANK0_GPIO6_CTRL_OUTOVER_LOW = 2, /*!< LOW : drive output low */
IO_BANK0_GPIO6_CTRL_OUTOVER_HIGH = 3, /*!< HIGH : drive output high */
} IO_BANK0_GPIO6_CTRL_OUTOVER_Enum;
/* ========================================== IO_BANK0 GPIO6_CTRL FUNCSEL [0..4] =========================================== */
typedef enum { /*!< IO_BANK0_GPIO6_CTRL_FUNCSEL */
IO_BANK0_GPIO6_CTRL_FUNCSEL_spi0_sclk = 1, /*!< spi0_sclk : spi0_sclk */
IO_BANK0_GPIO6_CTRL_FUNCSEL_uart1_cts = 2, /*!< uart1_cts : uart1_cts */
IO_BANK0_GPIO6_CTRL_FUNCSEL_i2c1_sda = 3, /*!< i2c1_sda : i2c1_sda */
IO_BANK0_GPIO6_CTRL_FUNCSEL_pwm_a_3 = 4, /*!< pwm_a_3 : pwm_a_3 */
IO_BANK0_GPIO6_CTRL_FUNCSEL_sio_6 = 5, /*!< sio_6 : sio_6 */
IO_BANK0_GPIO6_CTRL_FUNCSEL_pio0_6 = 6, /*!< pio0_6 : pio0_6 */
IO_BANK0_GPIO6_CTRL_FUNCSEL_pio1_6 = 7, /*!< pio1_6 : pio1_6 */
IO_BANK0_GPIO6_CTRL_FUNCSEL_usb_muxing_extphy_softcon = 8,/*!< usb_muxing_extphy_softcon : usb_muxing_extphy_softcon */
IO_BANK0_GPIO6_CTRL_FUNCSEL_usb_muxing_overcurr_detect = 9,/*!< usb_muxing_overcurr_detect : usb_muxing_overcurr_detect */
IO_BANK0_GPIO6_CTRL_FUNCSEL_null = 31, /*!< null : null */
} IO_BANK0_GPIO6_CTRL_FUNCSEL_Enum;
/* ===================================================== GPIO7_STATUS ====================================================== */
/* ====================================================== GPIO7_CTRL ======================================================= */
/* ========================================= IO_BANK0 GPIO7_CTRL IRQOVER [28..29] ========================================== */
typedef enum { /*!< IO_BANK0_GPIO7_CTRL_IRQOVER */
IO_BANK0_GPIO7_CTRL_IRQOVER_NORMAL = 0, /*!< NORMAL : don't invert the interrupt */
IO_BANK0_GPIO7_CTRL_IRQOVER_INVERT = 1, /*!< INVERT : invert the interrupt */
IO_BANK0_GPIO7_CTRL_IRQOVER_LOW = 2, /*!< LOW : drive interrupt low */
IO_BANK0_GPIO7_CTRL_IRQOVER_HIGH = 3, /*!< HIGH : drive interrupt high */
} IO_BANK0_GPIO7_CTRL_IRQOVER_Enum;
/* ========================================== IO_BANK0 GPIO7_CTRL INOVER [16..17] ========================================== */
typedef enum { /*!< IO_BANK0_GPIO7_CTRL_INOVER */
IO_BANK0_GPIO7_CTRL_INOVER_NORMAL = 0, /*!< NORMAL : don't invert the peri input */
IO_BANK0_GPIO7_CTRL_INOVER_INVERT = 1, /*!< INVERT : invert the peri input */
IO_BANK0_GPIO7_CTRL_INOVER_LOW = 2, /*!< LOW : drive peri input low */
IO_BANK0_GPIO7_CTRL_INOVER_HIGH = 3, /*!< HIGH : drive peri input high */
} IO_BANK0_GPIO7_CTRL_INOVER_Enum;
/* ========================================== IO_BANK0 GPIO7_CTRL OEOVER [12..13] ========================================== */
typedef enum { /*!< IO_BANK0_GPIO7_CTRL_OEOVER */
IO_BANK0_GPIO7_CTRL_OEOVER_NORMAL = 0, /*!< NORMAL : drive output enable from peripheral signal selected
by funcsel */
IO_BANK0_GPIO7_CTRL_OEOVER_INVERT = 1, /*!< INVERT : drive output enable from inverse of peripheral signal
selected by funcsel */
IO_BANK0_GPIO7_CTRL_OEOVER_DISABLE = 2, /*!< DISABLE : disable output */
IO_BANK0_GPIO7_CTRL_OEOVER_ENABLE = 3, /*!< ENABLE : enable output */
} IO_BANK0_GPIO7_CTRL_OEOVER_Enum;
/* ========================================== IO_BANK0 GPIO7_CTRL OUTOVER [8..9] =========================================== */
typedef enum { /*!< IO_BANK0_GPIO7_CTRL_OUTOVER */
IO_BANK0_GPIO7_CTRL_OUTOVER_NORMAL = 0, /*!< NORMAL : drive output from peripheral signal selected by funcsel */
IO_BANK0_GPIO7_CTRL_OUTOVER_INVERT = 1, /*!< INVERT : drive output from inverse of peripheral signal selected
by funcsel */
IO_BANK0_GPIO7_CTRL_OUTOVER_LOW = 2, /*!< LOW : drive output low */
IO_BANK0_GPIO7_CTRL_OUTOVER_HIGH = 3, /*!< HIGH : drive output high */
} IO_BANK0_GPIO7_CTRL_OUTOVER_Enum;
/* ========================================== IO_BANK0 GPIO7_CTRL FUNCSEL [0..4] =========================================== */
typedef enum { /*!< IO_BANK0_GPIO7_CTRL_FUNCSEL */
IO_BANK0_GPIO7_CTRL_FUNCSEL_spi0_tx = 1, /*!< spi0_tx : spi0_tx */
IO_BANK0_GPIO7_CTRL_FUNCSEL_uart1_rts = 2, /*!< uart1_rts : uart1_rts */
IO_BANK0_GPIO7_CTRL_FUNCSEL_i2c1_scl = 3, /*!< i2c1_scl : i2c1_scl */
IO_BANK0_GPIO7_CTRL_FUNCSEL_pwm_b_3 = 4, /*!< pwm_b_3 : pwm_b_3 */
IO_BANK0_GPIO7_CTRL_FUNCSEL_sio_7 = 5, /*!< sio_7 : sio_7 */
IO_BANK0_GPIO7_CTRL_FUNCSEL_pio0_7 = 6, /*!< pio0_7 : pio0_7 */
IO_BANK0_GPIO7_CTRL_FUNCSEL_pio1_7 = 7, /*!< pio1_7 : pio1_7 */
IO_BANK0_GPIO7_CTRL_FUNCSEL_usb_muxing_extphy_oe_n = 8,/*!< usb_muxing_extphy_oe_n : usb_muxing_extphy_oe_n */
IO_BANK0_GPIO7_CTRL_FUNCSEL_usb_muxing_vbus_detect = 9,/*!< usb_muxing_vbus_detect : usb_muxing_vbus_detect */
IO_BANK0_GPIO7_CTRL_FUNCSEL_null = 31, /*!< null : null */
} IO_BANK0_GPIO7_CTRL_FUNCSEL_Enum;
/* ===================================================== GPIO8_STATUS ====================================================== */
/* ====================================================== GPIO8_CTRL ======================================================= */
/* ========================================= IO_BANK0 GPIO8_CTRL IRQOVER [28..29] ========================================== */
typedef enum { /*!< IO_BANK0_GPIO8_CTRL_IRQOVER */
IO_BANK0_GPIO8_CTRL_IRQOVER_NORMAL = 0, /*!< NORMAL : don't invert the interrupt */
IO_BANK0_GPIO8_CTRL_IRQOVER_INVERT = 1, /*!< INVERT : invert the interrupt */
IO_BANK0_GPIO8_CTRL_IRQOVER_LOW = 2, /*!< LOW : drive interrupt low */
IO_BANK0_GPIO8_CTRL_IRQOVER_HIGH = 3, /*!< HIGH : drive interrupt high */
} IO_BANK0_GPIO8_CTRL_IRQOVER_Enum;
/* ========================================== IO_BANK0 GPIO8_CTRL INOVER [16..17] ========================================== */
typedef enum { /*!< IO_BANK0_GPIO8_CTRL_INOVER */
IO_BANK0_GPIO8_CTRL_INOVER_NORMAL = 0, /*!< NORMAL : don't invert the peri input */
IO_BANK0_GPIO8_CTRL_INOVER_INVERT = 1, /*!< INVERT : invert the peri input */
IO_BANK0_GPIO8_CTRL_INOVER_LOW = 2, /*!< LOW : drive peri input low */
IO_BANK0_GPIO8_CTRL_INOVER_HIGH = 3, /*!< HIGH : drive peri input high */
} IO_BANK0_GPIO8_CTRL_INOVER_Enum;
/* ========================================== IO_BANK0 GPIO8_CTRL OEOVER [12..13] ========================================== */
typedef enum { /*!< IO_BANK0_GPIO8_CTRL_OEOVER */
IO_BANK0_GPIO8_CTRL_OEOVER_NORMAL = 0, /*!< NORMAL : drive output enable from peripheral signal selected
by funcsel */
IO_BANK0_GPIO8_CTRL_OEOVER_INVERT = 1, /*!< INVERT : drive output enable from inverse of peripheral signal
selected by funcsel */
IO_BANK0_GPIO8_CTRL_OEOVER_DISABLE = 2, /*!< DISABLE : disable output */
IO_BANK0_GPIO8_CTRL_OEOVER_ENABLE = 3, /*!< ENABLE : enable output */
} IO_BANK0_GPIO8_CTRL_OEOVER_Enum;
/* ========================================== IO_BANK0 GPIO8_CTRL OUTOVER [8..9] =========================================== */
typedef enum { /*!< IO_BANK0_GPIO8_CTRL_OUTOVER */
IO_BANK0_GPIO8_CTRL_OUTOVER_NORMAL = 0, /*!< NORMAL : drive output from peripheral signal selected by funcsel */
IO_BANK0_GPIO8_CTRL_OUTOVER_INVERT = 1, /*!< INVERT : drive output from inverse of peripheral signal selected
by funcsel */
IO_BANK0_GPIO8_CTRL_OUTOVER_LOW = 2, /*!< LOW : drive output low */
IO_BANK0_GPIO8_CTRL_OUTOVER_HIGH = 3, /*!< HIGH : drive output high */
} IO_BANK0_GPIO8_CTRL_OUTOVER_Enum;
/* ========================================== IO_BANK0 GPIO8_CTRL FUNCSEL [0..4] =========================================== */
typedef enum { /*!< IO_BANK0_GPIO8_CTRL_FUNCSEL */
IO_BANK0_GPIO8_CTRL_FUNCSEL_spi1_rx = 1, /*!< spi1_rx : spi1_rx */
IO_BANK0_GPIO8_CTRL_FUNCSEL_uart1_tx = 2, /*!< uart1_tx : uart1_tx */
IO_BANK0_GPIO8_CTRL_FUNCSEL_i2c0_sda = 3, /*!< i2c0_sda : i2c0_sda */
IO_BANK0_GPIO8_CTRL_FUNCSEL_pwm_a_4 = 4, /*!< pwm_a_4 : pwm_a_4 */
IO_BANK0_GPIO8_CTRL_FUNCSEL_sio_8 = 5, /*!< sio_8 : sio_8 */
IO_BANK0_GPIO8_CTRL_FUNCSEL_pio0_8 = 6, /*!< pio0_8 : pio0_8 */
IO_BANK0_GPIO8_CTRL_FUNCSEL_pio1_8 = 7, /*!< pio1_8 : pio1_8 */
IO_BANK0_GPIO8_CTRL_FUNCSEL_usb_muxing_extphy_rcv = 8,/*!< usb_muxing_extphy_rcv : usb_muxing_extphy_rcv */
IO_BANK0_GPIO8_CTRL_FUNCSEL_usb_muxing_vbus_en = 9,/*!< usb_muxing_vbus_en : usb_muxing_vbus_en */
IO_BANK0_GPIO8_CTRL_FUNCSEL_null = 31, /*!< null : null */
} IO_BANK0_GPIO8_CTRL_FUNCSEL_Enum;
/* ===================================================== GPIO9_STATUS ====================================================== */
/* ====================================================== GPIO9_CTRL ======================================================= */
/* ========================================= IO_BANK0 GPIO9_CTRL IRQOVER [28..29] ========================================== */
typedef enum { /*!< IO_BANK0_GPIO9_CTRL_IRQOVER */
IO_BANK0_GPIO9_CTRL_IRQOVER_NORMAL = 0, /*!< NORMAL : don't invert the interrupt */
IO_BANK0_GPIO9_CTRL_IRQOVER_INVERT = 1, /*!< INVERT : invert the interrupt */
IO_BANK0_GPIO9_CTRL_IRQOVER_LOW = 2, /*!< LOW : drive interrupt low */
IO_BANK0_GPIO9_CTRL_IRQOVER_HIGH = 3, /*!< HIGH : drive interrupt high */
} IO_BANK0_GPIO9_CTRL_IRQOVER_Enum;
/* ========================================== IO_BANK0 GPIO9_CTRL INOVER [16..17] ========================================== */
typedef enum { /*!< IO_BANK0_GPIO9_CTRL_INOVER */
IO_BANK0_GPIO9_CTRL_INOVER_NORMAL = 0, /*!< NORMAL : don't invert the peri input */
IO_BANK0_GPIO9_CTRL_INOVER_INVERT = 1, /*!< INVERT : invert the peri input */
IO_BANK0_GPIO9_CTRL_INOVER_LOW = 2, /*!< LOW : drive peri input low */
IO_BANK0_GPIO9_CTRL_INOVER_HIGH = 3, /*!< HIGH : drive peri input high */
} IO_BANK0_GPIO9_CTRL_INOVER_Enum;
/* ========================================== IO_BANK0 GPIO9_CTRL OEOVER [12..13] ========================================== */
typedef enum { /*!< IO_BANK0_GPIO9_CTRL_OEOVER */
IO_BANK0_GPIO9_CTRL_OEOVER_NORMAL = 0, /*!< NORMAL : drive output enable from peripheral signal selected
by funcsel */
IO_BANK0_GPIO9_CTRL_OEOVER_INVERT = 1, /*!< INVERT : drive output enable from inverse of peripheral signal
selected by funcsel */
IO_BANK0_GPIO9_CTRL_OEOVER_DISABLE = 2, /*!< DISABLE : disable output */
IO_BANK0_GPIO9_CTRL_OEOVER_ENABLE = 3, /*!< ENABLE : enable output */
} IO_BANK0_GPIO9_CTRL_OEOVER_Enum;
/* ========================================== IO_BANK0 GPIO9_CTRL OUTOVER [8..9] =========================================== */
typedef enum { /*!< IO_BANK0_GPIO9_CTRL_OUTOVER */
IO_BANK0_GPIO9_CTRL_OUTOVER_NORMAL = 0, /*!< NORMAL : drive output from peripheral signal selected by funcsel */
IO_BANK0_GPIO9_CTRL_OUTOVER_INVERT = 1, /*!< INVERT : drive output from inverse of peripheral signal selected
by funcsel */
IO_BANK0_GPIO9_CTRL_OUTOVER_LOW = 2, /*!< LOW : drive output low */
IO_BANK0_GPIO9_CTRL_OUTOVER_HIGH = 3, /*!< HIGH : drive output high */
} IO_BANK0_GPIO9_CTRL_OUTOVER_Enum;
/* ========================================== IO_BANK0 GPIO9_CTRL FUNCSEL [0..4] =========================================== */
typedef enum { /*!< IO_BANK0_GPIO9_CTRL_FUNCSEL */
IO_BANK0_GPIO9_CTRL_FUNCSEL_spi1_ss_n = 1, /*!< spi1_ss_n : spi1_ss_n */
IO_BANK0_GPIO9_CTRL_FUNCSEL_uart1_rx = 2, /*!< uart1_rx : uart1_rx */
IO_BANK0_GPIO9_CTRL_FUNCSEL_i2c0_scl = 3, /*!< i2c0_scl : i2c0_scl */
IO_BANK0_GPIO9_CTRL_FUNCSEL_pwm_b_4 = 4, /*!< pwm_b_4 : pwm_b_4 */
IO_BANK0_GPIO9_CTRL_FUNCSEL_sio_9 = 5, /*!< sio_9 : sio_9 */
IO_BANK0_GPIO9_CTRL_FUNCSEL_pio0_9 = 6, /*!< pio0_9 : pio0_9 */
IO_BANK0_GPIO9_CTRL_FUNCSEL_pio1_9 = 7, /*!< pio1_9 : pio1_9 */
IO_BANK0_GPIO9_CTRL_FUNCSEL_usb_muxing_extphy_vp = 8,/*!< usb_muxing_extphy_vp : usb_muxing_extphy_vp */
IO_BANK0_GPIO9_CTRL_FUNCSEL_usb_muxing_overcurr_detect = 9,/*!< usb_muxing_overcurr_detect : usb_muxing_overcurr_detect */
IO_BANK0_GPIO9_CTRL_FUNCSEL_null = 31, /*!< null : null */
} IO_BANK0_GPIO9_CTRL_FUNCSEL_Enum;
/* ===================================================== GPIO10_STATUS ===================================================== */
/* ====================================================== GPIO10_CTRL ====================================================== */
/* ========================================= IO_BANK0 GPIO10_CTRL IRQOVER [28..29] ========================================= */
typedef enum { /*!< IO_BANK0_GPIO10_CTRL_IRQOVER */
IO_BANK0_GPIO10_CTRL_IRQOVER_NORMAL = 0, /*!< NORMAL : don't invert the interrupt */
IO_BANK0_GPIO10_CTRL_IRQOVER_INVERT = 1, /*!< INVERT : invert the interrupt */
IO_BANK0_GPIO10_CTRL_IRQOVER_LOW = 2, /*!< LOW : drive interrupt low */
IO_BANK0_GPIO10_CTRL_IRQOVER_HIGH = 3, /*!< HIGH : drive interrupt high */
} IO_BANK0_GPIO10_CTRL_IRQOVER_Enum;
/* ========================================= IO_BANK0 GPIO10_CTRL INOVER [16..17] ========================================== */
typedef enum { /*!< IO_BANK0_GPIO10_CTRL_INOVER */
IO_BANK0_GPIO10_CTRL_INOVER_NORMAL = 0, /*!< NORMAL : don't invert the peri input */
IO_BANK0_GPIO10_CTRL_INOVER_INVERT = 1, /*!< INVERT : invert the peri input */
IO_BANK0_GPIO10_CTRL_INOVER_LOW = 2, /*!< LOW : drive peri input low */
IO_BANK0_GPIO10_CTRL_INOVER_HIGH = 3, /*!< HIGH : drive peri input high */
} IO_BANK0_GPIO10_CTRL_INOVER_Enum;
/* ========================================= IO_BANK0 GPIO10_CTRL OEOVER [12..13] ========================================== */
typedef enum { /*!< IO_BANK0_GPIO10_CTRL_OEOVER */
IO_BANK0_GPIO10_CTRL_OEOVER_NORMAL = 0, /*!< NORMAL : drive output enable from peripheral signal selected
by funcsel */
IO_BANK0_GPIO10_CTRL_OEOVER_INVERT = 1, /*!< INVERT : drive output enable from inverse of peripheral signal
selected by funcsel */
IO_BANK0_GPIO10_CTRL_OEOVER_DISABLE = 2, /*!< DISABLE : disable output */
IO_BANK0_GPIO10_CTRL_OEOVER_ENABLE = 3, /*!< ENABLE : enable output */
} IO_BANK0_GPIO10_CTRL_OEOVER_Enum;
/* ========================================== IO_BANK0 GPIO10_CTRL OUTOVER [8..9] ========================================== */
typedef enum { /*!< IO_BANK0_GPIO10_CTRL_OUTOVER */
IO_BANK0_GPIO10_CTRL_OUTOVER_NORMAL = 0, /*!< NORMAL : drive output from peripheral signal selected by funcsel */
IO_BANK0_GPIO10_CTRL_OUTOVER_INVERT = 1, /*!< INVERT : drive output from inverse of peripheral signal selected
by funcsel */
IO_BANK0_GPIO10_CTRL_OUTOVER_LOW = 2, /*!< LOW : drive output low */
IO_BANK0_GPIO10_CTRL_OUTOVER_HIGH = 3, /*!< HIGH : drive output high */
} IO_BANK0_GPIO10_CTRL_OUTOVER_Enum;
/* ========================================== IO_BANK0 GPIO10_CTRL FUNCSEL [0..4] ========================================== */
typedef enum { /*!< IO_BANK0_GPIO10_CTRL_FUNCSEL */
IO_BANK0_GPIO10_CTRL_FUNCSEL_spi1_sclk = 1, /*!< spi1_sclk : spi1_sclk */
IO_BANK0_GPIO10_CTRL_FUNCSEL_uart1_cts = 2, /*!< uart1_cts : uart1_cts */
IO_BANK0_GPIO10_CTRL_FUNCSEL_i2c1_sda = 3, /*!< i2c1_sda : i2c1_sda */
IO_BANK0_GPIO10_CTRL_FUNCSEL_pwm_a_5 = 4, /*!< pwm_a_5 : pwm_a_5 */
IO_BANK0_GPIO10_CTRL_FUNCSEL_sio_10 = 5, /*!< sio_10 : sio_10 */
IO_BANK0_GPIO10_CTRL_FUNCSEL_pio0_10 = 6, /*!< pio0_10 : pio0_10 */
IO_BANK0_GPIO10_CTRL_FUNCSEL_pio1_10 = 7, /*!< pio1_10 : pio1_10 */
IO_BANK0_GPIO10_CTRL_FUNCSEL_usb_muxing_extphy_vm = 8,/*!< usb_muxing_extphy_vm : usb_muxing_extphy_vm */
IO_BANK0_GPIO10_CTRL_FUNCSEL_usb_muxing_vbus_detect = 9,/*!< usb_muxing_vbus_detect : usb_muxing_vbus_detect */
IO_BANK0_GPIO10_CTRL_FUNCSEL_null = 31, /*!< null : null */
} IO_BANK0_GPIO10_CTRL_FUNCSEL_Enum;
/* ===================================================== GPIO11_STATUS ===================================================== */
/* ====================================================== GPIO11_CTRL ====================================================== */
/* ========================================= IO_BANK0 GPIO11_CTRL IRQOVER [28..29] ========================================= */
typedef enum { /*!< IO_BANK0_GPIO11_CTRL_IRQOVER */
IO_BANK0_GPIO11_CTRL_IRQOVER_NORMAL = 0, /*!< NORMAL : don't invert the interrupt */
IO_BANK0_GPIO11_CTRL_IRQOVER_INVERT = 1, /*!< INVERT : invert the interrupt */
IO_BANK0_GPIO11_CTRL_IRQOVER_LOW = 2, /*!< LOW : drive interrupt low */
IO_BANK0_GPIO11_CTRL_IRQOVER_HIGH = 3, /*!< HIGH : drive interrupt high */
} IO_BANK0_GPIO11_CTRL_IRQOVER_Enum;
/* ========================================= IO_BANK0 GPIO11_CTRL INOVER [16..17] ========================================== */
typedef enum { /*!< IO_BANK0_GPIO11_CTRL_INOVER */
IO_BANK0_GPIO11_CTRL_INOVER_NORMAL = 0, /*!< NORMAL : don't invert the peri input */
IO_BANK0_GPIO11_CTRL_INOVER_INVERT = 1, /*!< INVERT : invert the peri input */
IO_BANK0_GPIO11_CTRL_INOVER_LOW = 2, /*!< LOW : drive peri input low */
IO_BANK0_GPIO11_CTRL_INOVER_HIGH = 3, /*!< HIGH : drive peri input high */
} IO_BANK0_GPIO11_CTRL_INOVER_Enum;
/* ========================================= IO_BANK0 GPIO11_CTRL OEOVER [12..13] ========================================== */
typedef enum { /*!< IO_BANK0_GPIO11_CTRL_OEOVER */
IO_BANK0_GPIO11_CTRL_OEOVER_NORMAL = 0, /*!< NORMAL : drive output enable from peripheral signal selected
by funcsel */
IO_BANK0_GPIO11_CTRL_OEOVER_INVERT = 1, /*!< INVERT : drive output enable from inverse of peripheral signal
selected by funcsel */
IO_BANK0_GPIO11_CTRL_OEOVER_DISABLE = 2, /*!< DISABLE : disable output */
IO_BANK0_GPIO11_CTRL_OEOVER_ENABLE = 3, /*!< ENABLE : enable output */
} IO_BANK0_GPIO11_CTRL_OEOVER_Enum;
/* ========================================== IO_BANK0 GPIO11_CTRL OUTOVER [8..9] ========================================== */
typedef enum { /*!< IO_BANK0_GPIO11_CTRL_OUTOVER */
IO_BANK0_GPIO11_CTRL_OUTOVER_NORMAL = 0, /*!< NORMAL : drive output from peripheral signal selected by funcsel */
IO_BANK0_GPIO11_CTRL_OUTOVER_INVERT = 1, /*!< INVERT : drive output from inverse of peripheral signal selected
by funcsel */
IO_BANK0_GPIO11_CTRL_OUTOVER_LOW = 2, /*!< LOW : drive output low */
IO_BANK0_GPIO11_CTRL_OUTOVER_HIGH = 3, /*!< HIGH : drive output high */
} IO_BANK0_GPIO11_CTRL_OUTOVER_Enum;
/* ========================================== IO_BANK0 GPIO11_CTRL FUNCSEL [0..4] ========================================== */
typedef enum { /*!< IO_BANK0_GPIO11_CTRL_FUNCSEL */
IO_BANK0_GPIO11_CTRL_FUNCSEL_spi1_tx = 1, /*!< spi1_tx : spi1_tx */
IO_BANK0_GPIO11_CTRL_FUNCSEL_uart1_rts = 2, /*!< uart1_rts : uart1_rts */
IO_BANK0_GPIO11_CTRL_FUNCSEL_i2c1_scl = 3, /*!< i2c1_scl : i2c1_scl */
IO_BANK0_GPIO11_CTRL_FUNCSEL_pwm_b_5 = 4, /*!< pwm_b_5 : pwm_b_5 */
IO_BANK0_GPIO11_CTRL_FUNCSEL_sio_11 = 5, /*!< sio_11 : sio_11 */
IO_BANK0_GPIO11_CTRL_FUNCSEL_pio0_11 = 6, /*!< pio0_11 : pio0_11 */
IO_BANK0_GPIO11_CTRL_FUNCSEL_pio1_11 = 7, /*!< pio1_11 : pio1_11 */
IO_BANK0_GPIO11_CTRL_FUNCSEL_usb_muxing_extphy_suspnd = 8,/*!< usb_muxing_extphy_suspnd : usb_muxing_extphy_suspnd */
IO_BANK0_GPIO11_CTRL_FUNCSEL_usb_muxing_vbus_en = 9,/*!< usb_muxing_vbus_en : usb_muxing_vbus_en */
IO_BANK0_GPIO11_CTRL_FUNCSEL_null = 31, /*!< null : null */
} IO_BANK0_GPIO11_CTRL_FUNCSEL_Enum;
/* ===================================================== GPIO12_STATUS ===================================================== */
/* ====================================================== GPIO12_CTRL ====================================================== */
/* ========================================= IO_BANK0 GPIO12_CTRL IRQOVER [28..29] ========================================= */
typedef enum { /*!< IO_BANK0_GPIO12_CTRL_IRQOVER */
IO_BANK0_GPIO12_CTRL_IRQOVER_NORMAL = 0, /*!< NORMAL : don't invert the interrupt */
IO_BANK0_GPIO12_CTRL_IRQOVER_INVERT = 1, /*!< INVERT : invert the interrupt */
IO_BANK0_GPIO12_CTRL_IRQOVER_LOW = 2, /*!< LOW : drive interrupt low */
IO_BANK0_GPIO12_CTRL_IRQOVER_HIGH = 3, /*!< HIGH : drive interrupt high */
} IO_BANK0_GPIO12_CTRL_IRQOVER_Enum;
/* ========================================= IO_BANK0 GPIO12_CTRL INOVER [16..17] ========================================== */
typedef enum { /*!< IO_BANK0_GPIO12_CTRL_INOVER */
IO_BANK0_GPIO12_CTRL_INOVER_NORMAL = 0, /*!< NORMAL : don't invert the peri input */
IO_BANK0_GPIO12_CTRL_INOVER_INVERT = 1, /*!< INVERT : invert the peri input */
IO_BANK0_GPIO12_CTRL_INOVER_LOW = 2, /*!< LOW : drive peri input low */
IO_BANK0_GPIO12_CTRL_INOVER_HIGH = 3, /*!< HIGH : drive peri input high */
} IO_BANK0_GPIO12_CTRL_INOVER_Enum;
/* ========================================= IO_BANK0 GPIO12_CTRL OEOVER [12..13] ========================================== */
typedef enum { /*!< IO_BANK0_GPIO12_CTRL_OEOVER */
IO_BANK0_GPIO12_CTRL_OEOVER_NORMAL = 0, /*!< NORMAL : drive output enable from peripheral signal selected
by funcsel */
IO_BANK0_GPIO12_CTRL_OEOVER_INVERT = 1, /*!< INVERT : drive output enable from inverse of peripheral signal
selected by funcsel */
IO_BANK0_GPIO12_CTRL_OEOVER_DISABLE = 2, /*!< DISABLE : disable output */
IO_BANK0_GPIO12_CTRL_OEOVER_ENABLE = 3, /*!< ENABLE : enable output */
} IO_BANK0_GPIO12_CTRL_OEOVER_Enum;
/* ========================================== IO_BANK0 GPIO12_CTRL OUTOVER [8..9] ========================================== */
typedef enum { /*!< IO_BANK0_GPIO12_CTRL_OUTOVER */
IO_BANK0_GPIO12_CTRL_OUTOVER_NORMAL = 0, /*!< NORMAL : drive output from peripheral signal selected by funcsel */
IO_BANK0_GPIO12_CTRL_OUTOVER_INVERT = 1, /*!< INVERT : drive output from inverse of peripheral signal selected
by funcsel */
IO_BANK0_GPIO12_CTRL_OUTOVER_LOW = 2, /*!< LOW : drive output low */
IO_BANK0_GPIO12_CTRL_OUTOVER_HIGH = 3, /*!< HIGH : drive output high */
} IO_BANK0_GPIO12_CTRL_OUTOVER_Enum;
/* ========================================== IO_BANK0 GPIO12_CTRL FUNCSEL [0..4] ========================================== */
typedef enum { /*!< IO_BANK0_GPIO12_CTRL_FUNCSEL */
IO_BANK0_GPIO12_CTRL_FUNCSEL_spi1_rx = 1, /*!< spi1_rx : spi1_rx */
IO_BANK0_GPIO12_CTRL_FUNCSEL_uart0_tx = 2, /*!< uart0_tx : uart0_tx */
IO_BANK0_GPIO12_CTRL_FUNCSEL_i2c0_sda = 3, /*!< i2c0_sda : i2c0_sda */
IO_BANK0_GPIO12_CTRL_FUNCSEL_pwm_a_6 = 4, /*!< pwm_a_6 : pwm_a_6 */
IO_BANK0_GPIO12_CTRL_FUNCSEL_sio_12 = 5, /*!< sio_12 : sio_12 */
IO_BANK0_GPIO12_CTRL_FUNCSEL_pio0_12 = 6, /*!< pio0_12 : pio0_12 */
IO_BANK0_GPIO12_CTRL_FUNCSEL_pio1_12 = 7, /*!< pio1_12 : pio1_12 */
IO_BANK0_GPIO12_CTRL_FUNCSEL_usb_muxing_extphy_speed = 8,/*!< usb_muxing_extphy_speed : usb_muxing_extphy_speed */
IO_BANK0_GPIO12_CTRL_FUNCSEL_usb_muxing_overcurr_detect = 9,/*!< usb_muxing_overcurr_detect : usb_muxing_overcurr_detect */
IO_BANK0_GPIO12_CTRL_FUNCSEL_null = 31, /*!< null : null */
} IO_BANK0_GPIO12_CTRL_FUNCSEL_Enum;
/* ===================================================== GPIO13_STATUS ===================================================== */
/* ====================================================== GPIO13_CTRL ====================================================== */
/* ========================================= IO_BANK0 GPIO13_CTRL IRQOVER [28..29] ========================================= */
typedef enum { /*!< IO_BANK0_GPIO13_CTRL_IRQOVER */
IO_BANK0_GPIO13_CTRL_IRQOVER_NORMAL = 0, /*!< NORMAL : don't invert the interrupt */
IO_BANK0_GPIO13_CTRL_IRQOVER_INVERT = 1, /*!< INVERT : invert the interrupt */
IO_BANK0_GPIO13_CTRL_IRQOVER_LOW = 2, /*!< LOW : drive interrupt low */
IO_BANK0_GPIO13_CTRL_IRQOVER_HIGH = 3, /*!< HIGH : drive interrupt high */
} IO_BANK0_GPIO13_CTRL_IRQOVER_Enum;
/* ========================================= IO_BANK0 GPIO13_CTRL INOVER [16..17] ========================================== */
typedef enum { /*!< IO_BANK0_GPIO13_CTRL_INOVER */
IO_BANK0_GPIO13_CTRL_INOVER_NORMAL = 0, /*!< NORMAL : don't invert the peri input */
IO_BANK0_GPIO13_CTRL_INOVER_INVERT = 1, /*!< INVERT : invert the peri input */
IO_BANK0_GPIO13_CTRL_INOVER_LOW = 2, /*!< LOW : drive peri input low */
IO_BANK0_GPIO13_CTRL_INOVER_HIGH = 3, /*!< HIGH : drive peri input high */
} IO_BANK0_GPIO13_CTRL_INOVER_Enum;
/* ========================================= IO_BANK0 GPIO13_CTRL OEOVER [12..13] ========================================== */
typedef enum { /*!< IO_BANK0_GPIO13_CTRL_OEOVER */
IO_BANK0_GPIO13_CTRL_OEOVER_NORMAL = 0, /*!< NORMAL : drive output enable from peripheral signal selected
by funcsel */
IO_BANK0_GPIO13_CTRL_OEOVER_INVERT = 1, /*!< INVERT : drive output enable from inverse of peripheral signal
selected by funcsel */
IO_BANK0_GPIO13_CTRL_OEOVER_DISABLE = 2, /*!< DISABLE : disable output */
IO_BANK0_GPIO13_CTRL_OEOVER_ENABLE = 3, /*!< ENABLE : enable output */
} IO_BANK0_GPIO13_CTRL_OEOVER_Enum;
/* ========================================== IO_BANK0 GPIO13_CTRL OUTOVER [8..9] ========================================== */
typedef enum { /*!< IO_BANK0_GPIO13_CTRL_OUTOVER */
IO_BANK0_GPIO13_CTRL_OUTOVER_NORMAL = 0, /*!< NORMAL : drive output from peripheral signal selected by funcsel */
IO_BANK0_GPIO13_CTRL_OUTOVER_INVERT = 1, /*!< INVERT : drive output from inverse of peripheral signal selected
by funcsel */
IO_BANK0_GPIO13_CTRL_OUTOVER_LOW = 2, /*!< LOW : drive output low */
IO_BANK0_GPIO13_CTRL_OUTOVER_HIGH = 3, /*!< HIGH : drive output high */
} IO_BANK0_GPIO13_CTRL_OUTOVER_Enum;
/* ========================================== IO_BANK0 GPIO13_CTRL FUNCSEL [0..4] ========================================== */
typedef enum { /*!< IO_BANK0_GPIO13_CTRL_FUNCSEL */
IO_BANK0_GPIO13_CTRL_FUNCSEL_spi1_ss_n = 1, /*!< spi1_ss_n : spi1_ss_n */
IO_BANK0_GPIO13_CTRL_FUNCSEL_uart0_rx = 2, /*!< uart0_rx : uart0_rx */
IO_BANK0_GPIO13_CTRL_FUNCSEL_i2c0_scl = 3, /*!< i2c0_scl : i2c0_scl */
IO_BANK0_GPIO13_CTRL_FUNCSEL_pwm_b_6 = 4, /*!< pwm_b_6 : pwm_b_6 */
IO_BANK0_GPIO13_CTRL_FUNCSEL_sio_13 = 5, /*!< sio_13 : sio_13 */
IO_BANK0_GPIO13_CTRL_FUNCSEL_pio0_13 = 6, /*!< pio0_13 : pio0_13 */
IO_BANK0_GPIO13_CTRL_FUNCSEL_pio1_13 = 7, /*!< pio1_13 : pio1_13 */
IO_BANK0_GPIO13_CTRL_FUNCSEL_usb_muxing_extphy_vpo = 8,/*!< usb_muxing_extphy_vpo : usb_muxing_extphy_vpo */
IO_BANK0_GPIO13_CTRL_FUNCSEL_usb_muxing_vbus_detect = 9,/*!< usb_muxing_vbus_detect : usb_muxing_vbus_detect */
IO_BANK0_GPIO13_CTRL_FUNCSEL_null = 31, /*!< null : null */
} IO_BANK0_GPIO13_CTRL_FUNCSEL_Enum;
/* ===================================================== GPIO14_STATUS ===================================================== */
/* ====================================================== GPIO14_CTRL ====================================================== */
/* ========================================= IO_BANK0 GPIO14_CTRL IRQOVER [28..29] ========================================= */
typedef enum { /*!< IO_BANK0_GPIO14_CTRL_IRQOVER */
IO_BANK0_GPIO14_CTRL_IRQOVER_NORMAL = 0, /*!< NORMAL : don't invert the interrupt */
IO_BANK0_GPIO14_CTRL_IRQOVER_INVERT = 1, /*!< INVERT : invert the interrupt */
IO_BANK0_GPIO14_CTRL_IRQOVER_LOW = 2, /*!< LOW : drive interrupt low */
IO_BANK0_GPIO14_CTRL_IRQOVER_HIGH = 3, /*!< HIGH : drive interrupt high */
} IO_BANK0_GPIO14_CTRL_IRQOVER_Enum;
/* ========================================= IO_BANK0 GPIO14_CTRL INOVER [16..17] ========================================== */
typedef enum { /*!< IO_BANK0_GPIO14_CTRL_INOVER */
IO_BANK0_GPIO14_CTRL_INOVER_NORMAL = 0, /*!< NORMAL : don't invert the peri input */
IO_BANK0_GPIO14_CTRL_INOVER_INVERT = 1, /*!< INVERT : invert the peri input */
IO_BANK0_GPIO14_CTRL_INOVER_LOW = 2, /*!< LOW : drive peri input low */
IO_BANK0_GPIO14_CTRL_INOVER_HIGH = 3, /*!< HIGH : drive peri input high */
} IO_BANK0_GPIO14_CTRL_INOVER_Enum;
/* ========================================= IO_BANK0 GPIO14_CTRL OEOVER [12..13] ========================================== */
typedef enum { /*!< IO_BANK0_GPIO14_CTRL_OEOVER */
IO_BANK0_GPIO14_CTRL_OEOVER_NORMAL = 0, /*!< NORMAL : drive output enable from peripheral signal selected
by funcsel */
IO_BANK0_GPIO14_CTRL_OEOVER_INVERT = 1, /*!< INVERT : drive output enable from inverse of peripheral signal
selected by funcsel */
IO_BANK0_GPIO14_CTRL_OEOVER_DISABLE = 2, /*!< DISABLE : disable output */
IO_BANK0_GPIO14_CTRL_OEOVER_ENABLE = 3, /*!< ENABLE : enable output */
} IO_BANK0_GPIO14_CTRL_OEOVER_Enum;
/* ========================================== IO_BANK0 GPIO14_CTRL OUTOVER [8..9] ========================================== */
typedef enum { /*!< IO_BANK0_GPIO14_CTRL_OUTOVER */
IO_BANK0_GPIO14_CTRL_OUTOVER_NORMAL = 0, /*!< NORMAL : drive output from peripheral signal selected by funcsel */
IO_BANK0_GPIO14_CTRL_OUTOVER_INVERT = 1, /*!< INVERT : drive output from inverse of peripheral signal selected
by funcsel */
IO_BANK0_GPIO14_CTRL_OUTOVER_LOW = 2, /*!< LOW : drive output low */
IO_BANK0_GPIO14_CTRL_OUTOVER_HIGH = 3, /*!< HIGH : drive output high */
} IO_BANK0_GPIO14_CTRL_OUTOVER_Enum;
/* ========================================== IO_BANK0 GPIO14_CTRL FUNCSEL [0..4] ========================================== */
typedef enum { /*!< IO_BANK0_GPIO14_CTRL_FUNCSEL */
IO_BANK0_GPIO14_CTRL_FUNCSEL_spi1_sclk = 1, /*!< spi1_sclk : spi1_sclk */
IO_BANK0_GPIO14_CTRL_FUNCSEL_uart0_cts = 2, /*!< uart0_cts : uart0_cts */
IO_BANK0_GPIO14_CTRL_FUNCSEL_i2c1_sda = 3, /*!< i2c1_sda : i2c1_sda */
IO_BANK0_GPIO14_CTRL_FUNCSEL_pwm_a_7 = 4, /*!< pwm_a_7 : pwm_a_7 */
IO_BANK0_GPIO14_CTRL_FUNCSEL_sio_14 = 5, /*!< sio_14 : sio_14 */
IO_BANK0_GPIO14_CTRL_FUNCSEL_pio0_14 = 6, /*!< pio0_14 : pio0_14 */
IO_BANK0_GPIO14_CTRL_FUNCSEL_pio1_14 = 7, /*!< pio1_14 : pio1_14 */
IO_BANK0_GPIO14_CTRL_FUNCSEL_usb_muxing_extphy_vmo = 8,/*!< usb_muxing_extphy_vmo : usb_muxing_extphy_vmo */
IO_BANK0_GPIO14_CTRL_FUNCSEL_usb_muxing_vbus_en = 9,/*!< usb_muxing_vbus_en : usb_muxing_vbus_en */
IO_BANK0_GPIO14_CTRL_FUNCSEL_null = 31, /*!< null : null */
} IO_BANK0_GPIO14_CTRL_FUNCSEL_Enum;
/* ===================================================== GPIO15_STATUS ===================================================== */
/* ====================================================== GPIO15_CTRL ====================================================== */
/* ========================================= IO_BANK0 GPIO15_CTRL IRQOVER [28..29] ========================================= */
typedef enum { /*!< IO_BANK0_GPIO15_CTRL_IRQOVER */
IO_BANK0_GPIO15_CTRL_IRQOVER_NORMAL = 0, /*!< NORMAL : don't invert the interrupt */
IO_BANK0_GPIO15_CTRL_IRQOVER_INVERT = 1, /*!< INVERT : invert the interrupt */
IO_BANK0_GPIO15_CTRL_IRQOVER_LOW = 2, /*!< LOW : drive interrupt low */
IO_BANK0_GPIO15_CTRL_IRQOVER_HIGH = 3, /*!< HIGH : drive interrupt high */
} IO_BANK0_GPIO15_CTRL_IRQOVER_Enum;
/* ========================================= IO_BANK0 GPIO15_CTRL INOVER [16..17] ========================================== */
typedef enum { /*!< IO_BANK0_GPIO15_CTRL_INOVER */
IO_BANK0_GPIO15_CTRL_INOVER_NORMAL = 0, /*!< NORMAL : don't invert the peri input */
IO_BANK0_GPIO15_CTRL_INOVER_INVERT = 1, /*!< INVERT : invert the peri input */
IO_BANK0_GPIO15_CTRL_INOVER_LOW = 2, /*!< LOW : drive peri input low */
IO_BANK0_GPIO15_CTRL_INOVER_HIGH = 3, /*!< HIGH : drive peri input high */
} IO_BANK0_GPIO15_CTRL_INOVER_Enum;
/* ========================================= IO_BANK0 GPIO15_CTRL OEOVER [12..13] ========================================== */
typedef enum { /*!< IO_BANK0_GPIO15_CTRL_OEOVER */
IO_BANK0_GPIO15_CTRL_OEOVER_NORMAL = 0, /*!< NORMAL : drive output enable from peripheral signal selected
by funcsel */
IO_BANK0_GPIO15_CTRL_OEOVER_INVERT = 1, /*!< INVERT : drive output enable from inverse of peripheral signal
selected by funcsel */
IO_BANK0_GPIO15_CTRL_OEOVER_DISABLE = 2, /*!< DISABLE : disable output */
IO_BANK0_GPIO15_CTRL_OEOVER_ENABLE = 3, /*!< ENABLE : enable output */
} IO_BANK0_GPIO15_CTRL_OEOVER_Enum;
/* ========================================== IO_BANK0 GPIO15_CTRL OUTOVER [8..9] ========================================== */
typedef enum { /*!< IO_BANK0_GPIO15_CTRL_OUTOVER */
IO_BANK0_GPIO15_CTRL_OUTOVER_NORMAL = 0, /*!< NORMAL : drive output from peripheral signal selected by funcsel */
IO_BANK0_GPIO15_CTRL_OUTOVER_INVERT = 1, /*!< INVERT : drive output from inverse of peripheral signal selected
by funcsel */
IO_BANK0_GPIO15_CTRL_OUTOVER_LOW = 2, /*!< LOW : drive output low */
IO_BANK0_GPIO15_CTRL_OUTOVER_HIGH = 3, /*!< HIGH : drive output high */
} IO_BANK0_GPIO15_CTRL_OUTOVER_Enum;
/* ========================================== IO_BANK0 GPIO15_CTRL FUNCSEL [0..4] ========================================== */
typedef enum { /*!< IO_BANK0_GPIO15_CTRL_FUNCSEL */
IO_BANK0_GPIO15_CTRL_FUNCSEL_spi1_tx = 1, /*!< spi1_tx : spi1_tx */
IO_BANK0_GPIO15_CTRL_FUNCSEL_uart0_rts = 2, /*!< uart0_rts : uart0_rts */
IO_BANK0_GPIO15_CTRL_FUNCSEL_i2c1_scl = 3, /*!< i2c1_scl : i2c1_scl */
IO_BANK0_GPIO15_CTRL_FUNCSEL_pwm_b_7 = 4, /*!< pwm_b_7 : pwm_b_7 */
IO_BANK0_GPIO15_CTRL_FUNCSEL_sio_15 = 5, /*!< sio_15 : sio_15 */
IO_BANK0_GPIO15_CTRL_FUNCSEL_pio0_15 = 6, /*!< pio0_15 : pio0_15 */
IO_BANK0_GPIO15_CTRL_FUNCSEL_pio1_15 = 7, /*!< pio1_15 : pio1_15 */
IO_BANK0_GPIO15_CTRL_FUNCSEL_usb_muxing_digital_dp = 8,/*!< usb_muxing_digital_dp : usb_muxing_digital_dp */
IO_BANK0_GPIO15_CTRL_FUNCSEL_usb_muxing_overcurr_detect = 9,/*!< usb_muxing_overcurr_detect : usb_muxing_overcurr_detect */
IO_BANK0_GPIO15_CTRL_FUNCSEL_null = 31, /*!< null : null */
} IO_BANK0_GPIO15_CTRL_FUNCSEL_Enum;
/* ===================================================== GPIO16_STATUS ===================================================== */
/* ====================================================== GPIO16_CTRL ====================================================== */
/* ========================================= IO_BANK0 GPIO16_CTRL IRQOVER [28..29] ========================================= */
typedef enum { /*!< IO_BANK0_GPIO16_CTRL_IRQOVER */
IO_BANK0_GPIO16_CTRL_IRQOVER_NORMAL = 0, /*!< NORMAL : don't invert the interrupt */
IO_BANK0_GPIO16_CTRL_IRQOVER_INVERT = 1, /*!< INVERT : invert the interrupt */
IO_BANK0_GPIO16_CTRL_IRQOVER_LOW = 2, /*!< LOW : drive interrupt low */
IO_BANK0_GPIO16_CTRL_IRQOVER_HIGH = 3, /*!< HIGH : drive interrupt high */
} IO_BANK0_GPIO16_CTRL_IRQOVER_Enum;
/* ========================================= IO_BANK0 GPIO16_CTRL INOVER [16..17] ========================================== */
typedef enum { /*!< IO_BANK0_GPIO16_CTRL_INOVER */
IO_BANK0_GPIO16_CTRL_INOVER_NORMAL = 0, /*!< NORMAL : don't invert the peri input */
IO_BANK0_GPIO16_CTRL_INOVER_INVERT = 1, /*!< INVERT : invert the peri input */
IO_BANK0_GPIO16_CTRL_INOVER_LOW = 2, /*!< LOW : drive peri input low */
IO_BANK0_GPIO16_CTRL_INOVER_HIGH = 3, /*!< HIGH : drive peri input high */
} IO_BANK0_GPIO16_CTRL_INOVER_Enum;
/* ========================================= IO_BANK0 GPIO16_CTRL OEOVER [12..13] ========================================== */
typedef enum { /*!< IO_BANK0_GPIO16_CTRL_OEOVER */
IO_BANK0_GPIO16_CTRL_OEOVER_NORMAL = 0, /*!< NORMAL : drive output enable from peripheral signal selected
by funcsel */
IO_BANK0_GPIO16_CTRL_OEOVER_INVERT = 1, /*!< INVERT : drive output enable from inverse of peripheral signal
selected by funcsel */
IO_BANK0_GPIO16_CTRL_OEOVER_DISABLE = 2, /*!< DISABLE : disable output */
IO_BANK0_GPIO16_CTRL_OEOVER_ENABLE = 3, /*!< ENABLE : enable output */
} IO_BANK0_GPIO16_CTRL_OEOVER_Enum;
/* ========================================== IO_BANK0 GPIO16_CTRL OUTOVER [8..9] ========================================== */
typedef enum { /*!< IO_BANK0_GPIO16_CTRL_OUTOVER */
IO_BANK0_GPIO16_CTRL_OUTOVER_NORMAL = 0, /*!< NORMAL : drive output from peripheral signal selected by funcsel */
IO_BANK0_GPIO16_CTRL_OUTOVER_INVERT = 1, /*!< INVERT : drive output from inverse of peripheral signal selected
by funcsel */
IO_BANK0_GPIO16_CTRL_OUTOVER_LOW = 2, /*!< LOW : drive output low */
IO_BANK0_GPIO16_CTRL_OUTOVER_HIGH = 3, /*!< HIGH : drive output high */
} IO_BANK0_GPIO16_CTRL_OUTOVER_Enum;
/* ========================================== IO_BANK0 GPIO16_CTRL FUNCSEL [0..4] ========================================== */
typedef enum { /*!< IO_BANK0_GPIO16_CTRL_FUNCSEL */
IO_BANK0_GPIO16_CTRL_FUNCSEL_spi0_rx = 1, /*!< spi0_rx : spi0_rx */
IO_BANK0_GPIO16_CTRL_FUNCSEL_uart0_tx = 2, /*!< uart0_tx : uart0_tx */
IO_BANK0_GPIO16_CTRL_FUNCSEL_i2c0_sda = 3, /*!< i2c0_sda : i2c0_sda */
IO_BANK0_GPIO16_CTRL_FUNCSEL_pwm_a_0 = 4, /*!< pwm_a_0 : pwm_a_0 */
IO_BANK0_GPIO16_CTRL_FUNCSEL_sio_16 = 5, /*!< sio_16 : sio_16 */
IO_BANK0_GPIO16_CTRL_FUNCSEL_pio0_16 = 6, /*!< pio0_16 : pio0_16 */
IO_BANK0_GPIO16_CTRL_FUNCSEL_pio1_16 = 7, /*!< pio1_16 : pio1_16 */
IO_BANK0_GPIO16_CTRL_FUNCSEL_usb_muxing_digital_dm = 8,/*!< usb_muxing_digital_dm : usb_muxing_digital_dm */
IO_BANK0_GPIO16_CTRL_FUNCSEL_usb_muxing_vbus_detect = 9,/*!< usb_muxing_vbus_detect : usb_muxing_vbus_detect */
IO_BANK0_GPIO16_CTRL_FUNCSEL_null = 31, /*!< null : null */
} IO_BANK0_GPIO16_CTRL_FUNCSEL_Enum;
/* ===================================================== GPIO17_STATUS ===================================================== */
/* ====================================================== GPIO17_CTRL ====================================================== */
/* ========================================= IO_BANK0 GPIO17_CTRL IRQOVER [28..29] ========================================= */
typedef enum { /*!< IO_BANK0_GPIO17_CTRL_IRQOVER */
IO_BANK0_GPIO17_CTRL_IRQOVER_NORMAL = 0, /*!< NORMAL : don't invert the interrupt */
IO_BANK0_GPIO17_CTRL_IRQOVER_INVERT = 1, /*!< INVERT : invert the interrupt */
IO_BANK0_GPIO17_CTRL_IRQOVER_LOW = 2, /*!< LOW : drive interrupt low */
IO_BANK0_GPIO17_CTRL_IRQOVER_HIGH = 3, /*!< HIGH : drive interrupt high */
} IO_BANK0_GPIO17_CTRL_IRQOVER_Enum;
/* ========================================= IO_BANK0 GPIO17_CTRL INOVER [16..17] ========================================== */
typedef enum { /*!< IO_BANK0_GPIO17_CTRL_INOVER */
IO_BANK0_GPIO17_CTRL_INOVER_NORMAL = 0, /*!< NORMAL : don't invert the peri input */
IO_BANK0_GPIO17_CTRL_INOVER_INVERT = 1, /*!< INVERT : invert the peri input */
IO_BANK0_GPIO17_CTRL_INOVER_LOW = 2, /*!< LOW : drive peri input low */
IO_BANK0_GPIO17_CTRL_INOVER_HIGH = 3, /*!< HIGH : drive peri input high */
} IO_BANK0_GPIO17_CTRL_INOVER_Enum;
/* ========================================= IO_BANK0 GPIO17_CTRL OEOVER [12..13] ========================================== */
typedef enum { /*!< IO_BANK0_GPIO17_CTRL_OEOVER */
IO_BANK0_GPIO17_CTRL_OEOVER_NORMAL = 0, /*!< NORMAL : drive output enable from peripheral signal selected
by funcsel */
IO_BANK0_GPIO17_CTRL_OEOVER_INVERT = 1, /*!< INVERT : drive output enable from inverse of peripheral signal
selected by funcsel */
IO_BANK0_GPIO17_CTRL_OEOVER_DISABLE = 2, /*!< DISABLE : disable output */
IO_BANK0_GPIO17_CTRL_OEOVER_ENABLE = 3, /*!< ENABLE : enable output */
} IO_BANK0_GPIO17_CTRL_OEOVER_Enum;
/* ========================================== IO_BANK0 GPIO17_CTRL OUTOVER [8..9] ========================================== */
typedef enum { /*!< IO_BANK0_GPIO17_CTRL_OUTOVER */
IO_BANK0_GPIO17_CTRL_OUTOVER_NORMAL = 0, /*!< NORMAL : drive output from peripheral signal selected by funcsel */
IO_BANK0_GPIO17_CTRL_OUTOVER_INVERT = 1, /*!< INVERT : drive output from inverse of peripheral signal selected
by funcsel */
IO_BANK0_GPIO17_CTRL_OUTOVER_LOW = 2, /*!< LOW : drive output low */
IO_BANK0_GPIO17_CTRL_OUTOVER_HIGH = 3, /*!< HIGH : drive output high */
} IO_BANK0_GPIO17_CTRL_OUTOVER_Enum;
/* ========================================== IO_BANK0 GPIO17_CTRL FUNCSEL [0..4] ========================================== */
typedef enum { /*!< IO_BANK0_GPIO17_CTRL_FUNCSEL */
IO_BANK0_GPIO17_CTRL_FUNCSEL_spi0_ss_n = 1, /*!< spi0_ss_n : spi0_ss_n */
IO_BANK0_GPIO17_CTRL_FUNCSEL_uart0_rx = 2, /*!< uart0_rx : uart0_rx */
IO_BANK0_GPIO17_CTRL_FUNCSEL_i2c0_scl = 3, /*!< i2c0_scl : i2c0_scl */
IO_BANK0_GPIO17_CTRL_FUNCSEL_pwm_b_0 = 4, /*!< pwm_b_0 : pwm_b_0 */
IO_BANK0_GPIO17_CTRL_FUNCSEL_sio_17 = 5, /*!< sio_17 : sio_17 */
IO_BANK0_GPIO17_CTRL_FUNCSEL_pio0_17 = 6, /*!< pio0_17 : pio0_17 */
IO_BANK0_GPIO17_CTRL_FUNCSEL_pio1_17 = 7, /*!< pio1_17 : pio1_17 */
IO_BANK0_GPIO17_CTRL_FUNCSEL_usb_muxing_vbus_en = 9,/*!< usb_muxing_vbus_en : usb_muxing_vbus_en */
IO_BANK0_GPIO17_CTRL_FUNCSEL_null = 31, /*!< null : null */
} IO_BANK0_GPIO17_CTRL_FUNCSEL_Enum;
/* ===================================================== GPIO18_STATUS ===================================================== */
/* ====================================================== GPIO18_CTRL ====================================================== */
/* ========================================= IO_BANK0 GPIO18_CTRL IRQOVER [28..29] ========================================= */
typedef enum { /*!< IO_BANK0_GPIO18_CTRL_IRQOVER */
IO_BANK0_GPIO18_CTRL_IRQOVER_NORMAL = 0, /*!< NORMAL : don't invert the interrupt */
IO_BANK0_GPIO18_CTRL_IRQOVER_INVERT = 1, /*!< INVERT : invert the interrupt */
IO_BANK0_GPIO18_CTRL_IRQOVER_LOW = 2, /*!< LOW : drive interrupt low */
IO_BANK0_GPIO18_CTRL_IRQOVER_HIGH = 3, /*!< HIGH : drive interrupt high */
} IO_BANK0_GPIO18_CTRL_IRQOVER_Enum;
/* ========================================= IO_BANK0 GPIO18_CTRL INOVER [16..17] ========================================== */
typedef enum { /*!< IO_BANK0_GPIO18_CTRL_INOVER */
IO_BANK0_GPIO18_CTRL_INOVER_NORMAL = 0, /*!< NORMAL : don't invert the peri input */
IO_BANK0_GPIO18_CTRL_INOVER_INVERT = 1, /*!< INVERT : invert the peri input */
IO_BANK0_GPIO18_CTRL_INOVER_LOW = 2, /*!< LOW : drive peri input low */
IO_BANK0_GPIO18_CTRL_INOVER_HIGH = 3, /*!< HIGH : drive peri input high */
} IO_BANK0_GPIO18_CTRL_INOVER_Enum;
/* ========================================= IO_BANK0 GPIO18_CTRL OEOVER [12..13] ========================================== */
typedef enum { /*!< IO_BANK0_GPIO18_CTRL_OEOVER */
IO_BANK0_GPIO18_CTRL_OEOVER_NORMAL = 0, /*!< NORMAL : drive output enable from peripheral signal selected
by funcsel */
IO_BANK0_GPIO18_CTRL_OEOVER_INVERT = 1, /*!< INVERT : drive output enable from inverse of peripheral signal
selected by funcsel */
IO_BANK0_GPIO18_CTRL_OEOVER_DISABLE = 2, /*!< DISABLE : disable output */
IO_BANK0_GPIO18_CTRL_OEOVER_ENABLE = 3, /*!< ENABLE : enable output */
} IO_BANK0_GPIO18_CTRL_OEOVER_Enum;
/* ========================================== IO_BANK0 GPIO18_CTRL OUTOVER [8..9] ========================================== */
typedef enum { /*!< IO_BANK0_GPIO18_CTRL_OUTOVER */
IO_BANK0_GPIO18_CTRL_OUTOVER_NORMAL = 0, /*!< NORMAL : drive output from peripheral signal selected by funcsel */
IO_BANK0_GPIO18_CTRL_OUTOVER_INVERT = 1, /*!< INVERT : drive output from inverse of peripheral signal selected
by funcsel */
IO_BANK0_GPIO18_CTRL_OUTOVER_LOW = 2, /*!< LOW : drive output low */
IO_BANK0_GPIO18_CTRL_OUTOVER_HIGH = 3, /*!< HIGH : drive output high */
} IO_BANK0_GPIO18_CTRL_OUTOVER_Enum;
/* ========================================== IO_BANK0 GPIO18_CTRL FUNCSEL [0..4] ========================================== */
typedef enum { /*!< IO_BANK0_GPIO18_CTRL_FUNCSEL */
IO_BANK0_GPIO18_CTRL_FUNCSEL_spi0_sclk = 1, /*!< spi0_sclk : spi0_sclk */
IO_BANK0_GPIO18_CTRL_FUNCSEL_uart0_cts = 2, /*!< uart0_cts : uart0_cts */
IO_BANK0_GPIO18_CTRL_FUNCSEL_i2c1_sda = 3, /*!< i2c1_sda : i2c1_sda */
IO_BANK0_GPIO18_CTRL_FUNCSEL_pwm_a_1 = 4, /*!< pwm_a_1 : pwm_a_1 */
IO_BANK0_GPIO18_CTRL_FUNCSEL_sio_18 = 5, /*!< sio_18 : sio_18 */
IO_BANK0_GPIO18_CTRL_FUNCSEL_pio0_18 = 6, /*!< pio0_18 : pio0_18 */
IO_BANK0_GPIO18_CTRL_FUNCSEL_pio1_18 = 7, /*!< pio1_18 : pio1_18 */
IO_BANK0_GPIO18_CTRL_FUNCSEL_usb_muxing_overcurr_detect = 9,/*!< usb_muxing_overcurr_detect : usb_muxing_overcurr_detect */
IO_BANK0_GPIO18_CTRL_FUNCSEL_null = 31, /*!< null : null */
} IO_BANK0_GPIO18_CTRL_FUNCSEL_Enum;
/* ===================================================== GPIO19_STATUS ===================================================== */
/* ====================================================== GPIO19_CTRL ====================================================== */
/* ========================================= IO_BANK0 GPIO19_CTRL IRQOVER [28..29] ========================================= */
typedef enum { /*!< IO_BANK0_GPIO19_CTRL_IRQOVER */
IO_BANK0_GPIO19_CTRL_IRQOVER_NORMAL = 0, /*!< NORMAL : don't invert the interrupt */
IO_BANK0_GPIO19_CTRL_IRQOVER_INVERT = 1, /*!< INVERT : invert the interrupt */
IO_BANK0_GPIO19_CTRL_IRQOVER_LOW = 2, /*!< LOW : drive interrupt low */
IO_BANK0_GPIO19_CTRL_IRQOVER_HIGH = 3, /*!< HIGH : drive interrupt high */
} IO_BANK0_GPIO19_CTRL_IRQOVER_Enum;
/* ========================================= IO_BANK0 GPIO19_CTRL INOVER [16..17] ========================================== */
typedef enum { /*!< IO_BANK0_GPIO19_CTRL_INOVER */
IO_BANK0_GPIO19_CTRL_INOVER_NORMAL = 0, /*!< NORMAL : don't invert the peri input */
IO_BANK0_GPIO19_CTRL_INOVER_INVERT = 1, /*!< INVERT : invert the peri input */
IO_BANK0_GPIO19_CTRL_INOVER_LOW = 2, /*!< LOW : drive peri input low */
IO_BANK0_GPIO19_CTRL_INOVER_HIGH = 3, /*!< HIGH : drive peri input high */
} IO_BANK0_GPIO19_CTRL_INOVER_Enum;
/* ========================================= IO_BANK0 GPIO19_CTRL OEOVER [12..13] ========================================== */
typedef enum { /*!< IO_BANK0_GPIO19_CTRL_OEOVER */
IO_BANK0_GPIO19_CTRL_OEOVER_NORMAL = 0, /*!< NORMAL : drive output enable from peripheral signal selected
by funcsel */
IO_BANK0_GPIO19_CTRL_OEOVER_INVERT = 1, /*!< INVERT : drive output enable from inverse of peripheral signal
selected by funcsel */
IO_BANK0_GPIO19_CTRL_OEOVER_DISABLE = 2, /*!< DISABLE : disable output */
IO_BANK0_GPIO19_CTRL_OEOVER_ENABLE = 3, /*!< ENABLE : enable output */
} IO_BANK0_GPIO19_CTRL_OEOVER_Enum;
/* ========================================== IO_BANK0 GPIO19_CTRL OUTOVER [8..9] ========================================== */
typedef enum { /*!< IO_BANK0_GPIO19_CTRL_OUTOVER */
IO_BANK0_GPIO19_CTRL_OUTOVER_NORMAL = 0, /*!< NORMAL : drive output from peripheral signal selected by funcsel */
IO_BANK0_GPIO19_CTRL_OUTOVER_INVERT = 1, /*!< INVERT : drive output from inverse of peripheral signal selected
by funcsel */
IO_BANK0_GPIO19_CTRL_OUTOVER_LOW = 2, /*!< LOW : drive output low */
IO_BANK0_GPIO19_CTRL_OUTOVER_HIGH = 3, /*!< HIGH : drive output high */
} IO_BANK0_GPIO19_CTRL_OUTOVER_Enum;
/* ========================================== IO_BANK0 GPIO19_CTRL FUNCSEL [0..4] ========================================== */
typedef enum { /*!< IO_BANK0_GPIO19_CTRL_FUNCSEL */
IO_BANK0_GPIO19_CTRL_FUNCSEL_spi0_tx = 1, /*!< spi0_tx : spi0_tx */
IO_BANK0_GPIO19_CTRL_FUNCSEL_uart0_rts = 2, /*!< uart0_rts : uart0_rts */
IO_BANK0_GPIO19_CTRL_FUNCSEL_i2c1_scl = 3, /*!< i2c1_scl : i2c1_scl */
IO_BANK0_GPIO19_CTRL_FUNCSEL_pwm_b_1 = 4, /*!< pwm_b_1 : pwm_b_1 */
IO_BANK0_GPIO19_CTRL_FUNCSEL_sio_19 = 5, /*!< sio_19 : sio_19 */
IO_BANK0_GPIO19_CTRL_FUNCSEL_pio0_19 = 6, /*!< pio0_19 : pio0_19 */
IO_BANK0_GPIO19_CTRL_FUNCSEL_pio1_19 = 7, /*!< pio1_19 : pio1_19 */
IO_BANK0_GPIO19_CTRL_FUNCSEL_usb_muxing_vbus_detect = 9,/*!< usb_muxing_vbus_detect : usb_muxing_vbus_detect */
IO_BANK0_GPIO19_CTRL_FUNCSEL_null = 31, /*!< null : null */
} IO_BANK0_GPIO19_CTRL_FUNCSEL_Enum;
/* ===================================================== GPIO20_STATUS ===================================================== */
/* ====================================================== GPIO20_CTRL ====================================================== */
/* ========================================= IO_BANK0 GPIO20_CTRL IRQOVER [28..29] ========================================= */
typedef enum { /*!< IO_BANK0_GPIO20_CTRL_IRQOVER */
IO_BANK0_GPIO20_CTRL_IRQOVER_NORMAL = 0, /*!< NORMAL : don't invert the interrupt */
IO_BANK0_GPIO20_CTRL_IRQOVER_INVERT = 1, /*!< INVERT : invert the interrupt */
IO_BANK0_GPIO20_CTRL_IRQOVER_LOW = 2, /*!< LOW : drive interrupt low */
IO_BANK0_GPIO20_CTRL_IRQOVER_HIGH = 3, /*!< HIGH : drive interrupt high */
} IO_BANK0_GPIO20_CTRL_IRQOVER_Enum;
/* ========================================= IO_BANK0 GPIO20_CTRL INOVER [16..17] ========================================== */
typedef enum { /*!< IO_BANK0_GPIO20_CTRL_INOVER */
IO_BANK0_GPIO20_CTRL_INOVER_NORMAL = 0, /*!< NORMAL : don't invert the peri input */
IO_BANK0_GPIO20_CTRL_INOVER_INVERT = 1, /*!< INVERT : invert the peri input */
IO_BANK0_GPIO20_CTRL_INOVER_LOW = 2, /*!< LOW : drive peri input low */
IO_BANK0_GPIO20_CTRL_INOVER_HIGH = 3, /*!< HIGH : drive peri input high */
} IO_BANK0_GPIO20_CTRL_INOVER_Enum;
/* ========================================= IO_BANK0 GPIO20_CTRL OEOVER [12..13] ========================================== */
typedef enum { /*!< IO_BANK0_GPIO20_CTRL_OEOVER */
IO_BANK0_GPIO20_CTRL_OEOVER_NORMAL = 0, /*!< NORMAL : drive output enable from peripheral signal selected
by funcsel */
IO_BANK0_GPIO20_CTRL_OEOVER_INVERT = 1, /*!< INVERT : drive output enable from inverse of peripheral signal
selected by funcsel */
IO_BANK0_GPIO20_CTRL_OEOVER_DISABLE = 2, /*!< DISABLE : disable output */
IO_BANK0_GPIO20_CTRL_OEOVER_ENABLE = 3, /*!< ENABLE : enable output */
} IO_BANK0_GPIO20_CTRL_OEOVER_Enum;
/* ========================================== IO_BANK0 GPIO20_CTRL OUTOVER [8..9] ========================================== */
typedef enum { /*!< IO_BANK0_GPIO20_CTRL_OUTOVER */
IO_BANK0_GPIO20_CTRL_OUTOVER_NORMAL = 0, /*!< NORMAL : drive output from peripheral signal selected by funcsel */
IO_BANK0_GPIO20_CTRL_OUTOVER_INVERT = 1, /*!< INVERT : drive output from inverse of peripheral signal selected
by funcsel */
IO_BANK0_GPIO20_CTRL_OUTOVER_LOW = 2, /*!< LOW : drive output low */
IO_BANK0_GPIO20_CTRL_OUTOVER_HIGH = 3, /*!< HIGH : drive output high */
} IO_BANK0_GPIO20_CTRL_OUTOVER_Enum;
/* ========================================== IO_BANK0 GPIO20_CTRL FUNCSEL [0..4] ========================================== */
typedef enum { /*!< IO_BANK0_GPIO20_CTRL_FUNCSEL */
IO_BANK0_GPIO20_CTRL_FUNCSEL_spi0_rx = 1, /*!< spi0_rx : spi0_rx */
IO_BANK0_GPIO20_CTRL_FUNCSEL_uart1_tx = 2, /*!< uart1_tx : uart1_tx */
IO_BANK0_GPIO20_CTRL_FUNCSEL_i2c0_sda = 3, /*!< i2c0_sda : i2c0_sda */
IO_BANK0_GPIO20_CTRL_FUNCSEL_pwm_a_2 = 4, /*!< pwm_a_2 : pwm_a_2 */
IO_BANK0_GPIO20_CTRL_FUNCSEL_sio_20 = 5, /*!< sio_20 : sio_20 */
IO_BANK0_GPIO20_CTRL_FUNCSEL_pio0_20 = 6, /*!< pio0_20 : pio0_20 */
IO_BANK0_GPIO20_CTRL_FUNCSEL_pio1_20 = 7, /*!< pio1_20 : pio1_20 */
IO_BANK0_GPIO20_CTRL_FUNCSEL_clocks_gpin_0 = 8,/*!< clocks_gpin_0 : clocks_gpin_0 */
IO_BANK0_GPIO20_CTRL_FUNCSEL_usb_muxing_vbus_en = 9,/*!< usb_muxing_vbus_en : usb_muxing_vbus_en */
IO_BANK0_GPIO20_CTRL_FUNCSEL_null = 31, /*!< null : null */
} IO_BANK0_GPIO20_CTRL_FUNCSEL_Enum;
/* ===================================================== GPIO21_STATUS ===================================================== */
/* ====================================================== GPIO21_CTRL ====================================================== */
/* ========================================= IO_BANK0 GPIO21_CTRL IRQOVER [28..29] ========================================= */
typedef enum { /*!< IO_BANK0_GPIO21_CTRL_IRQOVER */
IO_BANK0_GPIO21_CTRL_IRQOVER_NORMAL = 0, /*!< NORMAL : don't invert the interrupt */
IO_BANK0_GPIO21_CTRL_IRQOVER_INVERT = 1, /*!< INVERT : invert the interrupt */
IO_BANK0_GPIO21_CTRL_IRQOVER_LOW = 2, /*!< LOW : drive interrupt low */
IO_BANK0_GPIO21_CTRL_IRQOVER_HIGH = 3, /*!< HIGH : drive interrupt high */
} IO_BANK0_GPIO21_CTRL_IRQOVER_Enum;
/* ========================================= IO_BANK0 GPIO21_CTRL INOVER [16..17] ========================================== */
typedef enum { /*!< IO_BANK0_GPIO21_CTRL_INOVER */
IO_BANK0_GPIO21_CTRL_INOVER_NORMAL = 0, /*!< NORMAL : don't invert the peri input */
IO_BANK0_GPIO21_CTRL_INOVER_INVERT = 1, /*!< INVERT : invert the peri input */
IO_BANK0_GPIO21_CTRL_INOVER_LOW = 2, /*!< LOW : drive peri input low */
IO_BANK0_GPIO21_CTRL_INOVER_HIGH = 3, /*!< HIGH : drive peri input high */
} IO_BANK0_GPIO21_CTRL_INOVER_Enum;
/* ========================================= IO_BANK0 GPIO21_CTRL OEOVER [12..13] ========================================== */
typedef enum { /*!< IO_BANK0_GPIO21_CTRL_OEOVER */
IO_BANK0_GPIO21_CTRL_OEOVER_NORMAL = 0, /*!< NORMAL : drive output enable from peripheral signal selected
by funcsel */
IO_BANK0_GPIO21_CTRL_OEOVER_INVERT = 1, /*!< INVERT : drive output enable from inverse of peripheral signal
selected by funcsel */
IO_BANK0_GPIO21_CTRL_OEOVER_DISABLE = 2, /*!< DISABLE : disable output */
IO_BANK0_GPIO21_CTRL_OEOVER_ENABLE = 3, /*!< ENABLE : enable output */
} IO_BANK0_GPIO21_CTRL_OEOVER_Enum;
/* ========================================== IO_BANK0 GPIO21_CTRL OUTOVER [8..9] ========================================== */
typedef enum { /*!< IO_BANK0_GPIO21_CTRL_OUTOVER */
IO_BANK0_GPIO21_CTRL_OUTOVER_NORMAL = 0, /*!< NORMAL : drive output from peripheral signal selected by funcsel */
IO_BANK0_GPIO21_CTRL_OUTOVER_INVERT = 1, /*!< INVERT : drive output from inverse of peripheral signal selected
by funcsel */
IO_BANK0_GPIO21_CTRL_OUTOVER_LOW = 2, /*!< LOW : drive output low */
IO_BANK0_GPIO21_CTRL_OUTOVER_HIGH = 3, /*!< HIGH : drive output high */
} IO_BANK0_GPIO21_CTRL_OUTOVER_Enum;
/* ========================================== IO_BANK0 GPIO21_CTRL FUNCSEL [0..4] ========================================== */
typedef enum { /*!< IO_BANK0_GPIO21_CTRL_FUNCSEL */
IO_BANK0_GPIO21_CTRL_FUNCSEL_spi0_ss_n = 1, /*!< spi0_ss_n : spi0_ss_n */
IO_BANK0_GPIO21_CTRL_FUNCSEL_uart1_rx = 2, /*!< uart1_rx : uart1_rx */
IO_BANK0_GPIO21_CTRL_FUNCSEL_i2c0_scl = 3, /*!< i2c0_scl : i2c0_scl */
IO_BANK0_GPIO21_CTRL_FUNCSEL_pwm_b_2 = 4, /*!< pwm_b_2 : pwm_b_2 */
IO_BANK0_GPIO21_CTRL_FUNCSEL_sio_21 = 5, /*!< sio_21 : sio_21 */
IO_BANK0_GPIO21_CTRL_FUNCSEL_pio0_21 = 6, /*!< pio0_21 : pio0_21 */
IO_BANK0_GPIO21_CTRL_FUNCSEL_pio1_21 = 7, /*!< pio1_21 : pio1_21 */
IO_BANK0_GPIO21_CTRL_FUNCSEL_clocks_gpout_0 = 8,/*!< clocks_gpout_0 : clocks_gpout_0 */
IO_BANK0_GPIO21_CTRL_FUNCSEL_usb_muxing_overcurr_detect = 9,/*!< usb_muxing_overcurr_detect : usb_muxing_overcurr_detect */
IO_BANK0_GPIO21_CTRL_FUNCSEL_null = 31, /*!< null : null */
} IO_BANK0_GPIO21_CTRL_FUNCSEL_Enum;
/* ===================================================== GPIO22_STATUS ===================================================== */
/* ====================================================== GPIO22_CTRL ====================================================== */
/* ========================================= IO_BANK0 GPIO22_CTRL IRQOVER [28..29] ========================================= */
typedef enum { /*!< IO_BANK0_GPIO22_CTRL_IRQOVER */
IO_BANK0_GPIO22_CTRL_IRQOVER_NORMAL = 0, /*!< NORMAL : don't invert the interrupt */
IO_BANK0_GPIO22_CTRL_IRQOVER_INVERT = 1, /*!< INVERT : invert the interrupt */
IO_BANK0_GPIO22_CTRL_IRQOVER_LOW = 2, /*!< LOW : drive interrupt low */
IO_BANK0_GPIO22_CTRL_IRQOVER_HIGH = 3, /*!< HIGH : drive interrupt high */
} IO_BANK0_GPIO22_CTRL_IRQOVER_Enum;
/* ========================================= IO_BANK0 GPIO22_CTRL INOVER [16..17] ========================================== */
typedef enum { /*!< IO_BANK0_GPIO22_CTRL_INOVER */
IO_BANK0_GPIO22_CTRL_INOVER_NORMAL = 0, /*!< NORMAL : don't invert the peri input */
IO_BANK0_GPIO22_CTRL_INOVER_INVERT = 1, /*!< INVERT : invert the peri input */
IO_BANK0_GPIO22_CTRL_INOVER_LOW = 2, /*!< LOW : drive peri input low */
IO_BANK0_GPIO22_CTRL_INOVER_HIGH = 3, /*!< HIGH : drive peri input high */
} IO_BANK0_GPIO22_CTRL_INOVER_Enum;
/* ========================================= IO_BANK0 GPIO22_CTRL OEOVER [12..13] ========================================== */
typedef enum { /*!< IO_BANK0_GPIO22_CTRL_OEOVER */
IO_BANK0_GPIO22_CTRL_OEOVER_NORMAL = 0, /*!< NORMAL : drive output enable from peripheral signal selected
by funcsel */
IO_BANK0_GPIO22_CTRL_OEOVER_INVERT = 1, /*!< INVERT : drive output enable from inverse of peripheral signal
selected by funcsel */
IO_BANK0_GPIO22_CTRL_OEOVER_DISABLE = 2, /*!< DISABLE : disable output */
IO_BANK0_GPIO22_CTRL_OEOVER_ENABLE = 3, /*!< ENABLE : enable output */
} IO_BANK0_GPIO22_CTRL_OEOVER_Enum;
/* ========================================== IO_BANK0 GPIO22_CTRL OUTOVER [8..9] ========================================== */
typedef enum { /*!< IO_BANK0_GPIO22_CTRL_OUTOVER */
IO_BANK0_GPIO22_CTRL_OUTOVER_NORMAL = 0, /*!< NORMAL : drive output from peripheral signal selected by funcsel */
IO_BANK0_GPIO22_CTRL_OUTOVER_INVERT = 1, /*!< INVERT : drive output from inverse of peripheral signal selected
by funcsel */
IO_BANK0_GPIO22_CTRL_OUTOVER_LOW = 2, /*!< LOW : drive output low */
IO_BANK0_GPIO22_CTRL_OUTOVER_HIGH = 3, /*!< HIGH : drive output high */
} IO_BANK0_GPIO22_CTRL_OUTOVER_Enum;
/* ========================================== IO_BANK0 GPIO22_CTRL FUNCSEL [0..4] ========================================== */
typedef enum { /*!< IO_BANK0_GPIO22_CTRL_FUNCSEL */
IO_BANK0_GPIO22_CTRL_FUNCSEL_spi0_sclk = 1, /*!< spi0_sclk : spi0_sclk */
IO_BANK0_GPIO22_CTRL_FUNCSEL_uart1_cts = 2, /*!< uart1_cts : uart1_cts */
IO_BANK0_GPIO22_CTRL_FUNCSEL_i2c1_sda = 3, /*!< i2c1_sda : i2c1_sda */
IO_BANK0_GPIO22_CTRL_FUNCSEL_pwm_a_3 = 4, /*!< pwm_a_3 : pwm_a_3 */
IO_BANK0_GPIO22_CTRL_FUNCSEL_sio_22 = 5, /*!< sio_22 : sio_22 */
IO_BANK0_GPIO22_CTRL_FUNCSEL_pio0_22 = 6, /*!< pio0_22 : pio0_22 */
IO_BANK0_GPIO22_CTRL_FUNCSEL_pio1_22 = 7, /*!< pio1_22 : pio1_22 */
IO_BANK0_GPIO22_CTRL_FUNCSEL_clocks_gpin_1 = 8,/*!< clocks_gpin_1 : clocks_gpin_1 */
IO_BANK0_GPIO22_CTRL_FUNCSEL_usb_muxing_vbus_detect = 9,/*!< usb_muxing_vbus_detect : usb_muxing_vbus_detect */
IO_BANK0_GPIO22_CTRL_FUNCSEL_null = 31, /*!< null : null */
} IO_BANK0_GPIO22_CTRL_FUNCSEL_Enum;
/* ===================================================== GPIO23_STATUS ===================================================== */
/* ====================================================== GPIO23_CTRL ====================================================== */
/* ========================================= IO_BANK0 GPIO23_CTRL IRQOVER [28..29] ========================================= */
typedef enum { /*!< IO_BANK0_GPIO23_CTRL_IRQOVER */
IO_BANK0_GPIO23_CTRL_IRQOVER_NORMAL = 0, /*!< NORMAL : don't invert the interrupt */
IO_BANK0_GPIO23_CTRL_IRQOVER_INVERT = 1, /*!< INVERT : invert the interrupt */
IO_BANK0_GPIO23_CTRL_IRQOVER_LOW = 2, /*!< LOW : drive interrupt low */
IO_BANK0_GPIO23_CTRL_IRQOVER_HIGH = 3, /*!< HIGH : drive interrupt high */
} IO_BANK0_GPIO23_CTRL_IRQOVER_Enum;
/* ========================================= IO_BANK0 GPIO23_CTRL INOVER [16..17] ========================================== */
typedef enum { /*!< IO_BANK0_GPIO23_CTRL_INOVER */
IO_BANK0_GPIO23_CTRL_INOVER_NORMAL = 0, /*!< NORMAL : don't invert the peri input */
IO_BANK0_GPIO23_CTRL_INOVER_INVERT = 1, /*!< INVERT : invert the peri input */
IO_BANK0_GPIO23_CTRL_INOVER_LOW = 2, /*!< LOW : drive peri input low */
IO_BANK0_GPIO23_CTRL_INOVER_HIGH = 3, /*!< HIGH : drive peri input high */
} IO_BANK0_GPIO23_CTRL_INOVER_Enum;
/* ========================================= IO_BANK0 GPIO23_CTRL OEOVER [12..13] ========================================== */
typedef enum { /*!< IO_BANK0_GPIO23_CTRL_OEOVER */
IO_BANK0_GPIO23_CTRL_OEOVER_NORMAL = 0, /*!< NORMAL : drive output enable from peripheral signal selected
by funcsel */
IO_BANK0_GPIO23_CTRL_OEOVER_INVERT = 1, /*!< INVERT : drive output enable from inverse of peripheral signal
selected by funcsel */
IO_BANK0_GPIO23_CTRL_OEOVER_DISABLE = 2, /*!< DISABLE : disable output */
IO_BANK0_GPIO23_CTRL_OEOVER_ENABLE = 3, /*!< ENABLE : enable output */
} IO_BANK0_GPIO23_CTRL_OEOVER_Enum;
/* ========================================== IO_BANK0 GPIO23_CTRL OUTOVER [8..9] ========================================== */
typedef enum { /*!< IO_BANK0_GPIO23_CTRL_OUTOVER */
IO_BANK0_GPIO23_CTRL_OUTOVER_NORMAL = 0, /*!< NORMAL : drive output from peripheral signal selected by funcsel */
IO_BANK0_GPIO23_CTRL_OUTOVER_INVERT = 1, /*!< INVERT : drive output from inverse of peripheral signal selected
by funcsel */
IO_BANK0_GPIO23_CTRL_OUTOVER_LOW = 2, /*!< LOW : drive output low */
IO_BANK0_GPIO23_CTRL_OUTOVER_HIGH = 3, /*!< HIGH : drive output high */
} IO_BANK0_GPIO23_CTRL_OUTOVER_Enum;
/* ========================================== IO_BANK0 GPIO23_CTRL FUNCSEL [0..4] ========================================== */
typedef enum { /*!< IO_BANK0_GPIO23_CTRL_FUNCSEL */
IO_BANK0_GPIO23_CTRL_FUNCSEL_spi0_tx = 1, /*!< spi0_tx : spi0_tx */
IO_BANK0_GPIO23_CTRL_FUNCSEL_uart1_rts = 2, /*!< uart1_rts : uart1_rts */
IO_BANK0_GPIO23_CTRL_FUNCSEL_i2c1_scl = 3, /*!< i2c1_scl : i2c1_scl */
IO_BANK0_GPIO23_CTRL_FUNCSEL_pwm_b_3 = 4, /*!< pwm_b_3 : pwm_b_3 */
IO_BANK0_GPIO23_CTRL_FUNCSEL_sio_23 = 5, /*!< sio_23 : sio_23 */
IO_BANK0_GPIO23_CTRL_FUNCSEL_pio0_23 = 6, /*!< pio0_23 : pio0_23 */
IO_BANK0_GPIO23_CTRL_FUNCSEL_pio1_23 = 7, /*!< pio1_23 : pio1_23 */
IO_BANK0_GPIO23_CTRL_FUNCSEL_clocks_gpout_1 = 8,/*!< clocks_gpout_1 : clocks_gpout_1 */
IO_BANK0_GPIO23_CTRL_FUNCSEL_usb_muxing_vbus_en = 9,/*!< usb_muxing_vbus_en : usb_muxing_vbus_en */
IO_BANK0_GPIO23_CTRL_FUNCSEL_null = 31, /*!< null : null */
} IO_BANK0_GPIO23_CTRL_FUNCSEL_Enum;
/* ===================================================== GPIO24_STATUS ===================================================== */
/* ====================================================== GPIO24_CTRL ====================================================== */
/* ========================================= IO_BANK0 GPIO24_CTRL IRQOVER [28..29] ========================================= */
typedef enum { /*!< IO_BANK0_GPIO24_CTRL_IRQOVER */
IO_BANK0_GPIO24_CTRL_IRQOVER_NORMAL = 0, /*!< NORMAL : don't invert the interrupt */
IO_BANK0_GPIO24_CTRL_IRQOVER_INVERT = 1, /*!< INVERT : invert the interrupt */
IO_BANK0_GPIO24_CTRL_IRQOVER_LOW = 2, /*!< LOW : drive interrupt low */
IO_BANK0_GPIO24_CTRL_IRQOVER_HIGH = 3, /*!< HIGH : drive interrupt high */
} IO_BANK0_GPIO24_CTRL_IRQOVER_Enum;
/* ========================================= IO_BANK0 GPIO24_CTRL INOVER [16..17] ========================================== */
typedef enum { /*!< IO_BANK0_GPIO24_CTRL_INOVER */
IO_BANK0_GPIO24_CTRL_INOVER_NORMAL = 0, /*!< NORMAL : don't invert the peri input */
IO_BANK0_GPIO24_CTRL_INOVER_INVERT = 1, /*!< INVERT : invert the peri input */
IO_BANK0_GPIO24_CTRL_INOVER_LOW = 2, /*!< LOW : drive peri input low */
IO_BANK0_GPIO24_CTRL_INOVER_HIGH = 3, /*!< HIGH : drive peri input high */
} IO_BANK0_GPIO24_CTRL_INOVER_Enum;
/* ========================================= IO_BANK0 GPIO24_CTRL OEOVER [12..13] ========================================== */
typedef enum { /*!< IO_BANK0_GPIO24_CTRL_OEOVER */
IO_BANK0_GPIO24_CTRL_OEOVER_NORMAL = 0, /*!< NORMAL : drive output enable from peripheral signal selected
by funcsel */
IO_BANK0_GPIO24_CTRL_OEOVER_INVERT = 1, /*!< INVERT : drive output enable from inverse of peripheral signal
selected by funcsel */
IO_BANK0_GPIO24_CTRL_OEOVER_DISABLE = 2, /*!< DISABLE : disable output */
IO_BANK0_GPIO24_CTRL_OEOVER_ENABLE = 3, /*!< ENABLE : enable output */
} IO_BANK0_GPIO24_CTRL_OEOVER_Enum;
/* ========================================== IO_BANK0 GPIO24_CTRL OUTOVER [8..9] ========================================== */
typedef enum { /*!< IO_BANK0_GPIO24_CTRL_OUTOVER */
IO_BANK0_GPIO24_CTRL_OUTOVER_NORMAL = 0, /*!< NORMAL : drive output from peripheral signal selected by funcsel */
IO_BANK0_GPIO24_CTRL_OUTOVER_INVERT = 1, /*!< INVERT : drive output from inverse of peripheral signal selected
by funcsel */
IO_BANK0_GPIO24_CTRL_OUTOVER_LOW = 2, /*!< LOW : drive output low */
IO_BANK0_GPIO24_CTRL_OUTOVER_HIGH = 3, /*!< HIGH : drive output high */
} IO_BANK0_GPIO24_CTRL_OUTOVER_Enum;
/* ========================================== IO_BANK0 GPIO24_CTRL FUNCSEL [0..4] ========================================== */
typedef enum { /*!< IO_BANK0_GPIO24_CTRL_FUNCSEL */
IO_BANK0_GPIO24_CTRL_FUNCSEL_spi1_rx = 1, /*!< spi1_rx : spi1_rx */
IO_BANK0_GPIO24_CTRL_FUNCSEL_uart1_tx = 2, /*!< uart1_tx : uart1_tx */
IO_BANK0_GPIO24_CTRL_FUNCSEL_i2c0_sda = 3, /*!< i2c0_sda : i2c0_sda */
IO_BANK0_GPIO24_CTRL_FUNCSEL_pwm_a_4 = 4, /*!< pwm_a_4 : pwm_a_4 */
IO_BANK0_GPIO24_CTRL_FUNCSEL_sio_24 = 5, /*!< sio_24 : sio_24 */
IO_BANK0_GPIO24_CTRL_FUNCSEL_pio0_24 = 6, /*!< pio0_24 : pio0_24 */
IO_BANK0_GPIO24_CTRL_FUNCSEL_pio1_24 = 7, /*!< pio1_24 : pio1_24 */
IO_BANK0_GPIO24_CTRL_FUNCSEL_clocks_gpout_2 = 8,/*!< clocks_gpout_2 : clocks_gpout_2 */
IO_BANK0_GPIO24_CTRL_FUNCSEL_usb_muxing_overcurr_detect = 9,/*!< usb_muxing_overcurr_detect : usb_muxing_overcurr_detect */
IO_BANK0_GPIO24_CTRL_FUNCSEL_null = 31, /*!< null : null */
} IO_BANK0_GPIO24_CTRL_FUNCSEL_Enum;
/* ===================================================== GPIO25_STATUS ===================================================== */
/* ====================================================== GPIO25_CTRL ====================================================== */
/* ========================================= IO_BANK0 GPIO25_CTRL IRQOVER [28..29] ========================================= */
typedef enum { /*!< IO_BANK0_GPIO25_CTRL_IRQOVER */
IO_BANK0_GPIO25_CTRL_IRQOVER_NORMAL = 0, /*!< NORMAL : don't invert the interrupt */
IO_BANK0_GPIO25_CTRL_IRQOVER_INVERT = 1, /*!< INVERT : invert the interrupt */
IO_BANK0_GPIO25_CTRL_IRQOVER_LOW = 2, /*!< LOW : drive interrupt low */
IO_BANK0_GPIO25_CTRL_IRQOVER_HIGH = 3, /*!< HIGH : drive interrupt high */
} IO_BANK0_GPIO25_CTRL_IRQOVER_Enum;
/* ========================================= IO_BANK0 GPIO25_CTRL INOVER [16..17] ========================================== */
typedef enum { /*!< IO_BANK0_GPIO25_CTRL_INOVER */
IO_BANK0_GPIO25_CTRL_INOVER_NORMAL = 0, /*!< NORMAL : don't invert the peri input */
IO_BANK0_GPIO25_CTRL_INOVER_INVERT = 1, /*!< INVERT : invert the peri input */
IO_BANK0_GPIO25_CTRL_INOVER_LOW = 2, /*!< LOW : drive peri input low */
IO_BANK0_GPIO25_CTRL_INOVER_HIGH = 3, /*!< HIGH : drive peri input high */
} IO_BANK0_GPIO25_CTRL_INOVER_Enum;
/* ========================================= IO_BANK0 GPIO25_CTRL OEOVER [12..13] ========================================== */
typedef enum { /*!< IO_BANK0_GPIO25_CTRL_OEOVER */
IO_BANK0_GPIO25_CTRL_OEOVER_NORMAL = 0, /*!< NORMAL : drive output enable from peripheral signal selected
by funcsel */
IO_BANK0_GPIO25_CTRL_OEOVER_INVERT = 1, /*!< INVERT : drive output enable from inverse of peripheral signal
selected by funcsel */
IO_BANK0_GPIO25_CTRL_OEOVER_DISABLE = 2, /*!< DISABLE : disable output */
IO_BANK0_GPIO25_CTRL_OEOVER_ENABLE = 3, /*!< ENABLE : enable output */
} IO_BANK0_GPIO25_CTRL_OEOVER_Enum;
/* ========================================== IO_BANK0 GPIO25_CTRL OUTOVER [8..9] ========================================== */
typedef enum { /*!< IO_BANK0_GPIO25_CTRL_OUTOVER */
IO_BANK0_GPIO25_CTRL_OUTOVER_NORMAL = 0, /*!< NORMAL : drive output from peripheral signal selected by funcsel */
IO_BANK0_GPIO25_CTRL_OUTOVER_INVERT = 1, /*!< INVERT : drive output from inverse of peripheral signal selected
by funcsel */
IO_BANK0_GPIO25_CTRL_OUTOVER_LOW = 2, /*!< LOW : drive output low */
IO_BANK0_GPIO25_CTRL_OUTOVER_HIGH = 3, /*!< HIGH : drive output high */
} IO_BANK0_GPIO25_CTRL_OUTOVER_Enum;
/* ========================================== IO_BANK0 GPIO25_CTRL FUNCSEL [0..4] ========================================== */
typedef enum { /*!< IO_BANK0_GPIO25_CTRL_FUNCSEL */
IO_BANK0_GPIO25_CTRL_FUNCSEL_spi1_ss_n = 1, /*!< spi1_ss_n : spi1_ss_n */
IO_BANK0_GPIO25_CTRL_FUNCSEL_uart1_rx = 2, /*!< uart1_rx : uart1_rx */
IO_BANK0_GPIO25_CTRL_FUNCSEL_i2c0_scl = 3, /*!< i2c0_scl : i2c0_scl */
IO_BANK0_GPIO25_CTRL_FUNCSEL_pwm_b_4 = 4, /*!< pwm_b_4 : pwm_b_4 */
IO_BANK0_GPIO25_CTRL_FUNCSEL_sio_25 = 5, /*!< sio_25 : sio_25 */
IO_BANK0_GPIO25_CTRL_FUNCSEL_pio0_25 = 6, /*!< pio0_25 : pio0_25 */
IO_BANK0_GPIO25_CTRL_FUNCSEL_pio1_25 = 7, /*!< pio1_25 : pio1_25 */
IO_BANK0_GPIO25_CTRL_FUNCSEL_clocks_gpout_3 = 8,/*!< clocks_gpout_3 : clocks_gpout_3 */
IO_BANK0_GPIO25_CTRL_FUNCSEL_usb_muxing_vbus_detect = 9,/*!< usb_muxing_vbus_detect : usb_muxing_vbus_detect */
IO_BANK0_GPIO25_CTRL_FUNCSEL_null = 31, /*!< null : null */
} IO_BANK0_GPIO25_CTRL_FUNCSEL_Enum;
/* ===================================================== GPIO26_STATUS ===================================================== */
/* ====================================================== GPIO26_CTRL ====================================================== */
/* ========================================= IO_BANK0 GPIO26_CTRL IRQOVER [28..29] ========================================= */
typedef enum { /*!< IO_BANK0_GPIO26_CTRL_IRQOVER */
IO_BANK0_GPIO26_CTRL_IRQOVER_NORMAL = 0, /*!< NORMAL : don't invert the interrupt */
IO_BANK0_GPIO26_CTRL_IRQOVER_INVERT = 1, /*!< INVERT : invert the interrupt */
IO_BANK0_GPIO26_CTRL_IRQOVER_LOW = 2, /*!< LOW : drive interrupt low */
IO_BANK0_GPIO26_CTRL_IRQOVER_HIGH = 3, /*!< HIGH : drive interrupt high */
} IO_BANK0_GPIO26_CTRL_IRQOVER_Enum;
/* ========================================= IO_BANK0 GPIO26_CTRL INOVER [16..17] ========================================== */
typedef enum { /*!< IO_BANK0_GPIO26_CTRL_INOVER */
IO_BANK0_GPIO26_CTRL_INOVER_NORMAL = 0, /*!< NORMAL : don't invert the peri input */
IO_BANK0_GPIO26_CTRL_INOVER_INVERT = 1, /*!< INVERT : invert the peri input */
IO_BANK0_GPIO26_CTRL_INOVER_LOW = 2, /*!< LOW : drive peri input low */
IO_BANK0_GPIO26_CTRL_INOVER_HIGH = 3, /*!< HIGH : drive peri input high */
} IO_BANK0_GPIO26_CTRL_INOVER_Enum;
/* ========================================= IO_BANK0 GPIO26_CTRL OEOVER [12..13] ========================================== */
typedef enum { /*!< IO_BANK0_GPIO26_CTRL_OEOVER */
IO_BANK0_GPIO26_CTRL_OEOVER_NORMAL = 0, /*!< NORMAL : drive output enable from peripheral signal selected
by funcsel */
IO_BANK0_GPIO26_CTRL_OEOVER_INVERT = 1, /*!< INVERT : drive output enable from inverse of peripheral signal
selected by funcsel */
IO_BANK0_GPIO26_CTRL_OEOVER_DISABLE = 2, /*!< DISABLE : disable output */
IO_BANK0_GPIO26_CTRL_OEOVER_ENABLE = 3, /*!< ENABLE : enable output */
} IO_BANK0_GPIO26_CTRL_OEOVER_Enum;
/* ========================================== IO_BANK0 GPIO26_CTRL OUTOVER [8..9] ========================================== */
typedef enum { /*!< IO_BANK0_GPIO26_CTRL_OUTOVER */
IO_BANK0_GPIO26_CTRL_OUTOVER_NORMAL = 0, /*!< NORMAL : drive output from peripheral signal selected by funcsel */
IO_BANK0_GPIO26_CTRL_OUTOVER_INVERT = 1, /*!< INVERT : drive output from inverse of peripheral signal selected
by funcsel */
IO_BANK0_GPIO26_CTRL_OUTOVER_LOW = 2, /*!< LOW : drive output low */
IO_BANK0_GPIO26_CTRL_OUTOVER_HIGH = 3, /*!< HIGH : drive output high */
} IO_BANK0_GPIO26_CTRL_OUTOVER_Enum;
/* ========================================== IO_BANK0 GPIO26_CTRL FUNCSEL [0..4] ========================================== */
typedef enum { /*!< IO_BANK0_GPIO26_CTRL_FUNCSEL */
IO_BANK0_GPIO26_CTRL_FUNCSEL_spi1_sclk = 1, /*!< spi1_sclk : spi1_sclk */
IO_BANK0_GPIO26_CTRL_FUNCSEL_uart1_cts = 2, /*!< uart1_cts : uart1_cts */
IO_BANK0_GPIO26_CTRL_FUNCSEL_i2c1_sda = 3, /*!< i2c1_sda : i2c1_sda */
IO_BANK0_GPIO26_CTRL_FUNCSEL_pwm_a_5 = 4, /*!< pwm_a_5 : pwm_a_5 */
IO_BANK0_GPIO26_CTRL_FUNCSEL_sio_26 = 5, /*!< sio_26 : sio_26 */
IO_BANK0_GPIO26_CTRL_FUNCSEL_pio0_26 = 6, /*!< pio0_26 : pio0_26 */
IO_BANK0_GPIO26_CTRL_FUNCSEL_pio1_26 = 7, /*!< pio1_26 : pio1_26 */
IO_BANK0_GPIO26_CTRL_FUNCSEL_usb_muxing_vbus_en = 9,/*!< usb_muxing_vbus_en : usb_muxing_vbus_en */
IO_BANK0_GPIO26_CTRL_FUNCSEL_null = 31, /*!< null : null */
} IO_BANK0_GPIO26_CTRL_FUNCSEL_Enum;
/* ===================================================== GPIO27_STATUS ===================================================== */
/* ====================================================== GPIO27_CTRL ====================================================== */
/* ========================================= IO_BANK0 GPIO27_CTRL IRQOVER [28..29] ========================================= */
typedef enum { /*!< IO_BANK0_GPIO27_CTRL_IRQOVER */
IO_BANK0_GPIO27_CTRL_IRQOVER_NORMAL = 0, /*!< NORMAL : don't invert the interrupt */
IO_BANK0_GPIO27_CTRL_IRQOVER_INVERT = 1, /*!< INVERT : invert the interrupt */
IO_BANK0_GPIO27_CTRL_IRQOVER_LOW = 2, /*!< LOW : drive interrupt low */
IO_BANK0_GPIO27_CTRL_IRQOVER_HIGH = 3, /*!< HIGH : drive interrupt high */
} IO_BANK0_GPIO27_CTRL_IRQOVER_Enum;
/* ========================================= IO_BANK0 GPIO27_CTRL INOVER [16..17] ========================================== */
typedef enum { /*!< IO_BANK0_GPIO27_CTRL_INOVER */
IO_BANK0_GPIO27_CTRL_INOVER_NORMAL = 0, /*!< NORMAL : don't invert the peri input */
IO_BANK0_GPIO27_CTRL_INOVER_INVERT = 1, /*!< INVERT : invert the peri input */
IO_BANK0_GPIO27_CTRL_INOVER_LOW = 2, /*!< LOW : drive peri input low */
IO_BANK0_GPIO27_CTRL_INOVER_HIGH = 3, /*!< HIGH : drive peri input high */
} IO_BANK0_GPIO27_CTRL_INOVER_Enum;
/* ========================================= IO_BANK0 GPIO27_CTRL OEOVER [12..13] ========================================== */
typedef enum { /*!< IO_BANK0_GPIO27_CTRL_OEOVER */
IO_BANK0_GPIO27_CTRL_OEOVER_NORMAL = 0, /*!< NORMAL : drive output enable from peripheral signal selected
by funcsel */
IO_BANK0_GPIO27_CTRL_OEOVER_INVERT = 1, /*!< INVERT : drive output enable from inverse of peripheral signal
selected by funcsel */
IO_BANK0_GPIO27_CTRL_OEOVER_DISABLE = 2, /*!< DISABLE : disable output */
IO_BANK0_GPIO27_CTRL_OEOVER_ENABLE = 3, /*!< ENABLE : enable output */
} IO_BANK0_GPIO27_CTRL_OEOVER_Enum;
/* ========================================== IO_BANK0 GPIO27_CTRL OUTOVER [8..9] ========================================== */
typedef enum { /*!< IO_BANK0_GPIO27_CTRL_OUTOVER */
IO_BANK0_GPIO27_CTRL_OUTOVER_NORMAL = 0, /*!< NORMAL : drive output from peripheral signal selected by funcsel */
IO_BANK0_GPIO27_CTRL_OUTOVER_INVERT = 1, /*!< INVERT : drive output from inverse of peripheral signal selected
by funcsel */
IO_BANK0_GPIO27_CTRL_OUTOVER_LOW = 2, /*!< LOW : drive output low */
IO_BANK0_GPIO27_CTRL_OUTOVER_HIGH = 3, /*!< HIGH : drive output high */
} IO_BANK0_GPIO27_CTRL_OUTOVER_Enum;
/* ========================================== IO_BANK0 GPIO27_CTRL FUNCSEL [0..4] ========================================== */
typedef enum { /*!< IO_BANK0_GPIO27_CTRL_FUNCSEL */
IO_BANK0_GPIO27_CTRL_FUNCSEL_spi1_tx = 1, /*!< spi1_tx : spi1_tx */
IO_BANK0_GPIO27_CTRL_FUNCSEL_uart1_rts = 2, /*!< uart1_rts : uart1_rts */
IO_BANK0_GPIO27_CTRL_FUNCSEL_i2c1_scl = 3, /*!< i2c1_scl : i2c1_scl */
IO_BANK0_GPIO27_CTRL_FUNCSEL_pwm_b_5 = 4, /*!< pwm_b_5 : pwm_b_5 */
IO_BANK0_GPIO27_CTRL_FUNCSEL_sio_27 = 5, /*!< sio_27 : sio_27 */
IO_BANK0_GPIO27_CTRL_FUNCSEL_pio0_27 = 6, /*!< pio0_27 : pio0_27 */
IO_BANK0_GPIO27_CTRL_FUNCSEL_pio1_27 = 7, /*!< pio1_27 : pio1_27 */
IO_BANK0_GPIO27_CTRL_FUNCSEL_usb_muxing_overcurr_detect = 9,/*!< usb_muxing_overcurr_detect : usb_muxing_overcurr_detect */
IO_BANK0_GPIO27_CTRL_FUNCSEL_null = 31, /*!< null : null */
} IO_BANK0_GPIO27_CTRL_FUNCSEL_Enum;
/* ===================================================== GPIO28_STATUS ===================================================== */
/* ====================================================== GPIO28_CTRL ====================================================== */
/* ========================================= IO_BANK0 GPIO28_CTRL IRQOVER [28..29] ========================================= */
typedef enum { /*!< IO_BANK0_GPIO28_CTRL_IRQOVER */
IO_BANK0_GPIO28_CTRL_IRQOVER_NORMAL = 0, /*!< NORMAL : don't invert the interrupt */
IO_BANK0_GPIO28_CTRL_IRQOVER_INVERT = 1, /*!< INVERT : invert the interrupt */
IO_BANK0_GPIO28_CTRL_IRQOVER_LOW = 2, /*!< LOW : drive interrupt low */
IO_BANK0_GPIO28_CTRL_IRQOVER_HIGH = 3, /*!< HIGH : drive interrupt high */
} IO_BANK0_GPIO28_CTRL_IRQOVER_Enum;
/* ========================================= IO_BANK0 GPIO28_CTRL INOVER [16..17] ========================================== */
typedef enum { /*!< IO_BANK0_GPIO28_CTRL_INOVER */
IO_BANK0_GPIO28_CTRL_INOVER_NORMAL = 0, /*!< NORMAL : don't invert the peri input */
IO_BANK0_GPIO28_CTRL_INOVER_INVERT = 1, /*!< INVERT : invert the peri input */
IO_BANK0_GPIO28_CTRL_INOVER_LOW = 2, /*!< LOW : drive peri input low */
IO_BANK0_GPIO28_CTRL_INOVER_HIGH = 3, /*!< HIGH : drive peri input high */
} IO_BANK0_GPIO28_CTRL_INOVER_Enum;
/* ========================================= IO_BANK0 GPIO28_CTRL OEOVER [12..13] ========================================== */
typedef enum { /*!< IO_BANK0_GPIO28_CTRL_OEOVER */
IO_BANK0_GPIO28_CTRL_OEOVER_NORMAL = 0, /*!< NORMAL : drive output enable from peripheral signal selected
by funcsel */
IO_BANK0_GPIO28_CTRL_OEOVER_INVERT = 1, /*!< INVERT : drive output enable from inverse of peripheral signal
selected by funcsel */
IO_BANK0_GPIO28_CTRL_OEOVER_DISABLE = 2, /*!< DISABLE : disable output */
IO_BANK0_GPIO28_CTRL_OEOVER_ENABLE = 3, /*!< ENABLE : enable output */
} IO_BANK0_GPIO28_CTRL_OEOVER_Enum;
/* ========================================== IO_BANK0 GPIO28_CTRL OUTOVER [8..9] ========================================== */
typedef enum { /*!< IO_BANK0_GPIO28_CTRL_OUTOVER */
IO_BANK0_GPIO28_CTRL_OUTOVER_NORMAL = 0, /*!< NORMAL : drive output from peripheral signal selected by funcsel */
IO_BANK0_GPIO28_CTRL_OUTOVER_INVERT = 1, /*!< INVERT : drive output from inverse of peripheral signal selected
by funcsel */
IO_BANK0_GPIO28_CTRL_OUTOVER_LOW = 2, /*!< LOW : drive output low */
IO_BANK0_GPIO28_CTRL_OUTOVER_HIGH = 3, /*!< HIGH : drive output high */
} IO_BANK0_GPIO28_CTRL_OUTOVER_Enum;
/* ========================================== IO_BANK0 GPIO28_CTRL FUNCSEL [0..4] ========================================== */
typedef enum { /*!< IO_BANK0_GPIO28_CTRL_FUNCSEL */
IO_BANK0_GPIO28_CTRL_FUNCSEL_spi1_rx = 1, /*!< spi1_rx : spi1_rx */
IO_BANK0_GPIO28_CTRL_FUNCSEL_uart0_tx = 2, /*!< uart0_tx : uart0_tx */
IO_BANK0_GPIO28_CTRL_FUNCSEL_i2c0_sda = 3, /*!< i2c0_sda : i2c0_sda */
IO_BANK0_GPIO28_CTRL_FUNCSEL_pwm_a_6 = 4, /*!< pwm_a_6 : pwm_a_6 */
IO_BANK0_GPIO28_CTRL_FUNCSEL_sio_28 = 5, /*!< sio_28 : sio_28 */
IO_BANK0_GPIO28_CTRL_FUNCSEL_pio0_28 = 6, /*!< pio0_28 : pio0_28 */
IO_BANK0_GPIO28_CTRL_FUNCSEL_pio1_28 = 7, /*!< pio1_28 : pio1_28 */
IO_BANK0_GPIO28_CTRL_FUNCSEL_usb_muxing_vbus_detect = 9,/*!< usb_muxing_vbus_detect : usb_muxing_vbus_detect */
IO_BANK0_GPIO28_CTRL_FUNCSEL_null = 31, /*!< null : null */
} IO_BANK0_GPIO28_CTRL_FUNCSEL_Enum;
/* ===================================================== GPIO29_STATUS ===================================================== */
/* ====================================================== GPIO29_CTRL ====================================================== */
/* ========================================= IO_BANK0 GPIO29_CTRL IRQOVER [28..29] ========================================= */
typedef enum { /*!< IO_BANK0_GPIO29_CTRL_IRQOVER */
IO_BANK0_GPIO29_CTRL_IRQOVER_NORMAL = 0, /*!< NORMAL : don't invert the interrupt */
IO_BANK0_GPIO29_CTRL_IRQOVER_INVERT = 1, /*!< INVERT : invert the interrupt */
IO_BANK0_GPIO29_CTRL_IRQOVER_LOW = 2, /*!< LOW : drive interrupt low */
IO_BANK0_GPIO29_CTRL_IRQOVER_HIGH = 3, /*!< HIGH : drive interrupt high */
} IO_BANK0_GPIO29_CTRL_IRQOVER_Enum;
/* ========================================= IO_BANK0 GPIO29_CTRL INOVER [16..17] ========================================== */
typedef enum { /*!< IO_BANK0_GPIO29_CTRL_INOVER */
IO_BANK0_GPIO29_CTRL_INOVER_NORMAL = 0, /*!< NORMAL : don't invert the peri input */
IO_BANK0_GPIO29_CTRL_INOVER_INVERT = 1, /*!< INVERT : invert the peri input */
IO_BANK0_GPIO29_CTRL_INOVER_LOW = 2, /*!< LOW : drive peri input low */
IO_BANK0_GPIO29_CTRL_INOVER_HIGH = 3, /*!< HIGH : drive peri input high */
} IO_BANK0_GPIO29_CTRL_INOVER_Enum;
/* ========================================= IO_BANK0 GPIO29_CTRL OEOVER [12..13] ========================================== */
typedef enum { /*!< IO_BANK0_GPIO29_CTRL_OEOVER */
IO_BANK0_GPIO29_CTRL_OEOVER_NORMAL = 0, /*!< NORMAL : drive output enable from peripheral signal selected
by funcsel */
IO_BANK0_GPIO29_CTRL_OEOVER_INVERT = 1, /*!< INVERT : drive output enable from inverse of peripheral signal
selected by funcsel */
IO_BANK0_GPIO29_CTRL_OEOVER_DISABLE = 2, /*!< DISABLE : disable output */
IO_BANK0_GPIO29_CTRL_OEOVER_ENABLE = 3, /*!< ENABLE : enable output */
} IO_BANK0_GPIO29_CTRL_OEOVER_Enum;
/* ========================================== IO_BANK0 GPIO29_CTRL OUTOVER [8..9] ========================================== */
typedef enum { /*!< IO_BANK0_GPIO29_CTRL_OUTOVER */
IO_BANK0_GPIO29_CTRL_OUTOVER_NORMAL = 0, /*!< NORMAL : drive output from peripheral signal selected by funcsel */
IO_BANK0_GPIO29_CTRL_OUTOVER_INVERT = 1, /*!< INVERT : drive output from inverse of peripheral signal selected
by funcsel */
IO_BANK0_GPIO29_CTRL_OUTOVER_LOW = 2, /*!< LOW : drive output low */
IO_BANK0_GPIO29_CTRL_OUTOVER_HIGH = 3, /*!< HIGH : drive output high */
} IO_BANK0_GPIO29_CTRL_OUTOVER_Enum;
/* ========================================== IO_BANK0 GPIO29_CTRL FUNCSEL [0..4] ========================================== */
typedef enum { /*!< IO_BANK0_GPIO29_CTRL_FUNCSEL */
IO_BANK0_GPIO29_CTRL_FUNCSEL_spi1_ss_n = 1, /*!< spi1_ss_n : spi1_ss_n */
IO_BANK0_GPIO29_CTRL_FUNCSEL_uart0_rx = 2, /*!< uart0_rx : uart0_rx */
IO_BANK0_GPIO29_CTRL_FUNCSEL_i2c0_scl = 3, /*!< i2c0_scl : i2c0_scl */
IO_BANK0_GPIO29_CTRL_FUNCSEL_pwm_b_6 = 4, /*!< pwm_b_6 : pwm_b_6 */
IO_BANK0_GPIO29_CTRL_FUNCSEL_sio_29 = 5, /*!< sio_29 : sio_29 */
IO_BANK0_GPIO29_CTRL_FUNCSEL_pio0_29 = 6, /*!< pio0_29 : pio0_29 */
IO_BANK0_GPIO29_CTRL_FUNCSEL_pio1_29 = 7, /*!< pio1_29 : pio1_29 */
IO_BANK0_GPIO29_CTRL_FUNCSEL_usb_muxing_vbus_en = 9,/*!< usb_muxing_vbus_en : usb_muxing_vbus_en */
IO_BANK0_GPIO29_CTRL_FUNCSEL_null = 31, /*!< null : null */
} IO_BANK0_GPIO29_CTRL_FUNCSEL_Enum;
/* ========================================================= INTR0 ========================================================= */
/* ========================================================= INTR1 ========================================================= */
/* ========================================================= INTR2 ========================================================= */
/* ========================================================= INTR3 ========================================================= */
/* ====================================================== PROC0_INTE0 ====================================================== */
/* ====================================================== PROC0_INTE1 ====================================================== */
/* ====================================================== PROC0_INTE2 ====================================================== */
/* ====================================================== PROC0_INTE3 ====================================================== */
/* ====================================================== PROC0_INTF0 ====================================================== */
/* ====================================================== PROC0_INTF1 ====================================================== */
/* ====================================================== PROC0_INTF2 ====================================================== */
/* ====================================================== PROC0_INTF3 ====================================================== */
/* ====================================================== PROC0_INTS0 ====================================================== */
/* ====================================================== PROC0_INTS1 ====================================================== */
/* ====================================================== PROC0_INTS2 ====================================================== */
/* ====================================================== PROC0_INTS3 ====================================================== */
/* ====================================================== PROC1_INTE0 ====================================================== */
/* ====================================================== PROC1_INTE1 ====================================================== */
/* ====================================================== PROC1_INTE2 ====================================================== */
/* ====================================================== PROC1_INTE3 ====================================================== */
/* ====================================================== PROC1_INTF0 ====================================================== */
/* ====================================================== PROC1_INTF1 ====================================================== */
/* ====================================================== PROC1_INTF2 ====================================================== */
/* ====================================================== PROC1_INTF3 ====================================================== */
/* ====================================================== PROC1_INTS0 ====================================================== */
/* ====================================================== PROC1_INTS1 ====================================================== */
/* ====================================================== PROC1_INTS2 ====================================================== */
/* ====================================================== PROC1_INTS3 ====================================================== */
/* ================================================== DORMANT_WAKE_INTE0 =================================================== */
/* ================================================== DORMANT_WAKE_INTE1 =================================================== */
/* ================================================== DORMANT_WAKE_INTE2 =================================================== */
/* ================================================== DORMANT_WAKE_INTE3 =================================================== */
/* ================================================== DORMANT_WAKE_INTF0 =================================================== */
/* ================================================== DORMANT_WAKE_INTF1 =================================================== */
/* ================================================== DORMANT_WAKE_INTF2 =================================================== */
/* ================================================== DORMANT_WAKE_INTF3 =================================================== */
/* ================================================== DORMANT_WAKE_INTS0 =================================================== */
/* ================================================== DORMANT_WAKE_INTS1 =================================================== */
/* ================================================== DORMANT_WAKE_INTS2 =================================================== */
/* ================================================== DORMANT_WAKE_INTS3 =================================================== */
/* =========================================================================================================================== */
/* ================ IO_QSPI ================ */
/* =========================================================================================================================== */
/* ================================================= GPIO_QSPI_SCLK_STATUS ================================================= */
/* ================================================== GPIO_QSPI_SCLK_CTRL ================================================== */
/* ===================================== IO_QSPI GPIO_QSPI_SCLK_CTRL IRQOVER [28..29] ====================================== */
typedef enum { /*!< IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER */
IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_NORMAL = 0,/*!< NORMAL : don't invert the interrupt */
IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_INVERT = 1,/*!< INVERT : invert the interrupt */
IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_LOW = 2, /*!< LOW : drive interrupt low */
IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_HIGH = 3, /*!< HIGH : drive interrupt high */
} IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_Enum;
/* ====================================== IO_QSPI GPIO_QSPI_SCLK_CTRL INOVER [16..17] ====================================== */
typedef enum { /*!< IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER */
IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_NORMAL = 0,/*!< NORMAL : don't invert the peri input */
IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_INVERT = 1,/*!< INVERT : invert the peri input */
IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_LOW = 2, /*!< LOW : drive peri input low */
IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_HIGH = 3, /*!< HIGH : drive peri input high */
} IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_Enum;
/* ====================================== IO_QSPI GPIO_QSPI_SCLK_CTRL OEOVER [12..13] ====================================== */
typedef enum { /*!< IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER */
IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_NORMAL = 0,/*!< NORMAL : drive output enable from peripheral signal selected
by funcsel */
IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_INVERT = 1,/*!< INVERT : drive output enable from inverse of peripheral signal
selected by funcsel */
IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_DISABLE = 2,/*!< DISABLE : disable output */
IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_ENABLE = 3,/*!< ENABLE : enable output */
} IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_Enum;
/* ====================================== IO_QSPI GPIO_QSPI_SCLK_CTRL OUTOVER [8..9] ======================================= */
typedef enum { /*!< IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER */
IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_NORMAL = 0,/*!< NORMAL : drive output from peripheral signal selected by funcsel */
IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_INVERT = 1,/*!< INVERT : drive output from inverse of peripheral signal selected
by funcsel */
IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_LOW = 2, /*!< LOW : drive output low */
IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_HIGH = 3, /*!< HIGH : drive output high */
} IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_Enum;
/* ====================================== IO_QSPI GPIO_QSPI_SCLK_CTRL FUNCSEL [0..4] ======================================= */
typedef enum { /*!< IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL */
IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_xip_sclk = 0,/*!< xip_sclk : xip_sclk */
IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_sio_30 = 5,/*!< sio_30 : sio_30 */
IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_null = 31,/*!< null : null */
} IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_Enum;
/* ================================================== GPIO_QSPI_SS_STATUS ================================================== */
/* =================================================== GPIO_QSPI_SS_CTRL =================================================== */
/* ====================================== IO_QSPI GPIO_QSPI_SS_CTRL IRQOVER [28..29] ======================================= */
typedef enum { /*!< IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER */
IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_NORMAL = 0, /*!< NORMAL : don't invert the interrupt */
IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_INVERT = 1, /*!< INVERT : invert the interrupt */
IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_LOW = 2, /*!< LOW : drive interrupt low */
IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_HIGH = 3, /*!< HIGH : drive interrupt high */
} IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_Enum;
/* ======================================= IO_QSPI GPIO_QSPI_SS_CTRL INOVER [16..17] ======================================= */
typedef enum { /*!< IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER */
IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_NORMAL = 0, /*!< NORMAL : don't invert the peri input */
IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_INVERT = 1, /*!< INVERT : invert the peri input */
IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_LOW = 2, /*!< LOW : drive peri input low */
IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_HIGH = 3, /*!< HIGH : drive peri input high */
} IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_Enum;
/* ======================================= IO_QSPI GPIO_QSPI_SS_CTRL OEOVER [12..13] ======================================= */
typedef enum { /*!< IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER */
IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_NORMAL = 0, /*!< NORMAL : drive output enable from peripheral signal selected
by funcsel */
IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_INVERT = 1, /*!< INVERT : drive output enable from inverse of peripheral signal
selected by funcsel */
IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_DISABLE = 2, /*!< DISABLE : disable output */
IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_ENABLE = 3, /*!< ENABLE : enable output */
} IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_Enum;
/* ======================================= IO_QSPI GPIO_QSPI_SS_CTRL OUTOVER [8..9] ======================================== */
typedef enum { /*!< IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER */
IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_NORMAL = 0, /*!< NORMAL : drive output from peripheral signal selected by funcsel */
IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_INVERT = 1, /*!< INVERT : drive output from inverse of peripheral signal selected
by funcsel */
IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_LOW = 2, /*!< LOW : drive output low */
IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_HIGH = 3, /*!< HIGH : drive output high */
} IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_Enum;
/* ======================================= IO_QSPI GPIO_QSPI_SS_CTRL FUNCSEL [0..4] ======================================== */
typedef enum { /*!< IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL */
IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_xip_ss_n = 0,/*!< xip_ss_n : xip_ss_n */
IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_sio_31 = 5, /*!< sio_31 : sio_31 */
IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_null = 31, /*!< null : null */
} IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_Enum;
/* ================================================= GPIO_QSPI_SD0_STATUS ================================================== */
/* ================================================== GPIO_QSPI_SD0_CTRL =================================================== */
/* ====================================== IO_QSPI GPIO_QSPI_SD0_CTRL IRQOVER [28..29] ====================================== */
typedef enum { /*!< IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER */
IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_NORMAL = 0,/*!< NORMAL : don't invert the interrupt */
IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_INVERT = 1,/*!< INVERT : invert the interrupt */
IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_LOW = 2, /*!< LOW : drive interrupt low */
IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_HIGH = 3, /*!< HIGH : drive interrupt high */
} IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_Enum;
/* ====================================== IO_QSPI GPIO_QSPI_SD0_CTRL INOVER [16..17] ======================================= */
typedef enum { /*!< IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER */
IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_NORMAL = 0, /*!< NORMAL : don't invert the peri input */
IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_INVERT = 1, /*!< INVERT : invert the peri input */
IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_LOW = 2, /*!< LOW : drive peri input low */
IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_HIGH = 3, /*!< HIGH : drive peri input high */
} IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_Enum;
/* ====================================== IO_QSPI GPIO_QSPI_SD0_CTRL OEOVER [12..13] ======================================= */
typedef enum { /*!< IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER */
IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_NORMAL = 0, /*!< NORMAL : drive output enable from peripheral signal selected
by funcsel */
IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_INVERT = 1, /*!< INVERT : drive output enable from inverse of peripheral signal
selected by funcsel */
IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_DISABLE = 2,/*!< DISABLE : disable output */
IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_ENABLE = 3, /*!< ENABLE : enable output */
} IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_Enum;
/* ======================================= IO_QSPI GPIO_QSPI_SD0_CTRL OUTOVER [8..9] ======================================= */
typedef enum { /*!< IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER */
IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_NORMAL = 0,/*!< NORMAL : drive output from peripheral signal selected by funcsel */
IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_INVERT = 1,/*!< INVERT : drive output from inverse of peripheral signal selected
by funcsel */
IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_LOW = 2, /*!< LOW : drive output low */
IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_HIGH = 3, /*!< HIGH : drive output high */
} IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_Enum;
/* ======================================= IO_QSPI GPIO_QSPI_SD0_CTRL FUNCSEL [0..4] ======================================= */
typedef enum { /*!< IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL */
IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_xip_sd0 = 0,/*!< xip_sd0 : xip_sd0 */
IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_sio_32 = 5,/*!< sio_32 : sio_32 */
IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_null = 31, /*!< null : null */
} IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_Enum;
/* ================================================= GPIO_QSPI_SD1_STATUS ================================================== */
/* ================================================== GPIO_QSPI_SD1_CTRL =================================================== */
/* ====================================== IO_QSPI GPIO_QSPI_SD1_CTRL IRQOVER [28..29] ====================================== */
typedef enum { /*!< IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER */
IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_NORMAL = 0,/*!< NORMAL : don't invert the interrupt */
IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_INVERT = 1,/*!< INVERT : invert the interrupt */
IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_LOW = 2, /*!< LOW : drive interrupt low */
IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_HIGH = 3, /*!< HIGH : drive interrupt high */
} IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_Enum;
/* ====================================== IO_QSPI GPIO_QSPI_SD1_CTRL INOVER [16..17] ======================================= */
typedef enum { /*!< IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER */
IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_NORMAL = 0, /*!< NORMAL : don't invert the peri input */
IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_INVERT = 1, /*!< INVERT : invert the peri input */
IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_LOW = 2, /*!< LOW : drive peri input low */
IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_HIGH = 3, /*!< HIGH : drive peri input high */
} IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_Enum;
/* ====================================== IO_QSPI GPIO_QSPI_SD1_CTRL OEOVER [12..13] ======================================= */
typedef enum { /*!< IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER */
IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_NORMAL = 0, /*!< NORMAL : drive output enable from peripheral signal selected
by funcsel */
IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_INVERT = 1, /*!< INVERT : drive output enable from inverse of peripheral signal
selected by funcsel */
IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_DISABLE = 2,/*!< DISABLE : disable output */
IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_ENABLE = 3, /*!< ENABLE : enable output */
} IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_Enum;
/* ======================================= IO_QSPI GPIO_QSPI_SD1_CTRL OUTOVER [8..9] ======================================= */
typedef enum { /*!< IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER */
IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_NORMAL = 0,/*!< NORMAL : drive output from peripheral signal selected by funcsel */
IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_INVERT = 1,/*!< INVERT : drive output from inverse of peripheral signal selected
by funcsel */
IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_LOW = 2, /*!< LOW : drive output low */
IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_HIGH = 3, /*!< HIGH : drive output high */
} IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_Enum;
/* ======================================= IO_QSPI GPIO_QSPI_SD1_CTRL FUNCSEL [0..4] ======================================= */
typedef enum { /*!< IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL */
IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_xip_sd1 = 0,/*!< xip_sd1 : xip_sd1 */
IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_sio_33 = 5,/*!< sio_33 : sio_33 */
IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_null = 31, /*!< null : null */
} IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_Enum;
/* ================================================= GPIO_QSPI_SD2_STATUS ================================================== */
/* ================================================== GPIO_QSPI_SD2_CTRL =================================================== */
/* ====================================== IO_QSPI GPIO_QSPI_SD2_CTRL IRQOVER [28..29] ====================================== */
typedef enum { /*!< IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER */
IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_NORMAL = 0,/*!< NORMAL : don't invert the interrupt */
IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_INVERT = 1,/*!< INVERT : invert the interrupt */
IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_LOW = 2, /*!< LOW : drive interrupt low */
IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_HIGH = 3, /*!< HIGH : drive interrupt high */
} IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_Enum;
/* ====================================== IO_QSPI GPIO_QSPI_SD2_CTRL INOVER [16..17] ======================================= */
typedef enum { /*!< IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER */
IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_NORMAL = 0, /*!< NORMAL : don't invert the peri input */
IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_INVERT = 1, /*!< INVERT : invert the peri input */
IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_LOW = 2, /*!< LOW : drive peri input low */
IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_HIGH = 3, /*!< HIGH : drive peri input high */
} IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_Enum;
/* ====================================== IO_QSPI GPIO_QSPI_SD2_CTRL OEOVER [12..13] ======================================= */
typedef enum { /*!< IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER */
IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_NORMAL = 0, /*!< NORMAL : drive output enable from peripheral signal selected
by funcsel */
IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_INVERT = 1, /*!< INVERT : drive output enable from inverse of peripheral signal
selected by funcsel */
IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_DISABLE = 2,/*!< DISABLE : disable output */
IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_ENABLE = 3, /*!< ENABLE : enable output */
} IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_Enum;
/* ======================================= IO_QSPI GPIO_QSPI_SD2_CTRL OUTOVER [8..9] ======================================= */
typedef enum { /*!< IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER */
IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_NORMAL = 0,/*!< NORMAL : drive output from peripheral signal selected by funcsel */
IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_INVERT = 1,/*!< INVERT : drive output from inverse of peripheral signal selected
by funcsel */
IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_LOW = 2, /*!< LOW : drive output low */
IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_HIGH = 3, /*!< HIGH : drive output high */
} IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_Enum;
/* ======================================= IO_QSPI GPIO_QSPI_SD2_CTRL FUNCSEL [0..4] ======================================= */
typedef enum { /*!< IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL */
IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_xip_sd2 = 0,/*!< xip_sd2 : xip_sd2 */
IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_sio_34 = 5,/*!< sio_34 : sio_34 */
IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_null = 31, /*!< null : null */
} IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_Enum;
/* ================================================= GPIO_QSPI_SD3_STATUS ================================================== */
/* ================================================== GPIO_QSPI_SD3_CTRL =================================================== */
/* ====================================== IO_QSPI GPIO_QSPI_SD3_CTRL IRQOVER [28..29] ====================================== */
typedef enum { /*!< IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER */
IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_NORMAL = 0,/*!< NORMAL : don't invert the interrupt */
IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_INVERT = 1,/*!< INVERT : invert the interrupt */
IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_LOW = 2, /*!< LOW : drive interrupt low */
IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_HIGH = 3, /*!< HIGH : drive interrupt high */
} IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_Enum;
/* ====================================== IO_QSPI GPIO_QSPI_SD3_CTRL INOVER [16..17] ======================================= */
typedef enum { /*!< IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER */
IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_NORMAL = 0, /*!< NORMAL : don't invert the peri input */
IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_INVERT = 1, /*!< INVERT : invert the peri input */
IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_LOW = 2, /*!< LOW : drive peri input low */
IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_HIGH = 3, /*!< HIGH : drive peri input high */
} IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_Enum;
/* ====================================== IO_QSPI GPIO_QSPI_SD3_CTRL OEOVER [12..13] ======================================= */
typedef enum { /*!< IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER */
IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_NORMAL = 0, /*!< NORMAL : drive output enable from peripheral signal selected
by funcsel */
IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_INVERT = 1, /*!< INVERT : drive output enable from inverse of peripheral signal
selected by funcsel */
IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_DISABLE = 2,/*!< DISABLE : disable output */
IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_ENABLE = 3, /*!< ENABLE : enable output */
} IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_Enum;
/* ======================================= IO_QSPI GPIO_QSPI_SD3_CTRL OUTOVER [8..9] ======================================= */
typedef enum { /*!< IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER */
IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_NORMAL = 0,/*!< NORMAL : drive output from peripheral signal selected by funcsel */
IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_INVERT = 1,/*!< INVERT : drive output from inverse of peripheral signal selected
by funcsel */
IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_LOW = 2, /*!< LOW : drive output low */
IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_HIGH = 3, /*!< HIGH : drive output high */
} IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_Enum;
/* ======================================= IO_QSPI GPIO_QSPI_SD3_CTRL FUNCSEL [0..4] ======================================= */
typedef enum { /*!< IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL */
IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_xip_sd3 = 0,/*!< xip_sd3 : xip_sd3 */
IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_sio_35 = 5,/*!< sio_35 : sio_35 */
IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_null = 31, /*!< null : null */
} IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_Enum;
/* ========================================================= INTR ========================================================== */
/* ====================================================== PROC0_INTE ======================================================= */
/* ====================================================== PROC0_INTF ======================================================= */
/* ====================================================== PROC0_INTS ======================================================= */
/* ====================================================== PROC1_INTE ======================================================= */
/* ====================================================== PROC1_INTF ======================================================= */
/* ====================================================== PROC1_INTS ======================================================= */
/* =================================================== DORMANT_WAKE_INTE =================================================== */
/* =================================================== DORMANT_WAKE_INTF =================================================== */
/* =================================================== DORMANT_WAKE_INTS =================================================== */
/* =========================================================================================================================== */
/* ================ PADS_BANK0 ================ */
/* =========================================================================================================================== */
/* ==================================================== VOLTAGE_SELECT ===================================================== */
/* ==================================== PADS_BANK0 VOLTAGE_SELECT VOLTAGE_SELECT [0..0] ==================================== */
typedef enum { /*!< PADS_BANK0_VOLTAGE_SELECT_VOLTAGE_SELECT */
PADS_BANK0_VOLTAGE_SELECT_VOLTAGE_SELECT_3v3 = 0,/*!< 3v3 : Set voltage to 3.3V (DVDD >= 2V5) */
PADS_BANK0_VOLTAGE_SELECT_VOLTAGE_SELECT_1v8 = 1,/*!< 1v8 : Set voltage to 1.8V (DVDD <= 1V8) */
} PADS_BANK0_VOLTAGE_SELECT_VOLTAGE_SELECT_Enum;
/* ========================================================= GPIO0 ========================================================= */
/* ============================================= PADS_BANK0 GPIO0 DRIVE [4..5] ============================================= */
typedef enum { /*!< PADS_BANK0_GPIO0_DRIVE */
PADS_BANK0_GPIO0_DRIVE_2mA = 0, /*!< 2mA : 2mA */
PADS_BANK0_GPIO0_DRIVE_4mA = 1, /*!< 4mA : 4mA */
PADS_BANK0_GPIO0_DRIVE_8mA = 2, /*!< 8mA : 8mA */
PADS_BANK0_GPIO0_DRIVE_12mA = 3, /*!< 12mA : 12mA */
} PADS_BANK0_GPIO0_DRIVE_Enum;
/* ========================================================= GPIO1 ========================================================= */
/* ============================================= PADS_BANK0 GPIO1 DRIVE [4..5] ============================================= */
typedef enum { /*!< PADS_BANK0_GPIO1_DRIVE */
PADS_BANK0_GPIO1_DRIVE_2mA = 0, /*!< 2mA : 2mA */
PADS_BANK0_GPIO1_DRIVE_4mA = 1, /*!< 4mA : 4mA */
PADS_BANK0_GPIO1_DRIVE_8mA = 2, /*!< 8mA : 8mA */
PADS_BANK0_GPIO1_DRIVE_12mA = 3, /*!< 12mA : 12mA */
} PADS_BANK0_GPIO1_DRIVE_Enum;
/* ========================================================= GPIO2 ========================================================= */
/* ============================================= PADS_BANK0 GPIO2 DRIVE [4..5] ============================================= */
typedef enum { /*!< PADS_BANK0_GPIO2_DRIVE */
PADS_BANK0_GPIO2_DRIVE_2mA = 0, /*!< 2mA : 2mA */
PADS_BANK0_GPIO2_DRIVE_4mA = 1, /*!< 4mA : 4mA */
PADS_BANK0_GPIO2_DRIVE_8mA = 2, /*!< 8mA : 8mA */
PADS_BANK0_GPIO2_DRIVE_12mA = 3, /*!< 12mA : 12mA */
} PADS_BANK0_GPIO2_DRIVE_Enum;
/* ========================================================= GPIO3 ========================================================= */
/* ============================================= PADS_BANK0 GPIO3 DRIVE [4..5] ============================================= */
typedef enum { /*!< PADS_BANK0_GPIO3_DRIVE */
PADS_BANK0_GPIO3_DRIVE_2mA = 0, /*!< 2mA : 2mA */
PADS_BANK0_GPIO3_DRIVE_4mA = 1, /*!< 4mA : 4mA */
PADS_BANK0_GPIO3_DRIVE_8mA = 2, /*!< 8mA : 8mA */
PADS_BANK0_GPIO3_DRIVE_12mA = 3, /*!< 12mA : 12mA */
} PADS_BANK0_GPIO3_DRIVE_Enum;
/* ========================================================= GPIO4 ========================================================= */
/* ============================================= PADS_BANK0 GPIO4 DRIVE [4..5] ============================================= */
typedef enum { /*!< PADS_BANK0_GPIO4_DRIVE */
PADS_BANK0_GPIO4_DRIVE_2mA = 0, /*!< 2mA : 2mA */
PADS_BANK0_GPIO4_DRIVE_4mA = 1, /*!< 4mA : 4mA */
PADS_BANK0_GPIO4_DRIVE_8mA = 2, /*!< 8mA : 8mA */
PADS_BANK0_GPIO4_DRIVE_12mA = 3, /*!< 12mA : 12mA */
} PADS_BANK0_GPIO4_DRIVE_Enum;
/* ========================================================= GPIO5 ========================================================= */
/* ============================================= PADS_BANK0 GPIO5 DRIVE [4..5] ============================================= */
typedef enum { /*!< PADS_BANK0_GPIO5_DRIVE */
PADS_BANK0_GPIO5_DRIVE_2mA = 0, /*!< 2mA : 2mA */
PADS_BANK0_GPIO5_DRIVE_4mA = 1, /*!< 4mA : 4mA */
PADS_BANK0_GPIO5_DRIVE_8mA = 2, /*!< 8mA : 8mA */
PADS_BANK0_GPIO5_DRIVE_12mA = 3, /*!< 12mA : 12mA */
} PADS_BANK0_GPIO5_DRIVE_Enum;
/* ========================================================= GPIO6 ========================================================= */
/* ============================================= PADS_BANK0 GPIO6 DRIVE [4..5] ============================================= */
typedef enum { /*!< PADS_BANK0_GPIO6_DRIVE */
PADS_BANK0_GPIO6_DRIVE_2mA = 0, /*!< 2mA : 2mA */
PADS_BANK0_GPIO6_DRIVE_4mA = 1, /*!< 4mA : 4mA */
PADS_BANK0_GPIO6_DRIVE_8mA = 2, /*!< 8mA : 8mA */
PADS_BANK0_GPIO6_DRIVE_12mA = 3, /*!< 12mA : 12mA */
} PADS_BANK0_GPIO6_DRIVE_Enum;
/* ========================================================= GPIO7 ========================================================= */
/* ============================================= PADS_BANK0 GPIO7 DRIVE [4..5] ============================================= */
typedef enum { /*!< PADS_BANK0_GPIO7_DRIVE */
PADS_BANK0_GPIO7_DRIVE_2mA = 0, /*!< 2mA : 2mA */
PADS_BANK0_GPIO7_DRIVE_4mA = 1, /*!< 4mA : 4mA */
PADS_BANK0_GPIO7_DRIVE_8mA = 2, /*!< 8mA : 8mA */
PADS_BANK0_GPIO7_DRIVE_12mA = 3, /*!< 12mA : 12mA */
} PADS_BANK0_GPIO7_DRIVE_Enum;
/* ========================================================= GPIO8 ========================================================= */
/* ============================================= PADS_BANK0 GPIO8 DRIVE [4..5] ============================================= */
typedef enum { /*!< PADS_BANK0_GPIO8_DRIVE */
PADS_BANK0_GPIO8_DRIVE_2mA = 0, /*!< 2mA : 2mA */
PADS_BANK0_GPIO8_DRIVE_4mA = 1, /*!< 4mA : 4mA */
PADS_BANK0_GPIO8_DRIVE_8mA = 2, /*!< 8mA : 8mA */
PADS_BANK0_GPIO8_DRIVE_12mA = 3, /*!< 12mA : 12mA */
} PADS_BANK0_GPIO8_DRIVE_Enum;
/* ========================================================= GPIO9 ========================================================= */
/* ============================================= PADS_BANK0 GPIO9 DRIVE [4..5] ============================================= */
typedef enum { /*!< PADS_BANK0_GPIO9_DRIVE */
PADS_BANK0_GPIO9_DRIVE_2mA = 0, /*!< 2mA : 2mA */
PADS_BANK0_GPIO9_DRIVE_4mA = 1, /*!< 4mA : 4mA */
PADS_BANK0_GPIO9_DRIVE_8mA = 2, /*!< 8mA : 8mA */
PADS_BANK0_GPIO9_DRIVE_12mA = 3, /*!< 12mA : 12mA */
} PADS_BANK0_GPIO9_DRIVE_Enum;
/* ======================================================== GPIO10 ========================================================= */
/* ============================================ PADS_BANK0 GPIO10 DRIVE [4..5] ============================================= */
typedef enum { /*!< PADS_BANK0_GPIO10_DRIVE */
PADS_BANK0_GPIO10_DRIVE_2mA = 0, /*!< 2mA : 2mA */
PADS_BANK0_GPIO10_DRIVE_4mA = 1, /*!< 4mA : 4mA */
PADS_BANK0_GPIO10_DRIVE_8mA = 2, /*!< 8mA : 8mA */
PADS_BANK0_GPIO10_DRIVE_12mA = 3, /*!< 12mA : 12mA */
} PADS_BANK0_GPIO10_DRIVE_Enum;
/* ======================================================== GPIO11 ========================================================= */
/* ============================================ PADS_BANK0 GPIO11 DRIVE [4..5] ============================================= */
typedef enum { /*!< PADS_BANK0_GPIO11_DRIVE */
PADS_BANK0_GPIO11_DRIVE_2mA = 0, /*!< 2mA : 2mA */
PADS_BANK0_GPIO11_DRIVE_4mA = 1, /*!< 4mA : 4mA */
PADS_BANK0_GPIO11_DRIVE_8mA = 2, /*!< 8mA : 8mA */
PADS_BANK0_GPIO11_DRIVE_12mA = 3, /*!< 12mA : 12mA */
} PADS_BANK0_GPIO11_DRIVE_Enum;
/* ======================================================== GPIO12 ========================================================= */
/* ============================================ PADS_BANK0 GPIO12 DRIVE [4..5] ============================================= */
typedef enum { /*!< PADS_BANK0_GPIO12_DRIVE */
PADS_BANK0_GPIO12_DRIVE_2mA = 0, /*!< 2mA : 2mA */
PADS_BANK0_GPIO12_DRIVE_4mA = 1, /*!< 4mA : 4mA */
PADS_BANK0_GPIO12_DRIVE_8mA = 2, /*!< 8mA : 8mA */
PADS_BANK0_GPIO12_DRIVE_12mA = 3, /*!< 12mA : 12mA */
} PADS_BANK0_GPIO12_DRIVE_Enum;
/* ======================================================== GPIO13 ========================================================= */
/* ============================================ PADS_BANK0 GPIO13 DRIVE [4..5] ============================================= */
typedef enum { /*!< PADS_BANK0_GPIO13_DRIVE */
PADS_BANK0_GPIO13_DRIVE_2mA = 0, /*!< 2mA : 2mA */
PADS_BANK0_GPIO13_DRIVE_4mA = 1, /*!< 4mA : 4mA */
PADS_BANK0_GPIO13_DRIVE_8mA = 2, /*!< 8mA : 8mA */
PADS_BANK0_GPIO13_DRIVE_12mA = 3, /*!< 12mA : 12mA */
} PADS_BANK0_GPIO13_DRIVE_Enum;
/* ======================================================== GPIO14 ========================================================= */
/* ============================================ PADS_BANK0 GPIO14 DRIVE [4..5] ============================================= */
typedef enum { /*!< PADS_BANK0_GPIO14_DRIVE */
PADS_BANK0_GPIO14_DRIVE_2mA = 0, /*!< 2mA : 2mA */
PADS_BANK0_GPIO14_DRIVE_4mA = 1, /*!< 4mA : 4mA */
PADS_BANK0_GPIO14_DRIVE_8mA = 2, /*!< 8mA : 8mA */
PADS_BANK0_GPIO14_DRIVE_12mA = 3, /*!< 12mA : 12mA */
} PADS_BANK0_GPIO14_DRIVE_Enum;
/* ======================================================== GPIO15 ========================================================= */
/* ============================================ PADS_BANK0 GPIO15 DRIVE [4..5] ============================================= */
typedef enum { /*!< PADS_BANK0_GPIO15_DRIVE */
PADS_BANK0_GPIO15_DRIVE_2mA = 0, /*!< 2mA : 2mA */
PADS_BANK0_GPIO15_DRIVE_4mA = 1, /*!< 4mA : 4mA */
PADS_BANK0_GPIO15_DRIVE_8mA = 2, /*!< 8mA : 8mA */
PADS_BANK0_GPIO15_DRIVE_12mA = 3, /*!< 12mA : 12mA */
} PADS_BANK0_GPIO15_DRIVE_Enum;
/* ======================================================== GPIO16 ========================================================= */
/* ============================================ PADS_BANK0 GPIO16 DRIVE [4..5] ============================================= */
typedef enum { /*!< PADS_BANK0_GPIO16_DRIVE */
PADS_BANK0_GPIO16_DRIVE_2mA = 0, /*!< 2mA : 2mA */
PADS_BANK0_GPIO16_DRIVE_4mA = 1, /*!< 4mA : 4mA */
PADS_BANK0_GPIO16_DRIVE_8mA = 2, /*!< 8mA : 8mA */
PADS_BANK0_GPIO16_DRIVE_12mA = 3, /*!< 12mA : 12mA */
} PADS_BANK0_GPIO16_DRIVE_Enum;
/* ======================================================== GPIO17 ========================================================= */
/* ============================================ PADS_BANK0 GPIO17 DRIVE [4..5] ============================================= */
typedef enum { /*!< PADS_BANK0_GPIO17_DRIVE */
PADS_BANK0_GPIO17_DRIVE_2mA = 0, /*!< 2mA : 2mA */
PADS_BANK0_GPIO17_DRIVE_4mA = 1, /*!< 4mA : 4mA */
PADS_BANK0_GPIO17_DRIVE_8mA = 2, /*!< 8mA : 8mA */
PADS_BANK0_GPIO17_DRIVE_12mA = 3, /*!< 12mA : 12mA */
} PADS_BANK0_GPIO17_DRIVE_Enum;
/* ======================================================== GPIO18 ========================================================= */
/* ============================================ PADS_BANK0 GPIO18 DRIVE [4..5] ============================================= */
typedef enum { /*!< PADS_BANK0_GPIO18_DRIVE */
PADS_BANK0_GPIO18_DRIVE_2mA = 0, /*!< 2mA : 2mA */
PADS_BANK0_GPIO18_DRIVE_4mA = 1, /*!< 4mA : 4mA */
PADS_BANK0_GPIO18_DRIVE_8mA = 2, /*!< 8mA : 8mA */
PADS_BANK0_GPIO18_DRIVE_12mA = 3, /*!< 12mA : 12mA */
} PADS_BANK0_GPIO18_DRIVE_Enum;
/* ======================================================== GPIO19 ========================================================= */
/* ============================================ PADS_BANK0 GPIO19 DRIVE [4..5] ============================================= */
typedef enum { /*!< PADS_BANK0_GPIO19_DRIVE */
PADS_BANK0_GPIO19_DRIVE_2mA = 0, /*!< 2mA : 2mA */
PADS_BANK0_GPIO19_DRIVE_4mA = 1, /*!< 4mA : 4mA */
PADS_BANK0_GPIO19_DRIVE_8mA = 2, /*!< 8mA : 8mA */
PADS_BANK0_GPIO19_DRIVE_12mA = 3, /*!< 12mA : 12mA */
} PADS_BANK0_GPIO19_DRIVE_Enum;
/* ======================================================== GPIO20 ========================================================= */
/* ============================================ PADS_BANK0 GPIO20 DRIVE [4..5] ============================================= */
typedef enum { /*!< PADS_BANK0_GPIO20_DRIVE */
PADS_BANK0_GPIO20_DRIVE_2mA = 0, /*!< 2mA : 2mA */
PADS_BANK0_GPIO20_DRIVE_4mA = 1, /*!< 4mA : 4mA */
PADS_BANK0_GPIO20_DRIVE_8mA = 2, /*!< 8mA : 8mA */
PADS_BANK0_GPIO20_DRIVE_12mA = 3, /*!< 12mA : 12mA */
} PADS_BANK0_GPIO20_DRIVE_Enum;
/* ======================================================== GPIO21 ========================================================= */
/* ============================================ PADS_BANK0 GPIO21 DRIVE [4..5] ============================================= */
typedef enum { /*!< PADS_BANK0_GPIO21_DRIVE */
PADS_BANK0_GPIO21_DRIVE_2mA = 0, /*!< 2mA : 2mA */
PADS_BANK0_GPIO21_DRIVE_4mA = 1, /*!< 4mA : 4mA */
PADS_BANK0_GPIO21_DRIVE_8mA = 2, /*!< 8mA : 8mA */
PADS_BANK0_GPIO21_DRIVE_12mA = 3, /*!< 12mA : 12mA */
} PADS_BANK0_GPIO21_DRIVE_Enum;
/* ======================================================== GPIO22 ========================================================= */
/* ============================================ PADS_BANK0 GPIO22 DRIVE [4..5] ============================================= */
typedef enum { /*!< PADS_BANK0_GPIO22_DRIVE */
PADS_BANK0_GPIO22_DRIVE_2mA = 0, /*!< 2mA : 2mA */
PADS_BANK0_GPIO22_DRIVE_4mA = 1, /*!< 4mA : 4mA */
PADS_BANK0_GPIO22_DRIVE_8mA = 2, /*!< 8mA : 8mA */
PADS_BANK0_GPIO22_DRIVE_12mA = 3, /*!< 12mA : 12mA */
} PADS_BANK0_GPIO22_DRIVE_Enum;
/* ======================================================== GPIO23 ========================================================= */
/* ============================================ PADS_BANK0 GPIO23 DRIVE [4..5] ============================================= */
typedef enum { /*!< PADS_BANK0_GPIO23_DRIVE */
PADS_BANK0_GPIO23_DRIVE_2mA = 0, /*!< 2mA : 2mA */
PADS_BANK0_GPIO23_DRIVE_4mA = 1, /*!< 4mA : 4mA */
PADS_BANK0_GPIO23_DRIVE_8mA = 2, /*!< 8mA : 8mA */
PADS_BANK0_GPIO23_DRIVE_12mA = 3, /*!< 12mA : 12mA */
} PADS_BANK0_GPIO23_DRIVE_Enum;
/* ======================================================== GPIO24 ========================================================= */
/* ============================================ PADS_BANK0 GPIO24 DRIVE [4..5] ============================================= */
typedef enum { /*!< PADS_BANK0_GPIO24_DRIVE */
PADS_BANK0_GPIO24_DRIVE_2mA = 0, /*!< 2mA : 2mA */
PADS_BANK0_GPIO24_DRIVE_4mA = 1, /*!< 4mA : 4mA */
PADS_BANK0_GPIO24_DRIVE_8mA = 2, /*!< 8mA : 8mA */
PADS_BANK0_GPIO24_DRIVE_12mA = 3, /*!< 12mA : 12mA */
} PADS_BANK0_GPIO24_DRIVE_Enum;
/* ======================================================== GPIO25 ========================================================= */
/* ============================================ PADS_BANK0 GPIO25 DRIVE [4..5] ============================================= */
typedef enum { /*!< PADS_BANK0_GPIO25_DRIVE */
PADS_BANK0_GPIO25_DRIVE_2mA = 0, /*!< 2mA : 2mA */
PADS_BANK0_GPIO25_DRIVE_4mA = 1, /*!< 4mA : 4mA */
PADS_BANK0_GPIO25_DRIVE_8mA = 2, /*!< 8mA : 8mA */
PADS_BANK0_GPIO25_DRIVE_12mA = 3, /*!< 12mA : 12mA */
} PADS_BANK0_GPIO25_DRIVE_Enum;
/* ======================================================== GPIO26 ========================================================= */
/* ============================================ PADS_BANK0 GPIO26 DRIVE [4..5] ============================================= */
typedef enum { /*!< PADS_BANK0_GPIO26_DRIVE */
PADS_BANK0_GPIO26_DRIVE_2mA = 0, /*!< 2mA : 2mA */
PADS_BANK0_GPIO26_DRIVE_4mA = 1, /*!< 4mA : 4mA */
PADS_BANK0_GPIO26_DRIVE_8mA = 2, /*!< 8mA : 8mA */
PADS_BANK0_GPIO26_DRIVE_12mA = 3, /*!< 12mA : 12mA */
} PADS_BANK0_GPIO26_DRIVE_Enum;
/* ======================================================== GPIO27 ========================================================= */
/* ============================================ PADS_BANK0 GPIO27 DRIVE [4..5] ============================================= */
typedef enum { /*!< PADS_BANK0_GPIO27_DRIVE */
PADS_BANK0_GPIO27_DRIVE_2mA = 0, /*!< 2mA : 2mA */
PADS_BANK0_GPIO27_DRIVE_4mA = 1, /*!< 4mA : 4mA */
PADS_BANK0_GPIO27_DRIVE_8mA = 2, /*!< 8mA : 8mA */
PADS_BANK0_GPIO27_DRIVE_12mA = 3, /*!< 12mA : 12mA */
} PADS_BANK0_GPIO27_DRIVE_Enum;
/* ======================================================== GPIO28 ========================================================= */
/* ============================================ PADS_BANK0 GPIO28 DRIVE [4..5] ============================================= */
typedef enum { /*!< PADS_BANK0_GPIO28_DRIVE */
PADS_BANK0_GPIO28_DRIVE_2mA = 0, /*!< 2mA : 2mA */
PADS_BANK0_GPIO28_DRIVE_4mA = 1, /*!< 4mA : 4mA */
PADS_BANK0_GPIO28_DRIVE_8mA = 2, /*!< 8mA : 8mA */
PADS_BANK0_GPIO28_DRIVE_12mA = 3, /*!< 12mA : 12mA */
} PADS_BANK0_GPIO28_DRIVE_Enum;
/* ======================================================== GPIO29 ========================================================= */
/* ============================================ PADS_BANK0 GPIO29 DRIVE [4..5] ============================================= */
typedef enum { /*!< PADS_BANK0_GPIO29_DRIVE */
PADS_BANK0_GPIO29_DRIVE_2mA = 0, /*!< 2mA : 2mA */
PADS_BANK0_GPIO29_DRIVE_4mA = 1, /*!< 4mA : 4mA */
PADS_BANK0_GPIO29_DRIVE_8mA = 2, /*!< 8mA : 8mA */
PADS_BANK0_GPIO29_DRIVE_12mA = 3, /*!< 12mA : 12mA */
} PADS_BANK0_GPIO29_DRIVE_Enum;
/* ========================================================= SWCLK ========================================================= */
/* ============================================= PADS_BANK0 SWCLK DRIVE [4..5] ============================================= */
typedef enum { /*!< PADS_BANK0_SWCLK_DRIVE */
PADS_BANK0_SWCLK_DRIVE_2mA = 0, /*!< 2mA : 2mA */
PADS_BANK0_SWCLK_DRIVE_4mA = 1, /*!< 4mA : 4mA */
PADS_BANK0_SWCLK_DRIVE_8mA = 2, /*!< 8mA : 8mA */
PADS_BANK0_SWCLK_DRIVE_12mA = 3, /*!< 12mA : 12mA */
} PADS_BANK0_SWCLK_DRIVE_Enum;
/* ========================================================== SWD ========================================================== */
/* ============================================== PADS_BANK0 SWD DRIVE [4..5] ============================================== */
typedef enum { /*!< PADS_BANK0_SWD_DRIVE */
PADS_BANK0_SWD_DRIVE_2mA = 0, /*!< 2mA : 2mA */
PADS_BANK0_SWD_DRIVE_4mA = 1, /*!< 4mA : 4mA */
PADS_BANK0_SWD_DRIVE_8mA = 2, /*!< 8mA : 8mA */
PADS_BANK0_SWD_DRIVE_12mA = 3, /*!< 12mA : 12mA */
} PADS_BANK0_SWD_DRIVE_Enum;
/* =========================================================================================================================== */
/* ================ PADS_QSPI ================ */
/* =========================================================================================================================== */
/* ==================================================== VOLTAGE_SELECT ===================================================== */
/* ==================================== PADS_QSPI VOLTAGE_SELECT VOLTAGE_SELECT [0..0] ===================================== */
typedef enum { /*!< PADS_QSPI_VOLTAGE_SELECT_VOLTAGE_SELECT */
PADS_QSPI_VOLTAGE_SELECT_VOLTAGE_SELECT_3v3 = 0,/*!< 3v3 : Set voltage to 3.3V (DVDD >= 2V5) */
PADS_QSPI_VOLTAGE_SELECT_VOLTAGE_SELECT_1v8 = 1,/*!< 1v8 : Set voltage to 1.8V (DVDD <= 1V8) */
} PADS_QSPI_VOLTAGE_SELECT_VOLTAGE_SELECT_Enum;
/* ==================================================== GPIO_QSPI_SCLK ===================================================== */
/* ========================================= PADS_QSPI GPIO_QSPI_SCLK DRIVE [4..5] ========================================= */
typedef enum { /*!< PADS_QSPI_GPIO_QSPI_SCLK_DRIVE */
PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_2mA = 0, /*!< 2mA : 2mA */
PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_4mA = 1, /*!< 4mA : 4mA */
PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_8mA = 2, /*!< 8mA : 8mA */
PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_12mA = 3, /*!< 12mA : 12mA */
} PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_Enum;
/* ===================================================== GPIO_QSPI_SD0 ===================================================== */
/* ========================================= PADS_QSPI GPIO_QSPI_SD0 DRIVE [4..5] ========================================== */
typedef enum { /*!< PADS_QSPI_GPIO_QSPI_SD0_DRIVE */
PADS_QSPI_GPIO_QSPI_SD0_DRIVE_2mA = 0, /*!< 2mA : 2mA */
PADS_QSPI_GPIO_QSPI_SD0_DRIVE_4mA = 1, /*!< 4mA : 4mA */
PADS_QSPI_GPIO_QSPI_SD0_DRIVE_8mA = 2, /*!< 8mA : 8mA */
PADS_QSPI_GPIO_QSPI_SD0_DRIVE_12mA = 3, /*!< 12mA : 12mA */
} PADS_QSPI_GPIO_QSPI_SD0_DRIVE_Enum;
/* ===================================================== GPIO_QSPI_SD1 ===================================================== */
/* ========================================= PADS_QSPI GPIO_QSPI_SD1 DRIVE [4..5] ========================================== */
typedef enum { /*!< PADS_QSPI_GPIO_QSPI_SD1_DRIVE */
PADS_QSPI_GPIO_QSPI_SD1_DRIVE_2mA = 0, /*!< 2mA : 2mA */
PADS_QSPI_GPIO_QSPI_SD1_DRIVE_4mA = 1, /*!< 4mA : 4mA */
PADS_QSPI_GPIO_QSPI_SD1_DRIVE_8mA = 2, /*!< 8mA : 8mA */
PADS_QSPI_GPIO_QSPI_SD1_DRIVE_12mA = 3, /*!< 12mA : 12mA */
} PADS_QSPI_GPIO_QSPI_SD1_DRIVE_Enum;
/* ===================================================== GPIO_QSPI_SD2 ===================================================== */
/* ========================================= PADS_QSPI GPIO_QSPI_SD2 DRIVE [4..5] ========================================== */
typedef enum { /*!< PADS_QSPI_GPIO_QSPI_SD2_DRIVE */
PADS_QSPI_GPIO_QSPI_SD2_DRIVE_2mA = 0, /*!< 2mA : 2mA */
PADS_QSPI_GPIO_QSPI_SD2_DRIVE_4mA = 1, /*!< 4mA : 4mA */
PADS_QSPI_GPIO_QSPI_SD2_DRIVE_8mA = 2, /*!< 8mA : 8mA */
PADS_QSPI_GPIO_QSPI_SD2_DRIVE_12mA = 3, /*!< 12mA : 12mA */
} PADS_QSPI_GPIO_QSPI_SD2_DRIVE_Enum;
/* ===================================================== GPIO_QSPI_SD3 ===================================================== */
/* ========================================= PADS_QSPI GPIO_QSPI_SD3 DRIVE [4..5] ========================================== */
typedef enum { /*!< PADS_QSPI_GPIO_QSPI_SD3_DRIVE */
PADS_QSPI_GPIO_QSPI_SD3_DRIVE_2mA = 0, /*!< 2mA : 2mA */
PADS_QSPI_GPIO_QSPI_SD3_DRIVE_4mA = 1, /*!< 4mA : 4mA */
PADS_QSPI_GPIO_QSPI_SD3_DRIVE_8mA = 2, /*!< 8mA : 8mA */
PADS_QSPI_GPIO_QSPI_SD3_DRIVE_12mA = 3, /*!< 12mA : 12mA */
} PADS_QSPI_GPIO_QSPI_SD3_DRIVE_Enum;
/* ===================================================== GPIO_QSPI_SS ====================================================== */
/* ========================================== PADS_QSPI GPIO_QSPI_SS DRIVE [4..5] ========================================== */
typedef enum { /*!< PADS_QSPI_GPIO_QSPI_SS_DRIVE */
PADS_QSPI_GPIO_QSPI_SS_DRIVE_2mA = 0, /*!< 2mA : 2mA */
PADS_QSPI_GPIO_QSPI_SS_DRIVE_4mA = 1, /*!< 4mA : 4mA */
PADS_QSPI_GPIO_QSPI_SS_DRIVE_8mA = 2, /*!< 8mA : 8mA */
PADS_QSPI_GPIO_QSPI_SS_DRIVE_12mA = 3, /*!< 12mA : 12mA */
} PADS_QSPI_GPIO_QSPI_SS_DRIVE_Enum;
/* =========================================================================================================================== */
/* ================ XOSC ================ */
/* =========================================================================================================================== */
/* ========================================================= CTRL ========================================================== */
/* =============================================== XOSC CTRL ENABLE [12..23] =============================================== */
typedef enum { /*!< XOSC_CTRL_ENABLE */
XOSC_CTRL_ENABLE_DISABLE = 3358, /*!< DISABLE : DISABLE */
XOSC_CTRL_ENABLE_ENABLE = 4011, /*!< ENABLE : ENABLE */
} XOSC_CTRL_ENABLE_Enum;
/* ============================================= XOSC CTRL FREQ_RANGE [0..11] ============================================== */
typedef enum { /*!< XOSC_CTRL_FREQ_RANGE */
XOSC_CTRL_FREQ_RANGE_1_15MHZ = 2720, /*!< 1_15MHZ : 1_15MHZ */
XOSC_CTRL_FREQ_RANGE_RESERVED_1 = 2721, /*!< RESERVED_1 : RESERVED_1 */
XOSC_CTRL_FREQ_RANGE_RESERVED_2 = 2722, /*!< RESERVED_2 : RESERVED_2 */
XOSC_CTRL_FREQ_RANGE_RESERVED_3 = 2723, /*!< RESERVED_3 : RESERVED_3 */
} XOSC_CTRL_FREQ_RANGE_Enum;
/* ======================================================== STATUS ========================================================= */
/* ============================================= XOSC STATUS FREQ_RANGE [0..1] ============================================= */
typedef enum { /*!< XOSC_STATUS_FREQ_RANGE */
XOSC_STATUS_FREQ_RANGE_1_15MHZ = 0, /*!< 1_15MHZ : 1_15MHZ */
XOSC_STATUS_FREQ_RANGE_RESERVED_1 = 1, /*!< RESERVED_1 : RESERVED_1 */
XOSC_STATUS_FREQ_RANGE_RESERVED_2 = 2, /*!< RESERVED_2 : RESERVED_2 */
XOSC_STATUS_FREQ_RANGE_RESERVED_3 = 3, /*!< RESERVED_3 : RESERVED_3 */
} XOSC_STATUS_FREQ_RANGE_Enum;
/* ======================================================== DORMANT ======================================================== */
/* ======================================================== STARTUP ======================================================== */
/* ========================================================= COUNT ========================================================= */
/* =========================================================================================================================== */
/* ================ PLL_SYS ================ */
/* =========================================================================================================================== */
/* ========================================================== CS =========================================================== */
/* ========================================================== PWR ========================================================== */
/* ======================================================= FBDIV_INT ======================================================= */
/* ========================================================= PRIM ========================================================== */
/* =========================================================================================================================== */
/* ================ BUSCTRL ================ */
/* =========================================================================================================================== */
/* ===================================================== BUS_PRIORITY ====================================================== */
/* =================================================== BUS_PRIORITY_ACK ==================================================== */
/* ======================================================= PERFCTR0 ======================================================== */
/* ======================================================= PERFSEL0 ======================================================== */
/* =========================================== BUSCTRL PERFSEL0 PERFSEL0 [0..4] ============================================ */
typedef enum { /*!< BUSCTRL_PERFSEL0_PERFSEL0 */
BUSCTRL_PERFSEL0_PERFSEL0_apb_contested = 0, /*!< apb_contested : apb_contested */
BUSCTRL_PERFSEL0_PERFSEL0_apb = 1, /*!< apb : apb */
BUSCTRL_PERFSEL0_PERFSEL0_fastperi_contested = 2,/*!< fastperi_contested : fastperi_contested */
BUSCTRL_PERFSEL0_PERFSEL0_fastperi = 3, /*!< fastperi : fastperi */
BUSCTRL_PERFSEL0_PERFSEL0_sram5_contested = 4,/*!< sram5_contested : sram5_contested */
BUSCTRL_PERFSEL0_PERFSEL0_sram5 = 5, /*!< sram5 : sram5 */
BUSCTRL_PERFSEL0_PERFSEL0_sram4_contested = 6,/*!< sram4_contested : sram4_contested */
BUSCTRL_PERFSEL0_PERFSEL0_sram4 = 7, /*!< sram4 : sram4 */
BUSCTRL_PERFSEL0_PERFSEL0_sram3_contested = 8,/*!< sram3_contested : sram3_contested */
BUSCTRL_PERFSEL0_PERFSEL0_sram3 = 9, /*!< sram3 : sram3 */
BUSCTRL_PERFSEL0_PERFSEL0_sram2_contested = 10,/*!< sram2_contested : sram2_contested */
BUSCTRL_PERFSEL0_PERFSEL0_sram2 = 11, /*!< sram2 : sram2 */
BUSCTRL_PERFSEL0_PERFSEL0_sram1_contested = 12,/*!< sram1_contested : sram1_contested */
BUSCTRL_PERFSEL0_PERFSEL0_sram1 = 13, /*!< sram1 : sram1 */
BUSCTRL_PERFSEL0_PERFSEL0_sram0_contested = 14,/*!< sram0_contested : sram0_contested */
BUSCTRL_PERFSEL0_PERFSEL0_sram0 = 15, /*!< sram0 : sram0 */
BUSCTRL_PERFSEL0_PERFSEL0_xip_main_contested = 16,/*!< xip_main_contested : xip_main_contested */
BUSCTRL_PERFSEL0_PERFSEL0_xip_main = 17, /*!< xip_main : xip_main */
BUSCTRL_PERFSEL0_PERFSEL0_rom_contested = 18, /*!< rom_contested : rom_contested */
BUSCTRL_PERFSEL0_PERFSEL0_rom = 19, /*!< rom : rom */
} BUSCTRL_PERFSEL0_PERFSEL0_Enum;
/* ======================================================= PERFCTR1 ======================================================== */
/* ======================================================= PERFSEL1 ======================================================== */
/* =========================================== BUSCTRL PERFSEL1 PERFSEL1 [0..4] ============================================ */
typedef enum { /*!< BUSCTRL_PERFSEL1_PERFSEL1 */
BUSCTRL_PERFSEL1_PERFSEL1_apb_contested = 0, /*!< apb_contested : apb_contested */
BUSCTRL_PERFSEL1_PERFSEL1_apb = 1, /*!< apb : apb */
BUSCTRL_PERFSEL1_PERFSEL1_fastperi_contested = 2,/*!< fastperi_contested : fastperi_contested */
BUSCTRL_PERFSEL1_PERFSEL1_fastperi = 3, /*!< fastperi : fastperi */
BUSCTRL_PERFSEL1_PERFSEL1_sram5_contested = 4,/*!< sram5_contested : sram5_contested */
BUSCTRL_PERFSEL1_PERFSEL1_sram5 = 5, /*!< sram5 : sram5 */
BUSCTRL_PERFSEL1_PERFSEL1_sram4_contested = 6,/*!< sram4_contested : sram4_contested */
BUSCTRL_PERFSEL1_PERFSEL1_sram4 = 7, /*!< sram4 : sram4 */
BUSCTRL_PERFSEL1_PERFSEL1_sram3_contested = 8,/*!< sram3_contested : sram3_contested */
BUSCTRL_PERFSEL1_PERFSEL1_sram3 = 9, /*!< sram3 : sram3 */
BUSCTRL_PERFSEL1_PERFSEL1_sram2_contested = 10,/*!< sram2_contested : sram2_contested */
BUSCTRL_PERFSEL1_PERFSEL1_sram2 = 11, /*!< sram2 : sram2 */
BUSCTRL_PERFSEL1_PERFSEL1_sram1_contested = 12,/*!< sram1_contested : sram1_contested */
BUSCTRL_PERFSEL1_PERFSEL1_sram1 = 13, /*!< sram1 : sram1 */
BUSCTRL_PERFSEL1_PERFSEL1_sram0_contested = 14,/*!< sram0_contested : sram0_contested */
BUSCTRL_PERFSEL1_PERFSEL1_sram0 = 15, /*!< sram0 : sram0 */
BUSCTRL_PERFSEL1_PERFSEL1_xip_main_contested = 16,/*!< xip_main_contested : xip_main_contested */
BUSCTRL_PERFSEL1_PERFSEL1_xip_main = 17, /*!< xip_main : xip_main */
BUSCTRL_PERFSEL1_PERFSEL1_rom_contested = 18, /*!< rom_contested : rom_contested */
BUSCTRL_PERFSEL1_PERFSEL1_rom = 19, /*!< rom : rom */
} BUSCTRL_PERFSEL1_PERFSEL1_Enum;
/* ======================================================= PERFCTR2 ======================================================== */
/* ======================================================= PERFSEL2 ======================================================== */
/* =========================================== BUSCTRL PERFSEL2 PERFSEL2 [0..4] ============================================ */
typedef enum { /*!< BUSCTRL_PERFSEL2_PERFSEL2 */
BUSCTRL_PERFSEL2_PERFSEL2_apb_contested = 0, /*!< apb_contested : apb_contested */
BUSCTRL_PERFSEL2_PERFSEL2_apb = 1, /*!< apb : apb */
BUSCTRL_PERFSEL2_PERFSEL2_fastperi_contested = 2,/*!< fastperi_contested : fastperi_contested */
BUSCTRL_PERFSEL2_PERFSEL2_fastperi = 3, /*!< fastperi : fastperi */
BUSCTRL_PERFSEL2_PERFSEL2_sram5_contested = 4,/*!< sram5_contested : sram5_contested */
BUSCTRL_PERFSEL2_PERFSEL2_sram5 = 5, /*!< sram5 : sram5 */
BUSCTRL_PERFSEL2_PERFSEL2_sram4_contested = 6,/*!< sram4_contested : sram4_contested */
BUSCTRL_PERFSEL2_PERFSEL2_sram4 = 7, /*!< sram4 : sram4 */
BUSCTRL_PERFSEL2_PERFSEL2_sram3_contested = 8,/*!< sram3_contested : sram3_contested */
BUSCTRL_PERFSEL2_PERFSEL2_sram3 = 9, /*!< sram3 : sram3 */
BUSCTRL_PERFSEL2_PERFSEL2_sram2_contested = 10,/*!< sram2_contested : sram2_contested */
BUSCTRL_PERFSEL2_PERFSEL2_sram2 = 11, /*!< sram2 : sram2 */
BUSCTRL_PERFSEL2_PERFSEL2_sram1_contested = 12,/*!< sram1_contested : sram1_contested */
BUSCTRL_PERFSEL2_PERFSEL2_sram1 = 13, /*!< sram1 : sram1 */
BUSCTRL_PERFSEL2_PERFSEL2_sram0_contested = 14,/*!< sram0_contested : sram0_contested */
BUSCTRL_PERFSEL2_PERFSEL2_sram0 = 15, /*!< sram0 : sram0 */
BUSCTRL_PERFSEL2_PERFSEL2_xip_main_contested = 16,/*!< xip_main_contested : xip_main_contested */
BUSCTRL_PERFSEL2_PERFSEL2_xip_main = 17, /*!< xip_main : xip_main */
BUSCTRL_PERFSEL2_PERFSEL2_rom_contested = 18, /*!< rom_contested : rom_contested */
BUSCTRL_PERFSEL2_PERFSEL2_rom = 19, /*!< rom : rom */
} BUSCTRL_PERFSEL2_PERFSEL2_Enum;
/* ======================================================= PERFCTR3 ======================================================== */
/* ======================================================= PERFSEL3 ======================================================== */
/* =========================================== BUSCTRL PERFSEL3 PERFSEL3 [0..4] ============================================ */
typedef enum { /*!< BUSCTRL_PERFSEL3_PERFSEL3 */
BUSCTRL_PERFSEL3_PERFSEL3_apb_contested = 0, /*!< apb_contested : apb_contested */
BUSCTRL_PERFSEL3_PERFSEL3_apb = 1, /*!< apb : apb */
BUSCTRL_PERFSEL3_PERFSEL3_fastperi_contested = 2,/*!< fastperi_contested : fastperi_contested */
BUSCTRL_PERFSEL3_PERFSEL3_fastperi = 3, /*!< fastperi : fastperi */
BUSCTRL_PERFSEL3_PERFSEL3_sram5_contested = 4,/*!< sram5_contested : sram5_contested */
BUSCTRL_PERFSEL3_PERFSEL3_sram5 = 5, /*!< sram5 : sram5 */
BUSCTRL_PERFSEL3_PERFSEL3_sram4_contested = 6,/*!< sram4_contested : sram4_contested */
BUSCTRL_PERFSEL3_PERFSEL3_sram4 = 7, /*!< sram4 : sram4 */
BUSCTRL_PERFSEL3_PERFSEL3_sram3_contested = 8,/*!< sram3_contested : sram3_contested */
BUSCTRL_PERFSEL3_PERFSEL3_sram3 = 9, /*!< sram3 : sram3 */
BUSCTRL_PERFSEL3_PERFSEL3_sram2_contested = 10,/*!< sram2_contested : sram2_contested */
BUSCTRL_PERFSEL3_PERFSEL3_sram2 = 11, /*!< sram2 : sram2 */
BUSCTRL_PERFSEL3_PERFSEL3_sram1_contested = 12,/*!< sram1_contested : sram1_contested */
BUSCTRL_PERFSEL3_PERFSEL3_sram1 = 13, /*!< sram1 : sram1 */
BUSCTRL_PERFSEL3_PERFSEL3_sram0_contested = 14,/*!< sram0_contested : sram0_contested */
BUSCTRL_PERFSEL3_PERFSEL3_sram0 = 15, /*!< sram0 : sram0 */
BUSCTRL_PERFSEL3_PERFSEL3_xip_main_contested = 16,/*!< xip_main_contested : xip_main_contested */
BUSCTRL_PERFSEL3_PERFSEL3_xip_main = 17, /*!< xip_main : xip_main */
BUSCTRL_PERFSEL3_PERFSEL3_rom_contested = 18, /*!< rom_contested : rom_contested */
BUSCTRL_PERFSEL3_PERFSEL3_rom = 19, /*!< rom : rom */
} BUSCTRL_PERFSEL3_PERFSEL3_Enum;
/* =========================================================================================================================== */
/* ================ UART0 ================ */
/* =========================================================================================================================== */
/* ======================================================== UARTDR ========================================================= */
/* ======================================================== UARTRSR ======================================================== */
/* ======================================================== UARTFR ========================================================= */
/* ======================================================= UARTILPR ======================================================== */
/* ======================================================= UARTIBRD ======================================================== */
/* ======================================================= UARTFBRD ======================================================== */
/* ======================================================= UARTLCR_H ======================================================= */
/* ======================================================== UARTCR ========================================================= */
/* ======================================================= UARTIFLS ======================================================== */
/* ======================================================= UARTIMSC ======================================================== */
/* ======================================================== UARTRIS ======================================================== */
/* ======================================================== UARTMIS ======================================================== */
/* ======================================================== UARTICR ======================================================== */
/* ======================================================= UARTDMACR ======================================================= */
/* ===================================================== UARTPERIPHID0 ===================================================== */
/* ===================================================== UARTPERIPHID1 ===================================================== */
/* ===================================================== UARTPERIPHID2 ===================================================== */
/* ===================================================== UARTPERIPHID3 ===================================================== */
/* ===================================================== UARTPCELLID0 ====================================================== */
/* ===================================================== UARTPCELLID1 ====================================================== */
/* ===================================================== UARTPCELLID2 ====================================================== */
/* ===================================================== UARTPCELLID3 ====================================================== */
/* =========================================================================================================================== */
/* ================ SPI0 ================ */
/* =========================================================================================================================== */
/* ======================================================== SSPCR0 ========================================================= */
/* ======================================================== SSPCR1 ========================================================= */
/* ========================================================= SSPDR ========================================================= */
/* ========================================================= SSPSR ========================================================= */
/* ======================================================== SSPCPSR ======================================================== */
/* ======================================================== SSPIMSC ======================================================== */
/* ======================================================== SSPRIS ========================================================= */
/* ======================================================== SSPMIS ========================================================= */
/* ======================================================== SSPICR ========================================================= */
/* ======================================================= SSPDMACR ======================================================== */
/* ===================================================== SSPPERIPHID0 ====================================================== */
/* ===================================================== SSPPERIPHID1 ====================================================== */
/* ===================================================== SSPPERIPHID2 ====================================================== */
/* ===================================================== SSPPERIPHID3 ====================================================== */
/* ====================================================== SSPPCELLID0 ====================================================== */
/* ====================================================== SSPPCELLID1 ====================================================== */
/* ====================================================== SSPPCELLID2 ====================================================== */
/* ====================================================== SSPPCELLID3 ====================================================== */
/* =========================================================================================================================== */
/* ================ I2C0 ================ */
/* =========================================================================================================================== */
/* ======================================================== IC_CON ========================================================= */
/* ======================================= I2C0 IC_CON RX_FIFO_FULL_HLD_CTRL [9..9] ======================================== */
typedef enum { /*!< I2C0_IC_CON_RX_FIFO_FULL_HLD_CTRL */
I2C0_IC_CON_RX_FIFO_FULL_HLD_CTRL_DISABLED = 0,/*!< DISABLED : Overflow when RX_FIFO is full */
I2C0_IC_CON_RX_FIFO_FULL_HLD_CTRL_ENABLED = 1,/*!< ENABLED : Hold bus when RX_FIFO is full */
} I2C0_IC_CON_RX_FIFO_FULL_HLD_CTRL_Enum;
/* =========================================== I2C0 IC_CON TX_EMPTY_CTRL [8..8] ============================================ */
typedef enum { /*!< I2C0_IC_CON_TX_EMPTY_CTRL */
I2C0_IC_CON_TX_EMPTY_CTRL_DISABLED = 0, /*!< DISABLED : Default behaviour of TX_EMPTY interrupt */
I2C0_IC_CON_TX_EMPTY_CTRL_ENABLED = 1, /*!< ENABLED : Controlled generation of TX_EMPTY interrupt */
} I2C0_IC_CON_TX_EMPTY_CTRL_Enum;
/* ======================================== I2C0 IC_CON STOP_DET_IFADDRESSED [7..7] ======================================== */
typedef enum { /*!< I2C0_IC_CON_STOP_DET_IFADDRESSED */
I2C0_IC_CON_STOP_DET_IFADDRESSED_DISABLED = 0,/*!< DISABLED : slave issues STOP_DET intr always */
I2C0_IC_CON_STOP_DET_IFADDRESSED_ENABLED = 1, /*!< ENABLED : slave issues STOP_DET intr only if addressed */
} I2C0_IC_CON_STOP_DET_IFADDRESSED_Enum;
/* ========================================== I2C0 IC_CON IC_SLAVE_DISABLE [6..6] ========================================== */
typedef enum { /*!< I2C0_IC_CON_IC_SLAVE_DISABLE */
I2C0_IC_CON_IC_SLAVE_DISABLE_SLAVE_ENABLED = 0,/*!< SLAVE_ENABLED : Slave mode is enabled */
I2C0_IC_CON_IC_SLAVE_DISABLE_SLAVE_DISABLED = 1,/*!< SLAVE_DISABLED : Slave mode is disabled */
} I2C0_IC_CON_IC_SLAVE_DISABLE_Enum;
/* =========================================== I2C0 IC_CON IC_RESTART_EN [5..5] ============================================ */
typedef enum { /*!< I2C0_IC_CON_IC_RESTART_EN */
I2C0_IC_CON_IC_RESTART_EN_DISABLED = 0, /*!< DISABLED : Master restart disabled */
I2C0_IC_CON_IC_RESTART_EN_ENABLED = 1, /*!< ENABLED : Master restart enabled */
} I2C0_IC_CON_IC_RESTART_EN_Enum;
/* ======================================== I2C0 IC_CON IC_10BITADDR_MASTER [4..4] ========================================= */
typedef enum { /*!< I2C0_IC_CON_IC_10BITADDR_MASTER */
I2C0_IC_CON_IC_10BITADDR_MASTER_ADDR_7BITS = 0,/*!< ADDR_7BITS : Master 7Bit addressing mode */
I2C0_IC_CON_IC_10BITADDR_MASTER_ADDR_10BITS = 1,/*!< ADDR_10BITS : Master 10Bit addressing mode */
} I2C0_IC_CON_IC_10BITADDR_MASTER_Enum;
/* ========================================= I2C0 IC_CON IC_10BITADDR_SLAVE [3..3] ========================================= */
typedef enum { /*!< I2C0_IC_CON_IC_10BITADDR_SLAVE */
I2C0_IC_CON_IC_10BITADDR_SLAVE_ADDR_7BITS = 0,/*!< ADDR_7BITS : Slave 7Bit addressing */
I2C0_IC_CON_IC_10BITADDR_SLAVE_ADDR_10BITS = 1,/*!< ADDR_10BITS : Slave 10Bit addressing */
} I2C0_IC_CON_IC_10BITADDR_SLAVE_Enum;
/* =============================================== I2C0 IC_CON SPEED [1..2] ================================================ */
typedef enum { /*!< I2C0_IC_CON_SPEED */
I2C0_IC_CON_SPEED_STANDARD = 1, /*!< STANDARD : Standard Speed mode of operation */
I2C0_IC_CON_SPEED_FAST = 2, /*!< FAST : Fast or Fast Plus mode of operation */
I2C0_IC_CON_SPEED_HIGH = 3, /*!< HIGH : High Speed mode of operation */
} I2C0_IC_CON_SPEED_Enum;
/* ============================================ I2C0 IC_CON MASTER_MODE [0..0] ============================================= */
typedef enum { /*!< I2C0_IC_CON_MASTER_MODE */
I2C0_IC_CON_MASTER_MODE_DISABLED = 0, /*!< DISABLED : Master mode is disabled */
I2C0_IC_CON_MASTER_MODE_ENABLED = 1, /*!< ENABLED : Master mode is enabled */
} I2C0_IC_CON_MASTER_MODE_Enum;
/* ======================================================== IC_TAR ========================================================= */
/* ============================================= I2C0 IC_TAR SPECIAL [11..11] ============================================== */
typedef enum { /*!< I2C0_IC_TAR_SPECIAL */
I2C0_IC_TAR_SPECIAL_DISABLED = 0, /*!< DISABLED : Disables programming of GENERAL_CALL or START_BYTE
transmission */
I2C0_IC_TAR_SPECIAL_ENABLED = 1, /*!< ENABLED : Enables programming of GENERAL_CALL or START_BYTE
transmission */
} I2C0_IC_TAR_SPECIAL_Enum;
/* =========================================== I2C0 IC_TAR GC_OR_START [10..10] ============================================ */
typedef enum { /*!< I2C0_IC_TAR_GC_OR_START */
I2C0_IC_TAR_GC_OR_START_GENERAL_CALL = 0, /*!< GENERAL_CALL : GENERAL_CALL byte transmission */
I2C0_IC_TAR_GC_OR_START_START_BYTE = 1, /*!< START_BYTE : START byte transmission */
} I2C0_IC_TAR_GC_OR_START_Enum;
/* ======================================================== IC_SAR ========================================================= */
/* ====================================================== IC_DATA_CMD ====================================================== */
/* ======================================= I2C0 IC_DATA_CMD FIRST_DATA_BYTE [11..11] ======================================= */
typedef enum { /*!< I2C0_IC_DATA_CMD_FIRST_DATA_BYTE */
I2C0_IC_DATA_CMD_FIRST_DATA_BYTE_INACTIVE = 0,/*!< INACTIVE : Sequential data byte received */
I2C0_IC_DATA_CMD_FIRST_DATA_BYTE_ACTIVE = 1, /*!< ACTIVE : Non sequential data byte received */
} I2C0_IC_DATA_CMD_FIRST_DATA_BYTE_Enum;
/* =========================================== I2C0 IC_DATA_CMD RESTART [10..10] =========================================== */
typedef enum { /*!< I2C0_IC_DATA_CMD_RESTART */
I2C0_IC_DATA_CMD_RESTART_DISABLE = 0, /*!< DISABLE : Don't Issue RESTART before this command */
I2C0_IC_DATA_CMD_RESTART_ENABLE = 1, /*!< ENABLE : Issue RESTART before this command */
} I2C0_IC_DATA_CMD_RESTART_Enum;
/* ============================================= I2C0 IC_DATA_CMD STOP [9..9] ============================================== */
typedef enum { /*!< I2C0_IC_DATA_CMD_STOP */
I2C0_IC_DATA_CMD_STOP_DISABLE = 0, /*!< DISABLE : Don't Issue STOP after this command */
I2C0_IC_DATA_CMD_STOP_ENABLE = 1, /*!< ENABLE : Issue STOP after this command */
} I2C0_IC_DATA_CMD_STOP_Enum;
/* ============================================== I2C0 IC_DATA_CMD CMD [8..8] ============================================== */
typedef enum { /*!< I2C0_IC_DATA_CMD_CMD */
I2C0_IC_DATA_CMD_CMD_WRITE = 0, /*!< WRITE : Master Write Command */
I2C0_IC_DATA_CMD_CMD_READ = 1, /*!< READ : Master Read Command */
} I2C0_IC_DATA_CMD_CMD_Enum;
/* ==================================================== IC_SS_SCL_HCNT ===================================================== */
/* ==================================================== IC_SS_SCL_LCNT ===================================================== */
/* ==================================================== IC_FS_SCL_HCNT ===================================================== */
/* ==================================================== IC_FS_SCL_LCNT ===================================================== */
/* ===================================================== IC_INTR_STAT ====================================================== */
/* ======================================= I2C0 IC_INTR_STAT R_RESTART_DET [12..12] ======================================== */
typedef enum { /*!< I2C0_IC_INTR_STAT_R_RESTART_DET */
I2C0_IC_INTR_STAT_R_RESTART_DET_INACTIVE = 0, /*!< INACTIVE : R_RESTART_DET interrupt is inactive */
I2C0_IC_INTR_STAT_R_RESTART_DET_ACTIVE = 1, /*!< ACTIVE : R_RESTART_DET interrupt is active */
} I2C0_IC_INTR_STAT_R_RESTART_DET_Enum;
/* ========================================= I2C0 IC_INTR_STAT R_GEN_CALL [11..11] ========================================= */
typedef enum { /*!< I2C0_IC_INTR_STAT_R_GEN_CALL */
I2C0_IC_INTR_STAT_R_GEN_CALL_INACTIVE = 0, /*!< INACTIVE : R_GEN_CALL interrupt is inactive */
I2C0_IC_INTR_STAT_R_GEN_CALL_ACTIVE = 1, /*!< ACTIVE : R_GEN_CALL interrupt is active */
} I2C0_IC_INTR_STAT_R_GEN_CALL_Enum;
/* ======================================== I2C0 IC_INTR_STAT R_START_DET [10..10] ========================================= */
typedef enum { /*!< I2C0_IC_INTR_STAT_R_START_DET */
I2C0_IC_INTR_STAT_R_START_DET_INACTIVE = 0, /*!< INACTIVE : R_START_DET interrupt is inactive */
I2C0_IC_INTR_STAT_R_START_DET_ACTIVE = 1, /*!< ACTIVE : R_START_DET interrupt is active */
} I2C0_IC_INTR_STAT_R_START_DET_Enum;
/* ========================================== I2C0 IC_INTR_STAT R_STOP_DET [9..9] ========================================== */
typedef enum { /*!< I2C0_IC_INTR_STAT_R_STOP_DET */
I2C0_IC_INTR_STAT_R_STOP_DET_INACTIVE = 0, /*!< INACTIVE : R_STOP_DET interrupt is inactive */
I2C0_IC_INTR_STAT_R_STOP_DET_ACTIVE = 1, /*!< ACTIVE : R_STOP_DET interrupt is active */
} I2C0_IC_INTR_STAT_R_STOP_DET_Enum;
/* ========================================== I2C0 IC_INTR_STAT R_ACTIVITY [8..8] ========================================== */
typedef enum { /*!< I2C0_IC_INTR_STAT_R_ACTIVITY */
I2C0_IC_INTR_STAT_R_ACTIVITY_INACTIVE = 0, /*!< INACTIVE : R_ACTIVITY interrupt is inactive */
I2C0_IC_INTR_STAT_R_ACTIVITY_ACTIVE = 1, /*!< ACTIVE : R_ACTIVITY interrupt is active */
} I2C0_IC_INTR_STAT_R_ACTIVITY_Enum;
/* ========================================== I2C0 IC_INTR_STAT R_RX_DONE [7..7] =========================================== */
typedef enum { /*!< I2C0_IC_INTR_STAT_R_RX_DONE */
I2C0_IC_INTR_STAT_R_RX_DONE_INACTIVE = 0, /*!< INACTIVE : R_RX_DONE interrupt is inactive */
I2C0_IC_INTR_STAT_R_RX_DONE_ACTIVE = 1, /*!< ACTIVE : R_RX_DONE interrupt is active */
} I2C0_IC_INTR_STAT_R_RX_DONE_Enum;
/* ========================================== I2C0 IC_INTR_STAT R_TX_ABRT [6..6] =========================================== */
typedef enum { /*!< I2C0_IC_INTR_STAT_R_TX_ABRT */
I2C0_IC_INTR_STAT_R_TX_ABRT_INACTIVE = 0, /*!< INACTIVE : R_TX_ABRT interrupt is inactive */
I2C0_IC_INTR_STAT_R_TX_ABRT_ACTIVE = 1, /*!< ACTIVE : R_TX_ABRT interrupt is active */
} I2C0_IC_INTR_STAT_R_TX_ABRT_Enum;
/* =========================================== I2C0 IC_INTR_STAT R_RD_REQ [5..5] =========================================== */
typedef enum { /*!< I2C0_IC_INTR_STAT_R_RD_REQ */
I2C0_IC_INTR_STAT_R_RD_REQ_INACTIVE = 0, /*!< INACTIVE : R_RD_REQ interrupt is inactive */
I2C0_IC_INTR_STAT_R_RD_REQ_ACTIVE = 1, /*!< ACTIVE : R_RD_REQ interrupt is active */
} I2C0_IC_INTR_STAT_R_RD_REQ_Enum;
/* ========================================== I2C0 IC_INTR_STAT R_TX_EMPTY [4..4] ========================================== */
typedef enum { /*!< I2C0_IC_INTR_STAT_R_TX_EMPTY */
I2C0_IC_INTR_STAT_R_TX_EMPTY_INACTIVE = 0, /*!< INACTIVE : R_TX_EMPTY interrupt is inactive */
I2C0_IC_INTR_STAT_R_TX_EMPTY_ACTIVE = 1, /*!< ACTIVE : R_TX_EMPTY interrupt is active */
} I2C0_IC_INTR_STAT_R_TX_EMPTY_Enum;
/* ========================================== I2C0 IC_INTR_STAT R_TX_OVER [3..3] =========================================== */
typedef enum { /*!< I2C0_IC_INTR_STAT_R_TX_OVER */
I2C0_IC_INTR_STAT_R_TX_OVER_INACTIVE = 0, /*!< INACTIVE : R_TX_OVER interrupt is inactive */
I2C0_IC_INTR_STAT_R_TX_OVER_ACTIVE = 1, /*!< ACTIVE : R_TX_OVER interrupt is active */
} I2C0_IC_INTR_STAT_R_TX_OVER_Enum;
/* ========================================== I2C0 IC_INTR_STAT R_RX_FULL [2..2] =========================================== */
typedef enum { /*!< I2C0_IC_INTR_STAT_R_RX_FULL */
I2C0_IC_INTR_STAT_R_RX_FULL_INACTIVE = 0, /*!< INACTIVE : R_RX_FULL interrupt is inactive */
I2C0_IC_INTR_STAT_R_RX_FULL_ACTIVE = 1, /*!< ACTIVE : R_RX_FULL interrupt is active */
} I2C0_IC_INTR_STAT_R_RX_FULL_Enum;
/* ========================================== I2C0 IC_INTR_STAT R_RX_OVER [1..1] =========================================== */
typedef enum { /*!< I2C0_IC_INTR_STAT_R_RX_OVER */
I2C0_IC_INTR_STAT_R_RX_OVER_INACTIVE = 0, /*!< INACTIVE : R_RX_OVER interrupt is inactive */
I2C0_IC_INTR_STAT_R_RX_OVER_ACTIVE = 1, /*!< ACTIVE : R_RX_OVER interrupt is active */
} I2C0_IC_INTR_STAT_R_RX_OVER_Enum;
/* ========================================== I2C0 IC_INTR_STAT R_RX_UNDER [0..0] ========================================== */
typedef enum { /*!< I2C0_IC_INTR_STAT_R_RX_UNDER */
I2C0_IC_INTR_STAT_R_RX_UNDER_INACTIVE = 0, /*!< INACTIVE : RX_UNDER interrupt is inactive */
I2C0_IC_INTR_STAT_R_RX_UNDER_ACTIVE = 1, /*!< ACTIVE : RX_UNDER interrupt is active */
} I2C0_IC_INTR_STAT_R_RX_UNDER_Enum;
/* ===================================================== IC_INTR_MASK ====================================================== */
/* ======================================= I2C0 IC_INTR_MASK M_RESTART_DET [12..12] ======================================== */
typedef enum { /*!< I2C0_IC_INTR_MASK_M_RESTART_DET */
I2C0_IC_INTR_MASK_M_RESTART_DET_ENABLED = 0, /*!< ENABLED : RESTART_DET interrupt is masked */
I2C0_IC_INTR_MASK_M_RESTART_DET_DISABLED = 1, /*!< DISABLED : RESTART_DET interrupt is unmasked */
} I2C0_IC_INTR_MASK_M_RESTART_DET_Enum;
/* ========================================= I2C0 IC_INTR_MASK M_GEN_CALL [11..11] ========================================= */
typedef enum { /*!< I2C0_IC_INTR_MASK_M_GEN_CALL */
I2C0_IC_INTR_MASK_M_GEN_CALL_ENABLED = 0, /*!< ENABLED : GEN_CALL interrupt is masked */
I2C0_IC_INTR_MASK_M_GEN_CALL_DISABLED = 1, /*!< DISABLED : GEN_CALL interrupt is unmasked */
} I2C0_IC_INTR_MASK_M_GEN_CALL_Enum;
/* ======================================== I2C0 IC_INTR_MASK M_START_DET [10..10] ========================================= */
typedef enum { /*!< I2C0_IC_INTR_MASK_M_START_DET */
I2C0_IC_INTR_MASK_M_START_DET_ENABLED = 0, /*!< ENABLED : START_DET interrupt is masked */
I2C0_IC_INTR_MASK_M_START_DET_DISABLED = 1, /*!< DISABLED : START_DET interrupt is unmasked */
} I2C0_IC_INTR_MASK_M_START_DET_Enum;
/* ========================================== I2C0 IC_INTR_MASK M_STOP_DET [9..9] ========================================== */
typedef enum { /*!< I2C0_IC_INTR_MASK_M_STOP_DET */
I2C0_IC_INTR_MASK_M_STOP_DET_ENABLED = 0, /*!< ENABLED : STOP_DET interrupt is masked */
I2C0_IC_INTR_MASK_M_STOP_DET_DISABLED = 1, /*!< DISABLED : STOP_DET interrupt is unmasked */
} I2C0_IC_INTR_MASK_M_STOP_DET_Enum;
/* ========================================== I2C0 IC_INTR_MASK M_ACTIVITY [8..8] ========================================== */
typedef enum { /*!< I2C0_IC_INTR_MASK_M_ACTIVITY */
I2C0_IC_INTR_MASK_M_ACTIVITY_ENABLED = 0, /*!< ENABLED : ACTIVITY interrupt is masked */
I2C0_IC_INTR_MASK_M_ACTIVITY_DISABLED = 1, /*!< DISABLED : ACTIVITY interrupt is unmasked */
} I2C0_IC_INTR_MASK_M_ACTIVITY_Enum;
/* ========================================== I2C0 IC_INTR_MASK M_RX_DONE [7..7] =========================================== */
typedef enum { /*!< I2C0_IC_INTR_MASK_M_RX_DONE */
I2C0_IC_INTR_MASK_M_RX_DONE_ENABLED = 0, /*!< ENABLED : RX_DONE interrupt is masked */
I2C0_IC_INTR_MASK_M_RX_DONE_DISABLED = 1, /*!< DISABLED : RX_DONE interrupt is unmasked */
} I2C0_IC_INTR_MASK_M_RX_DONE_Enum;
/* ========================================== I2C0 IC_INTR_MASK M_TX_ABRT [6..6] =========================================== */
typedef enum { /*!< I2C0_IC_INTR_MASK_M_TX_ABRT */
I2C0_IC_INTR_MASK_M_TX_ABRT_ENABLED = 0, /*!< ENABLED : TX_ABORT interrupt is masked */
I2C0_IC_INTR_MASK_M_TX_ABRT_DISABLED = 1, /*!< DISABLED : TX_ABORT interrupt is unmasked */
} I2C0_IC_INTR_MASK_M_TX_ABRT_Enum;
/* =========================================== I2C0 IC_INTR_MASK M_RD_REQ [5..5] =========================================== */
typedef enum { /*!< I2C0_IC_INTR_MASK_M_RD_REQ */
I2C0_IC_INTR_MASK_M_RD_REQ_ENABLED = 0, /*!< ENABLED : RD_REQ interrupt is masked */
I2C0_IC_INTR_MASK_M_RD_REQ_DISABLED = 1, /*!< DISABLED : RD_REQ interrupt is unmasked */
} I2C0_IC_INTR_MASK_M_RD_REQ_Enum;
/* ========================================== I2C0 IC_INTR_MASK M_TX_EMPTY [4..4] ========================================== */
typedef enum { /*!< I2C0_IC_INTR_MASK_M_TX_EMPTY */
I2C0_IC_INTR_MASK_M_TX_EMPTY_ENABLED = 0, /*!< ENABLED : TX_EMPTY interrupt is masked */
I2C0_IC_INTR_MASK_M_TX_EMPTY_DISABLED = 1, /*!< DISABLED : TX_EMPTY interrupt is unmasked */
} I2C0_IC_INTR_MASK_M_TX_EMPTY_Enum;
/* ========================================== I2C0 IC_INTR_MASK M_TX_OVER [3..3] =========================================== */
typedef enum { /*!< I2C0_IC_INTR_MASK_M_TX_OVER */
I2C0_IC_INTR_MASK_M_TX_OVER_ENABLED = 0, /*!< ENABLED : TX_OVER interrupt is masked */
I2C0_IC_INTR_MASK_M_TX_OVER_DISABLED = 1, /*!< DISABLED : TX_OVER interrupt is unmasked */
} I2C0_IC_INTR_MASK_M_TX_OVER_Enum;
/* ========================================== I2C0 IC_INTR_MASK M_RX_FULL [2..2] =========================================== */
typedef enum { /*!< I2C0_IC_INTR_MASK_M_RX_FULL */
I2C0_IC_INTR_MASK_M_RX_FULL_ENABLED = 0, /*!< ENABLED : RX_FULL interrupt is masked */
I2C0_IC_INTR_MASK_M_RX_FULL_DISABLED = 1, /*!< DISABLED : RX_FULL interrupt is unmasked */
} I2C0_IC_INTR_MASK_M_RX_FULL_Enum;
/* ========================================== I2C0 IC_INTR_MASK M_RX_OVER [1..1] =========================================== */
typedef enum { /*!< I2C0_IC_INTR_MASK_M_RX_OVER */
I2C0_IC_INTR_MASK_M_RX_OVER_ENABLED = 0, /*!< ENABLED : RX_OVER interrupt is masked */
I2C0_IC_INTR_MASK_M_RX_OVER_DISABLED = 1, /*!< DISABLED : RX_OVER interrupt is unmasked */
} I2C0_IC_INTR_MASK_M_RX_OVER_Enum;
/* ========================================== I2C0 IC_INTR_MASK M_RX_UNDER [0..0] ========================================== */
typedef enum { /*!< I2C0_IC_INTR_MASK_M_RX_UNDER */
I2C0_IC_INTR_MASK_M_RX_UNDER_ENABLED = 0, /*!< ENABLED : RX_UNDER interrupt is masked */
I2C0_IC_INTR_MASK_M_RX_UNDER_DISABLED = 1, /*!< DISABLED : RX_UNDER interrupt is unmasked */
} I2C0_IC_INTR_MASK_M_RX_UNDER_Enum;
/* =================================================== IC_RAW_INTR_STAT ==================================================== */
/* ====================================== I2C0 IC_RAW_INTR_STAT RESTART_DET [12..12] ======================================= */
typedef enum { /*!< I2C0_IC_RAW_INTR_STAT_RESTART_DET */
I2C0_IC_RAW_INTR_STAT_RESTART_DET_INACTIVE = 0,/*!< INACTIVE : RESTART_DET interrupt is inactive */
I2C0_IC_RAW_INTR_STAT_RESTART_DET_ACTIVE = 1, /*!< ACTIVE : RESTART_DET interrupt is active */
} I2C0_IC_RAW_INTR_STAT_RESTART_DET_Enum;
/* ======================================== I2C0 IC_RAW_INTR_STAT GEN_CALL [11..11] ======================================== */
typedef enum { /*!< I2C0_IC_RAW_INTR_STAT_GEN_CALL */
I2C0_IC_RAW_INTR_STAT_GEN_CALL_INACTIVE = 0, /*!< INACTIVE : GEN_CALL interrupt is inactive */
I2C0_IC_RAW_INTR_STAT_GEN_CALL_ACTIVE = 1, /*!< ACTIVE : GEN_CALL interrupt is active */
} I2C0_IC_RAW_INTR_STAT_GEN_CALL_Enum;
/* ======================================= I2C0 IC_RAW_INTR_STAT START_DET [10..10] ======================================== */
typedef enum { /*!< I2C0_IC_RAW_INTR_STAT_START_DET */
I2C0_IC_RAW_INTR_STAT_START_DET_INACTIVE = 0, /*!< INACTIVE : START_DET interrupt is inactive */
I2C0_IC_RAW_INTR_STAT_START_DET_ACTIVE = 1, /*!< ACTIVE : START_DET interrupt is active */
} I2C0_IC_RAW_INTR_STAT_START_DET_Enum;
/* ========================================= I2C0 IC_RAW_INTR_STAT STOP_DET [9..9] ========================================= */
typedef enum { /*!< I2C0_IC_RAW_INTR_STAT_STOP_DET */
I2C0_IC_RAW_INTR_STAT_STOP_DET_INACTIVE = 0, /*!< INACTIVE : STOP_DET interrupt is inactive */
I2C0_IC_RAW_INTR_STAT_STOP_DET_ACTIVE = 1, /*!< ACTIVE : STOP_DET interrupt is active */
} I2C0_IC_RAW_INTR_STAT_STOP_DET_Enum;
/* ========================================= I2C0 IC_RAW_INTR_STAT ACTIVITY [8..8] ========================================= */
typedef enum { /*!< I2C0_IC_RAW_INTR_STAT_ACTIVITY */
I2C0_IC_RAW_INTR_STAT_ACTIVITY_INACTIVE = 0, /*!< INACTIVE : RAW_INTR_ACTIVITY interrupt is inactive */
I2C0_IC_RAW_INTR_STAT_ACTIVITY_ACTIVE = 1, /*!< ACTIVE : RAW_INTR_ACTIVITY interrupt is active */
} I2C0_IC_RAW_INTR_STAT_ACTIVITY_Enum;
/* ========================================= I2C0 IC_RAW_INTR_STAT RX_DONE [7..7] ========================================== */
typedef enum { /*!< I2C0_IC_RAW_INTR_STAT_RX_DONE */
I2C0_IC_RAW_INTR_STAT_RX_DONE_INACTIVE = 0, /*!< INACTIVE : RX_DONE interrupt is inactive */
I2C0_IC_RAW_INTR_STAT_RX_DONE_ACTIVE = 1, /*!< ACTIVE : RX_DONE interrupt is active */
} I2C0_IC_RAW_INTR_STAT_RX_DONE_Enum;
/* ========================================= I2C0 IC_RAW_INTR_STAT TX_ABRT [6..6] ========================================== */
typedef enum { /*!< I2C0_IC_RAW_INTR_STAT_TX_ABRT */
I2C0_IC_RAW_INTR_STAT_TX_ABRT_INACTIVE = 0, /*!< INACTIVE : TX_ABRT interrupt is inactive */
I2C0_IC_RAW_INTR_STAT_TX_ABRT_ACTIVE = 1, /*!< ACTIVE : TX_ABRT interrupt is active */
} I2C0_IC_RAW_INTR_STAT_TX_ABRT_Enum;
/* ========================================== I2C0 IC_RAW_INTR_STAT RD_REQ [5..5] ========================================== */
typedef enum { /*!< I2C0_IC_RAW_INTR_STAT_RD_REQ */
I2C0_IC_RAW_INTR_STAT_RD_REQ_INACTIVE = 0, /*!< INACTIVE : RD_REQ interrupt is inactive */
I2C0_IC_RAW_INTR_STAT_RD_REQ_ACTIVE = 1, /*!< ACTIVE : RD_REQ interrupt is active */
} I2C0_IC_RAW_INTR_STAT_RD_REQ_Enum;
/* ========================================= I2C0 IC_RAW_INTR_STAT TX_EMPTY [4..4] ========================================= */
typedef enum { /*!< I2C0_IC_RAW_INTR_STAT_TX_EMPTY */
I2C0_IC_RAW_INTR_STAT_TX_EMPTY_INACTIVE = 0, /*!< INACTIVE : TX_EMPTY interrupt is inactive */
I2C0_IC_RAW_INTR_STAT_TX_EMPTY_ACTIVE = 1, /*!< ACTIVE : TX_EMPTY interrupt is active */
} I2C0_IC_RAW_INTR_STAT_TX_EMPTY_Enum;
/* ========================================= I2C0 IC_RAW_INTR_STAT TX_OVER [3..3] ========================================== */
typedef enum { /*!< I2C0_IC_RAW_INTR_STAT_TX_OVER */
I2C0_IC_RAW_INTR_STAT_TX_OVER_INACTIVE = 0, /*!< INACTIVE : TX_OVER interrupt is inactive */
I2C0_IC_RAW_INTR_STAT_TX_OVER_ACTIVE = 1, /*!< ACTIVE : TX_OVER interrupt is active */
} I2C0_IC_RAW_INTR_STAT_TX_OVER_Enum;
/* ========================================= I2C0 IC_RAW_INTR_STAT RX_FULL [2..2] ========================================== */
typedef enum { /*!< I2C0_IC_RAW_INTR_STAT_RX_FULL */
I2C0_IC_RAW_INTR_STAT_RX_FULL_INACTIVE = 0, /*!< INACTIVE : RX_FULL interrupt is inactive */
I2C0_IC_RAW_INTR_STAT_RX_FULL_ACTIVE = 1, /*!< ACTIVE : RX_FULL interrupt is active */
} I2C0_IC_RAW_INTR_STAT_RX_FULL_Enum;
/* ========================================= I2C0 IC_RAW_INTR_STAT RX_OVER [1..1] ========================================== */
typedef enum { /*!< I2C0_IC_RAW_INTR_STAT_RX_OVER */
I2C0_IC_RAW_INTR_STAT_RX_OVER_INACTIVE = 0, /*!< INACTIVE : RX_OVER interrupt is inactive */
I2C0_IC_RAW_INTR_STAT_RX_OVER_ACTIVE = 1, /*!< ACTIVE : RX_OVER interrupt is active */
} I2C0_IC_RAW_INTR_STAT_RX_OVER_Enum;
/* ========================================= I2C0 IC_RAW_INTR_STAT RX_UNDER [0..0] ========================================= */
typedef enum { /*!< I2C0_IC_RAW_INTR_STAT_RX_UNDER */
I2C0_IC_RAW_INTR_STAT_RX_UNDER_INACTIVE = 0, /*!< INACTIVE : RX_UNDER interrupt is inactive */
I2C0_IC_RAW_INTR_STAT_RX_UNDER_ACTIVE = 1, /*!< ACTIVE : RX_UNDER interrupt is active */
} I2C0_IC_RAW_INTR_STAT_RX_UNDER_Enum;
/* ======================================================= IC_RX_TL ======================================================== */
/* ======================================================= IC_TX_TL ======================================================== */
/* ====================================================== IC_CLR_INTR ====================================================== */
/* ==================================================== IC_CLR_RX_UNDER ==================================================== */
/* ==================================================== IC_CLR_RX_OVER ===================================================== */
/* ==================================================== IC_CLR_TX_OVER ===================================================== */
/* ===================================================== IC_CLR_RD_REQ ===================================================== */
/* ==================================================== IC_CLR_TX_ABRT ===================================================== */
/* ==================================================== IC_CLR_RX_DONE ===================================================== */
/* ==================================================== IC_CLR_ACTIVITY ==================================================== */
/* ==================================================== IC_CLR_STOP_DET ==================================================== */
/* =================================================== IC_CLR_START_DET ==================================================== */
/* ==================================================== IC_CLR_GEN_CALL ==================================================== */
/* ======================================================= IC_ENABLE ======================================================= */
/* ========================================== I2C0 IC_ENABLE TX_CMD_BLOCK [2..2] =========================================== */
typedef enum { /*!< I2C0_IC_ENABLE_TX_CMD_BLOCK */
I2C0_IC_ENABLE_TX_CMD_BLOCK_NOT_BLOCKED = 0, /*!< NOT_BLOCKED : Tx Command execution not blocked */
I2C0_IC_ENABLE_TX_CMD_BLOCK_BLOCKED = 1, /*!< BLOCKED : Tx Command execution blocked */
} I2C0_IC_ENABLE_TX_CMD_BLOCK_Enum;
/* ============================================== I2C0 IC_ENABLE ABORT [1..1] ============================================== */
typedef enum { /*!< I2C0_IC_ENABLE_ABORT */
I2C0_IC_ENABLE_ABORT_DISABLE = 0, /*!< DISABLE : ABORT operation not in progress */
I2C0_IC_ENABLE_ABORT_ENABLED = 1, /*!< ENABLED : ABORT operation in progress */
} I2C0_IC_ENABLE_ABORT_Enum;
/* ============================================= I2C0 IC_ENABLE ENABLE [0..0] ============================================== */
typedef enum { /*!< I2C0_IC_ENABLE_ENABLE */
I2C0_IC_ENABLE_ENABLE_DISABLED = 0, /*!< DISABLED : I2C is disabled */
I2C0_IC_ENABLE_ENABLE_ENABLED = 1, /*!< ENABLED : I2C is enabled */
} I2C0_IC_ENABLE_ENABLE_Enum;
/* ======================================================= IC_STATUS ======================================================= */
/* ========================================== I2C0 IC_STATUS SLV_ACTIVITY [6..6] =========================================== */
typedef enum { /*!< I2C0_IC_STATUS_SLV_ACTIVITY */
I2C0_IC_STATUS_SLV_ACTIVITY_IDLE = 0, /*!< IDLE : Slave is idle */
I2C0_IC_STATUS_SLV_ACTIVITY_ACTIVE = 1, /*!< ACTIVE : Slave not idle */
} I2C0_IC_STATUS_SLV_ACTIVITY_Enum;
/* ========================================== I2C0 IC_STATUS MST_ACTIVITY [5..5] =========================================== */
typedef enum { /*!< I2C0_IC_STATUS_MST_ACTIVITY */
I2C0_IC_STATUS_MST_ACTIVITY_IDLE = 0, /*!< IDLE : Master is idle */
I2C0_IC_STATUS_MST_ACTIVITY_ACTIVE = 1, /*!< ACTIVE : Master not idle */
} I2C0_IC_STATUS_MST_ACTIVITY_Enum;
/* =============================================== I2C0 IC_STATUS RFF [4..4] =============================================== */
typedef enum { /*!< I2C0_IC_STATUS_RFF */
I2C0_IC_STATUS_RFF_NOT_FULL = 0, /*!< NOT_FULL : Rx FIFO not full */
I2C0_IC_STATUS_RFF_FULL = 1, /*!< FULL : Rx FIFO is full */
} I2C0_IC_STATUS_RFF_Enum;
/* ============================================== I2C0 IC_STATUS RFNE [3..3] =============================================== */
typedef enum { /*!< I2C0_IC_STATUS_RFNE */
I2C0_IC_STATUS_RFNE_EMPTY = 0, /*!< EMPTY : Rx FIFO is empty */
I2C0_IC_STATUS_RFNE_NOT_EMPTY = 1, /*!< NOT_EMPTY : Rx FIFO not empty */
} I2C0_IC_STATUS_RFNE_Enum;
/* =============================================== I2C0 IC_STATUS TFE [2..2] =============================================== */
typedef enum { /*!< I2C0_IC_STATUS_TFE */
I2C0_IC_STATUS_TFE_NON_EMPTY = 0, /*!< NON_EMPTY : Tx FIFO not empty */
I2C0_IC_STATUS_TFE_EMPTY = 1, /*!< EMPTY : Tx FIFO is empty */
} I2C0_IC_STATUS_TFE_Enum;
/* ============================================== I2C0 IC_STATUS TFNF [1..1] =============================================== */
typedef enum { /*!< I2C0_IC_STATUS_TFNF */
I2C0_IC_STATUS_TFNF_FULL = 0, /*!< FULL : Tx FIFO is full */
I2C0_IC_STATUS_TFNF_NOT_FULL = 1, /*!< NOT_FULL : Tx FIFO not full */
} I2C0_IC_STATUS_TFNF_Enum;
/* ============================================ I2C0 IC_STATUS ACTIVITY [0..0] ============================================= */
typedef enum { /*!< I2C0_IC_STATUS_ACTIVITY */
I2C0_IC_STATUS_ACTIVITY_INACTIVE = 0, /*!< INACTIVE : I2C is idle */
I2C0_IC_STATUS_ACTIVITY_ACTIVE = 1, /*!< ACTIVE : I2C is active */
} I2C0_IC_STATUS_ACTIVITY_Enum;
/* ======================================================= IC_TXFLR ======================================================== */
/* ======================================================= IC_RXFLR ======================================================== */
/* ====================================================== IC_SDA_HOLD ====================================================== */
/* =================================================== IC_TX_ABRT_SOURCE =================================================== */
/* ==================================== I2C0 IC_TX_ABRT_SOURCE ABRT_USER_ABRT [16..16] ===================================== */
typedef enum { /*!< I2C0_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT */
I2C0_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_ABRT_USER_ABRT_VOID = 0,/*!< ABRT_USER_ABRT_VOID : Transfer abort detected by master- scenario
not present */
I2C0_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_ABRT_USER_ABRT_GENERATED = 1,/*!< ABRT_USER_ABRT_GENERATED : Transfer abort detected by master */
} I2C0_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_Enum;
/* ==================================== I2C0 IC_TX_ABRT_SOURCE ABRT_SLVRD_INTX [15..15] ==================================== */
typedef enum { /*!< I2C0_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX */
I2C0_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_ABRT_SLVRD_INTX_VOID = 0,/*!< ABRT_SLVRD_INTX_VOID : Slave trying to transmit to remote master
in read mode- scenario not present */
I2C0_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_ABRT_SLVRD_INTX_GENERATED = 1,/*!< ABRT_SLVRD_INTX_GENERATED : Slave trying to transmit to remote
master in read mode */
} I2C0_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_Enum;
/* =================================== I2C0 IC_TX_ABRT_SOURCE ABRT_SLV_ARBLOST [14..14] ==================================== */
typedef enum { /*!< I2C0_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST */
I2C0_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_ABRT_SLV_ARBLOST_VOID = 0,/*!< ABRT_SLV_ARBLOST_VOID : Slave lost arbitration to remote master-
scenario not present */
I2C0_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_ABRT_SLV_ARBLOST_GENERATED = 1,/*!< ABRT_SLV_ARBLOST_GENERATED : Slave lost arbitration to remote
master */
} I2C0_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_Enum;
/* ================================= I2C0 IC_TX_ABRT_SOURCE ABRT_SLVFLUSH_TXFIFO [13..13] ================================== */
typedef enum { /*!< I2C0_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO */
I2C0_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_ABRT_SLVFLUSH_TXFIFO_VOID = 0,/*!< ABRT_SLVFLUSH_TXFIFO_VOID : Slave flushes existing data in TX-FIFO
upon getting read command- scenario not present */
I2C0_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_ABRT_SLVFLUSH_TXFIFO_GENERATED = 1,/*!< ABRT_SLVFLUSH_TXFIFO_GENERATED : Slave flushes existing data
in TX-FIFO upon getting read command */
} I2C0_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_Enum;
/* ======================================= I2C0 IC_TX_ABRT_SOURCE ARB_LOST [12..12] ======================================== */
typedef enum { /*!< I2C0_IC_TX_ABRT_SOURCE_ARB_LOST */
I2C0_IC_TX_ABRT_SOURCE_ARB_LOST_ABRT_LOST_VOID = 0,/*!< ABRT_LOST_VOID : Master or Slave-Transmitter lost arbitration-
scenario not present */
I2C0_IC_TX_ABRT_SOURCE_ARB_LOST_ABRT_LOST_GENERATED = 1,/*!< ABRT_LOST_GENERATED : Master or Slave-Transmitter lost arbitration */
} I2C0_IC_TX_ABRT_SOURCE_ARB_LOST_Enum;
/* ==================================== I2C0 IC_TX_ABRT_SOURCE ABRT_MASTER_DIS [11..11] ==================================== */
typedef enum { /*!< I2C0_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS */
I2C0_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_ABRT_MASTER_DIS_VOID = 0,/*!< ABRT_MASTER_DIS_VOID : User initiating master operation when
MASTER disabled- scenario not present */
I2C0_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_ABRT_MASTER_DIS_GENERATED = 1,/*!< ABRT_MASTER_DIS_GENERATED : User initiating master operation
when MASTER disabled */
} I2C0_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_Enum;
/* ================================== I2C0 IC_TX_ABRT_SOURCE ABRT_10B_RD_NORSTRT [10..10] ================================== */
typedef enum { /*!< I2C0_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT */
I2C0_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_ABRT_10B_RD_VOID = 0,/*!< ABRT_10B_RD_VOID : Master not trying to read in 10Bit addressing
mode when RESTART disabled */
I2C0_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_ABRT_10B_RD_GENERATED = 1,/*!< ABRT_10B_RD_GENERATED : Master trying to read in 10Bit addressing
mode when RESTART disabled */
} I2C0_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_Enum;
/* =================================== I2C0 IC_TX_ABRT_SOURCE ABRT_SBYTE_NORSTRT [9..9] ==================================== */
typedef enum { /*!< I2C0_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT */
I2C0_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_ABRT_SBYTE_NORSTRT_VOID = 0,/*!< ABRT_SBYTE_NORSTRT_VOID : User trying to send START byte when
RESTART disabled- scenario not present */
I2C0_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_ABRT_SBYTE_NORSTRT_GENERATED = 1,/*!< ABRT_SBYTE_NORSTRT_GENERATED : User trying to send START byte
when RESTART disabled */
} I2C0_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_Enum;
/* ===================================== I2C0 IC_TX_ABRT_SOURCE ABRT_HS_NORSTRT [8..8] ===================================== */
typedef enum { /*!< I2C0_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT */
I2C0_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_ABRT_HS_NORSTRT_VOID = 0,/*!< ABRT_HS_NORSTRT_VOID : User trying to switch Master to HS mode
when RESTART disabled- scenario not present */
I2C0_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_ABRT_HS_NORSTRT_GENERATED = 1,/*!< ABRT_HS_NORSTRT_GENERATED : User trying to switch Master to
HS mode when RESTART disabled */
} I2C0_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_Enum;
/* ==================================== I2C0 IC_TX_ABRT_SOURCE ABRT_SBYTE_ACKDET [7..7] ==================================== */
typedef enum { /*!< I2C0_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET */
I2C0_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_ABRT_SBYTE_ACKDET_VOID = 0,/*!< ABRT_SBYTE_ACKDET_VOID : ACK detected for START byte- scenario
not present */
I2C0_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_ABRT_SBYTE_ACKDET_GENERATED = 1,/*!< ABRT_SBYTE_ACKDET_GENERATED : ACK detected for START byte */
} I2C0_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_Enum;
/* ===================================== I2C0 IC_TX_ABRT_SOURCE ABRT_HS_ACKDET [6..6] ====================================== */
typedef enum { /*!< I2C0_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET */
I2C0_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_ABRT_HS_ACK_VOID = 0,/*!< ABRT_HS_ACK_VOID : HS Master code ACKed in HS Mode- scenario
not present */
I2C0_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_ABRT_HS_ACK_GENERATED = 1,/*!< ABRT_HS_ACK_GENERATED : HS Master code ACKed in HS Mode */
} I2C0_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_Enum;
/* ===================================== I2C0 IC_TX_ABRT_SOURCE ABRT_GCALL_READ [5..5] ===================================== */
typedef enum { /*!< I2C0_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ */
I2C0_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_ABRT_GCALL_READ_VOID = 0,/*!< ABRT_GCALL_READ_VOID : GCALL is followed by read from bus-scenario
not present */
I2C0_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_ABRT_GCALL_READ_GENERATED = 1,/*!< ABRT_GCALL_READ_GENERATED : GCALL is followed by read from bus */
} I2C0_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_Enum;
/* ==================================== I2C0 IC_TX_ABRT_SOURCE ABRT_GCALL_NOACK [4..4] ===================================== */
typedef enum { /*!< I2C0_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK */
I2C0_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_ABRT_GCALL_NOACK_VOID = 0,/*!< ABRT_GCALL_NOACK_VOID : GCALL not ACKed by any slave-scenario
not present */
I2C0_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_ABRT_GCALL_NOACK_GENERATED = 1,/*!< ABRT_GCALL_NOACK_GENERATED : GCALL not ACKed by any slave */
} I2C0_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_Enum;
/* ==================================== I2C0 IC_TX_ABRT_SOURCE ABRT_TXDATA_NOACK [3..3] ==================================== */
typedef enum { /*!< I2C0_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK */
I2C0_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_ABRT_TXDATA_NOACK_VOID = 0,/*!< ABRT_TXDATA_NOACK_VOID : Transmitted data non-ACKed by addressed
slave-scenario not present */
I2C0_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_ABRT_TXDATA_NOACK_GENERATED = 1,/*!< ABRT_TXDATA_NOACK_GENERATED : Transmitted data not ACKed by
addressed slave */
} I2C0_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_Enum;
/* =================================== I2C0 IC_TX_ABRT_SOURCE ABRT_10ADDR2_NOACK [2..2] ==================================== */
typedef enum { /*!< I2C0_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK */
I2C0_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_INACTIVE = 0,/*!< INACTIVE : This abort is not generated */
I2C0_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_ACTIVE = 1,/*!< ACTIVE : Byte 2 of 10Bit Address not ACKed by any slave */
} I2C0_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_Enum;
/* =================================== I2C0 IC_TX_ABRT_SOURCE ABRT_10ADDR1_NOACK [1..1] ==================================== */
typedef enum { /*!< I2C0_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK */
I2C0_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_INACTIVE = 0,/*!< INACTIVE : This abort is not generated */
I2C0_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_ACTIVE = 1,/*!< ACTIVE : Byte 1 of 10Bit Address not ACKed by any slave */
} I2C0_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_Enum;
/* =================================== I2C0 IC_TX_ABRT_SOURCE ABRT_7B_ADDR_NOACK [0..0] ==================================== */
typedef enum { /*!< I2C0_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK */
I2C0_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_INACTIVE = 0,/*!< INACTIVE : This abort is not generated */
I2C0_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_ACTIVE = 1,/*!< ACTIVE : This abort is generated because of NOACK for 7-bit
address */
} I2C0_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_Enum;
/* ================================================= IC_SLV_DATA_NACK_ONLY ================================================= */
/* ======================================== I2C0 IC_SLV_DATA_NACK_ONLY NACK [0..0] ========================================= */
typedef enum { /*!< I2C0_IC_SLV_DATA_NACK_ONLY_NACK */
I2C0_IC_SLV_DATA_NACK_ONLY_NACK_DISABLED = 0, /*!< DISABLED : Slave receiver generates NACK normally */
I2C0_IC_SLV_DATA_NACK_ONLY_NACK_ENABLED = 1, /*!< ENABLED : Slave receiver generates NACK upon data reception
only */
} I2C0_IC_SLV_DATA_NACK_ONLY_NACK_Enum;
/* ======================================================= IC_DMA_CR ======================================================= */
/* ============================================== I2C0 IC_DMA_CR TDMAE [1..1] ============================================== */
typedef enum { /*!< I2C0_IC_DMA_CR_TDMAE */
I2C0_IC_DMA_CR_TDMAE_DISABLED = 0, /*!< DISABLED : transmit FIFO DMA channel disabled */
I2C0_IC_DMA_CR_TDMAE_ENABLED = 1, /*!< ENABLED : Transmit FIFO DMA channel enabled */
} I2C0_IC_DMA_CR_TDMAE_Enum;
/* ============================================== I2C0 IC_DMA_CR RDMAE [0..0] ============================================== */
typedef enum { /*!< I2C0_IC_DMA_CR_RDMAE */
I2C0_IC_DMA_CR_RDMAE_DISABLED = 0, /*!< DISABLED : Receive FIFO DMA channel disabled */
I2C0_IC_DMA_CR_RDMAE_ENABLED = 1, /*!< ENABLED : Receive FIFO DMA channel enabled */
} I2C0_IC_DMA_CR_RDMAE_Enum;
/* ====================================================== IC_DMA_TDLR ====================================================== */
/* ====================================================== IC_DMA_RDLR ====================================================== */
/* ===================================================== IC_SDA_SETUP ====================================================== */
/* ================================================== IC_ACK_GENERAL_CALL ================================================== */
/* ===================================== I2C0 IC_ACK_GENERAL_CALL ACK_GEN_CALL [0..0] ====================================== */
typedef enum { /*!< I2C0_IC_ACK_GENERAL_CALL_ACK_GEN_CALL */
I2C0_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_DISABLED = 0,/*!< DISABLED : Generate NACK for a General Call */
I2C0_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_ENABLED = 1,/*!< ENABLED : Generate ACK for a General Call */
} I2C0_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_Enum;
/* =================================================== IC_ENABLE_STATUS ==================================================== */
/* ===================================== I2C0 IC_ENABLE_STATUS SLV_RX_DATA_LOST [2..2] ===================================== */
typedef enum { /*!< I2C0_IC_ENABLE_STATUS_SLV_RX_DATA_LOST */
I2C0_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_INACTIVE = 0,/*!< INACTIVE : Slave RX Data is not lost */
I2C0_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_ACTIVE = 1,/*!< ACTIVE : Slave RX Data is lost */
} I2C0_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_Enum;
/* ================================= I2C0 IC_ENABLE_STATUS SLV_DISABLED_WHILE_BUSY [1..1] ================================== */
typedef enum { /*!< I2C0_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY */
I2C0_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_INACTIVE = 0,/*!< INACTIVE : Slave is disabled when it is idle */
I2C0_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_ACTIVE = 1,/*!< ACTIVE : Slave is disabled when it is active */
} I2C0_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_Enum;
/* ========================================== I2C0 IC_ENABLE_STATUS IC_EN [0..0] =========================================== */
typedef enum { /*!< I2C0_IC_ENABLE_STATUS_IC_EN */
I2C0_IC_ENABLE_STATUS_IC_EN_DISABLED = 0, /*!< DISABLED : I2C disabled */
I2C0_IC_ENABLE_STATUS_IC_EN_ENABLED = 1, /*!< ENABLED : I2C enabled */
} I2C0_IC_ENABLE_STATUS_IC_EN_Enum;
/* ===================================================== IC_FS_SPKLEN ====================================================== */
/* ================================================== IC_CLR_RESTART_DET =================================================== */
/* ==================================================== IC_COMP_PARAM_1 ==================================================== */
/* ==================================================== IC_COMP_VERSION ==================================================== */
/* ===================================================== IC_COMP_TYPE ====================================================== */
/* =========================================================================================================================== */
/* ================ ADC ================ */
/* =========================================================================================================================== */
/* ========================================================== CS =========================================================== */
/* ======================================================== RESULT ========================================================= */
/* ========================================================== FCS ========================================================== */
/* ========================================================= FIFO ========================================================== */
/* ========================================================== DIV ========================================================== */
/* ========================================================= INTR ========================================================== */
/* ========================================================= INTE ========================================================== */
/* ========================================================= INTF ========================================================== */
/* ========================================================= INTS ========================================================== */
/* =========================================================================================================================== */
/* ================ PWM ================ */
/* =========================================================================================================================== */
/* ======================================================== CH0_CSR ======================================================== */
/* ============================================== PWM CH0_CSR DIVMODE [4..5] =============================================== */
typedef enum { /*!< PWM_CH0_CSR_DIVMODE */
PWM_CH0_CSR_DIVMODE_div = 0, /*!< div : Free-running counting at rate dictated by fractional divider */
PWM_CH0_CSR_DIVMODE_level = 1, /*!< level : Fractional divider operation is gated by the PWM B pin. */
PWM_CH0_CSR_DIVMODE_rise = 2, /*!< rise : Counter advances with each rising edge of the PWM B pin. */
PWM_CH0_CSR_DIVMODE_fall = 3, /*!< fall : Counter advances with each falling edge of the PWM B
pin. */
} PWM_CH0_CSR_DIVMODE_Enum;
/* ======================================================== CH0_DIV ======================================================== */
/* ======================================================== CH0_CTR ======================================================== */
/* ======================================================== CH0_CC ========================================================= */
/* ======================================================== CH0_TOP ======================================================== */
/* ======================================================== CH1_CSR ======================================================== */
/* ============================================== PWM CH1_CSR DIVMODE [4..5] =============================================== */
typedef enum { /*!< PWM_CH1_CSR_DIVMODE */
PWM_CH1_CSR_DIVMODE_div = 0, /*!< div : Free-running counting at rate dictated by fractional divider */
PWM_CH1_CSR_DIVMODE_level = 1, /*!< level : Fractional divider operation is gated by the PWM B pin. */
PWM_CH1_CSR_DIVMODE_rise = 2, /*!< rise : Counter advances with each rising edge of the PWM B pin. */
PWM_CH1_CSR_DIVMODE_fall = 3, /*!< fall : Counter advances with each falling edge of the PWM B
pin. */
} PWM_CH1_CSR_DIVMODE_Enum;
/* ======================================================== CH1_DIV ======================================================== */
/* ======================================================== CH1_CTR ======================================================== */
/* ======================================================== CH1_CC ========================================================= */
/* ======================================================== CH1_TOP ======================================================== */
/* ======================================================== CH2_CSR ======================================================== */
/* ============================================== PWM CH2_CSR DIVMODE [4..5] =============================================== */
typedef enum { /*!< PWM_CH2_CSR_DIVMODE */
PWM_CH2_CSR_DIVMODE_div = 0, /*!< div : Free-running counting at rate dictated by fractional divider */
PWM_CH2_CSR_DIVMODE_level = 1, /*!< level : Fractional divider operation is gated by the PWM B pin. */
PWM_CH2_CSR_DIVMODE_rise = 2, /*!< rise : Counter advances with each rising edge of the PWM B pin. */
PWM_CH2_CSR_DIVMODE_fall = 3, /*!< fall : Counter advances with each falling edge of the PWM B
pin. */
} PWM_CH2_CSR_DIVMODE_Enum;
/* ======================================================== CH2_DIV ======================================================== */
/* ======================================================== CH2_CTR ======================================================== */
/* ======================================================== CH2_CC ========================================================= */
/* ======================================================== CH2_TOP ======================================================== */
/* ======================================================== CH3_CSR ======================================================== */
/* ============================================== PWM CH3_CSR DIVMODE [4..5] =============================================== */
typedef enum { /*!< PWM_CH3_CSR_DIVMODE */
PWM_CH3_CSR_DIVMODE_div = 0, /*!< div : Free-running counting at rate dictated by fractional divider */
PWM_CH3_CSR_DIVMODE_level = 1, /*!< level : Fractional divider operation is gated by the PWM B pin. */
PWM_CH3_CSR_DIVMODE_rise = 2, /*!< rise : Counter advances with each rising edge of the PWM B pin. */
PWM_CH3_CSR_DIVMODE_fall = 3, /*!< fall : Counter advances with each falling edge of the PWM B
pin. */
} PWM_CH3_CSR_DIVMODE_Enum;
/* ======================================================== CH3_DIV ======================================================== */
/* ======================================================== CH3_CTR ======================================================== */
/* ======================================================== CH3_CC ========================================================= */
/* ======================================================== CH3_TOP ======================================================== */
/* ======================================================== CH4_CSR ======================================================== */
/* ============================================== PWM CH4_CSR DIVMODE [4..5] =============================================== */
typedef enum { /*!< PWM_CH4_CSR_DIVMODE */
PWM_CH4_CSR_DIVMODE_div = 0, /*!< div : Free-running counting at rate dictated by fractional divider */
PWM_CH4_CSR_DIVMODE_level = 1, /*!< level : Fractional divider operation is gated by the PWM B pin. */
PWM_CH4_CSR_DIVMODE_rise = 2, /*!< rise : Counter advances with each rising edge of the PWM B pin. */
PWM_CH4_CSR_DIVMODE_fall = 3, /*!< fall : Counter advances with each falling edge of the PWM B
pin. */
} PWM_CH4_CSR_DIVMODE_Enum;
/* ======================================================== CH4_DIV ======================================================== */
/* ======================================================== CH4_CTR ======================================================== */
/* ======================================================== CH4_CC ========================================================= */
/* ======================================================== CH4_TOP ======================================================== */
/* ======================================================== CH5_CSR ======================================================== */
/* ============================================== PWM CH5_CSR DIVMODE [4..5] =============================================== */
typedef enum { /*!< PWM_CH5_CSR_DIVMODE */
PWM_CH5_CSR_DIVMODE_div = 0, /*!< div : Free-running counting at rate dictated by fractional divider */
PWM_CH5_CSR_DIVMODE_level = 1, /*!< level : Fractional divider operation is gated by the PWM B pin. */
PWM_CH5_CSR_DIVMODE_rise = 2, /*!< rise : Counter advances with each rising edge of the PWM B pin. */
PWM_CH5_CSR_DIVMODE_fall = 3, /*!< fall : Counter advances with each falling edge of the PWM B
pin. */
} PWM_CH5_CSR_DIVMODE_Enum;
/* ======================================================== CH5_DIV ======================================================== */
/* ======================================================== CH5_CTR ======================================================== */
/* ======================================================== CH5_CC ========================================================= */
/* ======================================================== CH5_TOP ======================================================== */
/* ======================================================== CH6_CSR ======================================================== */
/* ============================================== PWM CH6_CSR DIVMODE [4..5] =============================================== */
typedef enum { /*!< PWM_CH6_CSR_DIVMODE */
PWM_CH6_CSR_DIVMODE_div = 0, /*!< div : Free-running counting at rate dictated by fractional divider */
PWM_CH6_CSR_DIVMODE_level = 1, /*!< level : Fractional divider operation is gated by the PWM B pin. */
PWM_CH6_CSR_DIVMODE_rise = 2, /*!< rise : Counter advances with each rising edge of the PWM B pin. */
PWM_CH6_CSR_DIVMODE_fall = 3, /*!< fall : Counter advances with each falling edge of the PWM B
pin. */
} PWM_CH6_CSR_DIVMODE_Enum;
/* ======================================================== CH6_DIV ======================================================== */
/* ======================================================== CH6_CTR ======================================================== */
/* ======================================================== CH6_CC ========================================================= */
/* ======================================================== CH6_TOP ======================================================== */
/* ======================================================== CH7_CSR ======================================================== */
/* ============================================== PWM CH7_CSR DIVMODE [4..5] =============================================== */
typedef enum { /*!< PWM_CH7_CSR_DIVMODE */
PWM_CH7_CSR_DIVMODE_div = 0, /*!< div : Free-running counting at rate dictated by fractional divider */
PWM_CH7_CSR_DIVMODE_level = 1, /*!< level : Fractional divider operation is gated by the PWM B pin. */
PWM_CH7_CSR_DIVMODE_rise = 2, /*!< rise : Counter advances with each rising edge of the PWM B pin. */
PWM_CH7_CSR_DIVMODE_fall = 3, /*!< fall : Counter advances with each falling edge of the PWM B
pin. */
} PWM_CH7_CSR_DIVMODE_Enum;
/* ======================================================== CH7_DIV ======================================================== */
/* ======================================================== CH7_CTR ======================================================== */
/* ======================================================== CH7_CC ========================================================= */
/* ======================================================== CH7_TOP ======================================================== */
/* ========================================================== EN =========================================================== */
/* ========================================================= INTR ========================================================== */
/* ========================================================= INTE ========================================================== */
/* ========================================================= INTF ========================================================== */
/* ========================================================= INTS ========================================================== */
/* =========================================================================================================================== */
/* ================ TIMER ================ */
/* =========================================================================================================================== */
/* ======================================================== TIMEHW ========================================================= */
/* ======================================================== TIMELW ========================================================= */
/* ======================================================== TIMEHR ========================================================= */
/* ======================================================== TIMELR ========================================================= */
/* ======================================================== ALARM0 ========================================================= */
/* ======================================================== ALARM1 ========================================================= */
/* ======================================================== ALARM2 ========================================================= */
/* ======================================================== ALARM3 ========================================================= */
/* ========================================================= ARMED ========================================================= */
/* ======================================================= TIMERAWH ======================================================== */
/* ======================================================= TIMERAWL ======================================================== */
/* ======================================================= DBGPAUSE ======================================================== */
/* ========================================================= PAUSE ========================================================= */
/* ========================================================= INTR ========================================================== */
/* ========================================================= INTE ========================================================== */
/* ========================================================= INTF ========================================================== */
/* ========================================================= INTS ========================================================== */
/* =========================================================================================================================== */
/* ================ WATCHDOG ================ */
/* =========================================================================================================================== */
/* ========================================================= CTRL ========================================================== */
/* ========================================================= LOAD ========================================================== */
/* ======================================================== REASON ========================================================= */
/* ======================================================= SCRATCH0 ======================================================== */
/* ======================================================= SCRATCH1 ======================================================== */
/* ======================================================= SCRATCH2 ======================================================== */
/* ======================================================= SCRATCH3 ======================================================== */
/* ======================================================= SCRATCH4 ======================================================== */
/* ======================================================= SCRATCH5 ======================================================== */
/* ======================================================= SCRATCH6 ======================================================== */
/* ======================================================= SCRATCH7 ======================================================== */
/* ========================================================= TICK ========================================================== */
/* =========================================================================================================================== */
/* ================ RTC ================ */
/* =========================================================================================================================== */
/* ======================================================= CLKDIV_M1 ======================================================= */
/* ======================================================== SETUP_0 ======================================================== */
/* ======================================================== SETUP_1 ======================================================== */
/* ========================================================= CTRL ========================================================== */
/* ====================================================== IRQ_SETUP_0 ====================================================== */
/* ====================================================== IRQ_SETUP_1 ====================================================== */
/* ========================================================= RTC_1 ========================================================= */
/* ========================================================= RTC_0 ========================================================= */
/* ========================================================= INTR ========================================================== */
/* ========================================================= INTE ========================================================== */
/* ========================================================= INTF ========================================================== */
/* ========================================================= INTS ========================================================== */
/* =========================================================================================================================== */
/* ================ ROSC ================ */
/* =========================================================================================================================== */
/* ========================================================= CTRL ========================================================== */
/* =============================================== ROSC CTRL ENABLE [12..23] =============================================== */
typedef enum { /*!< ROSC_CTRL_ENABLE */
ROSC_CTRL_ENABLE_DISABLE = 3358, /*!< DISABLE : DISABLE */
ROSC_CTRL_ENABLE_ENABLE = 4011, /*!< ENABLE : ENABLE */
} ROSC_CTRL_ENABLE_Enum;
/* ============================================= ROSC CTRL FREQ_RANGE [0..11] ============================================== */
typedef enum { /*!< ROSC_CTRL_FREQ_RANGE */
ROSC_CTRL_FREQ_RANGE_LOW = 4004, /*!< LOW : LOW */
ROSC_CTRL_FREQ_RANGE_MEDIUM = 4005, /*!< MEDIUM : MEDIUM */
ROSC_CTRL_FREQ_RANGE_HIGH = 4007, /*!< HIGH : HIGH */
ROSC_CTRL_FREQ_RANGE_TOOHIGH = 4006, /*!< TOOHIGH : TOOHIGH */
} ROSC_CTRL_FREQ_RANGE_Enum;
/* ========================================================= FREQA ========================================================= */
/* ============================================== ROSC FREQA PASSWD [16..31] =============================================== */
typedef enum { /*!< ROSC_FREQA_PASSWD */
ROSC_FREQA_PASSWD_PASS = 38550, /*!< PASS : PASS */
} ROSC_FREQA_PASSWD_Enum;
/* ========================================================= FREQB ========================================================= */
/* ============================================== ROSC FREQB PASSWD [16..31] =============================================== */
typedef enum { /*!< ROSC_FREQB_PASSWD */
ROSC_FREQB_PASSWD_PASS = 38550, /*!< PASS : PASS */
} ROSC_FREQB_PASSWD_Enum;
/* ======================================================== DORMANT ======================================================== */
/* ========================================================== DIV ========================================================== */
/* ================================================= ROSC DIV DIV [0..11] ================================================== */
typedef enum { /*!< ROSC_DIV_DIV */
ROSC_DIV_DIV_PASS = 2720, /*!< PASS : PASS */
} ROSC_DIV_DIV_Enum;
/* ========================================================= PHASE ========================================================= */
/* ======================================================== STATUS ========================================================= */
/* ======================================================= RANDOMBIT ======================================================= */
/* ========================================================= COUNT ========================================================= */
/* =========================================================================================================================== */
/* ================ VREG_AND_CHIP_RESET ================ */
/* =========================================================================================================================== */
/* ========================================================= VREG ========================================================== */
/* ========================================================== BOD ========================================================== */
/* ====================================================== CHIP_RESET ======================================================= */
/* =========================================================================================================================== */
/* ================ TBMAN ================ */
/* =========================================================================================================================== */
/* ======================================================= PLATFORM ======================================================== */
/* =========================================================================================================================== */
/* ================ DMA ================ */
/* =========================================================================================================================== */
/* ===================================================== CH0_READ_ADDR ===================================================== */
/* ==================================================== CH0_WRITE_ADDR ===================================================== */
/* ==================================================== CH0_TRANS_COUNT ==================================================== */
/* ===================================================== CH0_CTRL_TRIG ===================================================== */
/* ========================================== DMA CH0_CTRL_TRIG TREQ_SEL [15..20] ========================================== */
typedef enum { /*!< DMA_CH0_CTRL_TRIG_TREQ_SEL */
DMA_CH0_CTRL_TRIG_TREQ_SEL_TIMER0 = 59, /*!< TIMER0 : Select Timer 0 as TREQ */
DMA_CH0_CTRL_TRIG_TREQ_SEL_TIMER1 = 60, /*!< TIMER1 : Select Timer 1 as TREQ */
DMA_CH0_CTRL_TRIG_TREQ_SEL_TIMER2 = 61, /*!< TIMER2 : Select Timer 2 as TREQ (Optional) */
DMA_CH0_CTRL_TRIG_TREQ_SEL_TIMER3 = 62, /*!< TIMER3 : Select Timer 3 as TREQ (Optional) */
DMA_CH0_CTRL_TRIG_TREQ_SEL_PERMANENT = 63, /*!< PERMANENT : Permanent request, for unpaced transfers. */
} DMA_CH0_CTRL_TRIG_TREQ_SEL_Enum;
/* ========================================== DMA CH0_CTRL_TRIG RING_SIZE [6..9] =========================================== */
typedef enum { /*!< DMA_CH0_CTRL_TRIG_RING_SIZE */
DMA_CH0_CTRL_TRIG_RING_SIZE_RING_NONE = 0, /*!< RING_NONE : RING_NONE */
} DMA_CH0_CTRL_TRIG_RING_SIZE_Enum;
/* ========================================== DMA CH0_CTRL_TRIG DATA_SIZE [2..3] =========================================== */
typedef enum { /*!< DMA_CH0_CTRL_TRIG_DATA_SIZE */
DMA_CH0_CTRL_TRIG_DATA_SIZE_SIZE_BYTE = 0, /*!< SIZE_BYTE : SIZE_BYTE */
DMA_CH0_CTRL_TRIG_DATA_SIZE_SIZE_HALFWORD = 1,/*!< SIZE_HALFWORD : SIZE_HALFWORD */
DMA_CH0_CTRL_TRIG_DATA_SIZE_SIZE_WORD = 2, /*!< SIZE_WORD : SIZE_WORD */
} DMA_CH0_CTRL_TRIG_DATA_SIZE_Enum;
/* ===================================================== CH0_AL1_CTRL ====================================================== */
/* =================================================== CH0_AL1_READ_ADDR =================================================== */
/* ================================================== CH0_AL1_WRITE_ADDR =================================================== */
/* =============================================== CH0_AL1_TRANS_COUNT_TRIG ================================================ */
/* ===================================================== CH0_AL2_CTRL ====================================================== */
/* ================================================== CH0_AL2_TRANS_COUNT ================================================== */
/* =================================================== CH0_AL2_READ_ADDR =================================================== */
/* ================================================ CH0_AL2_WRITE_ADDR_TRIG ================================================ */
/* ===================================================== CH0_AL3_CTRL ====================================================== */
/* ================================================== CH0_AL3_WRITE_ADDR =================================================== */
/* ================================================== CH0_AL3_TRANS_COUNT ================================================== */
/* ================================================ CH0_AL3_READ_ADDR_TRIG ================================================= */
/* ===================================================== CH1_READ_ADDR ===================================================== */
/* ==================================================== CH1_WRITE_ADDR ===================================================== */
/* ==================================================== CH1_TRANS_COUNT ==================================================== */
/* ===================================================== CH1_CTRL_TRIG ===================================================== */
/* ========================================== DMA CH1_CTRL_TRIG TREQ_SEL [15..20] ========================================== */
typedef enum { /*!< DMA_CH1_CTRL_TRIG_TREQ_SEL */
DMA_CH1_CTRL_TRIG_TREQ_SEL_TIMER0 = 59, /*!< TIMER0 : Select Timer 0 as TREQ */
DMA_CH1_CTRL_TRIG_TREQ_SEL_TIMER1 = 60, /*!< TIMER1 : Select Timer 1 as TREQ */
DMA_CH1_CTRL_TRIG_TREQ_SEL_TIMER2 = 61, /*!< TIMER2 : Select Timer 2 as TREQ (Optional) */
DMA_CH1_CTRL_TRIG_TREQ_SEL_TIMER3 = 62, /*!< TIMER3 : Select Timer 3 as TREQ (Optional) */
DMA_CH1_CTRL_TRIG_TREQ_SEL_PERMANENT = 63, /*!< PERMANENT : Permanent request, for unpaced transfers. */
} DMA_CH1_CTRL_TRIG_TREQ_SEL_Enum;
/* ========================================== DMA CH1_CTRL_TRIG RING_SIZE [6..9] =========================================== */
typedef enum { /*!< DMA_CH1_CTRL_TRIG_RING_SIZE */
DMA_CH1_CTRL_TRIG_RING_SIZE_RING_NONE = 0, /*!< RING_NONE : RING_NONE */
} DMA_CH1_CTRL_TRIG_RING_SIZE_Enum;
/* ========================================== DMA CH1_CTRL_TRIG DATA_SIZE [2..3] =========================================== */
typedef enum { /*!< DMA_CH1_CTRL_TRIG_DATA_SIZE */
DMA_CH1_CTRL_TRIG_DATA_SIZE_SIZE_BYTE = 0, /*!< SIZE_BYTE : SIZE_BYTE */
DMA_CH1_CTRL_TRIG_DATA_SIZE_SIZE_HALFWORD = 1,/*!< SIZE_HALFWORD : SIZE_HALFWORD */
DMA_CH1_CTRL_TRIG_DATA_SIZE_SIZE_WORD = 2, /*!< SIZE_WORD : SIZE_WORD */
} DMA_CH1_CTRL_TRIG_DATA_SIZE_Enum;
/* ===================================================== CH1_AL1_CTRL ====================================================== */
/* =================================================== CH1_AL1_READ_ADDR =================================================== */
/* ================================================== CH1_AL1_WRITE_ADDR =================================================== */
/* =============================================== CH1_AL1_TRANS_COUNT_TRIG ================================================ */
/* ===================================================== CH1_AL2_CTRL ====================================================== */
/* ================================================== CH1_AL2_TRANS_COUNT ================================================== */
/* =================================================== CH1_AL2_READ_ADDR =================================================== */
/* ================================================ CH1_AL2_WRITE_ADDR_TRIG ================================================ */
/* ===================================================== CH1_AL3_CTRL ====================================================== */
/* ================================================== CH1_AL3_WRITE_ADDR =================================================== */
/* ================================================== CH1_AL3_TRANS_COUNT ================================================== */
/* ================================================ CH1_AL3_READ_ADDR_TRIG ================================================= */
/* ===================================================== CH2_READ_ADDR ===================================================== */
/* ==================================================== CH2_WRITE_ADDR ===================================================== */
/* ==================================================== CH2_TRANS_COUNT ==================================================== */
/* ===================================================== CH2_CTRL_TRIG ===================================================== */
/* ========================================== DMA CH2_CTRL_TRIG TREQ_SEL [15..20] ========================================== */
typedef enum { /*!< DMA_CH2_CTRL_TRIG_TREQ_SEL */
DMA_CH2_CTRL_TRIG_TREQ_SEL_TIMER0 = 59, /*!< TIMER0 : Select Timer 0 as TREQ */
DMA_CH2_CTRL_TRIG_TREQ_SEL_TIMER1 = 60, /*!< TIMER1 : Select Timer 1 as TREQ */
DMA_CH2_CTRL_TRIG_TREQ_SEL_TIMER2 = 61, /*!< TIMER2 : Select Timer 2 as TREQ (Optional) */
DMA_CH2_CTRL_TRIG_TREQ_SEL_TIMER3 = 62, /*!< TIMER3 : Select Timer 3 as TREQ (Optional) */
DMA_CH2_CTRL_TRIG_TREQ_SEL_PERMANENT = 63, /*!< PERMANENT : Permanent request, for unpaced transfers. */
} DMA_CH2_CTRL_TRIG_TREQ_SEL_Enum;
/* ========================================== DMA CH2_CTRL_TRIG RING_SIZE [6..9] =========================================== */
typedef enum { /*!< DMA_CH2_CTRL_TRIG_RING_SIZE */
DMA_CH2_CTRL_TRIG_RING_SIZE_RING_NONE = 0, /*!< RING_NONE : RING_NONE */
} DMA_CH2_CTRL_TRIG_RING_SIZE_Enum;
/* ========================================== DMA CH2_CTRL_TRIG DATA_SIZE [2..3] =========================================== */
typedef enum { /*!< DMA_CH2_CTRL_TRIG_DATA_SIZE */
DMA_CH2_CTRL_TRIG_DATA_SIZE_SIZE_BYTE = 0, /*!< SIZE_BYTE : SIZE_BYTE */
DMA_CH2_CTRL_TRIG_DATA_SIZE_SIZE_HALFWORD = 1,/*!< SIZE_HALFWORD : SIZE_HALFWORD */
DMA_CH2_CTRL_TRIG_DATA_SIZE_SIZE_WORD = 2, /*!< SIZE_WORD : SIZE_WORD */
} DMA_CH2_CTRL_TRIG_DATA_SIZE_Enum;
/* ===================================================== CH2_AL1_CTRL ====================================================== */
/* =================================================== CH2_AL1_READ_ADDR =================================================== */
/* ================================================== CH2_AL1_WRITE_ADDR =================================================== */
/* =============================================== CH2_AL1_TRANS_COUNT_TRIG ================================================ */
/* ===================================================== CH2_AL2_CTRL ====================================================== */
/* ================================================== CH2_AL2_TRANS_COUNT ================================================== */
/* =================================================== CH2_AL2_READ_ADDR =================================================== */
/* ================================================ CH2_AL2_WRITE_ADDR_TRIG ================================================ */
/* ===================================================== CH2_AL3_CTRL ====================================================== */
/* ================================================== CH2_AL3_WRITE_ADDR =================================================== */
/* ================================================== CH2_AL3_TRANS_COUNT ================================================== */
/* ================================================ CH2_AL3_READ_ADDR_TRIG ================================================= */
/* ===================================================== CH3_READ_ADDR ===================================================== */
/* ==================================================== CH3_WRITE_ADDR ===================================================== */
/* ==================================================== CH3_TRANS_COUNT ==================================================== */
/* ===================================================== CH3_CTRL_TRIG ===================================================== */
/* ========================================== DMA CH3_CTRL_TRIG TREQ_SEL [15..20] ========================================== */
typedef enum { /*!< DMA_CH3_CTRL_TRIG_TREQ_SEL */
DMA_CH3_CTRL_TRIG_TREQ_SEL_TIMER0 = 59, /*!< TIMER0 : Select Timer 0 as TREQ */
DMA_CH3_CTRL_TRIG_TREQ_SEL_TIMER1 = 60, /*!< TIMER1 : Select Timer 1 as TREQ */
DMA_CH3_CTRL_TRIG_TREQ_SEL_TIMER2 = 61, /*!< TIMER2 : Select Timer 2 as TREQ (Optional) */
DMA_CH3_CTRL_TRIG_TREQ_SEL_TIMER3 = 62, /*!< TIMER3 : Select Timer 3 as TREQ (Optional) */
DMA_CH3_CTRL_TRIG_TREQ_SEL_PERMANENT = 63, /*!< PERMANENT : Permanent request, for unpaced transfers. */
} DMA_CH3_CTRL_TRIG_TREQ_SEL_Enum;
/* ========================================== DMA CH3_CTRL_TRIG RING_SIZE [6..9] =========================================== */
typedef enum { /*!< DMA_CH3_CTRL_TRIG_RING_SIZE */
DMA_CH3_CTRL_TRIG_RING_SIZE_RING_NONE = 0, /*!< RING_NONE : RING_NONE */
} DMA_CH3_CTRL_TRIG_RING_SIZE_Enum;
/* ========================================== DMA CH3_CTRL_TRIG DATA_SIZE [2..3] =========================================== */
typedef enum { /*!< DMA_CH3_CTRL_TRIG_DATA_SIZE */
DMA_CH3_CTRL_TRIG_DATA_SIZE_SIZE_BYTE = 0, /*!< SIZE_BYTE : SIZE_BYTE */
DMA_CH3_CTRL_TRIG_DATA_SIZE_SIZE_HALFWORD = 1,/*!< SIZE_HALFWORD : SIZE_HALFWORD */
DMA_CH3_CTRL_TRIG_DATA_SIZE_SIZE_WORD = 2, /*!< SIZE_WORD : SIZE_WORD */
} DMA_CH3_CTRL_TRIG_DATA_SIZE_Enum;
/* ===================================================== CH3_AL1_CTRL ====================================================== */
/* =================================================== CH3_AL1_READ_ADDR =================================================== */
/* ================================================== CH3_AL1_WRITE_ADDR =================================================== */
/* =============================================== CH3_AL1_TRANS_COUNT_TRIG ================================================ */
/* ===================================================== CH3_AL2_CTRL ====================================================== */
/* ================================================== CH3_AL2_TRANS_COUNT ================================================== */
/* =================================================== CH3_AL2_READ_ADDR =================================================== */
/* ================================================ CH3_AL2_WRITE_ADDR_TRIG ================================================ */
/* ===================================================== CH3_AL3_CTRL ====================================================== */
/* ================================================== CH3_AL3_WRITE_ADDR =================================================== */
/* ================================================== CH3_AL3_TRANS_COUNT ================================================== */
/* ================================================ CH3_AL3_READ_ADDR_TRIG ================================================= */
/* ===================================================== CH4_READ_ADDR ===================================================== */
/* ==================================================== CH4_WRITE_ADDR ===================================================== */
/* ==================================================== CH4_TRANS_COUNT ==================================================== */
/* ===================================================== CH4_CTRL_TRIG ===================================================== */
/* ========================================== DMA CH4_CTRL_TRIG TREQ_SEL [15..20] ========================================== */
typedef enum { /*!< DMA_CH4_CTRL_TRIG_TREQ_SEL */
DMA_CH4_CTRL_TRIG_TREQ_SEL_TIMER0 = 59, /*!< TIMER0 : Select Timer 0 as TREQ */
DMA_CH4_CTRL_TRIG_TREQ_SEL_TIMER1 = 60, /*!< TIMER1 : Select Timer 1 as TREQ */
DMA_CH4_CTRL_TRIG_TREQ_SEL_TIMER2 = 61, /*!< TIMER2 : Select Timer 2 as TREQ (Optional) */
DMA_CH4_CTRL_TRIG_TREQ_SEL_TIMER3 = 62, /*!< TIMER3 : Select Timer 3 as TREQ (Optional) */
DMA_CH4_CTRL_TRIG_TREQ_SEL_PERMANENT = 63, /*!< PERMANENT : Permanent request, for unpaced transfers. */
} DMA_CH4_CTRL_TRIG_TREQ_SEL_Enum;
/* ========================================== DMA CH4_CTRL_TRIG RING_SIZE [6..9] =========================================== */
typedef enum { /*!< DMA_CH4_CTRL_TRIG_RING_SIZE */
DMA_CH4_CTRL_TRIG_RING_SIZE_RING_NONE = 0, /*!< RING_NONE : RING_NONE */
} DMA_CH4_CTRL_TRIG_RING_SIZE_Enum;
/* ========================================== DMA CH4_CTRL_TRIG DATA_SIZE [2..3] =========================================== */
typedef enum { /*!< DMA_CH4_CTRL_TRIG_DATA_SIZE */
DMA_CH4_CTRL_TRIG_DATA_SIZE_SIZE_BYTE = 0, /*!< SIZE_BYTE : SIZE_BYTE */
DMA_CH4_CTRL_TRIG_DATA_SIZE_SIZE_HALFWORD = 1,/*!< SIZE_HALFWORD : SIZE_HALFWORD */
DMA_CH4_CTRL_TRIG_DATA_SIZE_SIZE_WORD = 2, /*!< SIZE_WORD : SIZE_WORD */
} DMA_CH4_CTRL_TRIG_DATA_SIZE_Enum;
/* ===================================================== CH4_AL1_CTRL ====================================================== */
/* =================================================== CH4_AL1_READ_ADDR =================================================== */
/* ================================================== CH4_AL1_WRITE_ADDR =================================================== */
/* =============================================== CH4_AL1_TRANS_COUNT_TRIG ================================================ */
/* ===================================================== CH4_AL2_CTRL ====================================================== */
/* ================================================== CH4_AL2_TRANS_COUNT ================================================== */
/* =================================================== CH4_AL2_READ_ADDR =================================================== */
/* ================================================ CH4_AL2_WRITE_ADDR_TRIG ================================================ */
/* ===================================================== CH4_AL3_CTRL ====================================================== */
/* ================================================== CH4_AL3_WRITE_ADDR =================================================== */
/* ================================================== CH4_AL3_TRANS_COUNT ================================================== */
/* ================================================ CH4_AL3_READ_ADDR_TRIG ================================================= */
/* ===================================================== CH5_READ_ADDR ===================================================== */
/* ==================================================== CH5_WRITE_ADDR ===================================================== */
/* ==================================================== CH5_TRANS_COUNT ==================================================== */
/* ===================================================== CH5_CTRL_TRIG ===================================================== */
/* ========================================== DMA CH5_CTRL_TRIG TREQ_SEL [15..20] ========================================== */
typedef enum { /*!< DMA_CH5_CTRL_TRIG_TREQ_SEL */
DMA_CH5_CTRL_TRIG_TREQ_SEL_TIMER0 = 59, /*!< TIMER0 : Select Timer 0 as TREQ */
DMA_CH5_CTRL_TRIG_TREQ_SEL_TIMER1 = 60, /*!< TIMER1 : Select Timer 1 as TREQ */
DMA_CH5_CTRL_TRIG_TREQ_SEL_TIMER2 = 61, /*!< TIMER2 : Select Timer 2 as TREQ (Optional) */
DMA_CH5_CTRL_TRIG_TREQ_SEL_TIMER3 = 62, /*!< TIMER3 : Select Timer 3 as TREQ (Optional) */
DMA_CH5_CTRL_TRIG_TREQ_SEL_PERMANENT = 63, /*!< PERMANENT : Permanent request, for unpaced transfers. */
} DMA_CH5_CTRL_TRIG_TREQ_SEL_Enum;
/* ========================================== DMA CH5_CTRL_TRIG RING_SIZE [6..9] =========================================== */
typedef enum { /*!< DMA_CH5_CTRL_TRIG_RING_SIZE */
DMA_CH5_CTRL_TRIG_RING_SIZE_RING_NONE = 0, /*!< RING_NONE : RING_NONE */
} DMA_CH5_CTRL_TRIG_RING_SIZE_Enum;
/* ========================================== DMA CH5_CTRL_TRIG DATA_SIZE [2..3] =========================================== */
typedef enum { /*!< DMA_CH5_CTRL_TRIG_DATA_SIZE */
DMA_CH5_CTRL_TRIG_DATA_SIZE_SIZE_BYTE = 0, /*!< SIZE_BYTE : SIZE_BYTE */
DMA_CH5_CTRL_TRIG_DATA_SIZE_SIZE_HALFWORD = 1,/*!< SIZE_HALFWORD : SIZE_HALFWORD */
DMA_CH5_CTRL_TRIG_DATA_SIZE_SIZE_WORD = 2, /*!< SIZE_WORD : SIZE_WORD */
} DMA_CH5_CTRL_TRIG_DATA_SIZE_Enum;
/* ===================================================== CH5_AL1_CTRL ====================================================== */
/* =================================================== CH5_AL1_READ_ADDR =================================================== */
/* ================================================== CH5_AL1_WRITE_ADDR =================================================== */
/* =============================================== CH5_AL1_TRANS_COUNT_TRIG ================================================ */
/* ===================================================== CH5_AL2_CTRL ====================================================== */
/* ================================================== CH5_AL2_TRANS_COUNT ================================================== */
/* =================================================== CH5_AL2_READ_ADDR =================================================== */
/* ================================================ CH5_AL2_WRITE_ADDR_TRIG ================================================ */
/* ===================================================== CH5_AL3_CTRL ====================================================== */
/* ================================================== CH5_AL3_WRITE_ADDR =================================================== */
/* ================================================== CH5_AL3_TRANS_COUNT ================================================== */
/* ================================================ CH5_AL3_READ_ADDR_TRIG ================================================= */
/* ===================================================== CH6_READ_ADDR ===================================================== */
/* ==================================================== CH6_WRITE_ADDR ===================================================== */
/* ==================================================== CH6_TRANS_COUNT ==================================================== */
/* ===================================================== CH6_CTRL_TRIG ===================================================== */
/* ========================================== DMA CH6_CTRL_TRIG TREQ_SEL [15..20] ========================================== */
typedef enum { /*!< DMA_CH6_CTRL_TRIG_TREQ_SEL */
DMA_CH6_CTRL_TRIG_TREQ_SEL_TIMER0 = 59, /*!< TIMER0 : Select Timer 0 as TREQ */
DMA_CH6_CTRL_TRIG_TREQ_SEL_TIMER1 = 60, /*!< TIMER1 : Select Timer 1 as TREQ */
DMA_CH6_CTRL_TRIG_TREQ_SEL_TIMER2 = 61, /*!< TIMER2 : Select Timer 2 as TREQ (Optional) */
DMA_CH6_CTRL_TRIG_TREQ_SEL_TIMER3 = 62, /*!< TIMER3 : Select Timer 3 as TREQ (Optional) */
DMA_CH6_CTRL_TRIG_TREQ_SEL_PERMANENT = 63, /*!< PERMANENT : Permanent request, for unpaced transfers. */
} DMA_CH6_CTRL_TRIG_TREQ_SEL_Enum;
/* ========================================== DMA CH6_CTRL_TRIG RING_SIZE [6..9] =========================================== */
typedef enum { /*!< DMA_CH6_CTRL_TRIG_RING_SIZE */
DMA_CH6_CTRL_TRIG_RING_SIZE_RING_NONE = 0, /*!< RING_NONE : RING_NONE */
} DMA_CH6_CTRL_TRIG_RING_SIZE_Enum;
/* ========================================== DMA CH6_CTRL_TRIG DATA_SIZE [2..3] =========================================== */
typedef enum { /*!< DMA_CH6_CTRL_TRIG_DATA_SIZE */
DMA_CH6_CTRL_TRIG_DATA_SIZE_SIZE_BYTE = 0, /*!< SIZE_BYTE : SIZE_BYTE */
DMA_CH6_CTRL_TRIG_DATA_SIZE_SIZE_HALFWORD = 1,/*!< SIZE_HALFWORD : SIZE_HALFWORD */
DMA_CH6_CTRL_TRIG_DATA_SIZE_SIZE_WORD = 2, /*!< SIZE_WORD : SIZE_WORD */
} DMA_CH6_CTRL_TRIG_DATA_SIZE_Enum;
/* ===================================================== CH6_AL1_CTRL ====================================================== */
/* =================================================== CH6_AL1_READ_ADDR =================================================== */
/* ================================================== CH6_AL1_WRITE_ADDR =================================================== */
/* =============================================== CH6_AL1_TRANS_COUNT_TRIG ================================================ */
/* ===================================================== CH6_AL2_CTRL ====================================================== */
/* ================================================== CH6_AL2_TRANS_COUNT ================================================== */
/* =================================================== CH6_AL2_READ_ADDR =================================================== */
/* ================================================ CH6_AL2_WRITE_ADDR_TRIG ================================================ */
/* ===================================================== CH6_AL3_CTRL ====================================================== */
/* ================================================== CH6_AL3_WRITE_ADDR =================================================== */
/* ================================================== CH6_AL3_TRANS_COUNT ================================================== */
/* ================================================ CH6_AL3_READ_ADDR_TRIG ================================================= */
/* ===================================================== CH7_READ_ADDR ===================================================== */
/* ==================================================== CH7_WRITE_ADDR ===================================================== */
/* ==================================================== CH7_TRANS_COUNT ==================================================== */
/* ===================================================== CH7_CTRL_TRIG ===================================================== */
/* ========================================== DMA CH7_CTRL_TRIG TREQ_SEL [15..20] ========================================== */
typedef enum { /*!< DMA_CH7_CTRL_TRIG_TREQ_SEL */
DMA_CH7_CTRL_TRIG_TREQ_SEL_TIMER0 = 59, /*!< TIMER0 : Select Timer 0 as TREQ */
DMA_CH7_CTRL_TRIG_TREQ_SEL_TIMER1 = 60, /*!< TIMER1 : Select Timer 1 as TREQ */
DMA_CH7_CTRL_TRIG_TREQ_SEL_TIMER2 = 61, /*!< TIMER2 : Select Timer 2 as TREQ (Optional) */
DMA_CH7_CTRL_TRIG_TREQ_SEL_TIMER3 = 62, /*!< TIMER3 : Select Timer 3 as TREQ (Optional) */
DMA_CH7_CTRL_TRIG_TREQ_SEL_PERMANENT = 63, /*!< PERMANENT : Permanent request, for unpaced transfers. */
} DMA_CH7_CTRL_TRIG_TREQ_SEL_Enum;
/* ========================================== DMA CH7_CTRL_TRIG RING_SIZE [6..9] =========================================== */
typedef enum { /*!< DMA_CH7_CTRL_TRIG_RING_SIZE */
DMA_CH7_CTRL_TRIG_RING_SIZE_RING_NONE = 0, /*!< RING_NONE : RING_NONE */
} DMA_CH7_CTRL_TRIG_RING_SIZE_Enum;
/* ========================================== DMA CH7_CTRL_TRIG DATA_SIZE [2..3] =========================================== */
typedef enum { /*!< DMA_CH7_CTRL_TRIG_DATA_SIZE */
DMA_CH7_CTRL_TRIG_DATA_SIZE_SIZE_BYTE = 0, /*!< SIZE_BYTE : SIZE_BYTE */
DMA_CH7_CTRL_TRIG_DATA_SIZE_SIZE_HALFWORD = 1,/*!< SIZE_HALFWORD : SIZE_HALFWORD */
DMA_CH7_CTRL_TRIG_DATA_SIZE_SIZE_WORD = 2, /*!< SIZE_WORD : SIZE_WORD */
} DMA_CH7_CTRL_TRIG_DATA_SIZE_Enum;
/* ===================================================== CH7_AL1_CTRL ====================================================== */
/* =================================================== CH7_AL1_READ_ADDR =================================================== */
/* ================================================== CH7_AL1_WRITE_ADDR =================================================== */
/* =============================================== CH7_AL1_TRANS_COUNT_TRIG ================================================ */
/* ===================================================== CH7_AL2_CTRL ====================================================== */
/* ================================================== CH7_AL2_TRANS_COUNT ================================================== */
/* =================================================== CH7_AL2_READ_ADDR =================================================== */
/* ================================================ CH7_AL2_WRITE_ADDR_TRIG ================================================ */
/* ===================================================== CH7_AL3_CTRL ====================================================== */
/* ================================================== CH7_AL3_WRITE_ADDR =================================================== */
/* ================================================== CH7_AL3_TRANS_COUNT ================================================== */
/* ================================================ CH7_AL3_READ_ADDR_TRIG ================================================= */
/* ===================================================== CH8_READ_ADDR ===================================================== */
/* ==================================================== CH8_WRITE_ADDR ===================================================== */
/* ==================================================== CH8_TRANS_COUNT ==================================================== */
/* ===================================================== CH8_CTRL_TRIG ===================================================== */
/* ========================================== DMA CH8_CTRL_TRIG TREQ_SEL [15..20] ========================================== */
typedef enum { /*!< DMA_CH8_CTRL_TRIG_TREQ_SEL */
DMA_CH8_CTRL_TRIG_TREQ_SEL_TIMER0 = 59, /*!< TIMER0 : Select Timer 0 as TREQ */
DMA_CH8_CTRL_TRIG_TREQ_SEL_TIMER1 = 60, /*!< TIMER1 : Select Timer 1 as TREQ */
DMA_CH8_CTRL_TRIG_TREQ_SEL_TIMER2 = 61, /*!< TIMER2 : Select Timer 2 as TREQ (Optional) */
DMA_CH8_CTRL_TRIG_TREQ_SEL_TIMER3 = 62, /*!< TIMER3 : Select Timer 3 as TREQ (Optional) */
DMA_CH8_CTRL_TRIG_TREQ_SEL_PERMANENT = 63, /*!< PERMANENT : Permanent request, for unpaced transfers. */
} DMA_CH8_CTRL_TRIG_TREQ_SEL_Enum;
/* ========================================== DMA CH8_CTRL_TRIG RING_SIZE [6..9] =========================================== */
typedef enum { /*!< DMA_CH8_CTRL_TRIG_RING_SIZE */
DMA_CH8_CTRL_TRIG_RING_SIZE_RING_NONE = 0, /*!< RING_NONE : RING_NONE */
} DMA_CH8_CTRL_TRIG_RING_SIZE_Enum;
/* ========================================== DMA CH8_CTRL_TRIG DATA_SIZE [2..3] =========================================== */
typedef enum { /*!< DMA_CH8_CTRL_TRIG_DATA_SIZE */
DMA_CH8_CTRL_TRIG_DATA_SIZE_SIZE_BYTE = 0, /*!< SIZE_BYTE : SIZE_BYTE */
DMA_CH8_CTRL_TRIG_DATA_SIZE_SIZE_HALFWORD = 1,/*!< SIZE_HALFWORD : SIZE_HALFWORD */
DMA_CH8_CTRL_TRIG_DATA_SIZE_SIZE_WORD = 2, /*!< SIZE_WORD : SIZE_WORD */
} DMA_CH8_CTRL_TRIG_DATA_SIZE_Enum;
/* ===================================================== CH8_AL1_CTRL ====================================================== */
/* =================================================== CH8_AL1_READ_ADDR =================================================== */
/* ================================================== CH8_AL1_WRITE_ADDR =================================================== */
/* =============================================== CH8_AL1_TRANS_COUNT_TRIG ================================================ */
/* ===================================================== CH8_AL2_CTRL ====================================================== */
/* ================================================== CH8_AL2_TRANS_COUNT ================================================== */
/* =================================================== CH8_AL2_READ_ADDR =================================================== */
/* ================================================ CH8_AL2_WRITE_ADDR_TRIG ================================================ */
/* ===================================================== CH8_AL3_CTRL ====================================================== */
/* ================================================== CH8_AL3_WRITE_ADDR =================================================== */
/* ================================================== CH8_AL3_TRANS_COUNT ================================================== */
/* ================================================ CH8_AL3_READ_ADDR_TRIG ================================================= */
/* ===================================================== CH9_READ_ADDR ===================================================== */
/* ==================================================== CH9_WRITE_ADDR ===================================================== */
/* ==================================================== CH9_TRANS_COUNT ==================================================== */
/* ===================================================== CH9_CTRL_TRIG ===================================================== */
/* ========================================== DMA CH9_CTRL_TRIG TREQ_SEL [15..20] ========================================== */
typedef enum { /*!< DMA_CH9_CTRL_TRIG_TREQ_SEL */
DMA_CH9_CTRL_TRIG_TREQ_SEL_TIMER0 = 59, /*!< TIMER0 : Select Timer 0 as TREQ */
DMA_CH9_CTRL_TRIG_TREQ_SEL_TIMER1 = 60, /*!< TIMER1 : Select Timer 1 as TREQ */
DMA_CH9_CTRL_TRIG_TREQ_SEL_TIMER2 = 61, /*!< TIMER2 : Select Timer 2 as TREQ (Optional) */
DMA_CH9_CTRL_TRIG_TREQ_SEL_TIMER3 = 62, /*!< TIMER3 : Select Timer 3 as TREQ (Optional) */
DMA_CH9_CTRL_TRIG_TREQ_SEL_PERMANENT = 63, /*!< PERMANENT : Permanent request, for unpaced transfers. */
} DMA_CH9_CTRL_TRIG_TREQ_SEL_Enum;
/* ========================================== DMA CH9_CTRL_TRIG RING_SIZE [6..9] =========================================== */
typedef enum { /*!< DMA_CH9_CTRL_TRIG_RING_SIZE */
DMA_CH9_CTRL_TRIG_RING_SIZE_RING_NONE = 0, /*!< RING_NONE : RING_NONE */
} DMA_CH9_CTRL_TRIG_RING_SIZE_Enum;
/* ========================================== DMA CH9_CTRL_TRIG DATA_SIZE [2..3] =========================================== */
typedef enum { /*!< DMA_CH9_CTRL_TRIG_DATA_SIZE */
DMA_CH9_CTRL_TRIG_DATA_SIZE_SIZE_BYTE = 0, /*!< SIZE_BYTE : SIZE_BYTE */
DMA_CH9_CTRL_TRIG_DATA_SIZE_SIZE_HALFWORD = 1,/*!< SIZE_HALFWORD : SIZE_HALFWORD */
DMA_CH9_CTRL_TRIG_DATA_SIZE_SIZE_WORD = 2, /*!< SIZE_WORD : SIZE_WORD */
} DMA_CH9_CTRL_TRIG_DATA_SIZE_Enum;
/* ===================================================== CH9_AL1_CTRL ====================================================== */
/* =================================================== CH9_AL1_READ_ADDR =================================================== */
/* ================================================== CH9_AL1_WRITE_ADDR =================================================== */
/* =============================================== CH9_AL1_TRANS_COUNT_TRIG ================================================ */
/* ===================================================== CH9_AL2_CTRL ====================================================== */
/* ================================================== CH9_AL2_TRANS_COUNT ================================================== */
/* =================================================== CH9_AL2_READ_ADDR =================================================== */
/* ================================================ CH9_AL2_WRITE_ADDR_TRIG ================================================ */
/* ===================================================== CH9_AL3_CTRL ====================================================== */
/* ================================================== CH9_AL3_WRITE_ADDR =================================================== */
/* ================================================== CH9_AL3_TRANS_COUNT ================================================== */
/* ================================================ CH9_AL3_READ_ADDR_TRIG ================================================= */
/* ==================================================== CH10_READ_ADDR ===================================================== */
/* ==================================================== CH10_WRITE_ADDR ==================================================== */
/* =================================================== CH10_TRANS_COUNT ==================================================== */
/* ==================================================== CH10_CTRL_TRIG ===================================================== */
/* ========================================= DMA CH10_CTRL_TRIG TREQ_SEL [15..20] ========================================== */
typedef enum { /*!< DMA_CH10_CTRL_TRIG_TREQ_SEL */
DMA_CH10_CTRL_TRIG_TREQ_SEL_TIMER0 = 59, /*!< TIMER0 : Select Timer 0 as TREQ */
DMA_CH10_CTRL_TRIG_TREQ_SEL_TIMER1 = 60, /*!< TIMER1 : Select Timer 1 as TREQ */
DMA_CH10_CTRL_TRIG_TREQ_SEL_TIMER2 = 61, /*!< TIMER2 : Select Timer 2 as TREQ (Optional) */
DMA_CH10_CTRL_TRIG_TREQ_SEL_TIMER3 = 62, /*!< TIMER3 : Select Timer 3 as TREQ (Optional) */
DMA_CH10_CTRL_TRIG_TREQ_SEL_PERMANENT = 63, /*!< PERMANENT : Permanent request, for unpaced transfers. */
} DMA_CH10_CTRL_TRIG_TREQ_SEL_Enum;
/* ========================================== DMA CH10_CTRL_TRIG RING_SIZE [6..9] ========================================== */
typedef enum { /*!< DMA_CH10_CTRL_TRIG_RING_SIZE */
DMA_CH10_CTRL_TRIG_RING_SIZE_RING_NONE = 0, /*!< RING_NONE : RING_NONE */
} DMA_CH10_CTRL_TRIG_RING_SIZE_Enum;
/* ========================================== DMA CH10_CTRL_TRIG DATA_SIZE [2..3] ========================================== */
typedef enum { /*!< DMA_CH10_CTRL_TRIG_DATA_SIZE */
DMA_CH10_CTRL_TRIG_DATA_SIZE_SIZE_BYTE = 0, /*!< SIZE_BYTE : SIZE_BYTE */
DMA_CH10_CTRL_TRIG_DATA_SIZE_SIZE_HALFWORD = 1,/*!< SIZE_HALFWORD : SIZE_HALFWORD */
DMA_CH10_CTRL_TRIG_DATA_SIZE_SIZE_WORD = 2, /*!< SIZE_WORD : SIZE_WORD */
} DMA_CH10_CTRL_TRIG_DATA_SIZE_Enum;
/* ===================================================== CH10_AL1_CTRL ===================================================== */
/* ================================================== CH10_AL1_READ_ADDR =================================================== */
/* ================================================== CH10_AL1_WRITE_ADDR ================================================== */
/* =============================================== CH10_AL1_TRANS_COUNT_TRIG =============================================== */
/* ===================================================== CH10_AL2_CTRL ===================================================== */
/* ================================================= CH10_AL2_TRANS_COUNT ================================================== */
/* ================================================== CH10_AL2_READ_ADDR =================================================== */
/* =============================================== CH10_AL2_WRITE_ADDR_TRIG ================================================ */
/* ===================================================== CH10_AL3_CTRL ===================================================== */
/* ================================================== CH10_AL3_WRITE_ADDR ================================================== */
/* ================================================= CH10_AL3_TRANS_COUNT ================================================== */
/* ================================================ CH10_AL3_READ_ADDR_TRIG ================================================ */
/* ==================================================== CH11_READ_ADDR ===================================================== */
/* ==================================================== CH11_WRITE_ADDR ==================================================== */
/* =================================================== CH11_TRANS_COUNT ==================================================== */
/* ==================================================== CH11_CTRL_TRIG ===================================================== */
/* ========================================= DMA CH11_CTRL_TRIG TREQ_SEL [15..20] ========================================== */
typedef enum { /*!< DMA_CH11_CTRL_TRIG_TREQ_SEL */
DMA_CH11_CTRL_TRIG_TREQ_SEL_TIMER0 = 59, /*!< TIMER0 : Select Timer 0 as TREQ */
DMA_CH11_CTRL_TRIG_TREQ_SEL_TIMER1 = 60, /*!< TIMER1 : Select Timer 1 as TREQ */
DMA_CH11_CTRL_TRIG_TREQ_SEL_TIMER2 = 61, /*!< TIMER2 : Select Timer 2 as TREQ (Optional) */
DMA_CH11_CTRL_TRIG_TREQ_SEL_TIMER3 = 62, /*!< TIMER3 : Select Timer 3 as TREQ (Optional) */
DMA_CH11_CTRL_TRIG_TREQ_SEL_PERMANENT = 63, /*!< PERMANENT : Permanent request, for unpaced transfers. */
} DMA_CH11_CTRL_TRIG_TREQ_SEL_Enum;
/* ========================================== DMA CH11_CTRL_TRIG RING_SIZE [6..9] ========================================== */
typedef enum { /*!< DMA_CH11_CTRL_TRIG_RING_SIZE */
DMA_CH11_CTRL_TRIG_RING_SIZE_RING_NONE = 0, /*!< RING_NONE : RING_NONE */
} DMA_CH11_CTRL_TRIG_RING_SIZE_Enum;
/* ========================================== DMA CH11_CTRL_TRIG DATA_SIZE [2..3] ========================================== */
typedef enum { /*!< DMA_CH11_CTRL_TRIG_DATA_SIZE */
DMA_CH11_CTRL_TRIG_DATA_SIZE_SIZE_BYTE = 0, /*!< SIZE_BYTE : SIZE_BYTE */
DMA_CH11_CTRL_TRIG_DATA_SIZE_SIZE_HALFWORD = 1,/*!< SIZE_HALFWORD : SIZE_HALFWORD */
DMA_CH11_CTRL_TRIG_DATA_SIZE_SIZE_WORD = 2, /*!< SIZE_WORD : SIZE_WORD */
} DMA_CH11_CTRL_TRIG_DATA_SIZE_Enum;
/* ===================================================== CH11_AL1_CTRL ===================================================== */
/* ================================================== CH11_AL1_READ_ADDR =================================================== */
/* ================================================== CH11_AL1_WRITE_ADDR ================================================== */
/* =============================================== CH11_AL1_TRANS_COUNT_TRIG =============================================== */
/* ===================================================== CH11_AL2_CTRL ===================================================== */
/* ================================================= CH11_AL2_TRANS_COUNT ================================================== */
/* ================================================== CH11_AL2_READ_ADDR =================================================== */
/* =============================================== CH11_AL2_WRITE_ADDR_TRIG ================================================ */
/* ===================================================== CH11_AL3_CTRL ===================================================== */
/* ================================================== CH11_AL3_WRITE_ADDR ================================================== */
/* ================================================= CH11_AL3_TRANS_COUNT ================================================== */
/* ================================================ CH11_AL3_READ_ADDR_TRIG ================================================ */
/* ========================================================= INTR ========================================================== */
/* ========================================================= INTE0 ========================================================= */
/* ========================================================= INTF0 ========================================================= */
/* ========================================================= INTS0 ========================================================= */
/* ========================================================= INTE1 ========================================================= */
/* ========================================================= INTF1 ========================================================= */
/* ========================================================= INTS1 ========================================================= */
/* ======================================================== TIMER0 ========================================================= */
/* ======================================================== TIMER1 ========================================================= */
/* ======================================================== TIMER2 ========================================================= */
/* ======================================================== TIMER3 ========================================================= */
/* ================================================== MULTI_CHAN_TRIGGER =================================================== */
/* ====================================================== SNIFF_CTRL ======================================================= */
/* ============================================== DMA SNIFF_CTRL CALC [5..8] =============================================== */
typedef enum { /*!< DMA_SNIFF_CTRL_CALC */
DMA_SNIFF_CTRL_CALC_CRC32 = 0, /*!< CRC32 : Calculate a CRC-32 (IEEE802.3 polynomial) */
DMA_SNIFF_CTRL_CALC_CRC32R = 1, /*!< CRC32R : Calculate a CRC-32 (IEEE802.3 polynomial) with bit
reversed data */
DMA_SNIFF_CTRL_CALC_CRC16 = 2, /*!< CRC16 : Calculate a CRC-16-CCITT */
DMA_SNIFF_CTRL_CALC_CRC16R = 3, /*!< CRC16R : Calculate a CRC-16-CCITT with bit reversed data */
DMA_SNIFF_CTRL_CALC_EVEN = 14, /*!< EVEN : XOR reduction over all data. == 1 if the total 1 population
count is odd. */
DMA_SNIFF_CTRL_CALC_SUM = 15, /*!< SUM : Calculate a simple 32-bit checksum (addition with a 32
bit accumulator) */
} DMA_SNIFF_CTRL_CALC_Enum;
/* ====================================================== SNIFF_DATA ======================================================= */
/* ====================================================== FIFO_LEVELS ====================================================== */
/* ====================================================== CHAN_ABORT ======================================================= */
/* ====================================================== N_CHANNELS ======================================================= */
/* ==================================================== CH0_DBG_CTDREQ ===================================================== */
/* ====================================================== CH0_DBG_TCR ====================================================== */
/* ==================================================== CH1_DBG_CTDREQ ===================================================== */
/* ====================================================== CH1_DBG_TCR ====================================================== */
/* ==================================================== CH2_DBG_CTDREQ ===================================================== */
/* ====================================================== CH2_DBG_TCR ====================================================== */
/* ==================================================== CH3_DBG_CTDREQ ===================================================== */
/* ====================================================== CH3_DBG_TCR ====================================================== */
/* ==================================================== CH4_DBG_CTDREQ ===================================================== */
/* ====================================================== CH4_DBG_TCR ====================================================== */
/* ==================================================== CH5_DBG_CTDREQ ===================================================== */
/* ====================================================== CH5_DBG_TCR ====================================================== */
/* ==================================================== CH6_DBG_CTDREQ ===================================================== */
/* ====================================================== CH6_DBG_TCR ====================================================== */
/* ==================================================== CH7_DBG_CTDREQ ===================================================== */
/* ====================================================== CH7_DBG_TCR ====================================================== */
/* ==================================================== CH8_DBG_CTDREQ ===================================================== */
/* ====================================================== CH8_DBG_TCR ====================================================== */
/* ==================================================== CH9_DBG_CTDREQ ===================================================== */
/* ====================================================== CH9_DBG_TCR ====================================================== */
/* ==================================================== CH10_DBG_CTDREQ ==================================================== */
/* ===================================================== CH10_DBG_TCR ====================================================== */
/* ==================================================== CH11_DBG_CTDREQ ==================================================== */
/* ===================================================== CH11_DBG_TCR ====================================================== */
/* =========================================================================================================================== */
/* ================ USBCTRL_DPRAM ================ */
/* =========================================================================================================================== */
/* =================================================== SETUP_PACKET_LOW ==================================================== */
/* =================================================== SETUP_PACKET_HIGH =================================================== */
/* ==================================================== EP1_IN_CONTROL ===================================================== */
/* ================================== USBCTRL_DPRAM EP1_IN_CONTROL ENDPOINT_TYPE [26..27] ================================== */
typedef enum { /*!< USBCTRL_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE */
USBCTRL_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_Control = 0,/*!< Control : Control */
USBCTRL_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_Isochronous = 1,/*!< Isochronous : Isochronous */
USBCTRL_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_Bulk = 2,/*!< Bulk : Bulk */
USBCTRL_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_Interrupt = 3,/*!< Interrupt : Interrupt */
} USBCTRL_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_Enum;
/* ==================================================== EP1_OUT_CONTROL ==================================================== */
/* ================================= USBCTRL_DPRAM EP1_OUT_CONTROL ENDPOINT_TYPE [26..27] ================================== */
typedef enum { /*!< USBCTRL_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE */
USBCTRL_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_Control = 0,/*!< Control : Control */
USBCTRL_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_Isochronous = 1,/*!< Isochronous : Isochronous */
USBCTRL_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_Bulk = 2,/*!< Bulk : Bulk */
USBCTRL_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_Interrupt = 3,/*!< Interrupt : Interrupt */
} USBCTRL_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_Enum;
/* ==================================================== EP2_IN_CONTROL ===================================================== */
/* ================================== USBCTRL_DPRAM EP2_IN_CONTROL ENDPOINT_TYPE [26..27] ================================== */
typedef enum { /*!< USBCTRL_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE */
USBCTRL_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_Control = 0,/*!< Control : Control */
USBCTRL_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_Isochronous = 1,/*!< Isochronous : Isochronous */
USBCTRL_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_Bulk = 2,/*!< Bulk : Bulk */
USBCTRL_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_Interrupt = 3,/*!< Interrupt : Interrupt */
} USBCTRL_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_Enum;
/* ==================================================== EP2_OUT_CONTROL ==================================================== */
/* ================================= USBCTRL_DPRAM EP2_OUT_CONTROL ENDPOINT_TYPE [26..27] ================================== */
typedef enum { /*!< USBCTRL_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE */
USBCTRL_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_Control = 0,/*!< Control : Control */
USBCTRL_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_Isochronous = 1,/*!< Isochronous : Isochronous */
USBCTRL_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_Bulk = 2,/*!< Bulk : Bulk */
USBCTRL_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_Interrupt = 3,/*!< Interrupt : Interrupt */
} USBCTRL_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_Enum;
/* ==================================================== EP3_IN_CONTROL ===================================================== */
/* ================================== USBCTRL_DPRAM EP3_IN_CONTROL ENDPOINT_TYPE [26..27] ================================== */
typedef enum { /*!< USBCTRL_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE */
USBCTRL_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_Control = 0,/*!< Control : Control */
USBCTRL_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_Isochronous = 1,/*!< Isochronous : Isochronous */
USBCTRL_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_Bulk = 2,/*!< Bulk : Bulk */
USBCTRL_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_Interrupt = 3,/*!< Interrupt : Interrupt */
} USBCTRL_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_Enum;
/* ==================================================== EP3_OUT_CONTROL ==================================================== */
/* ================================= USBCTRL_DPRAM EP3_OUT_CONTROL ENDPOINT_TYPE [26..27] ================================== */
typedef enum { /*!< USBCTRL_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE */
USBCTRL_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_Control = 0,/*!< Control : Control */
USBCTRL_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_Isochronous = 1,/*!< Isochronous : Isochronous */
USBCTRL_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_Bulk = 2,/*!< Bulk : Bulk */
USBCTRL_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_Interrupt = 3,/*!< Interrupt : Interrupt */
} USBCTRL_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_Enum;
/* ==================================================== EP4_IN_CONTROL ===================================================== */
/* ================================== USBCTRL_DPRAM EP4_IN_CONTROL ENDPOINT_TYPE [26..27] ================================== */
typedef enum { /*!< USBCTRL_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE */
USBCTRL_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_Control = 0,/*!< Control : Control */
USBCTRL_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_Isochronous = 1,/*!< Isochronous : Isochronous */
USBCTRL_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_Bulk = 2,/*!< Bulk : Bulk */
USBCTRL_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_Interrupt = 3,/*!< Interrupt : Interrupt */
} USBCTRL_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_Enum;
/* ==================================================== EP4_OUT_CONTROL ==================================================== */
/* ================================= USBCTRL_DPRAM EP4_OUT_CONTROL ENDPOINT_TYPE [26..27] ================================== */
typedef enum { /*!< USBCTRL_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE */
USBCTRL_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_Control = 0,/*!< Control : Control */
USBCTRL_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_Isochronous = 1,/*!< Isochronous : Isochronous */
USBCTRL_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_Bulk = 2,/*!< Bulk : Bulk */
USBCTRL_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_Interrupt = 3,/*!< Interrupt : Interrupt */
} USBCTRL_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_Enum;
/* ==================================================== EP5_IN_CONTROL ===================================================== */
/* ================================== USBCTRL_DPRAM EP5_IN_CONTROL ENDPOINT_TYPE [26..27] ================================== */
typedef enum { /*!< USBCTRL_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE */
USBCTRL_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_Control = 0,/*!< Control : Control */
USBCTRL_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_Isochronous = 1,/*!< Isochronous : Isochronous */
USBCTRL_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_Bulk = 2,/*!< Bulk : Bulk */
USBCTRL_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_Interrupt = 3,/*!< Interrupt : Interrupt */
} USBCTRL_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_Enum;
/* ==================================================== EP5_OUT_CONTROL ==================================================== */
/* ================================= USBCTRL_DPRAM EP5_OUT_CONTROL ENDPOINT_TYPE [26..27] ================================== */
typedef enum { /*!< USBCTRL_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE */
USBCTRL_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_Control = 0,/*!< Control : Control */
USBCTRL_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_Isochronous = 1,/*!< Isochronous : Isochronous */
USBCTRL_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_Bulk = 2,/*!< Bulk : Bulk */
USBCTRL_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_Interrupt = 3,/*!< Interrupt : Interrupt */
} USBCTRL_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_Enum;
/* ==================================================== EP6_IN_CONTROL ===================================================== */
/* ================================== USBCTRL_DPRAM EP6_IN_CONTROL ENDPOINT_TYPE [26..27] ================================== */
typedef enum { /*!< USBCTRL_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE */
USBCTRL_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_Control = 0,/*!< Control : Control */
USBCTRL_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_Isochronous = 1,/*!< Isochronous : Isochronous */
USBCTRL_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_Bulk = 2,/*!< Bulk : Bulk */
USBCTRL_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_Interrupt = 3,/*!< Interrupt : Interrupt */
} USBCTRL_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_Enum;
/* ==================================================== EP6_OUT_CONTROL ==================================================== */
/* ================================= USBCTRL_DPRAM EP6_OUT_CONTROL ENDPOINT_TYPE [26..27] ================================== */
typedef enum { /*!< USBCTRL_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE */
USBCTRL_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_Control = 0,/*!< Control : Control */
USBCTRL_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_Isochronous = 1,/*!< Isochronous : Isochronous */
USBCTRL_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_Bulk = 2,/*!< Bulk : Bulk */
USBCTRL_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_Interrupt = 3,/*!< Interrupt : Interrupt */
} USBCTRL_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_Enum;
/* ==================================================== EP7_IN_CONTROL ===================================================== */
/* ================================== USBCTRL_DPRAM EP7_IN_CONTROL ENDPOINT_TYPE [26..27] ================================== */
typedef enum { /*!< USBCTRL_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE */
USBCTRL_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_Control = 0,/*!< Control : Control */
USBCTRL_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_Isochronous = 1,/*!< Isochronous : Isochronous */
USBCTRL_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_Bulk = 2,/*!< Bulk : Bulk */
USBCTRL_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_Interrupt = 3,/*!< Interrupt : Interrupt */
} USBCTRL_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_Enum;
/* ==================================================== EP7_OUT_CONTROL ==================================================== */
/* ================================= USBCTRL_DPRAM EP7_OUT_CONTROL ENDPOINT_TYPE [26..27] ================================== */
typedef enum { /*!< USBCTRL_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE */
USBCTRL_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_Control = 0,/*!< Control : Control */
USBCTRL_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_Isochronous = 1,/*!< Isochronous : Isochronous */
USBCTRL_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_Bulk = 2,/*!< Bulk : Bulk */
USBCTRL_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_Interrupt = 3,/*!< Interrupt : Interrupt */
} USBCTRL_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_Enum;
/* ==================================================== EP8_IN_CONTROL ===================================================== */
/* ================================== USBCTRL_DPRAM EP8_IN_CONTROL ENDPOINT_TYPE [26..27] ================================== */
typedef enum { /*!< USBCTRL_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE */
USBCTRL_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_Control = 0,/*!< Control : Control */
USBCTRL_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_Isochronous = 1,/*!< Isochronous : Isochronous */
USBCTRL_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_Bulk = 2,/*!< Bulk : Bulk */
USBCTRL_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_Interrupt = 3,/*!< Interrupt : Interrupt */
} USBCTRL_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_Enum;
/* ==================================================== EP8_OUT_CONTROL ==================================================== */
/* ================================= USBCTRL_DPRAM EP8_OUT_CONTROL ENDPOINT_TYPE [26..27] ================================== */
typedef enum { /*!< USBCTRL_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE */
USBCTRL_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_Control = 0,/*!< Control : Control */
USBCTRL_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_Isochronous = 1,/*!< Isochronous : Isochronous */
USBCTRL_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_Bulk = 2,/*!< Bulk : Bulk */
USBCTRL_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_Interrupt = 3,/*!< Interrupt : Interrupt */
} USBCTRL_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_Enum;
/* ==================================================== EP9_IN_CONTROL ===================================================== */
/* ================================== USBCTRL_DPRAM EP9_IN_CONTROL ENDPOINT_TYPE [26..27] ================================== */
typedef enum { /*!< USBCTRL_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE */
USBCTRL_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_Control = 0,/*!< Control : Control */
USBCTRL_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_Isochronous = 1,/*!< Isochronous : Isochronous */
USBCTRL_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_Bulk = 2,/*!< Bulk : Bulk */
USBCTRL_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_Interrupt = 3,/*!< Interrupt : Interrupt */
} USBCTRL_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_Enum;
/* ==================================================== EP9_OUT_CONTROL ==================================================== */
/* ================================= USBCTRL_DPRAM EP9_OUT_CONTROL ENDPOINT_TYPE [26..27] ================================== */
typedef enum { /*!< USBCTRL_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE */
USBCTRL_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_Control = 0,/*!< Control : Control */
USBCTRL_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_Isochronous = 1,/*!< Isochronous : Isochronous */
USBCTRL_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_Bulk = 2,/*!< Bulk : Bulk */
USBCTRL_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_Interrupt = 3,/*!< Interrupt : Interrupt */
} USBCTRL_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_Enum;
/* ==================================================== EP10_IN_CONTROL ==================================================== */
/* ================================= USBCTRL_DPRAM EP10_IN_CONTROL ENDPOINT_TYPE [26..27] ================================== */
typedef enum { /*!< USBCTRL_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE */
USBCTRL_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_Control = 0,/*!< Control : Control */
USBCTRL_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_Isochronous = 1,/*!< Isochronous : Isochronous */
USBCTRL_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_Bulk = 2,/*!< Bulk : Bulk */
USBCTRL_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_Interrupt = 3,/*!< Interrupt : Interrupt */
} USBCTRL_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_Enum;
/* =================================================== EP10_OUT_CONTROL ==================================================== */
/* ================================= USBCTRL_DPRAM EP10_OUT_CONTROL ENDPOINT_TYPE [26..27] ================================= */
typedef enum { /*!< USBCTRL_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE */
USBCTRL_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_Control = 0,/*!< Control : Control */
USBCTRL_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_Isochronous = 1,/*!< Isochronous : Isochronous */
USBCTRL_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_Bulk = 2,/*!< Bulk : Bulk */
USBCTRL_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_Interrupt = 3,/*!< Interrupt : Interrupt */
} USBCTRL_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_Enum;
/* ==================================================== EP11_IN_CONTROL ==================================================== */
/* ================================= USBCTRL_DPRAM EP11_IN_CONTROL ENDPOINT_TYPE [26..27] ================================== */
typedef enum { /*!< USBCTRL_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE */
USBCTRL_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_Control = 0,/*!< Control : Control */
USBCTRL_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_Isochronous = 1,/*!< Isochronous : Isochronous */
USBCTRL_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_Bulk = 2,/*!< Bulk : Bulk */
USBCTRL_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_Interrupt = 3,/*!< Interrupt : Interrupt */
} USBCTRL_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_Enum;
/* =================================================== EP11_OUT_CONTROL ==================================================== */
/* ================================= USBCTRL_DPRAM EP11_OUT_CONTROL ENDPOINT_TYPE [26..27] ================================= */
typedef enum { /*!< USBCTRL_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE */
USBCTRL_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_Control = 0,/*!< Control : Control */
USBCTRL_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_Isochronous = 1,/*!< Isochronous : Isochronous */
USBCTRL_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_Bulk = 2,/*!< Bulk : Bulk */
USBCTRL_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_Interrupt = 3,/*!< Interrupt : Interrupt */
} USBCTRL_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_Enum;
/* ==================================================== EP12_IN_CONTROL ==================================================== */
/* ================================= USBCTRL_DPRAM EP12_IN_CONTROL ENDPOINT_TYPE [26..27] ================================== */
typedef enum { /*!< USBCTRL_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE */
USBCTRL_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_Control = 0,/*!< Control : Control */
USBCTRL_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_Isochronous = 1,/*!< Isochronous : Isochronous */
USBCTRL_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_Bulk = 2,/*!< Bulk : Bulk */
USBCTRL_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_Interrupt = 3,/*!< Interrupt : Interrupt */
} USBCTRL_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_Enum;
/* =================================================== EP12_OUT_CONTROL ==================================================== */
/* ================================= USBCTRL_DPRAM EP12_OUT_CONTROL ENDPOINT_TYPE [26..27] ================================= */
typedef enum { /*!< USBCTRL_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE */
USBCTRL_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_Control = 0,/*!< Control : Control */
USBCTRL_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_Isochronous = 1,/*!< Isochronous : Isochronous */
USBCTRL_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_Bulk = 2,/*!< Bulk : Bulk */
USBCTRL_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_Interrupt = 3,/*!< Interrupt : Interrupt */
} USBCTRL_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_Enum;
/* ==================================================== EP13_IN_CONTROL ==================================================== */
/* ================================= USBCTRL_DPRAM EP13_IN_CONTROL ENDPOINT_TYPE [26..27] ================================== */
typedef enum { /*!< USBCTRL_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE */
USBCTRL_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_Control = 0,/*!< Control : Control */
USBCTRL_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_Isochronous = 1,/*!< Isochronous : Isochronous */
USBCTRL_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_Bulk = 2,/*!< Bulk : Bulk */
USBCTRL_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_Interrupt = 3,/*!< Interrupt : Interrupt */
} USBCTRL_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_Enum;
/* =================================================== EP13_OUT_CONTROL ==================================================== */
/* ================================= USBCTRL_DPRAM EP13_OUT_CONTROL ENDPOINT_TYPE [26..27] ================================= */
typedef enum { /*!< USBCTRL_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE */
USBCTRL_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_Control = 0,/*!< Control : Control */
USBCTRL_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_Isochronous = 1,/*!< Isochronous : Isochronous */
USBCTRL_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_Bulk = 2,/*!< Bulk : Bulk */
USBCTRL_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_Interrupt = 3,/*!< Interrupt : Interrupt */
} USBCTRL_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_Enum;
/* ==================================================== EP14_IN_CONTROL ==================================================== */
/* ================================= USBCTRL_DPRAM EP14_IN_CONTROL ENDPOINT_TYPE [26..27] ================================== */
typedef enum { /*!< USBCTRL_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE */
USBCTRL_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_Control = 0,/*!< Control : Control */
USBCTRL_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_Isochronous = 1,/*!< Isochronous : Isochronous */
USBCTRL_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_Bulk = 2,/*!< Bulk : Bulk */
USBCTRL_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_Interrupt = 3,/*!< Interrupt : Interrupt */
} USBCTRL_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_Enum;
/* =================================================== EP14_OUT_CONTROL ==================================================== */
/* ================================= USBCTRL_DPRAM EP14_OUT_CONTROL ENDPOINT_TYPE [26..27] ================================= */
typedef enum { /*!< USBCTRL_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE */
USBCTRL_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_Control = 0,/*!< Control : Control */
USBCTRL_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_Isochronous = 1,/*!< Isochronous : Isochronous */
USBCTRL_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_Bulk = 2,/*!< Bulk : Bulk */
USBCTRL_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_Interrupt = 3,/*!< Interrupt : Interrupt */
} USBCTRL_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_Enum;
/* ==================================================== EP15_IN_CONTROL ==================================================== */
/* ================================= USBCTRL_DPRAM EP15_IN_CONTROL ENDPOINT_TYPE [26..27] ================================== */
typedef enum { /*!< USBCTRL_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE */
USBCTRL_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_Control = 0,/*!< Control : Control */
USBCTRL_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_Isochronous = 1,/*!< Isochronous : Isochronous */
USBCTRL_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_Bulk = 2,/*!< Bulk : Bulk */
USBCTRL_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_Interrupt = 3,/*!< Interrupt : Interrupt */
} USBCTRL_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_Enum;
/* =================================================== EP15_OUT_CONTROL ==================================================== */
/* ================================= USBCTRL_DPRAM EP15_OUT_CONTROL ENDPOINT_TYPE [26..27] ================================= */
typedef enum { /*!< USBCTRL_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE */
USBCTRL_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_Control = 0,/*!< Control : Control */
USBCTRL_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_Isochronous = 1,/*!< Isochronous : Isochronous */
USBCTRL_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_Bulk = 2,/*!< Bulk : Bulk */
USBCTRL_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_Interrupt = 3,/*!< Interrupt : Interrupt */
} USBCTRL_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_Enum;
/* ================================================= EP0_IN_BUFFER_CONTROL ================================================= */
/* ========================= USBCTRL_DPRAM EP0_IN_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] ========================= */
typedef enum { /*!< USBCTRL_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */
USBCTRL_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */
USBCTRL_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */
USBCTRL_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */
USBCTRL_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */
} USBCTRL_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum;
/* ================================================ EP0_OUT_BUFFER_CONTROL ================================================= */
/* ======================== USBCTRL_DPRAM EP0_OUT_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] ========================= */
typedef enum { /*!< USBCTRL_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */
USBCTRL_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */
USBCTRL_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */
USBCTRL_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */
USBCTRL_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */
} USBCTRL_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum;
/* ================================================= EP1_IN_BUFFER_CONTROL ================================================= */
/* ========================= USBCTRL_DPRAM EP1_IN_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] ========================= */
typedef enum { /*!< USBCTRL_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */
USBCTRL_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */
USBCTRL_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */
USBCTRL_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */
USBCTRL_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */
} USBCTRL_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum;
/* ================================================ EP1_OUT_BUFFER_CONTROL ================================================= */
/* ======================== USBCTRL_DPRAM EP1_OUT_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] ========================= */
typedef enum { /*!< USBCTRL_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */
USBCTRL_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */
USBCTRL_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */
USBCTRL_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */
USBCTRL_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */
} USBCTRL_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum;
/* ================================================= EP2_IN_BUFFER_CONTROL ================================================= */
/* ========================= USBCTRL_DPRAM EP2_IN_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] ========================= */
typedef enum { /*!< USBCTRL_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */
USBCTRL_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */
USBCTRL_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */
USBCTRL_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */
USBCTRL_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */
} USBCTRL_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum;
/* ================================================ EP2_OUT_BUFFER_CONTROL ================================================= */
/* ======================== USBCTRL_DPRAM EP2_OUT_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] ========================= */
typedef enum { /*!< USBCTRL_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */
USBCTRL_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */
USBCTRL_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */
USBCTRL_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */
USBCTRL_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */
} USBCTRL_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum;
/* ================================================= EP3_IN_BUFFER_CONTROL ================================================= */
/* ========================= USBCTRL_DPRAM EP3_IN_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] ========================= */
typedef enum { /*!< USBCTRL_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */
USBCTRL_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */
USBCTRL_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */
USBCTRL_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */
USBCTRL_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */
} USBCTRL_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum;
/* ================================================ EP3_OUT_BUFFER_CONTROL ================================================= */
/* ======================== USBCTRL_DPRAM EP3_OUT_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] ========================= */
typedef enum { /*!< USBCTRL_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */
USBCTRL_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */
USBCTRL_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */
USBCTRL_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */
USBCTRL_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */
} USBCTRL_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum;
/* ================================================= EP4_IN_BUFFER_CONTROL ================================================= */
/* ========================= USBCTRL_DPRAM EP4_IN_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] ========================= */
typedef enum { /*!< USBCTRL_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */
USBCTRL_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */
USBCTRL_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */
USBCTRL_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */
USBCTRL_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */
} USBCTRL_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum;
/* ================================================ EP4_OUT_BUFFER_CONTROL ================================================= */
/* ======================== USBCTRL_DPRAM EP4_OUT_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] ========================= */
typedef enum { /*!< USBCTRL_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */
USBCTRL_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */
USBCTRL_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */
USBCTRL_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */
USBCTRL_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */
} USBCTRL_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum;
/* ================================================= EP5_IN_BUFFER_CONTROL ================================================= */
/* ========================= USBCTRL_DPRAM EP5_IN_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] ========================= */
typedef enum { /*!< USBCTRL_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */
USBCTRL_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */
USBCTRL_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */
USBCTRL_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */
USBCTRL_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */
} USBCTRL_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum;
/* ================================================ EP5_OUT_BUFFER_CONTROL ================================================= */
/* ======================== USBCTRL_DPRAM EP5_OUT_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] ========================= */
typedef enum { /*!< USBCTRL_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */
USBCTRL_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */
USBCTRL_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */
USBCTRL_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */
USBCTRL_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */
} USBCTRL_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum;
/* ================================================= EP6_IN_BUFFER_CONTROL ================================================= */
/* ========================= USBCTRL_DPRAM EP6_IN_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] ========================= */
typedef enum { /*!< USBCTRL_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */
USBCTRL_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */
USBCTRL_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */
USBCTRL_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */
USBCTRL_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */
} USBCTRL_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum;
/* ================================================ EP6_OUT_BUFFER_CONTROL ================================================= */
/* ======================== USBCTRL_DPRAM EP6_OUT_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] ========================= */
typedef enum { /*!< USBCTRL_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */
USBCTRL_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */
USBCTRL_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */
USBCTRL_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */
USBCTRL_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */
} USBCTRL_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum;
/* ================================================= EP7_IN_BUFFER_CONTROL ================================================= */
/* ========================= USBCTRL_DPRAM EP7_IN_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] ========================= */
typedef enum { /*!< USBCTRL_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */
USBCTRL_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */
USBCTRL_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */
USBCTRL_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */
USBCTRL_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */
} USBCTRL_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum;
/* ================================================ EP7_OUT_BUFFER_CONTROL ================================================= */
/* ======================== USBCTRL_DPRAM EP7_OUT_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] ========================= */
typedef enum { /*!< USBCTRL_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */
USBCTRL_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */
USBCTRL_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */
USBCTRL_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */
USBCTRL_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */
} USBCTRL_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum;
/* ================================================= EP8_IN_BUFFER_CONTROL ================================================= */
/* ========================= USBCTRL_DPRAM EP8_IN_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] ========================= */
typedef enum { /*!< USBCTRL_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */
USBCTRL_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */
USBCTRL_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */
USBCTRL_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */
USBCTRL_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */
} USBCTRL_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum;
/* ================================================ EP8_OUT_BUFFER_CONTROL ================================================= */
/* ======================== USBCTRL_DPRAM EP8_OUT_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] ========================= */
typedef enum { /*!< USBCTRL_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */
USBCTRL_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */
USBCTRL_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */
USBCTRL_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */
USBCTRL_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */
} USBCTRL_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum;
/* ================================================= EP9_IN_BUFFER_CONTROL ================================================= */
/* ========================= USBCTRL_DPRAM EP9_IN_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] ========================= */
typedef enum { /*!< USBCTRL_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */
USBCTRL_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */
USBCTRL_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */
USBCTRL_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */
USBCTRL_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */
} USBCTRL_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum;
/* ================================================ EP9_OUT_BUFFER_CONTROL ================================================= */
/* ======================== USBCTRL_DPRAM EP9_OUT_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] ========================= */
typedef enum { /*!< USBCTRL_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */
USBCTRL_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */
USBCTRL_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */
USBCTRL_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */
USBCTRL_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */
} USBCTRL_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum;
/* ================================================ EP10_IN_BUFFER_CONTROL ================================================= */
/* ======================== USBCTRL_DPRAM EP10_IN_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] ========================= */
typedef enum { /*!< USBCTRL_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */
USBCTRL_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */
USBCTRL_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */
USBCTRL_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */
USBCTRL_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */
} USBCTRL_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum;
/* ================================================ EP10_OUT_BUFFER_CONTROL ================================================ */
/* ======================== USBCTRL_DPRAM EP10_OUT_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] ======================== */
typedef enum { /*!< USBCTRL_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */
USBCTRL_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */
USBCTRL_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */
USBCTRL_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */
USBCTRL_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */
} USBCTRL_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum;
/* ================================================ EP11_IN_BUFFER_CONTROL ================================================= */
/* ======================== USBCTRL_DPRAM EP11_IN_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] ========================= */
typedef enum { /*!< USBCTRL_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */
USBCTRL_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */
USBCTRL_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */
USBCTRL_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */
USBCTRL_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */
} USBCTRL_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum;
/* ================================================ EP11_OUT_BUFFER_CONTROL ================================================ */
/* ======================== USBCTRL_DPRAM EP11_OUT_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] ======================== */
typedef enum { /*!< USBCTRL_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */
USBCTRL_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */
USBCTRL_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */
USBCTRL_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */
USBCTRL_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */
} USBCTRL_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum;
/* ================================================ EP12_IN_BUFFER_CONTROL ================================================= */
/* ======================== USBCTRL_DPRAM EP12_IN_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] ========================= */
typedef enum { /*!< USBCTRL_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */
USBCTRL_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */
USBCTRL_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */
USBCTRL_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */
USBCTRL_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */
} USBCTRL_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum;
/* ================================================ EP12_OUT_BUFFER_CONTROL ================================================ */
/* ======================== USBCTRL_DPRAM EP12_OUT_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] ======================== */
typedef enum { /*!< USBCTRL_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */
USBCTRL_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */
USBCTRL_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */
USBCTRL_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */
USBCTRL_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */
} USBCTRL_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum;
/* ================================================ EP13_IN_BUFFER_CONTROL ================================================= */
/* ======================== USBCTRL_DPRAM EP13_IN_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] ========================= */
typedef enum { /*!< USBCTRL_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */
USBCTRL_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */
USBCTRL_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */
USBCTRL_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */
USBCTRL_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */
} USBCTRL_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum;
/* ================================================ EP13_OUT_BUFFER_CONTROL ================================================ */
/* ======================== USBCTRL_DPRAM EP13_OUT_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] ======================== */
typedef enum { /*!< USBCTRL_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */
USBCTRL_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */
USBCTRL_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */
USBCTRL_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */
USBCTRL_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */
} USBCTRL_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum;
/* ================================================ EP14_IN_BUFFER_CONTROL ================================================= */
/* ======================== USBCTRL_DPRAM EP14_IN_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] ========================= */
typedef enum { /*!< USBCTRL_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */
USBCTRL_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */
USBCTRL_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */
USBCTRL_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */
USBCTRL_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */
} USBCTRL_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum;
/* ================================================ EP14_OUT_BUFFER_CONTROL ================================================ */
/* ======================== USBCTRL_DPRAM EP14_OUT_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] ======================== */
typedef enum { /*!< USBCTRL_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */
USBCTRL_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */
USBCTRL_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */
USBCTRL_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */
USBCTRL_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */
} USBCTRL_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum;
/* ================================================ EP15_IN_BUFFER_CONTROL ================================================= */
/* ======================== USBCTRL_DPRAM EP15_IN_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] ========================= */
typedef enum { /*!< USBCTRL_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */
USBCTRL_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */
USBCTRL_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */
USBCTRL_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */
USBCTRL_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */
} USBCTRL_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum;
/* ================================================ EP15_OUT_BUFFER_CONTROL ================================================ */
/* ======================== USBCTRL_DPRAM EP15_OUT_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] ======================== */
typedef enum { /*!< USBCTRL_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */
USBCTRL_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */
USBCTRL_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */
USBCTRL_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */
USBCTRL_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */
} USBCTRL_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum;
/* =========================================================================================================================== */
/* ================ USBCTRL_REGS ================ */
/* =========================================================================================================================== */
/* ======================================================= ADDR_ENDP ======================================================= */
/* ====================================================== ADDR_ENDP1 ======================================================= */
/* ====================================================== ADDR_ENDP2 ======================================================= */
/* ====================================================== ADDR_ENDP3 ======================================================= */
/* ====================================================== ADDR_ENDP4 ======================================================= */
/* ====================================================== ADDR_ENDP5 ======================================================= */
/* ====================================================== ADDR_ENDP6 ======================================================= */
/* ====================================================== ADDR_ENDP7 ======================================================= */
/* ====================================================== ADDR_ENDP8 ======================================================= */
/* ====================================================== ADDR_ENDP9 ======================================================= */
/* ====================================================== ADDR_ENDP10 ====================================================== */
/* ====================================================== ADDR_ENDP11 ====================================================== */
/* ====================================================== ADDR_ENDP12 ====================================================== */
/* ====================================================== ADDR_ENDP13 ====================================================== */
/* ====================================================== ADDR_ENDP14 ====================================================== */
/* ====================================================== ADDR_ENDP15 ====================================================== */
/* ======================================================= MAIN_CTRL ======================================================= */
/* ======================================================== SOF_WR ========================================================= */
/* ======================================================== SOF_RD ========================================================= */
/* ======================================================= SIE_CTRL ======================================================== */
/* ====================================================== SIE_STATUS ======================================================= */
/* ====================================================== INT_EP_CTRL ====================================================== */
/* ====================================================== BUFF_STATUS ====================================================== */
/* ================================================ BUFF_CPU_SHOULD_HANDLE ================================================= */
/* ======================================================= EP_ABORT ======================================================== */
/* ===================================================== EP_ABORT_DONE ===================================================== */
/* ===================================================== EP_STALL_ARM ====================================================== */
/* ======================================================= NAK_POLL ======================================================== */
/* ================================================== EP_STATUS_STALL_NAK ================================================== */
/* ====================================================== USB_MUXING ======================================================= */
/* ======================================================== USB_PWR ======================================================== */
/* ===================================================== USBPHY_DIRECT ===================================================== */
/* ================================================ USBPHY_DIRECT_OVERRIDE ================================================= */
/* ====================================================== USBPHY_TRIM ====================================================== */
/* ========================================================= INTR ========================================================== */
/* ========================================================= INTE ========================================================== */
/* ========================================================= INTF ========================================================== */
/* ========================================================= INTS ========================================================== */
/* =========================================================================================================================== */
/* ================ PIO0 ================ */
/* =========================================================================================================================== */
/* ========================================================= CTRL ========================================================== */
/* ========================================================= FSTAT ========================================================= */
/* ======================================================== FDEBUG ========================================================= */
/* ======================================================== FLEVEL ========================================================= */
/* ========================================================= TXF0 ========================================================== */
/* ========================================================= TXF1 ========================================================== */
/* ========================================================= TXF2 ========================================================== */
/* ========================================================= TXF3 ========================================================== */
/* ========================================================= RXF0 ========================================================== */
/* ========================================================= RXF1 ========================================================== */
/* ========================================================= RXF2 ========================================================== */
/* ========================================================= RXF3 ========================================================== */
/* ========================================================== IRQ ========================================================== */
/* ======================================================= IRQ_FORCE ======================================================= */
/* =================================================== INPUT_SYNC_BYPASS =================================================== */
/* ====================================================== DBG_PADOUT ======================================================= */
/* ======================================================= DBG_PADOE ======================================================= */
/* ====================================================== DBG_CFGINFO ====================================================== */
/* ====================================================== INSTR_MEM0 ======================================================= */
/* ====================================================== INSTR_MEM1 ======================================================= */
/* ====================================================== INSTR_MEM2 ======================================================= */
/* ====================================================== INSTR_MEM3 ======================================================= */
/* ====================================================== INSTR_MEM4 ======================================================= */
/* ====================================================== INSTR_MEM5 ======================================================= */
/* ====================================================== INSTR_MEM6 ======================================================= */
/* ====================================================== INSTR_MEM7 ======================================================= */
/* ====================================================== INSTR_MEM8 ======================================================= */
/* ====================================================== INSTR_MEM9 ======================================================= */
/* ====================================================== INSTR_MEM10 ====================================================== */
/* ====================================================== INSTR_MEM11 ====================================================== */
/* ====================================================== INSTR_MEM12 ====================================================== */
/* ====================================================== INSTR_MEM13 ====================================================== */
/* ====================================================== INSTR_MEM14 ====================================================== */
/* ====================================================== INSTR_MEM15 ====================================================== */
/* ====================================================== INSTR_MEM16 ====================================================== */
/* ====================================================== INSTR_MEM17 ====================================================== */
/* ====================================================== INSTR_MEM18 ====================================================== */
/* ====================================================== INSTR_MEM19 ====================================================== */
/* ====================================================== INSTR_MEM20 ====================================================== */
/* ====================================================== INSTR_MEM21 ====================================================== */
/* ====================================================== INSTR_MEM22 ====================================================== */
/* ====================================================== INSTR_MEM23 ====================================================== */
/* ====================================================== INSTR_MEM24 ====================================================== */
/* ====================================================== INSTR_MEM25 ====================================================== */
/* ====================================================== INSTR_MEM26 ====================================================== */
/* ====================================================== INSTR_MEM27 ====================================================== */
/* ====================================================== INSTR_MEM28 ====================================================== */
/* ====================================================== INSTR_MEM29 ====================================================== */
/* ====================================================== INSTR_MEM30 ====================================================== */
/* ====================================================== INSTR_MEM31 ====================================================== */
/* ====================================================== SM0_CLKDIV ======================================================= */
/* ===================================================== SM0_EXECCTRL ====================================================== */
/* ========================================== PIO0 SM0_EXECCTRL STATUS_SEL [4..4] ========================================== */
typedef enum { /*!< PIO0_SM0_EXECCTRL_STATUS_SEL */
PIO0_SM0_EXECCTRL_STATUS_SEL_TXLEVEL = 0, /*!< TXLEVEL : All-ones if TX FIFO level < N, otherwise all-zeroes */
PIO0_SM0_EXECCTRL_STATUS_SEL_RXLEVEL = 1, /*!< RXLEVEL : All-ones if RX FIFO level < N, otherwise all-zeroes */
} PIO0_SM0_EXECCTRL_STATUS_SEL_Enum;
/* ===================================================== SM0_SHIFTCTRL ===================================================== */
/* ======================================================= SM0_ADDR ======================================================== */
/* ======================================================= SM0_INSTR ======================================================= */
/* ====================================================== SM0_PINCTRL ====================================================== */
/* ====================================================== SM1_CLKDIV ======================================================= */
/* ===================================================== SM1_EXECCTRL ====================================================== */
/* ========================================== PIO0 SM1_EXECCTRL STATUS_SEL [4..4] ========================================== */
typedef enum { /*!< PIO0_SM1_EXECCTRL_STATUS_SEL */
PIO0_SM1_EXECCTRL_STATUS_SEL_TXLEVEL = 0, /*!< TXLEVEL : All-ones if TX FIFO level < N, otherwise all-zeroes */
PIO0_SM1_EXECCTRL_STATUS_SEL_RXLEVEL = 1, /*!< RXLEVEL : All-ones if RX FIFO level < N, otherwise all-zeroes */
} PIO0_SM1_EXECCTRL_STATUS_SEL_Enum;
/* ===================================================== SM1_SHIFTCTRL ===================================================== */
/* ======================================================= SM1_ADDR ======================================================== */
/* ======================================================= SM1_INSTR ======================================================= */
/* ====================================================== SM1_PINCTRL ====================================================== */
/* ====================================================== SM2_CLKDIV ======================================================= */
/* ===================================================== SM2_EXECCTRL ====================================================== */
/* ========================================== PIO0 SM2_EXECCTRL STATUS_SEL [4..4] ========================================== */
typedef enum { /*!< PIO0_SM2_EXECCTRL_STATUS_SEL */
PIO0_SM2_EXECCTRL_STATUS_SEL_TXLEVEL = 0, /*!< TXLEVEL : All-ones if TX FIFO level < N, otherwise all-zeroes */
PIO0_SM2_EXECCTRL_STATUS_SEL_RXLEVEL = 1, /*!< RXLEVEL : All-ones if RX FIFO level < N, otherwise all-zeroes */
} PIO0_SM2_EXECCTRL_STATUS_SEL_Enum;
/* ===================================================== SM2_SHIFTCTRL ===================================================== */
/* ======================================================= SM2_ADDR ======================================================== */
/* ======================================================= SM2_INSTR ======================================================= */
/* ====================================================== SM2_PINCTRL ====================================================== */
/* ====================================================== SM3_CLKDIV ======================================================= */
/* ===================================================== SM3_EXECCTRL ====================================================== */
/* ========================================== PIO0 SM3_EXECCTRL STATUS_SEL [4..4] ========================================== */
typedef enum { /*!< PIO0_SM3_EXECCTRL_STATUS_SEL */
PIO0_SM3_EXECCTRL_STATUS_SEL_TXLEVEL = 0, /*!< TXLEVEL : All-ones if TX FIFO level < N, otherwise all-zeroes */
PIO0_SM3_EXECCTRL_STATUS_SEL_RXLEVEL = 1, /*!< RXLEVEL : All-ones if RX FIFO level < N, otherwise all-zeroes */
} PIO0_SM3_EXECCTRL_STATUS_SEL_Enum;
/* ===================================================== SM3_SHIFTCTRL ===================================================== */
/* ======================================================= SM3_ADDR ======================================================== */
/* ======================================================= SM3_INSTR ======================================================= */
/* ====================================================== SM3_PINCTRL ====================================================== */
/* ========================================================= INTR ========================================================== */
/* ======================================================= IRQ0_INTE ======================================================= */
/* ======================================================= IRQ0_INTF ======================================================= */
/* ======================================================= IRQ0_INTS ======================================================= */
/* ======================================================= IRQ1_INTE ======================================================= */
/* ======================================================= IRQ1_INTF ======================================================= */
/* ======================================================= IRQ1_INTS ======================================================= */
/* =========================================================================================================================== */
/* ================ SIO ================ */
/* =========================================================================================================================== */
/* ========================================================= CPUID ========================================================= */
/* ======================================================== GPIO_IN ======================================================== */
/* ====================================================== GPIO_HI_IN ======================================================= */
/* ======================================================= GPIO_OUT ======================================================== */
/* ===================================================== GPIO_OUT_SET ====================================================== */
/* ===================================================== GPIO_OUT_CLR ====================================================== */
/* ===================================================== GPIO_OUT_XOR ====================================================== */
/* ======================================================== GPIO_OE ======================================================== */
/* ====================================================== GPIO_OE_SET ====================================================== */
/* ====================================================== GPIO_OE_CLR ====================================================== */
/* ====================================================== GPIO_OE_XOR ====================================================== */
/* ====================================================== GPIO_HI_OUT ====================================================== */
/* ==================================================== GPIO_HI_OUT_SET ==================================================== */
/* ==================================================== GPIO_HI_OUT_CLR ==================================================== */
/* ==================================================== GPIO_HI_OUT_XOR ==================================================== */
/* ====================================================== GPIO_HI_OE ======================================================= */
/* ==================================================== GPIO_HI_OE_SET ===================================================== */
/* ==================================================== GPIO_HI_OE_CLR ===================================================== */
/* ==================================================== GPIO_HI_OE_XOR ===================================================== */
/* ======================================================== FIFO_ST ======================================================== */
/* ======================================================== FIFO_WR ======================================================== */
/* ======================================================== FIFO_RD ======================================================== */
/* ====================================================== SPINLOCK_ST ====================================================== */
/* ===================================================== DIV_UDIVIDEND ===================================================== */
/* ===================================================== DIV_UDIVISOR ====================================================== */
/* ===================================================== DIV_SDIVIDEND ===================================================== */
/* ===================================================== DIV_SDIVISOR ====================================================== */
/* ===================================================== DIV_QUOTIENT ====================================================== */
/* ===================================================== DIV_REMAINDER ===================================================== */
/* ======================================================== DIV_CSR ======================================================== */
/* ==================================================== INTERP0_ACCUM0 ===================================================== */
/* ==================================================== INTERP0_ACCUM1 ===================================================== */
/* ===================================================== INTERP0_BASE0 ===================================================== */
/* ===================================================== INTERP0_BASE1 ===================================================== */
/* ===================================================== INTERP0_BASE2 ===================================================== */
/* =================================================== INTERP0_POP_LANE0 =================================================== */
/* =================================================== INTERP0_POP_LANE1 =================================================== */
/* =================================================== INTERP0_POP_FULL ==================================================== */
/* ================================================== INTERP0_PEEK_LANE0 =================================================== */
/* ================================================== INTERP0_PEEK_LANE1 =================================================== */
/* =================================================== INTERP0_PEEK_FULL =================================================== */
/* ================================================== INTERP0_CTRL_LANE0 =================================================== */
/* ================================================== INTERP0_CTRL_LANE1 =================================================== */
/* ================================================== INTERP0_ACCUM0_ADD =================================================== */
/* ================================================== INTERP0_ACCUM1_ADD =================================================== */
/* ================================================== INTERP0_BASE_1AND0 =================================================== */
/* ==================================================== INTERP1_ACCUM0 ===================================================== */
/* ==================================================== INTERP1_ACCUM1 ===================================================== */
/* ===================================================== INTERP1_BASE0 ===================================================== */
/* ===================================================== INTERP1_BASE1 ===================================================== */
/* ===================================================== INTERP1_BASE2 ===================================================== */
/* =================================================== INTERP1_POP_LANE0 =================================================== */
/* =================================================== INTERP1_POP_LANE1 =================================================== */
/* =================================================== INTERP1_POP_FULL ==================================================== */
/* ================================================== INTERP1_PEEK_LANE0 =================================================== */
/* ================================================== INTERP1_PEEK_LANE1 =================================================== */
/* =================================================== INTERP1_PEEK_FULL =================================================== */
/* ================================================== INTERP1_CTRL_LANE0 =================================================== */
/* ================================================== INTERP1_CTRL_LANE1 =================================================== */
/* ================================================== INTERP1_ACCUM0_ADD =================================================== */
/* ================================================== INTERP1_ACCUM1_ADD =================================================== */
/* ================================================== INTERP1_BASE_1AND0 =================================================== */
/* ======================================================= SPINLOCK0 ======================================================= */
/* ======================================================= SPINLOCK1 ======================================================= */
/* ======================================================= SPINLOCK2 ======================================================= */
/* ======================================================= SPINLOCK3 ======================================================= */
/* ======================================================= SPINLOCK4 ======================================================= */
/* ======================================================= SPINLOCK5 ======================================================= */
/* ======================================================= SPINLOCK6 ======================================================= */
/* ======================================================= SPINLOCK7 ======================================================= */
/* ======================================================= SPINLOCK8 ======================================================= */
/* ======================================================= SPINLOCK9 ======================================================= */
/* ====================================================== SPINLOCK10 ======================================================= */
/* ====================================================== SPINLOCK11 ======================================================= */
/* ====================================================== SPINLOCK12 ======================================================= */
/* ====================================================== SPINLOCK13 ======================================================= */
/* ====================================================== SPINLOCK14 ======================================================= */
/* ====================================================== SPINLOCK15 ======================================================= */
/* ====================================================== SPINLOCK16 ======================================================= */
/* ====================================================== SPINLOCK17 ======================================================= */
/* ====================================================== SPINLOCK18 ======================================================= */
/* ====================================================== SPINLOCK19 ======================================================= */
/* ====================================================== SPINLOCK20 ======================================================= */
/* ====================================================== SPINLOCK21 ======================================================= */
/* ====================================================== SPINLOCK22 ======================================================= */
/* ====================================================== SPINLOCK23 ======================================================= */
/* ====================================================== SPINLOCK24 ======================================================= */
/* ====================================================== SPINLOCK25 ======================================================= */
/* ====================================================== SPINLOCK26 ======================================================= */
/* ====================================================== SPINLOCK27 ======================================================= */
/* ====================================================== SPINLOCK28 ======================================================= */
/* ====================================================== SPINLOCK29 ======================================================= */
/* ====================================================== SPINLOCK30 ======================================================= */
/* ====================================================== SPINLOCK31 ======================================================= */
/* =========================================================================================================================== */
/* ================ PPB ================ */
/* =========================================================================================================================== */
/* ======================================================= SYST_CSR ======================================================== */
/* ======================================================= SYST_RVR ======================================================== */
/* ======================================================= SYST_CVR ======================================================== */
/* ====================================================== SYST_CALIB ======================================================= */
/* ======================================================= NVIC_ISER ======================================================= */
/* ======================================================= NVIC_ICER ======================================================= */
/* ======================================================= NVIC_ISPR ======================================================= */
/* ======================================================= NVIC_ICPR ======================================================= */
/* ======================================================= NVIC_IPR0 ======================================================= */
/* ======================================================= NVIC_IPR1 ======================================================= */
/* ======================================================= NVIC_IPR2 ======================================================= */
/* ======================================================= NVIC_IPR3 ======================================================= */
/* ======================================================= NVIC_IPR4 ======================================================= */
/* ======================================================= NVIC_IPR5 ======================================================= */
/* ======================================================= NVIC_IPR6 ======================================================= */
/* ======================================================= NVIC_IPR7 ======================================================= */
/* ========================================================= CPUID ========================================================= */
/* ========================================================= ICSR ========================================================== */
/* ========================================================= VTOR ========================================================== */
/* ========================================================= AIRCR ========================================================= */
/* ========================================================== SCR ========================================================== */
/* ========================================================== CCR ========================================================== */
/* ========================================================= SHPR2 ========================================================= */
/* ========================================================= SHPR3 ========================================================= */
/* ========================================================= SHCSR ========================================================= */
/* ======================================================= MPU_TYPE ======================================================== */
/* ======================================================= MPU_CTRL ======================================================== */
/* ======================================================== MPU_RNR ======================================================== */
/* ======================================================= MPU_RBAR ======================================================== */
/* ======================================================= MPU_RASR ======================================================== */
/** @} */ /* End of group EnumValue_peripherals */
#ifdef __cplusplus
}
#endif
#endif /* RP2040_H */
/** @} */ /* End of group RP2040 */
/** @} */ /* End of group Raspberry Pi */
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