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https://github.com/RIOT-OS/RIOT.git
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eb0f6582c7
Deep-sleep was based on using rx pin as external interrupt to be able to wake up from stop mode. If rx pin cannot be used as interrupt or user does not need to wake up from stop from the CAN, an option is now present. If en_deep_sleep_wake_up is set to false, setting the device to sleep simply unblock stop mode. Otherwise the behavior is unchanged.
206 lines
6.7 KiB
C
206 lines
6.7 KiB
C
/*
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* Copyright (C) 2016 OTA keys S.A.
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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*/
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/**
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* @ingroup cpu_stm32
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* @ingroup drivers_can
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* @defgroup candev_stm32 STM32 CAN controller
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* @brief STM32 CAN controller driver (bxCAN)
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*
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* The STM32Fx microcontroller can have an integrated CAN controller (bxCAN)
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*
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* This driver has been tested with a STM32F0,STM32F2 and STM32F4 MCU
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* but should work on others.
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*
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* The default bitrate is set to 500 kbps and the default sample point is set to
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* 87.5%.
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* @{
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*
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* @file
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* @brief bxCAN specific definitions
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*
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* @author Vincent Dupont <vincent@otakeys.com>
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* @}
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*/
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#ifndef CANDEV_STM32_H
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#define CANDEV_STM32_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include "can/candev.h"
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#if defined(CPU_LINE_STM32F413xx) || defined(CPU_LINE_STM32F423xx)
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#define CANDEV_STM32_CHAN_NUMOF 3
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#elif defined(CPU_FAM_STM32F1) || defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4)
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#define CANDEV_STM32_CHAN_NUMOF 2
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#elif defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F3) || \
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defined(CPU_FAM_STM32L4) || DOXYGEN
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/** Number of channels in the device (up to 3) */
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#define CANDEV_STM32_CHAN_NUMOF 1
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#else
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#error "CAN STM32: CPU not supported"
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#endif
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/**
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* @name ISR functions
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* @{
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*/
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#if defined(CPU_FAM_STM32F1)
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#define ISR_CAN1_TX isr_usb_hp_can1_tx
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#define ISR_CAN1_RX0 isr_usb_lp_can1_rx0
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#define ISR_CAN1_RX1 isr_can1_rx1
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#define ISR_CAN1_SCE isr_can1_sce
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#else
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#define ISR_CAN1_TX isr_can1_tx
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#define ISR_CAN1_RX0 isr_can1_rx0
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#define ISR_CAN1_RX1 isr_can1_rx1
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#define ISR_CAN1_SCE isr_can1_sce
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#define ISR_CAN2_TX isr_can2_tx
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#define ISR_CAN2_RX0 isr_can2_rx0
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#define ISR_CAN2_RX1 isr_can2_rx1
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#define ISR_CAN2_SCE isr_can2_sce
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#define ISR_CAN3_TX isr_can3_tx
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#define ISR_CAN3_RX0 isr_can3_rx0
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#define ISR_CAN3_RX1 isr_can3_rx1
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#define ISR_CAN3_SCE isr_can3_sce
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#endif
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/** @} */
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#if CANDEV_STM32_CHAN_NUMOF > 1 || DOXYGEN
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/** The maximum number of filters: 28 for dual channel, 14 for single channel */
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#define CAN_STM32_NB_FILTER 28
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#else
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#define CAN_STM32_NB_FILTER 14
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#endif
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#ifndef CANDEV_STM32_DEFAULT_BITRATE
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/** Default bitrate */
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#define CANDEV_STM32_DEFAULT_BITRATE 500000U
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#endif
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#ifndef CANDEV_STM32_DEFAULT_SPT
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/** Default sampling-point */
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#define CANDEV_STM32_DEFAULT_SPT 875
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#endif
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/** bxCAN device configuration */
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typedef struct {
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CAN_TypeDef *can; /**< CAN device */
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uint32_t rcc_mask; /**< RCC mask to enable clock */
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gpio_t rx_pin; /**< RX pin */
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gpio_t tx_pin; /**< TX pin */
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#ifndef CPU_FAM_STM32F1
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gpio_af_t af; /**< Alternate pin function to use */
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#endif
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bool en_deep_sleep_wake_up; /**< Enable deep-sleep wake-up interrupt */
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#if CANDEV_STM32_CHAN_NUMOF > 1 || defined(DOXYGEN)
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CAN_TypeDef *can_master; /**< Master CAN device */
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uint32_t master_rcc_mask; /**< Master device RCC mask */
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/** First filter in the bank. For a master channel it must be 0.
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* For a slave channel, it is used without checking with the master channel,
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* beware bot to overwrite the master config. */
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uint8_t first_filter;
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/** Number of filters to use. Must be less or equal
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* to CAN_STM32_NB_FILTER - first_filter */
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uint8_t nb_filters;
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#endif
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#if defined(CPU_FAM_STM32F0)
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uint8_t irqn; /**< CAN common IRQ channel */
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#else
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uint8_t tx_irqn; /**< TX IRQ channel */
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uint8_t rx0_irqn; /**< RX0 IRQ channel */
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uint8_t rx1_irqn; /**< RX1 IRQ channel */
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uint8_t sce_irqn; /**< SCE IRQ channel */
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#endif
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uint8_t ttcm : 1; /**< Time triggered communication mode */
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uint8_t abom : 1; /**< Automatic bus-off management */
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uint8_t awum : 1; /**< Automatic wakeup mode */
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uint8_t nart : 1; /**< No automatic retransmission */
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uint8_t rflm : 1; /**< Receive FIFO locked mode */
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uint8_t txfp : 1; /**< Transmit FIFO priority */
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uint8_t lbkm : 1; /**< Loopback mode */
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uint8_t silm : 1; /**< Silent mode */
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} can_conf_t;
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/** can_conf_t is re-defined */
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#define HAVE_CAN_CONF_T
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/** The number of transmit mailboxes */
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#define CAN_STM32_TX_MAILBOXES 3
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/** The number of receive FIFO */
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#define CAN_STM32_RX_MAILBOXES 2
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#ifndef CAN_STM32_RX_MAIL_FIFO
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/** This is the maximum number of frame the driver can receive simultaneously */
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#define CAN_STM32_RX_MAIL_FIFO 12
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#endif
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/** bxCAN candev descriptor */
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typedef struct can can_t;
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/** can_t is re-defined */
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#define HAVE_CAN_T
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/** This structure holds anything related to the receive part */
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typedef struct candev_stm32_rx_fifo {
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struct can_frame frame[CAN_STM32_RX_MAIL_FIFO]; /**< Receive FIFO */
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int write_idx; /**< Write index in the receive FIFO */
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int read_idx; /**< Read index in the receive FIFO*/
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int is_full; /**< Flag set when the FIFO is full */
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} candev_stm32_rx_fifo_t;
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/** Internal interrupt flags */
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typedef struct candev_stm32_isr {
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int isr_tx : 3; /**< Tx mailboxes interrupt */
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int isr_rx : 2; /**< Rx FIFO interrupt */
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int isr_wkup : 1; /**< Wake up interrupt */
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} candev_stm32_isr_t;
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/** STM32 CAN device descriptor */
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struct can {
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candev_t candev; /**< Common candev struct */
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const can_conf_t *conf; /**< Configuration */
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gpio_t rx_pin; /**< RX pin */
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gpio_t tx_pin; /**< TX pin */
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gpio_af_t af; /**< Alternate pin function to use */
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/** Tx mailboxes */
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const struct can_frame *tx_mailbox[CAN_STM32_TX_MAILBOXES];
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candev_stm32_rx_fifo_t rx_fifo; /**< Rx FIFOs */
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candev_stm32_isr_t isr_flags; /**< ISR flags */
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};
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#ifndef CPU_FAM_STM32F1
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/**
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* @brief Set the pins of an stm32 CAN device
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*
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* @param[in,out] dev the device to set pins
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* @param[in] tx_pin tx pin
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* @param[in] rx_pin rx pin
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* @param[in] af alternate function
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*/
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void candev_stm32_set_pins(can_t *dev, gpio_t tx_pin, gpio_t rx_pin,
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gpio_af_t af);
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#else
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/**
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* @brief Set the pins of an stm32 CAN device
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*
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* @param[in,out] dev the device to set pins
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* @param[in] tx_pin tx pin
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* @param[in] rx_pin rx pin
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*/
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void candev_stm32_set_pins(can_t *dev, gpio_t tx_pin, gpio_t rx_pin);
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#endif
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#ifdef __cplusplus
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}
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#endif
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#endif /* CANDEV_STM32_H */
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