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96 lines
5.2 KiB
C
96 lines
5.2 KiB
C
/**
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* \file
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*
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* \brief Instance description for DAC
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*
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* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
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*
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* \asf_license_start
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*
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* \page License
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. The name of Atmel may not be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* 4. This software may only be redistributed and used in connection with an
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* Atmel microcontroller product.
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*
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* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* \asf_license_stop
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*
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*/
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/*
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* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
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*/
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#ifndef _SAML21_DAC_INSTANCE_
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#define _SAML21_DAC_INSTANCE_
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/* ========== Register definition for DAC peripheral ========== */
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#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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#define REG_DAC_CTRLA (0x42003000U) /**< \brief (DAC) Control A */
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#define REG_DAC_CTRLB (0x42003001U) /**< \brief (DAC) Control B */
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#define REG_DAC_EVCTRL (0x42003002U) /**< \brief (DAC) Event Control */
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#define REG_DAC_INTENCLR (0x42003004U) /**< \brief (DAC) Interrupt Enable Clear */
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#define REG_DAC_INTENSET (0x42003005U) /**< \brief (DAC) Interrupt Enable Set */
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#define REG_DAC_INTFLAG (0x42003006U) /**< \brief (DAC) Interrupt Flag Status and Clear */
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#define REG_DAC_STATUS (0x42003007U) /**< \brief (DAC) Status */
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#define REG_DAC_SYNCBUSY (0x42003008U) /**< \brief (DAC) Synchronization Busy */
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#define REG_DAC_DACCTRL0 (0x4200300CU) /**< \brief (DAC) DAC 0 Control */
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#define REG_DAC_DACCTRL1 (0x4200300EU) /**< \brief (DAC) DAC 1 Control */
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#define REG_DAC_DATA0 (0x42003010U) /**< \brief (DAC) DAC 0 Data */
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#define REG_DAC_DATA1 (0x42003012U) /**< \brief (DAC) DAC 1 Data */
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#define REG_DAC_DATABUF0 (0x42003014U) /**< \brief (DAC) DAC 0 Data Buffer */
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#define REG_DAC_DATABUF1 (0x42003016U) /**< \brief (DAC) DAC 1 Data Buffer */
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#define REG_DAC_DBGCTRL (0x42003018U) /**< \brief (DAC) Debug Control */
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#else
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#define REG_DAC_CTRLA (*(RwReg8 *)0x42003000U) /**< \brief (DAC) Control A */
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#define REG_DAC_CTRLB (*(RwReg8 *)0x42003001U) /**< \brief (DAC) Control B */
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#define REG_DAC_EVCTRL (*(RwReg8 *)0x42003002U) /**< \brief (DAC) Event Control */
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#define REG_DAC_INTENCLR (*(RwReg8 *)0x42003004U) /**< \brief (DAC) Interrupt Enable Clear */
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#define REG_DAC_INTENSET (*(RwReg8 *)0x42003005U) /**< \brief (DAC) Interrupt Enable Set */
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#define REG_DAC_INTFLAG (*(RwReg8 *)0x42003006U) /**< \brief (DAC) Interrupt Flag Status and Clear */
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#define REG_DAC_STATUS (*(RoReg8 *)0x42003007U) /**< \brief (DAC) Status */
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#define REG_DAC_SYNCBUSY (*(RoReg *)0x42003008U) /**< \brief (DAC) Synchronization Busy */
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#define REG_DAC_DACCTRL0 (*(RwReg16*)0x4200300CU) /**< \brief (DAC) DAC 0 Control */
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#define REG_DAC_DACCTRL1 (*(RwReg16*)0x4200300EU) /**< \brief (DAC) DAC 1 Control */
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#define REG_DAC_DATA0 (*(WoReg16*)0x42003010U) /**< \brief (DAC) DAC 0 Data */
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#define REG_DAC_DATA1 (*(WoReg16*)0x42003012U) /**< \brief (DAC) DAC 1 Data */
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#define REG_DAC_DATABUF0 (*(WoReg16*)0x42003014U) /**< \brief (DAC) DAC 0 Data Buffer */
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#define REG_DAC_DATABUF1 (*(WoReg16*)0x42003016U) /**< \brief (DAC) DAC 1 Data Buffer */
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#define REG_DAC_DBGCTRL (*(RwReg8 *)0x42003018U) /**< \brief (DAC) Debug Control */
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#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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/* ========== Instance parameters for DAC peripheral ========== */
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#define DAC_DAC_NUM 2 // Number of DACs
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#define DAC_DATA_SIZE 12 // Number of bits in data
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#define DAC_DMAC_ID_EMPTY_0 38
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#define DAC_DMAC_ID_EMPTY_1 39
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#define DAC_DMAC_ID_EMPTY_LSB 38
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#define DAC_DMAC_ID_EMPTY_MSB 39
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#define DAC_DMAC_ID_EMPTY_SIZE 2
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#define DAC_GCLK_ID 32 // Index of Generic Clock
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#endif /* _SAML21_DAC_INSTANCE_ */
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