mirror of
https://github.com/RIOT-OS/RIOT.git
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252 lines
7.9 KiB
C
252 lines
7.9 KiB
C
/*
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* Copyright (C) 2014 Freie Universität Berlin
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup boards_stm32f3discovery
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* @{
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*
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* @file
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* @brief Peripheral MCU configuration for the STM32F3discovery board
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*
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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*/
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#ifndef PERIPH_CONF_H_
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#define PERIPH_CONF_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @name Clock system configuration
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* @{
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*/
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#define CLOCK_HSE (8000000U) /* external oscillator */
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#define CLOCK_CORECLOCK (72000000U) /* desired core clock frequency */
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/* the actual PLL values are automatically generated */
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#define CLOCK_PLL_MUL (CLOCK_CORECLOCK / CLOCK_HSE)
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#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
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#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1
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#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2
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#define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY_1
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/** @} */
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/**
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* @brief Timer configuration
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* @{
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*/
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#define TIMER_NUMOF (1U)
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#define TIMER_0_EN 1
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#define TIMER_IRQ_PRIO 1
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/* Timer 0 configuration */
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#define TIMER_0_DEV TIM2
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#define TIMER_0_CHANNELS 4
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#define TIMER_0_PRESCALER (71U)
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#define TIMER_0_MAX_VALUE (0xffffffff)
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#define TIMER_0_CLKEN() (RCC->APB1ENR |= RCC_APB1ENR_TIM2EN)
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#define TIMER_0_ISR isr_tim2
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#define TIMER_0_IRQ_CHAN TIM2_IRQn
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/** @} */
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/**
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* @brief UART configuration
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* @{
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*/
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#define UART_NUMOF (3U)
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#define UART_0_EN 1
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#define UART_1_EN 1
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#define UART_2_EN 1
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#define UART_IRQ_PRIO 1
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/* UART 0 device configuration */
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#define UART_0_DEV USART1
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#define UART_0_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_USART1EN)
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#define UART_0_CLK (CLOCK_CORECLOCK / 1) /* UART clock runs with 72MHz (F_CPU / 1) */
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#define UART_0_IRQ_CHAN USART1_IRQn
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#define UART_0_ISR isr_usart1
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/* UART 0 pin configuration */
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#define UART_0_PORT_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIOAEN)
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#define UART_0_PORT GPIOA
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#define UART_0_TX_PIN 9
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#define UART_0_RX_PIN 10
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#define UART_0_AF 7
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/* UART 1 device configuration */
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#define UART_1_DEV USART2
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#define UART_1_CLKEN() (RCC->APB1ENR |= RCC_APB1ENR_USART2EN)
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#define UART_1_CLK (CLOCK_CORECLOCK / 2) /* UART clock runs with 36MHz (F_CPU / 2) */
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#define UART_1_IRQ_CHAN USART2_IRQn
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#define UART_1_ISR isr_usart2
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/* UART 1 pin configuration */
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#define UART_1_PORT_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIODEN)
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#define UART_1_PORT GPIOD
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#define UART_1_TX_PIN 5
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#define UART_1_RX_PIN 6
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#define UART_1_AF 7
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/* UART 1 device configuration */
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#define UART_2_DEV USART3
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#define UART_2_CLKEN() (RCC->APB1ENR |= RCC_APB1ENR_USART3EN)
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#define UART_2_CLK (CLOCK_CORECLOCK / 2) /* UART clock runs with 36MHz (F_CPU / 2) */
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#define UART_2_IRQ_CHAN USART3_IRQn
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#define UART_2_ISR isr_usart3
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/* UART 1 pin configuration */
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#define UART_2_PORT_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIODEN)
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#define UART_2_PORT GPIOD
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#define UART_2_TX_PIN 8
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#define UART_2_RX_PIN 9
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#define UART_2_AF 7
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/** @} */
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/**
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* @brief PWM configuration
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* @{
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*/
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#define PWM_NUMOF (1U)
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#define PWM_0_EN 1
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#define PWM_1_EN 1
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#define PWM_MAX_CHANNELS 4
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/* PWM 0 device configuration */
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#define PWM_0_DEV TIM3
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#define PWM_0_CHANNELS 4
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#define PWM_0_CLK (36000000U)
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#define PWM_0_CLKEN() (RCC->APB1ENR |= RCC_APB1ENR_TIM3EN)
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#define PWM_0_CLKDIS() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
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/* PWM 0 pin configuration */
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#define PWM_0_PORT GPIOC
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#define PWM_0_PORT_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIOCEN)
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#define PWM_0_PIN_CH0 6
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#define PWM_0_PIN_CH1 7
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#define PWM_0_PIN_CH2 8
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#define PWM_0_PIN_CH3 9
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#define PWM_0_PIN_AF 2
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/* PWM 1 device configuration */
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#define PWM_1_DEV TIM4
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#define PWM_1_CHANNELS 4
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#define PWM_1_CLK (36000000U)
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#define PWM_1_CLKEN() (RCC->APB1ENR |= RCC_APB1ENR_TIM4EN)
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#define PWM_1_CLKDIS() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
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/* PWM 1 pin configuration */
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#define PWM_1_PORT GPIOD
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#define PWM_1_PORT_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIODEN)
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#define PWM_1_PIN_CH0 12
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#define PWM_1_PIN_CH1 13
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#define PWM_1_PIN_CH2 14
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#define PWM_1_PIN_CH3 15
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#define PWM_1_PIN_AF 2
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/** @} */
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/**
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* @name SPI configuration
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* @{
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*/
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#define SPI_NUMOF (2U)
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#define SPI_0_EN 1
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#define SPI_1_EN 1
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#define SPI_IRQ_PRIO 1
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/* SPI 0 device config */
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#define SPI_0_DEV SPI1
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#define SPI_0_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_SPI1EN)
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#define SPI_0_CLKDIS() (RCC->APB2ENR &= ~RCC_APB2ENR_SPI1EN)
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#define SPI_0_IRQ SPI1_IRQn
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#define SPI_0_IRQ_HANDLER isr_spi1
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/* SPI 0 pin configuration */
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#define SPI_0_SCK_PORT GPIOA
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#define SPI_0_SCK_PIN 5
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#define SPI_0_SCK_AF 5
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#define SPI_0_SCK_PORT_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIOAEN)
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#define SPI_0_MISO_PORT GPIOA
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#define SPI_0_MISO_PIN 6
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#define SPI_0_MISO_AF 5
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#define SPI_0_MISO_PORT_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIOAEN)
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#define SPI_0_MOSI_PORT GPIOA
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#define SPI_0_MOSI_PIN 7
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#define SPI_0_MOSI_AF 5
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#define SPI_0_MOSI_PORT_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIOAEN)
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/* SPI 1 device config */
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#define SPI_1_DEV SPI3
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#define SPI_1_CLKEN() (RCC->APB1ENR |= RCC_APB1ENR_SPI3EN)
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#define SPI_1_CLKDIS() (RCC->APB1ENR &= ~RCC_APB1ENR_SPI3EN)
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#define SPI_1_IRQ SPI3_IRQn
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#define SPI_1_IRQ_HANDLER isr_spi3
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/* SPI 1 pin configuration */
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#define SPI_1_SCK_PORT GPIOC
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#define SPI_1_SCK_PIN 10
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#define SPI_1_SCK_AF 6
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#define SPI_1_SCK_PORT_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIOCEN)
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#define SPI_1_MISO_PORT GPIOC
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#define SPI_1_MISO_PIN 11
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#define SPI_1_MISO_AF 6
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#define SPI_1_MISO_PORT_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIOCEN)
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#define SPI_1_MOSI_PORT GPIOC
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#define SPI_1_MOSI_PIN 12
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#define SPI_1_MOSI_AF 6
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#define SPI_1_MOSI_PORT_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIOCEN)
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/** @} */
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/**
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* @name I2C configuration
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* @{
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*/
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#define I2C_NUMOF (2U)
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#define I2C_0_EN 1
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#define I2C_1_EN 1
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#define I2C_IRQ_PRIO 1
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#define I2C_APBCLK (36000000U)
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/* I2C 0 device configuration */
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#define I2C_0_DEV I2C1
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#define I2C_0_CLKEN() (RCC->APB1ENR |= RCC_APB1ENR_I2C1EN)
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#define I2C_0_CLKDIS() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
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#define I2C_0_EVT_IRQ I2C1_EV_IRQn
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#define I2C_0_EVT_ISR isr_i2c1_ev
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#define I2C_0_ERR_IRQ I2C1_ER_IRQn
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#define I2C_0_ERR_ISR isr_i2c1_er
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/* I2C 0 pin configuration */
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#define I2C_0_SCL_PORT GPIOB
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#define I2C_0_SCL_PIN 6
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#define I2C_0_SCL_AF 4
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#define I2C_0_SCL_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIOBEN)
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#define I2C_0_SDA_PORT GPIOB
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#define I2C_0_SDA_PIN 7
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#define I2C_0_SDA_AF 4
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#define I2C_0_SDA_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIOBEN)
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/* I2C 1 device configuration */
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#define I2C_1_DEV I2C2
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#define I2C_1_CLKEN() (RCC->APB1ENR |= RCC_APB1ENR_I2C2EN)
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#define I2C_1_CLKDIS() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
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#define I2C_1_EVT_IRQ I2C2_EV_IRQn
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#define I2C_1_EVT_ISR isr_i2c2_ev
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#define I2C_1_ERR_IRQ I2C2_ER_IRQn
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#define I2C_1_ERR_ISR isr_i2c2_er
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/* I2C 1 pin configuration */
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#define I2C_1_SCL_PORT GPIOF
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#define I2C_1_SCL_PIN 1
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#define I2C_1_SCL_AF 4
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#define I2C_1_SCL_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIOFEN)
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#define I2C_1_SDA_PORT GPIOF
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#define I2C_1_SDA_PIN 0
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#define I2C_1_SDA_AF 4
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#define I2C_1_SDA_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIOFEN)
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#endif /* PERIPH_CONF_H_ */
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