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https://github.com/RIOT-OS/RIOT.git
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148 lines
3.5 KiB
C
148 lines
3.5 KiB
C
/*
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* Copyright (C) 2015-2016 Freie Universität Berlin
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_stm32f1
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* @{
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*
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* @file
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* @brief CPU specific definitions for internal peripheral handling
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*
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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*/
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#ifndef PERIPH_CPU_H
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#define PERIPH_CPU_H
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#include "periph_cpu_common.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief Available number of ADC devices
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*/
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#define ADC_DEVS (2U)
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/**
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* @brief Starting address of the CPU ID
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*/
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#define CPUID_ADDR (0x1ffff7e8)
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/**
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* @brief All timers for the STM32F1 have 4 CC channels
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*/
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#define TIMER_CHANNELS (4U)
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/**
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* @brief All timers have a width of 16-bit
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*/
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#define TIMER_MAXVAL (0xffff)
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/**
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* @brief Generate GPIO mode bitfields
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*
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* We use 4 bit to determine the pin functions:
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* - bit 4: ODR value
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* - bit 2+3: in/out
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* - bit 1: PU enable
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* - bit 2: OD enable
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*/
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#define GPIO_MODE(mode, cnf, odr) (mode | (cnf << 2) | (odr << 4))
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/**
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* @brief Define the number of available PM modes
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*/
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#define PM_NUM_MODES (2U)
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/**
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* @brief Override the default initial PM blocker
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* @todo we block all modes per default, until PM is cleanly implemented
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*/
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#define PM_BLOCKER_INITIAL { .val_u32 = 0x01010101 }
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/**
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* @brief Define the config flag for stop mode
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*/
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#define PM_STOP_CONFIG (PWR_CR_LPDS)
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#ifndef DOXYGEN
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/**
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* @brief Override GPIO mode options
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*
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* We use 4 bit to encode CNF and MODE.
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* @{
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*/
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#define HAVE_GPIO_MODE_T
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typedef enum {
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GPIO_IN = GPIO_MODE(0, 1, 0), /**< input w/o pull R */
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GPIO_IN_PD = GPIO_MODE(0, 2, 0), /**< input with pull-down */
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GPIO_IN_PU = GPIO_MODE(0, 2, 1), /**< input with pull-up */
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GPIO_OUT = GPIO_MODE(3, 0, 0), /**< push-pull output */
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GPIO_OD = GPIO_MODE(3, 1, 0), /**< open-drain w/o pull R */
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GPIO_OD_PU = (0xff) /**< not supported by HW */
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} gpio_mode_t;
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/** @} */
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#endif /* ndef DOXYGEN */
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/**
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* @brief Override values for pull register configuration
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* @{
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*/
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#define HAVE_GPIO_PP_T
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typedef enum {
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GPIO_NOPULL = 4, /**< do not use internal pull resistors */
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GPIO_PULLUP = 9, /**< enable internal pull-up resistor */
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GPIO_PULLDOWN = 8 /**< enable internal pull-down resistor */
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} gpio_pp_t;
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/** @} */
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#ifndef DOXYGEN
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/**
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* @brief Override flank configuration values
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* @{
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*/
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#define HAVE_GPIO_FLANK_T
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typedef enum {
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GPIO_RISING = 1, /**< emit interrupt on rising flank */
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GPIO_FALLING = 2, /**< emit interrupt on falling flank */
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GPIO_BOTH = 3 /**< emit interrupt on both flanks */
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} gpio_flank_t;
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/** @} */
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#endif /* ndef DOXYGEN */
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/**
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* @brief Available ports on the STM32F1 family
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*/
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enum {
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PORT_A = 0, /**< port A */
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PORT_B = 1, /**< port B */
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PORT_C = 2, /**< port C */
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PORT_D = 3, /**< port D */
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PORT_E = 4, /**< port E */
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PORT_F = 5, /**< port F */
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PORT_G = 6, /**< port G */
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};
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/**
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* @brief ADC channel configuration data
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*/
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typedef struct {
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gpio_t pin; /**< pin connected to the channel */
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uint8_t dev; /**< ADCx - 1 device used for the channel */
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uint8_t chan; /**< CPU ADC channel connected to the pin */
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} adc_conf_t;
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#ifdef __cplusplus
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}
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#endif
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#endif /* PERIPH_CPU_H */
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/** @} */
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