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https://github.com/RIOT-OS/RIOT.git
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124 lines
3.6 KiB
C
124 lines
3.6 KiB
C
/*
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* Copyright (C) 2014 Freie Universität Berlin
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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*/
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/**
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* @ingroup boards_spark-core
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* @{
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*
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* @file
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* @brief Peripheral MCU configuration for the spark-core board
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*
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* @author Christian Mehlis <mehlis@inf.fu-berlin.de>
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*/
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#ifndef PERIPH_CONF_H_
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#define PERIPH_CONF_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @name Clock system configuration
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* @{
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**/
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#define CLOCK_HSE (16000000U) /* frequency of external oscillator */
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#define CLOCK_CORECLOCK (72000000U) /* targeted core clock frequency */
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/* configuration of PLL prescaler and multiply values */
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/* CORECLOCK := HSE / PLL_HSE_DIV * PLL_HSE_MUL */
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#define CLOCK_PLL_HSE_DIV RCC_CFGR_PLLXTPRE_HSE
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#define CLOCK_PLL_HSE_MUL RCC_CFGR_PLLMULL9
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/* configuration of peripheral bus clock prescalers */
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#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 /* AHB clock -> 72MHz */
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#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* APB2 clock -> 72MHz */
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#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* APB1 clock -> 36MHz */
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/* configuration of flash access cycles */
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#define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY_2
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/** @} */
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/**
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* @brief Timer configuration
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* @{
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*/
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#define TIMER_NUMOF (2U)
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#define TIMER_0_EN 1
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#define TIMER_1_EN 1
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/* Timer 0 configuration */
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#define TIMER_0_DEV_0 TIM2
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#define TIMER_0_DEV_1 TIM3
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#define TIMER_0_CHANNELS 4
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#define TIMER_0_PRESCALER (72U)
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#define TIMER_0_MAX_VALUE (0xffff)
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#define TIMER_0_CLKEN() (RCC->APB1ENR |= (RCC_APB1ENR_TIM2EN | RCC_APB1ENR_TIM3EN))
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#define TIMER_0_ISR_0 isr_tim2
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#define TIMER_0_ISR_1 isr_tim3
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#define TIMER_0_IRQ_CHAN_0 TIM2_IRQn
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#define TIMER_0_IRQ_CHAN_1 TIM3_IRQn
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#define TIMER_0_IRQ_PRIO 1
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#define TIMER_0_TRIG_SEL TIM_SMCR_TS_0
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/* Timer 1 configuration */
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#define TIMER_1_DEV_0 TIM4
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#define TIMER_1_DEV_1 TIM5
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#define TIMER_1_CHANNELS 4
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#define TIMER_1_PRESCALER (36000U)
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#define TIMER_1_MAX_VALUE (0xffff)
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#define TIMER_1_CLKEN() (RCC->APB1ENR |= (RCC_APB1ENR_TIM4EN | RCC_APB1ENR_TIM5EN))
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#define TIMER_1_ISR_0 isr_tim4
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#define TIMER_1_ISR_1 isr_tim5
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#define TIMER_1_IRQ_CHAN_0 TIM4_IRQn
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#define TIMER_1_IRQ_CHAN_1 TIM5_IRQn
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#define TIMER_1_IRQ_PRIO 1
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#define TIMER_1_TRIG_SEL TIM_SMCR_TS_1
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/** @} */
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/**
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* @brief UART configuration
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* @{
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*/
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#define UART_NUMOF (1U)
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#define UART_0_EN 1
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#define UART_IRQ_PRIO 1
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/* UART 0 device configuration */
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#define UART_0_DEV USART2
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#define UART_0_CLKEN() (RCC->APB1ENR |= RCC_APB1ENR_USART2EN)
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#define UART_0_IRQ USART2_IRQn
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#define UART_0_ISR isr_usart2
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#define UART_0_BUS_FREQ (CLOCK_CORECLOCK/2)
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/* UART 0 pin configuration */
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#define UART_0_RX_PIN GPIO(PORT_A,3)
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#define UART_0_TX_PIN GPIO(PORT_A,2)
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/** @} */
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/**
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* @brief SPI configuration
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* @{
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*/
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#define SPI_NUMOF (1U)
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#define SPI_0_EN 1
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/* SPI 0 device configuration */
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#define SPI_0_DEV SPI1
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#define SPI_0_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_SPI1EN)
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#define SPI_0_CLKDIS() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
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#define SPI_0_BUS_DIV 0 /* 1 -> SPI runs with full CPU clock, 0 -> half CPU clock */
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/* SPI 0 pin configuration */
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#define SPI_0_CLK_PIN GPIO(PORT_B,15)
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#define SPI_0_MOSI_PIN GPIO(PORT_B,17)
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#define SPI_0_MISO_PIN GPIO(PORT_B,16)
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/** @} */
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#ifdef __cplusplus
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} /* end extern "C" */
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#endif
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#endif /* PERIPH_CONF_H_ */
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/** @} */
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