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7d1d5e77d8
New CPU FE310 from SiFive based on RISC-V architecture build: add makefile for RISC-V builds Makefile for builds using RISC-V tools
20 lines
727 B
Makefile
20 lines
727 B
Makefile
# Target architecture for the build.
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export TARGET_ARCH ?= riscv-none-embed
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# define build specific options
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CFLAGS_CPU = -march=rv32imac -mabi=ilp32 -mcmodel=medlow -msmall-data-limit=8
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CFLAGS_LINK = -nostartfiles -ffunction-sections -fdata-sections
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CFLAGS_DBG ?= -g3 -Og
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#CFLAGS_OPT ?= -Os
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export LINKFLAGS += -L$(RIOTCPU)/$(CPU)/ldscripts
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export LINKER_SCRIPT ?= $(CPU_MODEL).ld
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export LINKFLAGS += -T$(LINKER_SCRIPT)
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# export compiler flags
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export CFLAGS += $(CFLAGS_CPU) $(CFLAGS_DBG) $(CFLAGS_OPT) $(CFLAGS_LINK)
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# export assmebly flags
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export ASFLAGS += $(CFLAGS_CPU) $(CFLAGS_DBG)
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# export linker flags
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export LINKFLAGS += $(CFLAGS_CPU) $(CFLAGS_LINK) $(CFLAGS_DBG) $(CFLAGS_OPT) -Wl,--gc-sections -static -lgcc
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