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d37adee32d
There is no hardware limitation for custom boards based on STM32 to uses SPI bus with signals coming from different PORT and alternate functions. This patch allow alternate's function definition per pin basis, thus enable the support of SPI bus signals routed on differents PORT. Signed-off-by: Yannick Gicquel <ygicquel@gmail.com>
258 lines
6.4 KiB
C
258 lines
6.4 KiB
C
/*
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* Copyright (C) 2016-2017 OTA keys S.A.
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup boards_nucleo-f207zg
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* @{
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*
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* @file
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* @name Peripheral MCU configuration for the nucleo-f207zg board
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*
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* @author Vincent Dupont <vincent@otakeys.com>
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* @author Aurelien Gonce <aurelien.gonce@altran.fr>
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* @author Toon Stegen <toon.stegen@altran.com>
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*/
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#ifndef PERIPH_CONF_H
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#define PERIPH_CONF_H
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#include "periph_cpu.h"
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#include "f2/cfg_clock_120_8_1.h"
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#include "cfg_i2c1_pb8_pb9.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @name DMA streams configuration
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* @{
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*/
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#ifdef MODULE_PERIPH_DMA
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static const dma_conf_t dma_config[] = {
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{ .stream = 10 }, /* DMA2 Stream 2 - SPI1_RX */
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{ .stream = 11 }, /* DMA2 Stream 3 - SPI1_TX */
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{ .stream = 3 }, /* DMA1 Stream 3 - SPI2_RX/USART3_TX */
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{ .stream = 4 }, /* DMA1 Stream 4 - SPI2_TX */
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{ .stream = 14 }, /* DMA2 Stream 6 - USART6_TX */
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{ .stream = 6 }, /* DMA1 Stream 6 - USART2_TX */
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};
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#define DMA_0_ISR isr_dma2_stream2
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#define DMA_1_ISR isr_dma2_stream3
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#define DMA_2_ISR isr_dma1_stream3
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#define DMA_3_ISR isr_dma1_stream4
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#define DMA_4_ISR isr_dma2_stream6
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#define DMA_5_ISR isr_dma1_stream6
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#define DMA_NUMOF ARRAY_SIZE(dma_config)
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#endif
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/** @} */
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/**
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* @name PWM configuration
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* @{
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*/
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static const pwm_conf_t pwm_config[] = {
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{
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.dev = TIM1,
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.rcc_mask = RCC_APB2ENR_TIM1EN,
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.chan = { { .pin = GPIO_PIN(PORT_E, 9) /* D6 */, .cc_chan = 0},
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{ .pin = GPIO_PIN(PORT_E, 11) /* D5 */, .cc_chan = 1},
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{ .pin = GPIO_PIN(PORT_E, 13) /* D3 */, .cc_chan = 2},
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{ .pin = GPIO_UNDEF, .cc_chan = 0} },
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.af = GPIO_AF1,
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.bus = APB2
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},
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{
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.dev = TIM4,
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.rcc_mask = RCC_APB1ENR_TIM4EN,
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.chan = { { .pin = GPIO_PIN(PORT_D, 15) /* D9 */, .cc_chan = 3},
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{ .pin = GPIO_UNDEF, .cc_chan = 0},
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{ .pin = GPIO_UNDEF, .cc_chan = 0},
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{ .pin = GPIO_UNDEF, .cc_chan = 0} },
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.af = GPIO_AF2,
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.bus = APB1
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},
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};
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#define PWM_NUMOF ARRAY_SIZE(pwm_config)
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/** @} */
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/**
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* @name Timer configuration
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* @{
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*/
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static const timer_conf_t timer_config[] = {
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{
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.dev = TIM2,
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.max = 0xffffffff,
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.rcc_mask = RCC_APB1ENR_TIM2EN,
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.bus = APB1,
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.irqn = TIM2_IRQn
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},
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{
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.dev = TIM5,
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.max = 0xffffffff,
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.rcc_mask = RCC_APB1ENR_TIM5EN,
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.bus = APB1,
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.irqn = TIM5_IRQn
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}
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};
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#define TIMER_0_ISR isr_tim2
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#define TIMER_1_ISR isr_tim5
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#define TIMER_NUMOF ARRAY_SIZE(timer_config)
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/** @} */
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/**
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* @name UART configuration
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* @{
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*/
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static const uart_conf_t uart_config[] = {
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{
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.dev = USART3,
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.rcc_mask = RCC_APB1ENR_USART3EN,
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.rx_pin = GPIO_PIN(PORT_D, 9),
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.tx_pin = GPIO_PIN(PORT_D, 8),
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.rx_af = GPIO_AF7,
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.tx_af = GPIO_AF7,
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.bus = APB1,
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.irqn = USART3_IRQn,
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#ifdef MODULE_PERIPH_DMA
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.dma = 2,
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.dma_chan = 4
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#endif
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},
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{
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.dev = USART6,
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.rcc_mask = RCC_APB2ENR_USART6EN,
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.rx_pin = GPIO_PIN(PORT_G, 9),
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.tx_pin = GPIO_PIN(PORT_G, 14),
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.rx_af = GPIO_AF8,
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.tx_af = GPIO_AF8,
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.bus = APB2,
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.irqn = USART6_IRQn,
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#ifdef MODULE_PERIPH_DMA
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.dma = 4,
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.dma_chan = 5
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#endif
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},
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{
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.dev = USART2,
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.rcc_mask = RCC_APB1ENR_USART2EN,
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.rx_pin = GPIO_PIN(PORT_D, 6),
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.tx_pin = GPIO_PIN(PORT_D, 5),
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.rx_af = GPIO_AF7,
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.tx_af = GPIO_AF7,
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.bus = APB1,
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.irqn = USART2_IRQn,
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#ifdef MODULE_PERIPH_DMA
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.dma = 5,
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.dma_chan = 4
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#endif
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},
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};
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#define UART_0_ISR (isr_usart3)
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#define UART_1_ISR (isr_usart6)
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#define UART_2_ISR (isr_usart2)
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#define UART_NUMOF ARRAY_SIZE(uart_config)
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/** @} */
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/**
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* @name SPI configuration
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*
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* @note The spi_divtable is auto-generated from
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* `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
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* @{
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*/
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static const uint8_t spi_divtable[2][5] = {
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{ /* for APB1 @ 30000000Hz */
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7, /* -> 117187Hz */
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5, /* -> 468750Hz */
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4, /* -> 937500Hz */
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2, /* -> 3750000Hz */
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1 /* -> 7500000Hz */
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},
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{ /* for APB2 @ 60000000Hz */
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7, /* -> 234375Hz */
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6, /* -> 468750Hz */
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5, /* -> 937500Hz */
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3, /* -> 3750000Hz */
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2 /* -> 7500000Hz */
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}
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};
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static const spi_conf_t spi_config[] = {
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{
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.dev = SPI1,
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.mosi_pin = GPIO_PIN(PORT_A, 7),
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.miso_pin = GPIO_PIN(PORT_A, 6),
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.sclk_pin = GPIO_PIN(PORT_A, 5),
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.cs_pin = GPIO_PIN(PORT_A, 4),
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.mosi_af = GPIO_AF5,
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.miso_af = GPIO_AF5,
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.sclk_af = GPIO_AF5,
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.cs_af = GPIO_AF5,
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.rccmask = RCC_APB2ENR_SPI1EN,
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.apbbus = APB2,
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#ifdef MODULE_PERIPH_DMA
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.tx_dma = 1,
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.tx_dma_chan = 3,
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.rx_dma = 0,
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.rx_dma_chan = 3,
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#endif
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},
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{
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.dev = SPI2,
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.mosi_pin = GPIO_PIN(PORT_B, 15),
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.miso_pin = GPIO_PIN(PORT_C, 2),
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.sclk_pin = GPIO_PIN(PORT_B, 13),
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.cs_pin = GPIO_PIN(PORT_B, 12),
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.mosi_af = GPIO_AF5,
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.miso_af = GPIO_AF5,
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.sclk_af = GPIO_AF5,
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.cs_af = GPIO_AF5,
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.rccmask = RCC_APB1ENR_SPI2EN,
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.apbbus = APB1,
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#ifdef MODULE_PERIPH_DMA
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.tx_dma = 3,
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.tx_dma_chan = 0,
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.rx_dma = 2,
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.rx_dma_chan = 0,
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#endif
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}
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};
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#define SPI_NUMOF ARRAY_SIZE(spi_config)
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/** @} */
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/**
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* @name ADC configuration
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*
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* We need to define the following fields:
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* PIN, device (ADCx), channel
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* @{
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*/
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#define ADC_CONFIG { \
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{GPIO_PIN(PORT_A, 3), 0, 3}, \
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{GPIO_PIN(PORT_C, 0), 1, 0} \
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}
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#define ADC_NUMOF (2)
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#endif /* PERIPH_CONF_H */
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/** @} */
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