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de486ff79f
Tested on the following Freescale Kinetis K60 CPUs: - MK60DN512VLL10 The port should with a high probability also support the following variations of the above CPUs (untested): - MK60DN256VLL10 And possibly also: - MK60DX256VLL10 - MK60DX512VLL10 - MK60DN512VLQ10 - MK60DN256VLQ10 - MK60DX256VLQ10 - MK60DN512VMC10 - MK60DN256VMC10 - MK60DX256VMC10 - MK60DN512VMD10 - MK60DX256VMD10 - MK60DN256VMD10 Currently not working on the following CPUs (Missing PIT channel chaining necessary for kinetis_common/periph/timer implementation): - MK60DN256ZVLL10 - MK60DN512ZVLL10 - MK60DX256ZVLL10 - MK60DX512ZVLL10 - MK60DN512ZVLQ10 - MK60DN256ZVLQ10 - MK60DX256ZVLQ10 - MK60DN512ZVMC10 - MK60DN256ZVMC10 - MK60DX256ZVMC10 - MK60DN512ZVMD10 - MK60DX256ZVMD10 - MK60DN256ZVMD10 Regarding header files from Freescale: dist/tools/licenses: Add Freescale CMSIS PAL license pattern Redistribution is OK according to: https://community.freescale.com/message/477976?et=watches.email.thread#477976 Archive copy in case the above link disappears: https://web.archive.org/web/20150328073057/https://community.freescale.com/message/477976?et=watches.email.thread Applies to: - MK60DZ10.h (K60 variant)
86 lines
1.7 KiB
C
86 lines
1.7 KiB
C
/*
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* Copyright (C) 2015 Eistec AB
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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*/
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/**
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* @ingroup cpu_k60
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* @{
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*
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* @file
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* @brief Device I/O helpers for UARTs on K60, implementation.
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*
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* @author Joakim Gebart <joakim.gebart@eistec.se>
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*
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* @}
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*/
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#include <string.h>
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#include "devio-uart.h"
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#include "periph/uart.h"
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#include "cpu.h"
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static inline long uart_write_r(uart_t uart_num, struct _reent *r, int fd, const char *ptr,
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int len)
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{
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int i = 0;
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while (i < len) {
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uart_write_blocking(uart_num, ptr[i]);
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++i;
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}
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return i;
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}
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static long uart_read_r(uart_t uart_num, struct _reent *r, int fd, char *ptr, int len)
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{
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/* not yet implemented */
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return 0;
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}
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#if UART_0_EN
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long uart0_write_r(struct _reent *r, int fd, const char *ptr, int len)
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{
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return uart_write_r(UART_0, r, fd, ptr, len);
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}
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#endif
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#if UART_1_EN
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long uart1_write_r(struct _reent *r, int fd, const char *ptr, int len)
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{
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return uart_write_r(UART_1, r, fd, ptr, len);
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}
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#endif
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#if UART_2_EN
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long uart2_write_r(struct _reent *r, int fd, const char *ptr, int len)
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{
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return uart_write_r(UART_2, r, fd, ptr, len);
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}
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#endif
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#if UART_3_EN
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long uart3_write_r(struct _reent *r, int fd, const char *ptr, int len)
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{
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return uart_write_r(UART_3, r, fd, ptr, len);
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}
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#endif
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#if UART_4_EN
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long uart4_write_r(struct _reent *r, int fd, const char *ptr, int len)
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{
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return uart_write_r(UART_4, r, fd, ptr, len);
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}
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#endif
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#if UART_0_EN
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long uart0_read_r(struct _reent *r, int fd, char *ptr, int len)
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{
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return uart_read_r(UART_0, r, fd, ptr, len);
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}
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#endif
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