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https://github.com/RIOT-OS/RIOT.git
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f7a77ebb04
The driver uses the netdev interface. Due to the limited capabilities of the transceiver (32 byte FIFO and no source address in the layer2 frame), it relies on 6LowPAN compression and adds the source address to the frame for that.
254 lines
6.3 KiB
C
254 lines
6.3 KiB
C
/*
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* Copyright (C) 2019 Otto-von-Guericke-Universität Magdeburg
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup drivers_nrf24l01p_ng
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* @{
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*
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* @file
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* @brief Functions to communicate with the NRF24L01+ (NG) transceiver
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* via SPI
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*
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* @author Fabian Hüßler <fabian.huessler@ovgu.de>
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*/
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#ifndef NRF24L01P_NG_COMMUNICATION_H
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#define NRF24L01P_NG_COMMUNICATION_H
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#include "nrf24l01p_ng.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief Mask for 5 bit register address
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*/
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#define NRF24L01P_NG_ADDR_MASK (0x1F)
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/**
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* @brief Mask for 3 bit pipe number
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*/
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#define NRF24L01P_NG_PIPE_MASK (0x07)
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/**
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* @brief Read register value
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* (1 to 5 bytes)
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*/
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#define NRF24L01P_NG_CMD_R_REGISTER(reg) \
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(0x00 | ((reg) & NRF24L01P_NG_ADDR_MASK))
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/**
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* @brief Write register value
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* (1 to 5 bytes)
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*/
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#define NRF24L01P_NG_CMD_W_REGISTER(reg) \
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(0x20 | ((reg) & NRF24L01P_NG_ADDR_MASK))
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/**
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* @brief Read RX payload buffer
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* (1 to 32 bytes)
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*/
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#define NRF24L01P_NG_CMD_R_RX_PAYLOAD (0x61)
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/**
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* @brief Write TX payload buffer
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* (1 to 32 bytes)
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*/
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#define NRF24L01P_NG_CMD_W_TX_PAYLOAD (0xA0)
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/**
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* @brief Flush TX buffer
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* (0 bytes data)
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*/
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#define NRF24L01P_NG_CMD_FLUSH_TX (0xE1)
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/**
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* @brief Flush RX buffer
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* (0 bytes data)
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*/
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#define NRF24L01P_NG_CMD_FLUSH_RX (0xE2)
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/**
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* @brief Reuse last transmitted payload
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* (0 bytes data)
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*/
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#define NRF24L01P_NG_CMD_REUSE_TX_PL (0xE3)
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/**
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* @brief Read RX payload width for the top R_RX_PAYLOAD in RX FIFO
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* (1 byte data)
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*/
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#define NRF24L01P_NG_CMD_R_RX_PL_WID (0x60)
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/**
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* @brief Write payload to be transmitted together with ACK for certain pipe
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* (1 to 32 bytes data)
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*/
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#define NRF24L01P_NG_CMD_W_ACK_PAYLOAD(pipe) \
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(0xA8 | ((pipe) & NRF24L01P_NG_PIPE_MASK))
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/**
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* @brief Disable auto ACK on this specific frame
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*/
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#define NRF24L01P_NG_CMD_W_TX_PAYLOAD_NO_ACK (0xB0)
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/**
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* @brief No operation
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*/
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#define NRF24L01P_NG_CMD_NOP (0xFF)
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/**
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* @brief Acquire the SPI bus of the transceiver
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*
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* @param[in] dev NRF24L01+ device handle
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*
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* @return @see spi_acquire
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*/
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int nrf24l01p_ng_acquire(nrf24l01p_ng_t *dev);
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/**
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* @brief Release the SPI bus of the transceiver
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*
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* @param[in] dev NRF24L01+ device handle
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*
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* @return @see spi_release
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*/
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void nrf24l01p_ng_release(nrf24l01p_ng_t *dev);
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/**
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* @brief Read a register value
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*
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* @param[in] dev NRF24L01+ device handle
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* @param[in] reg Register address
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* @param[out] dest Output register
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* @param[in] len Output register width
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*
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* @return Status register value
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*/
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uint8_t nrf24l01p_ng_read_reg(const nrf24l01p_ng_t *dev, uint8_t reg,
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uint8_t *dest, size_t len);
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/**
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* @brief Write a register value
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*
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* @param[in] dev NRF24L01+ device handle
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* @param[in] reg Register address
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* @param[in] src Data to be written into the register
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* @param[in] len Register width
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*
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* @return Status register value
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*/
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uint8_t nrf24l01p_ng_write_reg(const nrf24l01p_ng_t *dev, uint8_t reg,
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const uint8_t *src, size_t len);
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/**
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* @brief Read received payload
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*
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* @param[in] dev NRF24L01+ device handle
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* @param[out] dest Output payload buffer
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* @param[in] len Output payload length
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*
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* @return Status register value
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*/
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uint8_t nrf24l01p_ng_read_rx_payload(const nrf24l01p_ng_t *dev, void *dest,
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size_t len);
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/**
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* @brief Write payload to be transmitted
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*
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* @param[in] dev NRF24L01+ device handle
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* @param[in] src Input payload buffer
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* @param[in] len Input payload length
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*
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* @return Status register value
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*/
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uint8_t nrf24l01p_ng_write_tx_payload(const nrf24l01p_ng_t *dev,
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const void *src, size_t len);
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/**
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* @brief Flush TX FIFO
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*
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* @param[in] dev NRF24L01+ device handle
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*
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* @return Status register value
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*/
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uint8_t nrf24l01p_ng_flush_tx(const nrf24l01p_ng_t *dev);
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/**
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* @brief Flush RX FIFO
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*
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* @param[in] dev NRF24L01+ device handle
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*
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* @return Status register value
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*/
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uint8_t nrf24l01p_ng_flush_rx(const nrf24l01p_ng_t *dev);
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/**
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* @brief Reuse TX payload in FIFO
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*
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* This function can be used to reattempt to transmit a frame, after a MAX_RT
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* interrupt was triggered.
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*
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* @param[in] dev NRF24L01+ device handle
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*
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* @return Status register value
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*/
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uint8_t nrf24l01p_ng_reuse_tx_pl(const nrf24l01p_ng_t *dev);
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/**
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* @brief Read received payload width
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*
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* @param[in] dev NRF24L01+ device handle
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* @param[out] dest Payload width
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*
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* @return Status register value
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*/
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uint8_t nrf24l01p_ng_read_rx_pl_width(const nrf24l01p_ng_t *dev,
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uint8_t *dest);
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/**
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* @brief Write Payload to be transmitted in an ACK frame
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*
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* @param[in] dev NRF24L01+ device handle
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* @param[in] src Input payload buffer
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* @param[in] len Input payload length
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* @param[in] pipe Index of data pipe
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*
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* @return Status register value
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*/
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uint8_t nrf24l01p_ng_write_ack_pl(const nrf24l01p_ng_t *dev, const void *src,
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size_t len, uint8_t pipe);
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/**
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* @brief Write payload to be transmitted but do not expect an ACK for
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* this frame
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*
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* @param[in] dev NRF24L01+ device handle
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* @param[in] src Input payload buffer
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* @param[in] len Input payload length
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*
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* @return Status register value
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*/
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uint8_t nrf24l01p_ng_write_tx_pl_no_ack(const nrf24l01p_ng_t *dev,
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const void *src, size_t len);
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/**
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* @brief Get status register value
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*
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* @param[in] dev NRF24L01+ device handle
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*
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* @return Status register value
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*/
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uint8_t nrf24l01p_ng_get_status(const nrf24l01p_ng_t *dev);
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#ifdef __cplusplus
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}
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#endif
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#endif /* NRF24L01P_NG_COMMUNICATION_H */
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/** @} */
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