mirror of
https://github.com/RIOT-OS/RIOT.git
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175 lines
4.6 KiB
C
175 lines
4.6 KiB
C
/*
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* Copyright (C) 2015 Eistec AB
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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*/
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/**
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* @defgroup cpu_k60 Freescale Kinetis K60
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* @ingroup cpu
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* @brief CPU specific implementations for the Freescale Kinetis K60
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* @{
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*
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* @file
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* @brief Implementation specific CPU configuration options
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*
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* @author Joakim Nohlgård <joakim.nohlgard@eistec.se>
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*/
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#ifndef CPU_CONF_H
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#define CPU_CONF_H
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#include "cpu_conf_common.h"
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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#include <stdint.h>
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#if defined(CPU_MODEL_MK60DN512VLL10) || defined(CPU_MODEL_MK60DN256VLL10)
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#include "vendor/MK60D10.h"
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/** The expected CPUID value, can be used to implement a check that we are
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* running on the right hardware */
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#define K60_EXPECTED_CPUID 0x410fc241u
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/* K60 rev 2.x replaced the RNG module in 1.x by the RNGA PRNG module */
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#define KINETIS_RNGA (RNG)
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#else
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#error Unknown CPU model. Update Makefile.include in the board directory.
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#endif
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/**
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* @brief This CPU provides an additional ADC clock divider as CFG1[ADICLK]=1
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*/
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#define KINETIS_HAVE_ADICLK_BUS_DIV_2 1
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/**
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* @brief ARM Cortex-M specific CPU configuration
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* @{
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*/
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#define CPU_DEFAULT_IRQ_PRIO (1U)
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#define CPU_IRQ_NUMOF (104U)
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#define CPU_FLASH_BASE (0x00000000)
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/** @} */
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/**
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* @name GPIO pin mux function numbers
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*/
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/** @{ */
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#define PIN_MUX_FUNCTION_ANALOG 0
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#define PIN_MUX_FUNCTION_GPIO 1
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/** @} */
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/**
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* @name GPIO interrupt flank settings
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*/
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/** @{ */
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#define PIN_INTERRUPT_RISING 0b1001
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#define PIN_INTERRUPT_FALLING 0b1010
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#define PIN_INTERRUPT_EDGE 0b1011
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/** @} */
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/**
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* @name Timer hardware information
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*/
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/** @{ */
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#define LPTMR_CLKEN() (bit_set32(&SIM->SCGC5, SIM_SCGC5_LPTMR_SHIFT)) /**< Enable LPTMR0 clock gate */
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#define PIT_CLKEN() (bit_set32(&SIM->SCGC6, SIM_SCGC6_PIT_SHIFT)) /**< Enable PIT clock gate */
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/** @} */
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/**
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* @name Power mode hardware details
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*/
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/** @{ */
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#define KINETIS_PMCTRL SMC->PMCTRL
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#define KINETIS_PMCTRL_SET_MODE(x) (KINETIS_PMCTRL = SMC_PMCTRL_STOPM(x) | SMC_PMCTRL_LPWUI_MASK)
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/* Clear LLS protection, clear VLPS, VLPW, VLPR protection */
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/* Note: This register can only be written once after each reset, so we must
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* enable all power modes that we wish to use. */
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#define KINETIS_PMPROT_UNLOCK() (SMC->PMPROT |= SMC_PMPROT_ALLS_MASK | SMC_PMPROT_AVLP_MASK)
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/**
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* @name STOP mode bitfield values
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* @{
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*/
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/** @brief Normal STOP */
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#define KINETIS_POWER_MODE_NORMAL (0b000)
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/** @brief VLPS STOP */
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#define KINETIS_POWER_MODE_VLPS (0b010)
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/** @brief LLS STOP */
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#define KINETIS_POWER_MODE_LLS (0b011)
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/** @} */
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/**
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* @brief Wake up source number for the LPTMR0
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*
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* In order to let the hwtimer wake the CPU from low power modes, we need to
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* enable this wake up source.
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*/
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#define KINETIS_LLWU_WAKEUP_MODULE_LPTMR 0
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/**
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* @brief IRQn name to enable LLWU IRQ in NVIC
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*/
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#define KINETIS_LLWU_IRQ LLW_IRQn
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/**
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* @brief Enable clock gate on LLWU module.
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*/
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#define LLWU_UNLOCK() (BITBAND_REG32(SIM->SCGC4, SIM_SCGC4_LLWU_SHIFT) = 1)
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/**
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* @brief Internal modules whose interrupts are mapped to LLWU wake up sources.
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*
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* Other modules CAN NOT be used to wake the CPU from LLS or VLLSx power modes.
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*/
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typedef enum llwu_wakeup_module {
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KINETIS_LPM_WAKEUP_MODULE_LPTMR = 0,
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KINETIS_LPM_WAKEUP_MODULE_CMP0 = 1,
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KINETIS_LPM_WAKEUP_MODULE_CMP1 = 2,
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KINETIS_LPM_WAKEUP_MODULE_CMP2 = 3,
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KINETIS_LPM_WAKEUP_MODULE_TSI = 4,
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KINETIS_LPM_WAKEUP_MODULE_RTC_ALARM = 5,
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KINETIS_LPM_WAKEUP_MODULE_RESERVED = 6,
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KINETIS_LPM_WAKEUP_MODULE_RTC_SECONDS = 7,
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KINETIS_LPM_WAKEUP_MODULE_END,
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} llwu_wakeup_module_t;
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/**
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* @brief enum that maps physical pins to wakeup pin numbers in LLWU module
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*
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* Other pins CAN NOT be used to wake the CPU from LLS or VLLSx power modes.
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*/
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typedef enum llwu_wakeup_pin {
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KINETIS_LPM_WAKEUP_PIN_PTE1 = 0,
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KINETIS_LPM_WAKEUP_PIN_PTE2 = 1,
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KINETIS_LPM_WAKEUP_PIN_PTE4 = 2,
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KINETIS_LPM_WAKEUP_PIN_PTA4 = 3,
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KINETIS_LPM_WAKEUP_PIN_PTA13 = 4,
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KINETIS_LPM_WAKEUP_PIN_PTB0 = 5,
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KINETIS_LPM_WAKEUP_PIN_PTC1 = 6,
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KINETIS_LPM_WAKEUP_PIN_PTC3 = 7,
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KINETIS_LPM_WAKEUP_PIN_PTC4 = 8,
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KINETIS_LPM_WAKEUP_PIN_PTC5 = 9,
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KINETIS_LPM_WAKEUP_PIN_PTC6 = 10,
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KINETIS_LPM_WAKEUP_PIN_PTC11 = 11,
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KINETIS_LPM_WAKEUP_PIN_PTD0 = 12,
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KINETIS_LPM_WAKEUP_PIN_PTD2 = 13,
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KINETIS_LPM_WAKEUP_PIN_PTD4 = 14,
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KINETIS_LPM_WAKEUP_PIN_PTD6 = 15,
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KINETIS_LPM_WAKEUP_PIN_END
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} llwu_wakeup_pin_t;
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#endif /* CPU_CONF_H */
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/** @} */
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