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RIOT/cpu/atmega_common/include/irq_arch.h
Marian Buschsieweke 9e566370bf
cpu/atmega_common: Fixed irq_arch implementation
The inline assembly implementation was badly in need of improvement.

- irq_disable() took 2 CPU cycles more than needed
    - The current interrupt state was stored in a temporary register and
      afterwards copied to the target register, rather than storing it in the
      target register right away
    - The lower bits of the state were cleared (as they have no meaning for the
      interrupt status), but the API purposely never required such things from
      implementations.
- irq_restore() took 5 CPU cycles. This was reduced to 3 CPU cycles (or 2 CPU
  cycles in the best case)
2020-05-26 15:19:14 +02:00

111 lines
2.5 KiB
C

/*
* Copyright (C) 2014 Freie Universität Berlin, Hinnerk van Bruinehsen
* 2018 RWTH Aachen, Josua Arndt <jarndt@ias.rwth-aachen.de>
* 2020 Otto-von-Guericke-Universität Magdeburg
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup cpu_atmega_common
* @{
*
* @file
* @brief Implementation of the kernels irq interface
*
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
* @author Hinnerk van Bruinehsen <h.v.bruinehsen@fu-berlin.de>
* @author Josua Arndt <jarndt@ias.rwth-aachen.de>
* @author Marian Buschsieweke <marian.buschsieweke@ovgu.de>
*
*/
#ifndef IRQ_ARCH_H
#define IRQ_ARCH_H
#include <stdint.h>
#include <stdio.h>
#include <stdint.h>
#include "irq.h"
#include "cpu.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Disable all maskable interrupts
*/
__attribute__((always_inline)) static inline unsigned int irq_disable(void)
{
uint8_t mask;
__asm__ volatile(
"in %[dest], __SREG__" "\n\t"
"cli" "\n\t"
: [dest] "=r"(mask)
: /* no inputs */
: "memory"
);
return mask;
}
/**
* @brief Enable all maskable interrupts
*/
__attribute__((always_inline)) static inline unsigned int irq_enable(void)
{
uint8_t mask;
__asm__ volatile(
"in %[dest], __SREG__" "\n\t"
"sei" "\n\t"
: [dest] "=r"(mask)
: /* no inputs */
: "memory"
);
return mask;
}
/**
* @brief Restore the state of the IRQ flags
*/
__attribute__((always_inline)) static inline void irq_restore(unsigned int _state)
{
uint8_t state = (uint8_t)_state;
/*
* Implementation in pseudo-code:
*
* disable_irqs();
* if (state & BIT7) {
* enable_irqs();
* }
*
* This takes 3 CPU Cycles if BIT7 is set (IRQs are enabled), otherwise 2.
*/
__asm__ volatile(
"cli" "\n\t"
"sbrc %[state], 7" "\n\t"
"sei" "\n\t"
: /* no outputs */
: [state] "r"(state)
: "memory"
);
}
/**
* @brief See if the current context is inside an ISR
*/
__attribute__((always_inline)) static inline int irq_is_in(void)
{
uint8_t state = atmega_get_state();
return (state & ATMEGA_STATE_FLAG_ISR);
}
#ifdef __cplusplus
}
#endif
/** @} */
#endif /* IRQ_ARCH_H */