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d37adee32d
There is no hardware limitation for custom boards based on STM32 to uses SPI bus with signals coming from different PORT and alternate functions. This patch allow alternate's function definition per pin basis, thus enable the support of SPI bus signals routed on differents PORT. Signed-off-by: Yannick Gicquel <ygicquel@gmail.com>
301 lines
8.4 KiB
C
301 lines
8.4 KiB
C
/*
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* Copyright (C) 2014 Hamburg University of Applied Sciences
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* 2014-2017 Freie Universität Berlin
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* 2016-2017 OTA keys S.A.
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_stm32_common
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* @ingroup drivers_periph_spi
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* @{
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*
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* @file
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* @brief Low-level SPI driver implementation
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*
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* @author Peter Kietzmann <peter.kietzmann@haw-hamburg.de>
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* @author Fabian Nack <nack@inf.fu-berlin.de>
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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* @author Vincent Dupont <vincent@otakeys.com>
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* @author Joakim Nohlgård <joakim.nohlgard@eistec.se>
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* @author Thomas Eichinger <thomas.eichinger@fu-berlin.de>
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*
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* @}
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*/
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#include "cpu.h"
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#include "mutex.h"
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#include "assert.h"
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#include "periph/spi.h"
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#include "pm_layered.h"
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/**
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* @brief Number of bits to shift the BR value in the CR1 register
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*/
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#define BR_SHIFT (3U)
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/**
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* @brief Allocate one lock per SPI device
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*/
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static mutex_t locks[SPI_NUMOF];
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static inline SPI_TypeDef *dev(spi_t bus)
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{
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return spi_config[bus].dev;
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}
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void spi_init(spi_t bus)
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{
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assert(bus < SPI_NUMOF);
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/* initialize device lock */
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mutex_init(&locks[bus]);
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/* trigger pin initialization */
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spi_init_pins(bus);
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periph_clk_en(spi_config[bus].apbbus, spi_config[bus].rccmask);
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/* reset configuration */
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dev(bus)->CR1 = 0;
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#ifdef SPI_I2SCFGR_I2SE
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dev(bus)->I2SCFGR = 0;
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#endif
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/* configure SPI for 8-bit data width */
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#ifdef SPI_CR2_FRXTH
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dev(bus)->CR2 = (SPI_CR2_FRXTH | SPI_CR2_DS_0 | SPI_CR2_DS_1 | SPI_CR2_DS_2);
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#else
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dev(bus)->CR2 = 0;
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#endif
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periph_clk_dis(spi_config[bus].apbbus, spi_config[bus].rccmask);
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}
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void spi_init_pins(spi_t bus)
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{
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#ifdef CPU_FAM_STM32F1
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gpio_init_af(spi_config[bus].sclk_pin, GPIO_AF_OUT_PP);
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gpio_init_af(spi_config[bus].mosi_pin, GPIO_AF_OUT_PP);
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gpio_init(spi_config[bus].miso_pin, GPIO_IN);
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#else
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gpio_init(spi_config[bus].mosi_pin, GPIO_OUT);
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gpio_init(spi_config[bus].miso_pin, GPIO_IN);
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gpio_init(spi_config[bus].sclk_pin, GPIO_OUT);
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gpio_init_af(spi_config[bus].mosi_pin, spi_config[bus].mosi_af);
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gpio_init_af(spi_config[bus].miso_pin, spi_config[bus].miso_af);
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gpio_init_af(spi_config[bus].sclk_pin, spi_config[bus].sclk_af);
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#endif
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}
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int spi_init_cs(spi_t bus, spi_cs_t cs)
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{
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if (bus >= SPI_NUMOF) {
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return SPI_NODEV;
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}
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if (cs == SPI_CS_UNDEF ||
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(((cs & SPI_HWCS_MASK) == SPI_HWCS_MASK) && (cs & ~(SPI_HWCS_MASK)))) {
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return SPI_NOCS;
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}
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if (cs == SPI_HWCS_MASK) {
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if (spi_config[bus].cs_pin == GPIO_UNDEF) {
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return SPI_NOCS;
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}
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#ifdef CPU_FAM_STM32F1
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gpio_init_af(spi_config[bus].cs_pin, GPIO_AF_OUT_PP);
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#else
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gpio_init(spi_config[bus].cs_pin, GPIO_OUT);
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gpio_init_af(spi_config[bus].cs_pin, spi_config[bus].cs_af);
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#endif
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}
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else {
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gpio_init((gpio_t)cs, GPIO_OUT);
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gpio_set((gpio_t)cs);
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}
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return SPI_OK;
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}
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#ifdef MODULE_PERIPH_SPI_GPIO_MODE
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int spi_init_with_gpio_mode(spi_t bus, spi_gpio_mode_t mode)
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{
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assert(bus < SPI_NUMOF);
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int ret = 0;
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#ifdef CPU_FAM_STM32F1
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/* This has no effect on STM32F1 */
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return ret;
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#else
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ret += gpio_init(spi_config[bus].mosi_pin, mode.mosi);
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ret += gpio_init(spi_config[bus].miso_pin, mode.miso);
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ret += gpio_init(spi_config[bus].sclk_pin, mode.sclk);
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gpio_init_af(spi_config[bus].mosi_pin, spi_config[bus].mosi_af);
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gpio_init_af(spi_config[bus].miso_pin, spi_config[bus].miso_af);
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gpio_init_af(spi_config[bus].sclk_pin, spi_config[bus].sclk_af);
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return ret;
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#endif
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}
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#endif
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int spi_acquire(spi_t bus, spi_cs_t cs, spi_mode_t mode, spi_clk_t clk)
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{
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/* lock bus */
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mutex_lock(&locks[bus]);
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#ifdef STM32_PM_STOP
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/* block STOP mode */
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pm_block(STM32_PM_STOP);
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#endif
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/* enable SPI device clock */
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periph_clk_en(spi_config[bus].apbbus, spi_config[bus].rccmask);
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/* enable device */
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uint8_t br = spi_divtable[spi_config[bus].apbbus][clk];
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dev(bus)->CR1 = ((br << BR_SHIFT) | mode | SPI_CR1_MSTR);
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if (cs != SPI_HWCS_MASK) {
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dev(bus)->CR1 |= (SPI_CR1_SSM | SPI_CR1_SSI);
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}
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else {
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dev(bus)->CR2 |= (SPI_CR2_SSOE);
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}
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return SPI_OK;
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}
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void spi_release(spi_t bus)
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{
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/* disable device and release lock */
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dev(bus)->CR1 = 0;
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dev(bus)->CR2 &= ~(SPI_CR2_SSOE);
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periph_clk_dis(spi_config[bus].apbbus, spi_config[bus].rccmask);
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#ifdef STM32_PM_STOP
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/* unblock STOP mode */
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pm_unblock(STM32_PM_STOP);
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#endif
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mutex_unlock(&locks[bus]);
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}
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static inline void _wait_for_end(spi_t bus)
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{
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/* make sure the transfer is completed before continuing, see reference
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* manual(s) -> section 'Disabling the SPI' */
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while (!(dev(bus)->SR & SPI_SR_TXE)) {}
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while (dev(bus)->SR & SPI_SR_BSY) {}
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}
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#ifdef MODULE_PERIPH_DMA
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static void _transfer_dma(spi_t bus, const void *out, void *in, size_t len)
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{
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uint8_t tmp = 0;
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dma_acquire(spi_config[bus].tx_dma);
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dma_acquire(spi_config[bus].rx_dma);
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if (!out) {
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dma_configure(spi_config[bus].tx_dma, spi_config[bus].tx_dma_chan, &tmp,
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&(dev(bus)->DR), len, DMA_MEM_TO_PERIPH, 0);
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}
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else {
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dma_configure(spi_config[bus].tx_dma, spi_config[bus].tx_dma_chan, out,
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&(dev(bus)->DR), len, DMA_MEM_TO_PERIPH, DMA_INC_SRC_ADDR);
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}
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if (!in) {
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dma_configure(spi_config[bus].rx_dma, spi_config[bus].rx_dma_chan,
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&(dev(bus)->DR), &tmp, len, DMA_PERIPH_TO_MEM, 0);
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}
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else {
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dma_configure(spi_config[bus].rx_dma, spi_config[bus].rx_dma_chan,
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&(dev(bus)->DR), in, len, DMA_PERIPH_TO_MEM, DMA_INC_DST_ADDR);
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}
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dev(bus)->CR2 |= SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN;
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dma_start(spi_config[bus].rx_dma);
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dma_start(spi_config[bus].tx_dma);
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dma_wait(spi_config[bus].rx_dma);
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dma_wait(spi_config[bus].tx_dma);
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dev(bus)->CR2 &= ~(SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
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dma_stop(spi_config[bus].tx_dma);
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dma_stop(spi_config[bus].rx_dma);
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dma_release(spi_config[bus].tx_dma);
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dma_release(spi_config[bus].rx_dma);
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_wait_for_end(bus);
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}
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#endif
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static void _transfer_no_dma(spi_t bus, const void *out, void *in, size_t len)
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{
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const uint8_t *outbuf = out;
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uint8_t *inbuf = in;
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/* we need to recast the data register to uint_8 to force 8-bit access */
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volatile uint8_t *DR = (volatile uint8_t*)&(dev(bus)->DR);
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/* transfer data, use shortpath if only sending data */
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if (!inbuf) {
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for (size_t i = 0; i < len; i++) {
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while (!(dev(bus)->SR & SPI_SR_TXE));
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*DR = outbuf[i];
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}
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/* wait until everything is finished and empty the receive buffer */
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while (!(dev(bus)->SR & SPI_SR_TXE)) {}
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while (dev(bus)->SR & SPI_SR_BSY) {}
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while (dev(bus)->SR & SPI_SR_RXNE) {
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dev(bus)->DR; /* we might just read 2 bytes at once here */
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}
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}
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else if (!outbuf) {
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for (size_t i = 0; i < len; i++) {
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while (!(dev(bus)->SR & SPI_SR_TXE));
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*DR = 0;
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while (!(dev(bus)->SR & SPI_SR_RXNE));
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inbuf[i] = *DR;
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}
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}
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else {
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for (size_t i = 0; i < len; i++) {
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while (!(dev(bus)->SR & SPI_SR_TXE));
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*DR = outbuf[i];
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while (!(dev(bus)->SR & SPI_SR_RXNE));
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inbuf[i] = *DR;
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}
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}
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_wait_for_end(bus);
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}
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void spi_transfer_bytes(spi_t bus, spi_cs_t cs, bool cont,
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const void *out, void *in, size_t len)
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{
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/* make sure at least one input or one output buffer is given */
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assert(out || in);
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/* active the given chip select line */
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dev(bus)->CR1 |= (SPI_CR1_SPE); /* this pulls the HW CS line low */
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if ((cs != SPI_HWCS_MASK) && (cs != SPI_CS_UNDEF)) {
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gpio_clear((gpio_t)cs);
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}
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#ifdef MODULE_PERIPH_DMA
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if (spi_config[bus].tx_dma != DMA_STREAM_UNDEF
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&& spi_config[bus].rx_dma != DMA_STREAM_UNDEF) {
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_transfer_dma(bus, out, in, len);
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}
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else {
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#endif
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_transfer_no_dma(bus, out, in, len);
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#ifdef MODULE_PERIPH_DMA
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}
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#endif
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/* release the chip select if not specified differently */
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if ((!cont) && (cs != SPI_CS_UNDEF)) {
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dev(bus)->CR1 &= ~(SPI_CR1_SPE); /* pull HW CS line high */
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if (cs != SPI_HWCS_MASK) {
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gpio_set((gpio_t)cs);
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}
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}
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}
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