mirror of
https://github.com/RIOT-OS/RIOT.git
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d6499fa8fd
GCC 12 create a bogus array out of bounds warning as it assumes that
because there is special handling for `uart == 0` and `uart == 1`,
`uart` can indeed be `1`. There is an `assert(uart < UART_NUMOF)` above
that would blow up prior to any out of bounds access.
In any case, optimizing out the special handling of `uart == 1` for
when `UART_NUMOF == 1` likely improves the generated code and fixes
the warning.
/home/maribu/Repos/software/RIOT/cc2650/cpu/cc26xx_cc13xx/periph/uart.c:88:8: error: array subscript 1 is above array bounds of 'uart_isr_ctx_t[1]' [-Werror=array-bounds]
88 | ctx[uart].rx_cb = rx_cb;
| ~~~^~~~~~
/home/maribu/Repos/software/RIOT/cc2650/cpu/cc26xx_cc13xx/periph/uart.c:52:23: note: while referencing 'ctx'
52 | static uart_isr_ctx_t ctx[UART_NUMOF];
| ^~~
/home/maribu/Repos/software/RIOT/cc2650/cpu/cc26xx_cc13xx/periph/uart.c:89:8: error: array subscript 1 is above array bounds of 'uart_isr_ctx_t[1]' [-Werror=array-bounds]
89 | ctx[uart].arg = arg;
| ~~~^~~~~~
/home/maribu/Repos/software/RIOT/cc2650/cpu/cc26xx_cc13xx/periph/uart.c:52:23: note: while referencing 'ctx'
52 | static uart_isr_ctx_t ctx[UART_NUMOF];
| ^~~
238 lines
6.0 KiB
C
238 lines
6.0 KiB
C
/*
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* Copyright (C) 2016 Leon George
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* Copyright (C) 2020 Locha Inc
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_cc26xx_cc13xx
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* @ingroup drivers_periph_uart
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* @{
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*
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* @file
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* @brief Low-level UART driver implementation
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*
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* @author Leon M. George <leon@georgemail.eu>
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* @author Anton Gerasimov <tossel@gmail.com>
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* @author Jean Pierre Dudey <jeandudey@hotmail.com>
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*
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* @}
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*/
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#include <assert.h>
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#include "cpu.h"
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#include "periph/uart.h"
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#include "periph_conf.h"
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#include "cc26xx_cc13xx_power.h"
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/**
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* @brief Bit mask for the fractional part of the baudrate
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*/
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#define FRAC_BITS (6U)
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#define FRAC_MASK (0x3f)
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/**
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* @brief Get the enable mask depending on enabled HW flow control
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*/
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#ifdef MODULE_PERIPH_UART_HW_FC
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#define ENABLE_MASK (UART_CTSEN | UART_CTL_RTSEN | \
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UART_CTL_RXE | UART_CTL_TXE | UART_CTL_UARTEN)
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#else
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#define ENABLE_MASK (UART_CTL_RXE | UART_CTL_TXE | UART_CTL_UARTEN)
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#endif
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/**
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* @brief allocate memory to store callback functions
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*/
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static uart_isr_ctx_t ctx[UART_NUMOF];
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int uart_init(uart_t uart, uint32_t baudrate, uart_rx_cb_t rx_cb, void *arg)
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{
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assert(uart < UART_NUMOF);
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uart_regs_t *uart_reg = uart_config[uart].regs;
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int tx_pin = uart_config[uart].tx_pin;
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int rx_pin = uart_config[uart].rx_pin;
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int intn = uart_config[uart].intn;
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#ifdef MODULE_PERIPH_UART_HW_FC
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int rts_pin = uart_config[uart].rts_pin;
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int cts_pin = uart_config[uart].cts_pin;
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#endif
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if ((UART_NUMOF == 1) || (uart == 0)) {
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/* UART0 requires serial domain to be enabled */
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if (!power_is_domain_enabled(POWER_DOMAIN_SERIAL)) {
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power_enable_domain(POWER_DOMAIN_SERIAL);
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}
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}
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#ifdef CPU_VARIANT_X2
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else if (uart == 1) {
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/* UART1 requires periph domain to be enabled */
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if (!power_is_domain_enabled(POWER_DOMAIN_PERIPHERALS)) {
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power_enable_domain(POWER_DOMAIN_PERIPHERALS);
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}
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}
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#endif
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uart_poweron(uart);
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/* disable and reset the UART */
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uart_reg->CTL = 0;
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/* save context */
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ctx[uart].rx_cb = rx_cb;
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ctx[uart].arg = arg;
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/* configure pins */
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if (uart == 0) {
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IOC->CFG[tx_pin] = IOCFG_PORTID_UART0_TX;
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IOC->CFG[rx_pin] = (IOCFG_PORTID_UART0_RX | IOCFG_INPUT_ENABLE);
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#ifdef MODULE_PERIPH_UART_HW_FC
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if (rts_pin != GPIO_UNDEF && cts_pin != GPIO_UNDEF) {
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IOC->CFG[rts_pin] = IOCFG_PORTID_UART0_RTS;
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IOC->CFG[cts_pin] = (IOCFG_PORTID_UART0_CTS | IOCFG_INPUT_ENABLE);
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}
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#endif
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}
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#ifdef CPU_VARIANT_X2
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else if (uart == 1) {
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IOC->CFG[tx_pin] = IOCFG_PORTID_UART1_TX;
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IOC->CFG[rx_pin] = (IOCFG_PORTID_UART1_RX | IOCFG_INPUT_ENABLE);
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#ifdef MODULE_PERIPH_UART_HW_FC
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if (rts_pin != GPIO_UNDEF && cts_pin != GPIO_UNDEF) {
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IOC->CFG[rts_pin] = IOCFG_PORTID_UART1_RTS;
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IOC->CFG[cts_pin] = (IOCFG_PORTID_UART1_CTS | IOCFG_INPUT_ENABLE);
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}
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#endif
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}
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#endif
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/* calculate baud-rate */
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uint32_t tmp = (CLOCK_CORECLOCK * 4);
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tmp += (baudrate / 2);
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tmp /= baudrate;
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uart_reg->IBRD = (tmp >> FRAC_BITS);
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uart_reg->FBRD = (tmp & FRAC_MASK);
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/* configure line to 8N1 mode, LRCH must be written after IBRD and FBRD! */
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uart_reg->LCRH = UART_LCRH_WLEN_8;
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/* enable the RX interrupt */
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uart_reg->IMSC = UART_IMSC_RXIM;
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NVIC_EnableIRQ(intn);
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/* start the UART */
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uart_reg->CTL = ENABLE_MASK;
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return UART_OK;
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}
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#ifdef MODULE_PERIPH_UART_MODECFG
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int uart_mode(uart_t uart, uart_data_bits_t data_bits, uart_parity_t parity,
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uart_stop_bits_t stop_bits)
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{
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assert(data_bits == UART_DATA_BITS_5 ||
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data_bits == UART_DATA_BITS_6 ||
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data_bits == UART_DATA_BITS_7 ||
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data_bits == UART_DATA_BITS_8);
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assert(parity == UART_PARITY_NONE ||
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parity == UART_PARITY_EVEN ||
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parity == UART_PARITY_ODD ||
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parity == UART_PARITY_MARK ||
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parity == UART_PARITY_SPACE);
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assert(stop_bits == UART_STOP_BITS_1 ||
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stop_bits == UART_STOP_BITS_2);
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assert(uart < UART_NUMOF);
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uart_regs_t *uart_reg = uart_config[uart].regs;
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/* cc26xx/cc13xx does not support mark or space parity */
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if (parity == UART_PARITY_MARK || parity == UART_PARITY_SPACE) {
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return UART_NOMODE;
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}
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/* Disable UART and clear old settings */
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uart_reg->CTL = 0;
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uart_reg->LCRH = 0;
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/* Apply setting and enable UART */
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/* cppcheck-suppress redundantAssignment
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* (reason: disable-enable cycle requires writing zero first) */
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uart_reg->LCRH = data_bits | parity | stop_bits;
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uart_reg->CTL = ENABLE_MASK;
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return UART_OK;
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}
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#endif
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void uart_write(uart_t uart, const uint8_t *data, size_t len)
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{
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assert(uart < UART_NUMOF);
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uart_regs_t *uart_reg = uart_config[uart].regs;
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for (size_t i = 0; i < len; i++) {
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while (uart_reg->FR & UART_FR_TXFF) {}
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uart_reg->DR = data[i];
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}
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}
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void uart_poweron(uart_t uart)
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{
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assert(uart < UART_NUMOF);
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uart_regs_t *uart_reg = uart_config[uart].regs;
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/* Enable clock for this UART */
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power_clock_enable_uart(uart);
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uart_reg->CTL = ENABLE_MASK;
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}
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void uart_poweroff(uart_t uart)
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{
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assert(uart < UART_NUMOF);
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uart_regs_t *uart_reg = uart_config[uart].regs;
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uart_reg->CTL = 0;
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/* Disable clock for this UART */
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power_clock_disable_uart(uart);
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}
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static void isr_uart(uart_t uart)
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{
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assert(uart < UART_NUMOF);
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uart_regs_t *uart_reg = uart_config[uart].regs;
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/* remember pending interrupts */
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uint32_t mis = uart_reg->MIS;
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/* clear them */
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uart_reg->ICR = mis;
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/* read received byte and pass it to the RX callback */
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if (mis & UART_MIS_RXMIS) {
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ctx[uart].rx_cb(ctx[uart].arg, (uint8_t)uart_reg->DR);
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}
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cortexm_isr_end();
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}
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void isr_uart0(void) {
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isr_uart(0);
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}
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void isr_uart1(void) {
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isr_uart(1);
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}
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