mirror of
https://github.com/RIOT-OS/RIOT.git
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198 lines
4.8 KiB
C
198 lines
4.8 KiB
C
/*
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* Copyright (C) 2020 Mesotic SAS
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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*/
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/**
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* @ingroup cpu_sam0_common
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* @{
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*
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* @file
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* @brief Low-level Ethernet driver implementation
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*
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* @author Dylan Laduranty <dylan.laduranty@mesotic.com>
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*
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* @}
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*/
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#include <string.h>
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#include "iolist.h"
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#include "net/gnrc/netif/ethernet.h"
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#include "net/gnrc.h"
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#include "net/ethernet.h"
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#include "net/netdev/eth.h"
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#include "net/eui_provider.h"
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#include "periph/gpio.h"
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#include "sam0_eth_netdev.h"
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#define ENABLE_DEBUG 0
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#include "debug.h"
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#include "log.h"
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/* Internal helpers */
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extern int sam0_eth_init(void);
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extern void sam0_eth_poweron(void);
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extern void sam0_eth_poweroff(void);
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extern int sam0_eth_send(const struct iolist *iolist);
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extern int sam0_eth_receive_blocking(char *data, unsigned max_len);
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extern bool sam0_eth_has_queued_pkt(void);
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extern void sam0_eth_set_mac(const eui48_t *mac);
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extern void sam0_eth_get_mac(char *out);
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extern void sam0_clear_rx_buffers(void);
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/* SAM0 CPUs only have one GMAC IP, so it is safe to
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statically defines one in this file */
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static sam0_eth_netdev_t _sam0_eth_dev;
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static int _sam0_eth_init(netdev_t *netdev)
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{
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sam0_eth_init();
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eui48_t hwaddr;
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netdev_eui48_get(netdev, &hwaddr);
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sam0_eth_set_mac(&hwaddr);
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return 0;
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}
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static void _sam0_eth_isr(netdev_t *netdev)
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{
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netdev->event_callback(netdev, NETDEV_EVENT_RX_COMPLETE);
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return;
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}
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static int _sam0_eth_recv(netdev_t *netdev, void *buf, size_t len, void *info)
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{
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(void)info;
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(void)netdev;
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unsigned ret = sam0_eth_receive_blocking((char *)buf, len);
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/* frame received, check if another frame is queued */
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if (buf && sam0_eth_has_queued_pkt()) {
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netdev_trigger_event_isr(netdev);
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}
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return ret;
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}
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static int _sam0_eth_send(netdev_t *netdev, const iolist_t *iolist)
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{
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int ret;
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netdev->event_callback(netdev, NETDEV_EVENT_TX_STARTED);
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ret = sam0_eth_send(iolist);
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if (ret == -EOVERFLOW) {
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/* TODO: use a specific netdev callback here ? */
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return -EOVERFLOW;
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}
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netdev->event_callback(netdev, NETDEV_EVENT_TX_COMPLETE);
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return ret;
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}
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static int _sam0_eth_get(netdev_t *netdev, netopt_t opt, void *val, size_t max_len)
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{
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int res = -1;
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switch (opt) {
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case NETOPT_ADDRESS:
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assert(max_len >= ETHERNET_ADDR_LEN);
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sam0_eth_get_mac((char *)val);
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res = ETHERNET_ADDR_LEN;
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break;
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default:
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res = netdev_eth_get(netdev, opt, val, max_len);
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break;
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}
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return res;
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}
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static int _set_state(netopt_state_t state)
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{
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switch (state) {
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case NETOPT_STATE_SLEEP:
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sam0_eth_poweroff();
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break;
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case NETOPT_STATE_IDLE:
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sam0_eth_poweron();
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break;
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default:
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return -ENOTSUP;
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}
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return sizeof(netopt_state_t);
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}
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static int _sam0_eth_set(netdev_t *netdev, netopt_t opt, const void *val, size_t max_len)
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{
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int res = -1;
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switch (opt) {
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case NETOPT_ADDRESS:
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assert(max_len >= ETHERNET_ADDR_LEN);
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sam0_eth_set_mac((eui48_t *)val);
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res = ETHERNET_ADDR_LEN;
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break;
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case NETOPT_STATE:
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assert(max_len <= sizeof(netopt_state_t));
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return _set_state(*((const netopt_state_t *)val));
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default:
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res = netdev_eth_set(netdev, opt, val, max_len);
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break;
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}
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return res;
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}
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static const netdev_driver_t _sam0_eth_driver =
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{
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.send = _sam0_eth_send,
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.recv = _sam0_eth_recv,
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.init = _sam0_eth_init,
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.isr = _sam0_eth_isr,
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.get = _sam0_eth_get,
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.set = _sam0_eth_set,
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};
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void sam0_eth_setup(netdev_t* netdev)
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{
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DEBUG_PUTS("[sam0_eth]: initializing SAM0 Ethernet MAC (GMAC) device");
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_sam0_eth_dev.netdev = netdev;
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/* set the netdev driver */
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netdev->driver = &_sam0_eth_driver;
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/* Register SAM0 Ethernet to netdev */
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netdev_register(netdev, NETDEV_SAM0_ETH, 0);
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}
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void isr_gmac(void)
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{
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uint32_t isr;
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uint32_t rsr;
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isr = GMAC->ISR.reg;
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rsr = GMAC->RSR.reg;
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(void)isr;
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/* New frame received, signal it to netdev */
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if (rsr & GMAC_RSR_REC) {
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netdev_trigger_event_isr(_sam0_eth_dev.netdev);
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}
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/* Buffers Not Available, this can occur if there is a heavy traffic
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on the network. In this case, disable the GMAC reception, flush
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our internal buffers and re-enable the reception. This will drop
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a few packets but it allows the GMAC IP to remains functional */
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if (rsr & GMAC_RSR_BNA) {
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GMAC->NCR.reg &= ~GMAC_NCR_RXEN;
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sam0_clear_rx_buffers();
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GMAC->NCR.reg |= GMAC_NCR_RXEN;
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}
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GMAC->RSR.reg = rsr;
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cortexm_isr_end();
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}
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