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df37e69b90
Currently the cc2538 is based on from-scratch adaption which is
not feature complete and thus lacks defines etc. Introducing the
official vendor header will ease future extension and adaptions
of the CPU and its features.
745 lines
49 KiB
C
Executable File
745 lines
49 KiB
C
Executable File
/******************************************************************************
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* Filename: hw_udma.h
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* Revised: $Date: 2013-04-30 17:13:44 +0200 (Tue, 30 Apr 2013) $
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* Revision: $Revision: 9943 $
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*
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* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* Neither the name of Texas Instruments Incorporated nor the names of
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* its contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************/
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#ifndef __HW_UDMA_H__
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#define __HW_UDMA_H__
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//*****************************************************************************
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//
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// The following are defines for the UDMA register offsets.
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//
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//*****************************************************************************
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#define UDMA_STAT 0x400FF000 // DMA status The STAT register
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// returns the status of the uDMA
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// controller. This register cannot
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// be read when the uDMA controller
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// is in the reset state.
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#define UDMA_CFG 0x400FF004 // DMA configuration The CFG
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// register controls the
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// configuration of the uDMA
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// controller.
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#define UDMA_CTLBASE 0x400FF008 // DMA channel control base
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// pointer The CTLBASE register
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// must be configured so that the
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// base pointer points to a
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// location in system memory. The
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// amount of system memory that
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// must be assigned to the uDMA
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// controller depends on the number
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// of uDMA channels used and
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// whether the alternate channel
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// control data structure is used.
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// See Section 10.2.5 for details
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// about the Channel Control Table.
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// The base address must be aligned
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// on a 1024-byte boundary. This
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// register cannot be read when the
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// uDMA controller is in the reset
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// state.
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#define UDMA_ALTBASE 0x400FF00C // DMA alternate channel control
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// base pointer The ALTBASE
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// register returns the base
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// address of the alternate channel
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// control data. This register
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// removes the necessity for
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// application software to
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// calculate the base address of
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// the alternate channel control
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// structures. This register cannot
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// be read when the uDMA controller
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// is in the reset state.
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#define UDMA_WAITSTAT 0x400FF010 // DMA channel wait-on-request
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// status This read-only register
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// indicates that the uDMA channel
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// is waiting on a request. A
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// peripheral can hold off the uDMA
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// from performing a single request
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// until the peripheral is ready
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// for a burst request to enhance
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// the uDMA performance. The use of
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// this feature is dependent on the
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// design of the peripheral and is
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// not controllable by software in
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// any way. This register cannot be
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// read when the uDMA controller is
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// in the reset state.
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#define UDMA_SWREQ 0x400FF014 // DMA channel software request
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// Each bit of the SWREQ register
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// represents the corresponding
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// uDMA channel. Setting a bit
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// generates a request for the
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// specified uDMA channel.
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#define UDMA_USEBURSTSET 0x400FF018 // DMA channel useburst set Each
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// bit of the USEBURSTSET register
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// represents the corresponding
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// uDMA channel. Setting a bit
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// disables the channel single
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// request input from generating
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// requests, configuring the
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// channel to only accept burst
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// requests. Reading the register
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// returns the status of USEBURST.
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// If the amount of data to
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// transfer is a multiple of the
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// arbitration (burst) size, the
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// corresponding SET[n] bit is
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// cleared after completing the
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// final transfer. If there are
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// fewer items remaining to
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// transfer than the arbitration
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// (burst) size, the uDMA
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// controller automatically clears
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// the corresponding SET[n] bit,
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// allowing the remaining items to
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// transfer using single requests.
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// To resume transfers using burst
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// requests, the corresponding bit
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// must be set again. A bit must
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// not be set if the corresponding
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// peripheral does not support the
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// burst request model.
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#define UDMA_USEBURSTCLR 0x400FF01C // DMA channel useburst clear Each
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// bit of the USEBURSTCLR register
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// represents the corresponding
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// uDMA channel. Setting a bit
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// clears the corresponding SET[n]
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// bit in the USEBURSTSET register.
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#define UDMA_REQMASKSET 0x400FF020 // DMA channel request mask set
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// Each bit of the REQMASKSET
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// register represents the
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// corresponding uDMA channel.
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// Setting a bit disables uDMA
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// requests for the channel.
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// Reading the register returns the
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// request mask status. When a uDMA
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// channel request is masked, that
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// means the peripheral can no
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// longer request uDMA transfers.
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// The channel can then be used for
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// software-initiated transfers.
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#define UDMA_REQMASKCLR 0x400FF024 // DMA channel request mask clear
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// Each bit of the REQMASKCLR
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// register represents the
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// corresponding uDMA channel.
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// Setting a bit clears the
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// corresponding SET[n] bit in the
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// REQMASKSET register.
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#define UDMA_ENASET 0x400FF028 // DMA channel enable set Each bit
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// of the ENASET register
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// represents the corresponding
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// uDMA channel. Setting a bit
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// enables the corresponding uDMA
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// channel. Reading the register
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// returns the enable status of the
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// channels. If a channel is
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// enabled but the request mask is
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// set (REQMASKSET), then the
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// channel can be used for
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// software-initiated transfers.
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#define UDMA_ENACLR 0x400FF02C // DMA channel enable clear Each
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// bit of the ENACLR register
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// represents the corresponding
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// uDMA channel. Setting a bit
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// clears the corresponding SET[n]
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// bit in the ENASET register.
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#define UDMA_ALTSET 0x400FF030 // DMA channel primary alternate
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// set Each bit of the ALTSET
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// register represents the
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// corresponding uDMA channel.
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// Setting a bit configures the
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// uDMA channel to use the
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// alternate control data
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// structure. Reading the register
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// returns the status of which
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// control data structure is in use
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// for the corresponding uDMA
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// channel.
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#define UDMA_ALTCLR 0x400FF034 // DMA channel primary alternate
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// clear Each bit of the ALTCLR
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// register represents the
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// corresponding uDMA channel.
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// Setting a bit clears the
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// corresponding SET[n] bit in the
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// ALTSET register.
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#define UDMA_PRIOSET 0x400FF038 // DMA channel priority set Each
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// bit of the PRIOSET register
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// represents the corresponding
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// uDMA channel. Setting a bit
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// configures the uDMA channel to
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// have a high priority level.
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// Reading the register returns the
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// status of the channel priority
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// mask.
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#define UDMA_PRIOCLR 0x400FF03C // DMA channel priority clear Each
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// bit of the DMAPRIOCLR register
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// represents the corresponding
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// uDMA channel. Setting a bit
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// clears the corresponding SET[n]
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// bit in the PRIOSET register.
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#define UDMA_ERRCLR 0x400FF04C // DMA bus error clear The ERRCLR
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// register is used to read and
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// clear the uDMA bus error status.
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// The error status is set if the
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// uDMA controller encountered a
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// bus error while performing a
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// transfer. If a bus error occurs
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// on a channel, that channel is
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// automatically disabled by the
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// uDMA controller. The other
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// channels are unaffected.
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#define UDMA_CHASGN 0x400FF500 // DMA channel assignment Each bit
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// of the CHASGN register
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// represents the corresponding
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// uDMA channel. Setting a bit
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// selects the secondary channel
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// assignment as specified in the
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// section "Channel Assignments"
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#define UDMA_CHIS 0x400FF504 // DMA channel interrupt status
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// Each bit of the CHIS register
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// represents the corresponding
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// uDMA channel. A bit is set when
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// that uDMA channel causes a
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// completion interrupt. The bits
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// are cleared by writing 1.
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#define UDMA_CHMAP0 0x400FF510 // DMA channel map select 0 Each
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// 4-bit field of the CHMAP0
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// register configures the uDMA
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// channel assignment as specified
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// in the uDMA channel assignment
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// table in the "Channel
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// Assignments" section.
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#define UDMA_CHMAP1 0x400FF514 // DMA channel map select 1 Each
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// 4-bit field of the CHMAP1
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// register configures the uDMA
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// channel assignment as specified
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// in the uDMA channel assignment
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// table in the "Channel
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// Assignments" section.
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#define UDMA_CHMAP2 0x400FF518 // DMA channel map select 2 Each
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// 4-bit field of the CHMAP2
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// register configures the uDMA
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// channel assignment as specified
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// in the uDMA channel assignment
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// table in the "Channel
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// Assignments" section.
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#define UDMA_CHMAP3 0x400FF51C // DMA channel map select 3 Each
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// 4-bit field of the CHMAP3
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// register configures the uDMA
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// channel assignment as specified
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// in the uDMA channel assignment
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// table in the "Channel
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// Assignments" section.
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the UDMA_STAT register.
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//
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//*****************************************************************************
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#define UDMA_STAT_DMACHANS_M 0x001F0000 // Available uDMA channels minus 1
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// This field contains a value
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// equal to the number of uDMA
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// channels the uDMA controller is
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// configured to use, minus one.
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// The value of 0x1F corresponds to
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// 32 uDMA channels.
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#define UDMA_STAT_DMACHANS_S 16
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#define UDMA_STAT_STATE_M 0x000000F0 // Control state machine status
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// This field shows the current
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// status of the control
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// state-machine. Status can be one
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// of the following: 0x0: Idle 0x1:
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// Reading channel controller data
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// 0x2: Reading source end pointer
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// 0x3: Reading destination end
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// pointer 0x4: Reading source data
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// 0x5: Writing destination data
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// 0x6: Waiting for uDMA request to
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// clear 0x7: Writing channel
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// controller data 0x8: Stalled
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// 0x9: Done 0xA-0xF: Undefined
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#define UDMA_STAT_STATE_S 4
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#define UDMA_STAT_MASTEN 0x00000001 // Master enable status 0: The
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// uDMA controller is disabled. 1:
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// The uDMA controller is enabled.
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#define UDMA_STAT_MASTEN_M 0x00000001
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#define UDMA_STAT_MASTEN_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the UDMA_CFG register.
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//
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//*****************************************************************************
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#define UDMA_CFG_MASTEN 0x00000001 // Controller master enable 0:
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// Disables the uDMA controller. 1:
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// Enables the uDMA controller.
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#define UDMA_CFG_MASTEN_M 0x00000001
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#define UDMA_CFG_MASTEN_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the UDMA_CTLBASE register.
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//
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//*****************************************************************************
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#define UDMA_CTLBASE_ADDR_M 0xFFFFFC00 // Channel control base address
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// This field contains the pointer
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// to the base address of the
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// channel control table. The base
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// address must be 1024-byte
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// alligned.
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#define UDMA_CTLBASE_ADDR_S 10
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the UDMA_ALTBASE register.
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//
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//*****************************************************************************
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#define UDMA_ALTBASE_ADDR_M 0xFFFFFFFF // Alternate channel address
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// pointer This field provides the
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// base address of the alternate
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// channel control structures.
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#define UDMA_ALTBASE_ADDR_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the
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// UDMA_WAITSTAT register.
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//
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//*****************************************************************************
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#define UDMA_WAITSTAT_WAITREQ_M 0xFFFFFFFF // Channel [n] wait status These
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// bits provide the tchannel
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// wait-on-request status. Bit 0
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// corresponds to channel 0. 1: The
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// corresponding channel is waiting
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// on a request. 0: The
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// corresponding channel is not
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// waiting on a request.
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#define UDMA_WAITSTAT_WAITREQ_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the UDMA_SWREQ register.
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//
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//*****************************************************************************
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#define UDMA_SWREQ_SWREQ_M 0xFFFFFFFF // Channel [n] software request
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// These bits generate software
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// requests. Bit 0 corresponds to
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// channel 0. 1: Generate a
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// software request for the
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// corresponding channel 0: No
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// request generated These bits are
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// automatically cleared when the
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// software request has been
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// completed.
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#define UDMA_SWREQ_SWREQ_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the
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// UDMA_USEBURSTSET register.
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//
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//*****************************************************************************
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#define UDMA_USEBURSTSET_SET_M 0xFFFFFFFF // Channel [n] useburst set 0:
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// uDMA channel [n] responds to
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// single or burst requests. 1:
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// uDMA channel [n] responds only
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// to burst requests. Bit 0
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// corresponds to channel 0. This
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// bit is automatically cleared as
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// described above. A bit can also
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// be manually cleared by setting
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// the corresponding CLR[n] bit in
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// the DMAUSEBURSTCLR register.
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#define UDMA_USEBURSTSET_SET_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the
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// UDMA_USEBURSTCLR register.
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//
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//*****************************************************************************
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#define UDMA_USEBURSTCLR_CLR_M 0xFFFFFFFF // Channel [n] useburst clear 0:
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// No effect 1: Setting a bit
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// clears the corresponding SET[n]
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// bit in the DMAUSEBURSTSET
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// register meaning that uDMA
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// channel [n] responds to single
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// and burst requests.
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#define UDMA_USEBURSTCLR_CLR_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the
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// UDMA_REQMASKSET register.
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//
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//*****************************************************************************
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#define UDMA_REQMASKSET_SET_M 0xFFFFFFFF // Channel [n] request mask set 0:
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// The peripheral associated with
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// channel [n] is enabled to
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// request uDMA transfers 1: The
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// peripheral associated with
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// channel [n] is not able to
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// request uDMA transfers. Channel
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// [n] may be used for
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// software-initiated transfers.
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// Bit 0 corresponds to channel 0.
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// A bit can only be cleared by
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// setting the corresponding CLR[n]
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// bit in the DMAREQMASKCLR
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// register.
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#define UDMA_REQMASKSET_SET_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the
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// UDMA_REQMASKCLR register.
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//
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//*****************************************************************************
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#define UDMA_REQMASKCLR_CLR_M 0xFFFFFFFF // Channel [n] request mask clear
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// 0: No effect 1: Setting a bit
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// clears the corresponding SET[n]
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// bit in the DMAREQMASKSET
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// register meaning that the
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// peripheral associated with
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// channel [n] is enabled to
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// request uDMA transfers.
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#define UDMA_REQMASKCLR_CLR_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the UDMA_ENASET register.
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//
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//*****************************************************************************
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#define UDMA_ENASET_SET_M 0xFFFFFFFF // Channel [n] enable set 0: uDMA
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// channel [n] is disabled 1: uDMA
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// channel [n] is enabled Bit 0
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// corresponds to channel 0. A bit
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// can only be cleared by setting
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// the corresponding CLR[n] bit in
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// the DMAENACLR register.
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#define UDMA_ENASET_SET_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the UDMA_ENACLR register.
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//
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//*****************************************************************************
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#define UDMA_ENACLR_CLR_M 0xFFFFFFFF // Channel [n] enable clear 0: No
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// effect 1: Setting a bit clears
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// the corresponding SET[n] bit in
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// the DMAENASET register meaning
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// that channel [n] is disabled for
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// uDMA transfers. Note: The
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// controller disables a channel
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// when it completes the uDMA
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// cycle.
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#define UDMA_ENACLR_CLR_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the UDMA_ALTSET register.
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//
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//*****************************************************************************
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#define UDMA_ALTSET_SET_M 0xFFFFFFFF // Channel [n] alternate set 0:
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// uDMA channel [n] is using the
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// primary control structure 1:
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// uDMA channel [n] is using the
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// alternate control structure Bit
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// 0 corresponds to channel 0. A
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// bit can only be cleared by
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// setting the corresponding CLR[n]
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// bit in the DMAALTCLR register.
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// Note: For Ping-Pong and
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// Scatter-Gather cycle types, the
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// uDMA controller automatically
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// sets these bits to select the
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// alternate channel control data
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// structure.
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#define UDMA_ALTSET_SET_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the UDMA_ALTCLR register.
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//
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//*****************************************************************************
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#define UDMA_ALTCLR_CLR_M 0xFFFFFFFF // Channel [n] alternate clear 0:
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// No effect 1: Setting a bit
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// clears the corresponding SET[n]
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// bit in the DMAALTSET register
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// meaning that channel [n] is
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// using the primary control
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// structure. Note: For Ping-Pong
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// and Scatter-Gather cycle types,
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// the uDMA controller
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// automatically sets these bits to
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// select the alternate channel
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// control data structure.
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#define UDMA_ALTCLR_CLR_S 0
|
|
//*****************************************************************************
|
|
//
|
|
// The following are defines for the bit fields in the UDMA_PRIOSET register.
|
|
//
|
|
//*****************************************************************************
|
|
#define UDMA_PRIOSET_SET_M 0xFFFFFFFF // Channel [n] priority set 0:
|
|
// uDMA channel [n] is using the
|
|
// default priority level 1: uDMA
|
|
// channel [n] is using a high
|
|
// priority level Bit 0 corresponds
|
|
// to channel 0. A bit can only be
|
|
// cleared by setting the
|
|
// corresponding CLR[n] bit in the
|
|
// DMAPRIOCLR register.
|
|
#define UDMA_PRIOSET_SET_S 0
|
|
//*****************************************************************************
|
|
//
|
|
// The following are defines for the bit fields in the UDMA_PRIOCLR register.
|
|
//
|
|
//*****************************************************************************
|
|
#define UDMA_PRIOCLR_CLR_M 0xFFFFFFFF // Channel [n] priority clear 0:
|
|
// No effect 1: Setting a bit
|
|
// clears the corresponding SET[n]
|
|
// bit in the DMAPRIOSET register
|
|
// meaning that channel [n] is
|
|
// using the default priority
|
|
// level.
|
|
#define UDMA_PRIOCLR_CLR_S 0
|
|
//*****************************************************************************
|
|
//
|
|
// The following are defines for the bit fields in the UDMA_ERRCLR register.
|
|
//
|
|
//*****************************************************************************
|
|
#define UDMA_ERRCLR_ERRCLR 0x00000001 // uDMA bus error status 0: No bus
|
|
// error is pending 1: A bus error
|
|
// is pending This bit is cleared
|
|
// by writing 1 to it.
|
|
#define UDMA_ERRCLR_ERRCLR_M 0x00000001
|
|
#define UDMA_ERRCLR_ERRCLR_S 0
|
|
//*****************************************************************************
|
|
//
|
|
// The following are defines for the bit fields in the UDMA_CHASGN register.
|
|
//
|
|
//*****************************************************************************
|
|
#define UDMA_CHASGN_CHASGN_M 0xFFFFFFFF // Channel [n] assignment select
|
|
// 0: Use the primary channel
|
|
// assignment 1: Use the secondary
|
|
// channel assignment
|
|
#define UDMA_CHASGN_CHASGN_S 0
|
|
//*****************************************************************************
|
|
//
|
|
// The following are defines for the bit fields in the UDMA_CHIS register.
|
|
//
|
|
//*****************************************************************************
|
|
#define UDMA_CHIS_CHIS_M 0xFFFFFFFF // Channel [n] interrupt status 0:
|
|
// The corresponding uDMA channel
|
|
// has not caused an interrupt. 1:
|
|
// The corresponding uDMA channel
|
|
// has caused an interrupt. This
|
|
// bit is cleared by writing 1 to
|
|
// it.
|
|
#define UDMA_CHIS_CHIS_S 0
|
|
//*****************************************************************************
|
|
//
|
|
// The following are defines for the bit fields in the UDMA_CHMAP0 register.
|
|
//
|
|
//*****************************************************************************
|
|
#define UDMA_CHMAP0_CH7SEL_M 0xF0000000 // uDMA channel 7 source select
|
|
// See section titled "Channel
|
|
// Assignments" in Micro Direct
|
|
// Memory Access chapter.
|
|
#define UDMA_CHMAP0_CH7SEL_S 28
|
|
#define UDMA_CHMAP0_CH6SEL_M 0x0F000000 // uDMA channel 6 source select
|
|
// See section titled "Channel
|
|
// Assignments" in Micro Direct
|
|
// Memory Access chapter.
|
|
#define UDMA_CHMAP0_CH6SEL_S 24
|
|
#define UDMA_CHMAP0_CH5SEL_M 0x00F00000 // uDMA channel 5 source select
|
|
// See section titled "Channel
|
|
// Assignments" in Micro Direct
|
|
// Memory Access chapter.
|
|
#define UDMA_CHMAP0_CH5SEL_S 20
|
|
#define UDMA_CHMAP0_CH4SEL_M 0x000F0000 // uDMA channel 4 source select
|
|
// See section titled "Channel
|
|
// Assignments" in Micro Direct
|
|
// Memory Access chapter.
|
|
#define UDMA_CHMAP0_CH4SEL_S 16
|
|
#define UDMA_CHMAP0_CH3SEL_M 0x0000F000 // uDMA channel 3 source select
|
|
// See section titled "Channel
|
|
// Assignments" in Micro Direct
|
|
// Memory Access chapter.
|
|
#define UDMA_CHMAP0_CH3SEL_S 12
|
|
#define UDMA_CHMAP0_CH2SEL_M 0x00000F00 // uDMA channel 2 source select
|
|
// See section titled "Channel
|
|
// Assignments" in Micro Direct
|
|
// Memory Access chapter.
|
|
#define UDMA_CHMAP0_CH2SEL_S 8
|
|
#define UDMA_CHMAP0_CH1SEL_M 0x000000F0 // uDMA channel 1 source select
|
|
// See section titled "Channel
|
|
// Assignments" in Micro Direct
|
|
// Memory Access chapter.
|
|
#define UDMA_CHMAP0_CH1SEL_S 4
|
|
#define UDMA_CHMAP0_CH0SEL_M 0x0000000F // uDMA channel 0 source select
|
|
// See section titled "Channel
|
|
// Assignments" in Micro Direct
|
|
// Memory Access chapter.
|
|
#define UDMA_CHMAP0_CH0SEL_S 0
|
|
//*****************************************************************************
|
|
//
|
|
// The following are defines for the bit fields in the UDMA_CHMAP1 register.
|
|
//
|
|
//*****************************************************************************
|
|
#define UDMA_CHMAP1_CH15SEL_M 0xF0000000 // uDMA channel 15 source select
|
|
// See section titled "Channel
|
|
// Assignments" in Micro Direct
|
|
// Memory Access chapter.
|
|
#define UDMA_CHMAP1_CH15SEL_S 28
|
|
#define UDMA_CHMAP1_CH14SEL_M 0x0F000000 // uDMA channel 14 source select
|
|
// See section titled "Channel
|
|
// Assignments" in Micro Direct
|
|
// Memory Access chapter.
|
|
#define UDMA_CHMAP1_CH14SEL_S 24
|
|
#define UDMA_CHMAP1_CH13SEL_M 0x00F00000 // uDMA channel 13 source select
|
|
// See section titled "Channel
|
|
// Assignments" in Micro Direct
|
|
// Memory Access chapter.
|
|
#define UDMA_CHMAP1_CH13SEL_S 20
|
|
#define UDMA_CHMAP1_CH12SEL_M 0x000F0000 // uDMA channel 12 source select
|
|
// See section titled "Channel
|
|
// Assignments" in Micro Direct
|
|
// Memory Access chapter.
|
|
#define UDMA_CHMAP1_CH12SEL_S 16
|
|
#define UDMA_CHMAP1_CH11SEL_M 0x0000F000 // uDMA channel 11 source select
|
|
// See section titled "Channel
|
|
// Assignments" in Micro Direct
|
|
// Memory Access chapter.
|
|
#define UDMA_CHMAP1_CH11SEL_S 12
|
|
#define UDMA_CHMAP1_CH10SEL_M 0x00000F00 // uDMA channel 10 source select
|
|
// See section titled "Channel
|
|
// Assignments" in Micro Direct
|
|
// Memory Access chapter.
|
|
#define UDMA_CHMAP1_CH10SEL_S 8
|
|
#define UDMA_CHMAP1_CH9SEL_M 0x000000F0 // uDMA channel 9 source select
|
|
// See section titled "Channel
|
|
// Assignments" in Micro Direct
|
|
// Memory Access chapter.
|
|
#define UDMA_CHMAP1_CH9SEL_S 4
|
|
#define UDMA_CHMAP1_CH8SEL_M 0x0000000F // uDMA channel 8 source select
|
|
// See section titled "Channel
|
|
// Assignments" in Micro Direct
|
|
// Memory Access chapter.
|
|
#define UDMA_CHMAP1_CH8SEL_S 0
|
|
//*****************************************************************************
|
|
//
|
|
// The following are defines for the bit fields in the UDMA_CHMAP2 register.
|
|
//
|
|
//*****************************************************************************
|
|
#define UDMA_CHMAP2_CH23SEL_M 0xF0000000 // uDMA channel 23 source select
|
|
// See section titled "Channel
|
|
// Assignments" in Micro Direct
|
|
// Memory Access chapter.
|
|
#define UDMA_CHMAP2_CH23SEL_S 28
|
|
#define UDMA_CHMAP2_CH22SEL_M 0x0F000000 // uDMA channel 22 source select
|
|
// See section titled "Channel
|
|
// Assignments" in Micro Direct
|
|
// Memory Access chapter.
|
|
#define UDMA_CHMAP2_CH22SEL_S 24
|
|
#define UDMA_CHMAP2_CH21SEL_M 0x00F00000 // uDMA channel 21 source select
|
|
// See section titled "Channel
|
|
// Assignments" in Micro Direct
|
|
// Memory Access chapter.
|
|
#define UDMA_CHMAP2_CH21SEL_S 20
|
|
#define UDMA_CHMAP2_CH20SEL_M 0x000F0000 // uDMA channel 20 source select
|
|
// See section titled "Channel
|
|
// Assignments" in Micro Direct
|
|
// Memory Access chapter.
|
|
#define UDMA_CHMAP2_CH20SEL_S 16
|
|
#define UDMA_CHMAP2_CH19SEL_M 0x0000F000 // uDMA channel 19 source select
|
|
// See section titled "Channel
|
|
// Assignments" in Micro Direct
|
|
// Memory Access chapter.
|
|
#define UDMA_CHMAP2_CH19SEL_S 12
|
|
#define UDMA_CHMAP2_CH18SEL_M 0x00000F00 // uDMA channel 18 source select
|
|
// See section titled "Channel
|
|
// Assignments" in Micro Direct
|
|
// Memory Access chapter.
|
|
#define UDMA_CHMAP2_CH18SEL_S 8
|
|
#define UDMA_CHMAP2_CH17SEL_M 0x000000F0 // uDMA channel 17 source select
|
|
// See section titled "Channel
|
|
// Assignments" in Micro Direct
|
|
// Memory Access chapter.
|
|
#define UDMA_CHMAP2_CH17SEL_S 4
|
|
#define UDMA_CHMAP2_CH16SEL_M 0x0000000F // uDMA channel 16 source select
|
|
// See section titled "Channel
|
|
// Assignments" in Micro Direct
|
|
// Memory Access chapter.
|
|
#define UDMA_CHMAP2_CH16SEL_S 0
|
|
//*****************************************************************************
|
|
//
|
|
// The following are defines for the bit fields in the UDMA_CHMAP3 register.
|
|
//
|
|
//*****************************************************************************
|
|
#define UDMA_CHMAP3_CH31SEL_M 0xF0000000 // uDMA channel 31 source select
|
|
// See section titled "Channel
|
|
// Assignments" in Micro Direct
|
|
// Memory Access chapter.
|
|
#define UDMA_CHMAP3_CH31SEL_S 28
|
|
#define UDMA_CHMAP3_CH30SEL_M 0x0F000000 // uDMA channel 30 source select
|
|
// See section titled "Channel
|
|
// Assignments" in Micro Direct
|
|
// Memory Access chapter.
|
|
#define UDMA_CHMAP3_CH30SEL_S 24
|
|
#define UDMA_CHMAP3_CH29SEL_M 0x00F00000 // uDMA channel 29 source select
|
|
// See section titled "Channel
|
|
// Assignments" in Micro Direct
|
|
// Memory Access chapter.
|
|
#define UDMA_CHMAP3_CH29SEL_S 20
|
|
#define UDMA_CHMAP3_CH28SEL_M 0x000F0000 // uDMA channel 28 source select
|
|
// See section titled "Channel
|
|
// Assignments" in Micro Direct
|
|
// Memory Access chapter.
|
|
#define UDMA_CHMAP3_CH28SEL_S 16
|
|
#define UDMA_CHMAP3_CH27SEL_M 0x0000F000 // uDMA channel 27 source select
|
|
// See section titled "Channel
|
|
// Assignments" in Micro Direct
|
|
// Memory Access chapter.
|
|
#define UDMA_CHMAP3_CH27SEL_S 12
|
|
#define UDMA_CHMAP3_CH26SEL_M 0x00000F00 // uDMA channel 26 source select
|
|
// See section titled "Channel
|
|
// Assignments" in Micro Direct
|
|
// Memory Access chapter.
|
|
#define UDMA_CHMAP3_CH26SEL_S 8
|
|
#define UDMA_CHMAP3_CH25SEL_M 0x000000F0 // uDMA channel 25 source select
|
|
// See section titled "Channel
|
|
// Assignments" in Micro Direct
|
|
// Memory Access chapter.
|
|
#define UDMA_CHMAP3_CH25SEL_S 4
|
|
#define UDMA_CHMAP3_CH24SEL_M 0x0000000F // uDMA channel 24 source select
|
|
// See section titled "Channel
|
|
// Assignments" in Micro Direct
|
|
// Memory Access chapter.
|
|
#define UDMA_CHMAP3_CH24SEL_S 0
|
|
|
|
|
|
#endif // __HW_UDMA_H__
|
|
|