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df37e69b90
Currently the cc2538 is based on from-scratch adaption which is
not feature complete and thus lacks defines etc. Introducing the
official vendor header will ease future extension and adaptions
of the CPU and its features.
267 lines
15 KiB
C
Executable File
267 lines
15 KiB
C
Executable File
/******************************************************************************
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* Filename: hw_cctest.h
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* Revised: $Date: 2013-04-30 17:13:44 +0200 (Tue, 30 Apr 2013) $
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* Revision: $Revision: 9943 $
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*
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* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* Neither the name of Texas Instruments Incorporated nor the names of
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* its contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************/
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#ifndef __HW_CCTEST_H__
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#define __HW_CCTEST_H__
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//*****************************************************************************
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//
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// The following are defines for the CCTEST register offsets.
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//
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//*****************************************************************************
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#define CCTEST_IO 0x44010000 // Output strength control
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#define CCTEST_OBSSEL0 0x44010014 // Select output signal on
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// observation output 0
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#define CCTEST_OBSSEL1 0x44010018 // Select output signal on
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// observation output 1
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#define CCTEST_OBSSEL2 0x4401001C // Select output signal on
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// observation output 2
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#define CCTEST_OBSSEL3 0x44010020 // Select output signal on
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// observation output 3
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#define CCTEST_OBSSEL4 0x44010024 // Select output signal on
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// observation output 4
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#define CCTEST_OBSSEL5 0x44010028 // Select output signal on
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// observation output 5
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#define CCTEST_OBSSEL6 0x4401002C // Select output signal on
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// observation output 6
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#define CCTEST_OBSSEL7 0x44010030 // Select output signal on
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// observation output 7
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#define CCTEST_TR0 0x44010034 // Test register 0
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#define CCTEST_USBCTRL 0x44010050 // USB PHY stand-by control
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the CCTEST_IO register.
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//
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//*****************************************************************************
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#define CCTEST_IO_SC 0x00000001 // I/O strength control bit Common
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// to all digital output pads
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// Should be set when unregulated
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// voltage is below approximately
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// 2.6 V.
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#define CCTEST_IO_SC_M 0x00000001
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#define CCTEST_IO_SC_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the
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// CCTEST_OBSSEL0 register.
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//
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//*****************************************************************************
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#define CCTEST_OBSSEL0_EN 0x00000080 // Observation output 0 enable
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// control for PC0 0: Observation
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// output disabled 1: Observation
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// output enabled Note: If enabled,
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// this overwrites the standard
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// GPIO behavior of PC0.
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#define CCTEST_OBSSEL0_EN_M 0x00000080
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#define CCTEST_OBSSEL0_EN_S 7
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#define CCTEST_OBSSEL0_SEL_M 0x0000007F // n - obs_sigs[n] output on
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// output 0: 0: rfc_obs_sig0 1:
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// rfc_obs_sig1 2: rfc_obs_sig2
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// Others: Reserved
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#define CCTEST_OBSSEL0_SEL_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the
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// CCTEST_OBSSEL1 register.
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//
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//*****************************************************************************
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#define CCTEST_OBSSEL1_EN 0x00000080 // Observation output 1 enable
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// control for PC1 0: Observation
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// output disabled 1: Observation
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// output enabled Note: If enabled,
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// this overwrites the standard
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// GPIO behavior of PC1.
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#define CCTEST_OBSSEL1_EN_M 0x00000080
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#define CCTEST_OBSSEL1_EN_S 7
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#define CCTEST_OBSSEL1_SEL_M 0x0000007F // n - obs_sigs[n] output on
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// output 1: 0: rfc_obs_sig0 1:
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// rfc_obs_sig1 2: rfc_obs_sig2
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// Others: Reserved
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#define CCTEST_OBSSEL1_SEL_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the
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// CCTEST_OBSSEL2 register.
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//
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//*****************************************************************************
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#define CCTEST_OBSSEL2_EN 0x00000080 // Observation output 2 enable
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// control for PC2 0: Observation
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// output disabled 1: Observation
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// output enabled Note: If enabled,
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// this overwrites the standard
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// GPIO behavior of PC2.
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#define CCTEST_OBSSEL2_EN_M 0x00000080
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#define CCTEST_OBSSEL2_EN_S 7
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#define CCTEST_OBSSEL2_SEL_M 0x0000007F // n - obs_sigs[n] output on
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// output 2: 0: rfc_obs_sig0 1:
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// rfc_obs_sig1 2: rfc_obs_sig2
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// Others: Reserved
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#define CCTEST_OBSSEL2_SEL_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the
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// CCTEST_OBSSEL3 register.
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//
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//*****************************************************************************
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#define CCTEST_OBSSEL3_EN 0x00000080 // Observation output 3 enable
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// control for PC3 0: Observation
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// output disabled 1: Observation
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// output enabled Note: If enabled,
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// this overwrites the standard
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// GPIO behavior of PC3.
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#define CCTEST_OBSSEL3_EN_M 0x00000080
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#define CCTEST_OBSSEL3_EN_S 7
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#define CCTEST_OBSSEL3_SEL_M 0x0000007F // n - obs_sigs[n] output on
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// output 3: 0: rfc_obs_sig0 1:
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// rfc_obs_sig1 2: rfc_obs_sig2
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// Others: Reserved
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#define CCTEST_OBSSEL3_SEL_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the
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// CCTEST_OBSSEL4 register.
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//
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//*****************************************************************************
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#define CCTEST_OBSSEL4_EN 0x00000080 // Observation output 4 enable
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// control for PC4 0: Observation
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// output disabled 1: Observation
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// output enabled Note: If enabled,
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// this overwrites the standard
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// GPIO behavior of PC4.
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#define CCTEST_OBSSEL4_EN_M 0x00000080
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#define CCTEST_OBSSEL4_EN_S 7
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#define CCTEST_OBSSEL4_SEL_M 0x0000007F // n - obs_sigs[n] output on
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// output 4: 0: rfc_obs_sig0 1:
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// rfc_obs_sig1 2: rfc_obs_sig2
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// Others: Reserved
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#define CCTEST_OBSSEL4_SEL_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the
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// CCTEST_OBSSEL5 register.
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//
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//*****************************************************************************
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#define CCTEST_OBSSEL5_EN 0x00000080 // Observation output 5 enable
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// control for PC5 0: Observation
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// output disabled 1: Observation
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// output enabled Note: If enabled,
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// this overwrites the standard
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// GPIO behavior of PC5.
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#define CCTEST_OBSSEL5_EN_M 0x00000080
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#define CCTEST_OBSSEL5_EN_S 7
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#define CCTEST_OBSSEL5_SEL_M 0x0000007F // n - obs_sigs[n] output on
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// output 5: 0: rfc_obs_sig0 1:
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// rfc_obs_sig1 2: rfc_obs_sig2
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// Others: Reserved
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#define CCTEST_OBSSEL5_SEL_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the
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// CCTEST_OBSSEL6 register.
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//
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//*****************************************************************************
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#define CCTEST_OBSSEL6_EN 0x00000080 // Observation output 6 enable
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// control for PC6 0: Observation
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// output disabled 1: Observation
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// output enabled Note: If enabled,
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// this overwrites the standard
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// GPIO behavior of PC6.
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#define CCTEST_OBSSEL6_EN_M 0x00000080
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#define CCTEST_OBSSEL6_EN_S 7
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#define CCTEST_OBSSEL6_SEL_M 0x0000007F // n - obs_sigs[n] output on
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// output 6: 0: rfc_obs_sig0 1:
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// rfc_obs_sig1 2: rfc_obs_sig2
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// Others: Reserved
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#define CCTEST_OBSSEL6_SEL_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the
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// CCTEST_OBSSEL7 register.
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//
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//*****************************************************************************
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#define CCTEST_OBSSEL7_EN 0x00000080 // Observation output 7 enable
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// control for PC7 0: Observation
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// output disabled 1: Observation
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// output enabled Note: If enabled,
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// this overwrites the standard
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// GPIO behavior of PC7.
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#define CCTEST_OBSSEL7_EN_M 0x00000080
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#define CCTEST_OBSSEL7_EN_S 7
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#define CCTEST_OBSSEL7_SEL_M 0x0000007F // n - obs_sigs[n] output on
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// output 7: 0: rfc_obs_sig0 1:
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// rfc_obs_sig1 2: rfc_obs_sig2
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// Others: Reserved
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#define CCTEST_OBSSEL7_SEL_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the CCTEST_TR0 register.
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//
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//*****************************************************************************
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#define CCTEST_TR0_ADCTM 0x00000002 // Set to 1 to connect the
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// temperature sensor to the
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// SOC_ADC. See also
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// RFCORE_XREG_ATEST register
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// description to enable the
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// temperature sensor.
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#define CCTEST_TR0_ADCTM_M 0x00000002
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#define CCTEST_TR0_ADCTM_S 1
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the
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// CCTEST_USBCTRL register.
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//
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//*****************************************************************************
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#define CCTEST_USBCTRL_USB_STB 0x00000001 // USB PHY stand-by override bit
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// When this bit is cleared to 0
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// (default state) the USB module
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// cannot change the stand-by mode
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// of the PHY (USB pads) and the
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// PHY is forced out of stand-by
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// mode. This bit must be 1 as well
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// as the stand-by control from the
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// USB controller, before the mode
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// of the PHY is stand-by.
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#define CCTEST_USBCTRL_USB_STB_M \
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0x00000001
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#define CCTEST_USBCTRL_USB_STB_S 0
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#endif // __HW_CCTEST_H__
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