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https://github.com/RIOT-OS/RIOT.git
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179 lines
4.4 KiB
C
179 lines
4.4 KiB
C
/*
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* Copyright (C) 2017 Inria
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup boards_nucleo-l496zg
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* @{
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*
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* @file
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* @brief Peripheral MCU configuration for the nucleo144-l496 board
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*
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* @author Alexandre Abadie <alexandre.abadie@inria.fr>
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*/
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#ifndef PERIPH_CONF_H
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#define PERIPH_CONF_H
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#include "periph_cpu.h"
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#include "l4/cfg_clock_80_1.h"
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#include "cfg_i2c1_pb8_pb9.h"
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#include "cfg_rtt_default.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @name Timer configuration
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* @{
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*/
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static const timer_conf_t timer_config[] = {
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{
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.dev = TIM2,
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.max = 0xffffffff,
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.rcc_mask = RCC_APB1ENR1_TIM2EN,
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.bus = APB1,
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.irqn = TIM2_IRQn
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},
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{
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.dev = TIM5,
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.max = 0xffffffff,
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.rcc_mask = RCC_APB1ENR1_TIM5EN,
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.bus = APB1,
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.irqn = TIM5_IRQn
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},
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};
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#define TIMER_0_ISR isr_tim2
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#define TIMER_1_ISR isr_tim5
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#define TIMER_NUMOF ARRAY_SIZE(timer_config)
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/** @} */
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/**
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* @name UART configuration
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* @{
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*/
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static const uart_conf_t uart_config[] = {
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{
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.dev = LPUART1,
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.rcc_mask = RCC_APB1ENR2_LPUART1EN,
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.rx_pin = GPIO_PIN(PORT_G, 8),
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.tx_pin = GPIO_PIN(PORT_G, 7),
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.rx_af = GPIO_AF8,
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.tx_af = GPIO_AF8,
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.bus = APB12,
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.irqn = LPUART1_IRQn,
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.type = STM32_LPUART,
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.clk_src = 0,
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},
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{
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.dev = USART3,
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.rcc_mask = RCC_APB1ENR1_USART3EN,
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.rx_pin = GPIO_PIN(PORT_D, 9),
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.tx_pin = GPIO_PIN(PORT_D, 8),
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.rx_af = GPIO_AF7,
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.tx_af = GPIO_AF7,
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.bus = APB1,
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.irqn = USART3_IRQn,
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.type = STM32_USART,
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.clk_src = 0, /* Use APB clock */
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#ifdef UART_USE_DMA
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.dma_stream = 5,
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.dma_chan = 4
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#endif
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}
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};
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#define UART_0_ISR (isr_lpuart1)
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#define UART_1_ISR (isr_usart3)
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#define UART_1_DMA_ISR (isr_dma1_stream5)
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#define UART_NUMOF ARRAY_SIZE(uart_config)
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/** @} */
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/**
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* @name PWM configuration
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* @{
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*/
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static const pwm_conf_t pwm_config[] = {
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{
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.dev = TIM1,
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.rcc_mask = RCC_APB2ENR_TIM1EN,
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.chan = { { .pin = GPIO_PIN(PORT_E, 9) /* D6 */, .cc_chan = 0},
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{ .pin = GPIO_PIN(PORT_E, 11) /* D5 */, .cc_chan = 1},
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{ .pin = GPIO_PIN(PORT_E, 13) /* D3 */, .cc_chan = 2},
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{ .pin = GPIO_UNDEF, .cc_chan = 0} },
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.af = GPIO_AF1,
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.bus = APB2
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},
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{
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.dev = TIM4,
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.rcc_mask = RCC_APB1ENR1_TIM4EN,
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.chan = { { .pin = GPIO_PIN(PORT_D, 15) /* D9 */, .cc_chan = 3},
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{ .pin = GPIO_UNDEF, .cc_chan = 0},
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{ .pin = GPIO_UNDEF, .cc_chan = 0},
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{ .pin = GPIO_UNDEF, .cc_chan = 0} },
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.af = GPIO_AF2,
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.bus = APB1
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},
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};
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#define PWM_NUMOF ARRAY_SIZE(pwm_config)
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/** @} */
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/**
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* @name SPI configuration
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*
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* @note The spi_divtable is auto-generated from
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* `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
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* @{
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*/
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static const uint8_t spi_divtable[2][5] = {
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{ /* for APB1 @ 20000000Hz */
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7, /* -> 78125Hz */
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5, /* -> 312500Hz */
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3, /* -> 1250000Hz */
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1, /* -> 5000000Hz */
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0 /* -> 10000000Hz */
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},
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{ /* for APB2 @ 40000000Hz */
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7, /* -> 156250Hz */
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6, /* -> 312500Hz */
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4, /* -> 1250000Hz */
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2, /* -> 5000000Hz */
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1 /* -> 10000000Hz */
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}
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};
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static const spi_conf_t spi_config[] = {
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{
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.dev = SPI1,
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.mosi_pin = GPIO_PIN(PORT_A, 7),
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.miso_pin = GPIO_PIN(PORT_A, 6),
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.sclk_pin = GPIO_PIN(PORT_A, 5),
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.cs_pin = GPIO_UNDEF,
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.mosi_af = GPIO_AF5,
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.miso_af = GPIO_AF5,
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.sclk_af = GPIO_AF5,
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.cs_af = GPIO_AF5,
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.rccmask = RCC_APB2ENR_SPI1EN,
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.apbbus = APB2
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}
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};
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#define SPI_NUMOF ARRAY_SIZE(spi_config)
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#endif /* PERIPH_CONF_H */
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/** @} */
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