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7d1d5e77d8
New CPU FE310 from SiFive based on RISC-V architecture build: add makefile for RISC-V builds Makefile for builds using RISC-V tools
15 lines
291 B
C
15 lines
291 B
C
// See LICENSE for license details
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#ifndef _SIFIVE_CLINT_H
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#define _SIFIVE_CLINT_H
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#define CLINT_MSIP 0x0000
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#define CLINT_MSIP_size 0x4
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#define CLINT_MTIMECMP 0x4000
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#define CLINT_MTIMECMP_size 0x8
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#define CLINT_MTIME 0xBFF8
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#define CLINT_MTIME_size 0x8
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#endif /* _SIFIVE_CLINT_H */
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