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https://github.com/RIOT-OS/RIOT.git
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d91f438589
The function configures additional features of the DMA stream for F2/F4/F7. `dma_setup_ext` added to configure F2/F4/F7 specific additional features like `MBURST`, `PBURST`, `FIFO` and Peripheral flow controller. It is supposed to be used after `dma_setup` and `dma_prepare`.
275 lines
7.7 KiB
C
275 lines
7.7 KiB
C
/*
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* Copyright (C) 2016 Freie Universität Berlin
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* 2017 OTA keys S.A.
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_stm32
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* @{
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*
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* @file
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* @brief DMA CPU specific definitions for the STM32 family
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*
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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* @author Vincent Dupont <vincent@otakeys.com>
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* @author Joshua DeWeese <jdeweese@primecontrols.com>
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*/
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#ifndef PERIPH_CPU_DMA_H
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#define PERIPH_CPU_DMA_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief DMA configuration
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*/
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typedef struct {
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/** DMA stream on stm32f2/4/7, channel on others
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* STM32F2/4/7:
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* - 0: DMA1 / Stream0
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* - 1: DMA1 / Stream1
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* - ...
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* - 7: DMA1 / Stream7
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* - 8: DAM2 / Stream0
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* - ...
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* - 15: DMA2 / Stream7
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* STM32F0/1/3/L0/1/4:
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* - 0: DMA1 / Channel1
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* - ...
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* - 4: DMA1 / Channel5
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* - ...
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* - 6: DMA1 / Channel7
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* - 7: Reserved
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* - 8: DMA2 / Channel1
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* - ...
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* - 12: DMA2 / Channel5
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* - ...
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* - 14: DMA2 / Channel7
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*/
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int stream;
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} dma_conf_t;
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/**
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* @brief DMA type
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*/
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typedef unsigned dma_t;
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/**
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* @brief DMA modes
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*/
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typedef enum {
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DMA_PERIPH_TO_MEM = 0, /**< Peripheral to memory */
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DMA_MEM_TO_PERIPH = 1, /**< Memory to peripheral */
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DMA_MEM_TO_MEM = 2, /**< Memory to memory */
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} dma_mode_t;
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/**
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* @brief Burst Transfer modes for F2/F4/F7
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*/
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typedef enum {
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DMA_BURST_SINGLE = 0, /**< single transfer */
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DMA_BURST_INCR4 = 1, /**< incremental burst of 4 beats */
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DMA_BURST_INCR8 = 2, /**< incremental burst of 8 beats */
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DMA_BURST_INCR16 = 3, /**< incremental burst of 16 beats */
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} dma_burst_t;
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/**
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* @brief Threshold selection in FIFO mode for F2/F4F7
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*/
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typedef enum {
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DMA_FIFO_FULL_1_4 = 0, /**< 1/4 full FIFO */
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DMA_FIFO_FULL_1_2 = 1, /**< 1/2 full FIFO */
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DMA_FIFO_FULL_3_4 = 2, /**< 3/4 full FIFO */
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DMA_FIFO_FULL = 3, /**< Full FIFO */
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} dma_fifo_thresh_t;
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/**
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* @brief DMA channel/trigger configuration for DMA peripherals without
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* channel/trigger filtering such as the stm32f1 and stm32f3.
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*/
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#define DMA_CHAN_CONFIG_UNSUPPORTED (UINT8_MAX)
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/**
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* @name DMA Increment modes
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* @{
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*/
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#define DMA_INC_SRC_ADDR (0x04) /**< DMA increment source address */
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#define DMA_INC_DST_ADDR (0x08) /**< DMA increment destination address */
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#define DMA_INC_BOTH_ADDR (DMA_INC_SRC_ADDR | DMA_INC_DST_ADDR) /**< DMA increment source + destination address */
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/** @} */
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/**
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* @name DMA data width
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* @{
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*/
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#define DMA_DATA_WIDTH_BYTE (0x00) /**< Byte width */
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#define DMA_DATA_WIDTH_HALF_WORD (0x01) /**< Half word width (2 bytes)*/
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#define DMA_DATA_WIDTH_WORD (0x02) /**< Word width (4 bytes)*/
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/** @} */
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#ifdef MODULE_PERIPH_DMA
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/**
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* @brief DMA stream not defined
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*/
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#define DMA_STREAM_UNDEF (UINT_MAX)
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/**
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* @brief Initialize DMA
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*/
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void dma_init(void);
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/**
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* @brief Execute a DMA transfer
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*
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* This function blocks until the transfer is completed. This is a convenience
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* function which configure, start, wait and stop a DMA transfer.
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*
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* @param[in] dma logical DMA stream
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* @param[in] chan DMA channel (on stm32f2/4/7, CxS or unused on others)
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* @param[in] src source buffer
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* @param[out] dst destination buffer
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* @param[in] len number of transfers to perform
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* @param[in] mode DMA mode
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* @param[in] flags DMA configuration
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*
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* @return < 0 on error, the number of transferred bytes otherwise
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*/
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int dma_transfer(dma_t dma, int chan, const volatile void *src, volatile void *dst, size_t len,
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dma_mode_t mode, uint8_t flags);
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/**
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* @brief Acquire a DMA stream
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*
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* @param[in] dma logical DMA stream
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*/
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void dma_acquire(dma_t dma);
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/**
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* @brief Release a DMA stream
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*
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* @param[in] dma logical DMA stream
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*/
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void dma_release(dma_t dma);
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/**
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* @brief Start a DMA transfer on a stream
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*
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* Start a DMA transfer on a given stream. The stream must be configured first
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* by a @p dma_configure call.
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*
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* @param[in] dma logical DMA stream
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*/
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void dma_start(dma_t dma);
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/**
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* @brief Suspend a DMA transfer on a stream
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*
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* @param[in] dma logical DMA stream
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*
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* @return the remaining number of transfers to perform
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*/
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uint16_t dma_suspend(dma_t dma);
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/**
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* @brief Resume a suspended DMA transfer on a stream
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*
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* @param[in] dma logical DMA stream
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* @param[in] reamaining the remaining number of transfers to perform
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*/
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void dma_resume(dma_t dma, uint16_t remaining);
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/**
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* @brief Stop a DMA transfer on a stream
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*
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* @param[in] dma logical DMA stream
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*/
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void dma_stop(dma_t dma);
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/**
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* @brief Wait for the end of a transfer
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*
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* @param[in] dma logical DMA stream
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*/
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void dma_wait(dma_t dma);
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/**
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* @brief Configure a DMA stream for a new transfer
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*
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* @param[in] dma logical DMA stream
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* @param[in] chan DMA channel (on stm32f2/4/7, CxS or unused on others)
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* @param[in] src source buffer
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* @param[out] dst destination buffer
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* @param[in] len number of transfers to perform
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* @param[in] mode DMA mode
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* @param[in] flags DMA configuration
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*
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* @return < 0 on error, 0 on success
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*/
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int dma_configure(dma_t dma, int chan, const volatile void *src, volatile void *dst, size_t len,
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dma_mode_t mode, uint8_t flags);
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/**
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* @brief Low level initial DMA stream configuration
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*
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* This function is supposed to be used together with @ref dma_prepare. This
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* function sets up the one-time configuration of a stream and @ref dma_prepare
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* configures the per-transfer registers.
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*
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* @param[in] dma Logical DMA stream
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* @param[in] chan DMA channel (on stm32f2/4/7, CxS or unused on others)
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* @param[in] periph_addr Peripheral register address
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* @param[in] mode DMA direction mode
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* @param[in] width DMA transfer width (one of DMA_DATA_WIDTH_*)
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* @param[in] inc_periph Increment peripheral address after read/write
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*/
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void dma_setup(dma_t dma, int chan, void *periph_addr, dma_mode_t mode,
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uint8_t width, bool inc_periph);
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/**
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* @brief Low level extended initial DMA stream configuration for F2/F4/F7
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*
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* The function configures additional features of the DMA stream for F2/F4/F7.
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* It is supposed to be used after @ref dma_setup and before @ref dma_prepare.
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*
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* @note This function is only implemented for F2/F4/F7. For other families
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* it is only a dummy. It is not used by @ref dma_configure or the
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* convenience function @ref dma_transfer.
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*
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* @warn The combination of FIFO threshold and the memory burst transfer
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* has to be valid.
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*
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* @param[in] dma Logical DMA stream
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* @param[in] pburst Peripeheral burst transfer configuration
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* @param[in] mburst Memory burst transfer configuration
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* @param[in] fifo FIFO mode enable
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* @param[in] thresh FIFO threshold
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* @param[in] pfctrl Peripheral used as flow controller
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*/
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void dma_setup_ext(dma_t dma, dma_burst_t pburst, dma_burst_t mburst,
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bool fifo, dma_fifo_thresh_t thresh, bool pfctrl);
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/**
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* @brief Low level DMA transfer configuration
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*
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* @param[in] dma Logical DMA stream
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* @param[in] mem Memory address
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* @param[in] len Number of transfers to perform
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* @param[in] inc_mem Increment the memory address (by the transfer width) after read/write
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*/
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void dma_prepare(dma_t dma, void *mem, size_t len, bool incr_mem);
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#endif /* MODULE_PERIPH_DMA */
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#ifdef __cplusplus
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}
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#endif
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#endif /* PERIPH_CPU_DMA_H */
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/** @} */
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