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https://github.com/RIOT-OS/RIOT.git
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Koen Zandberg
d8ec0b292f
This PR sets the DMA configuration for the UART peripherals on the stm32f4 boards to the undef value to disable the DMA. This to prevent from accidentally configuring the DMA to stream 0 channel 0 when enabling DMA.
186 lines
4.5 KiB
C
186 lines
4.5 KiB
C
/*
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* Copyright (C) 2019 Inria
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* 2019 Freie Universität Berln
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* 2019 Kaspar Schleiser <kaspar@schleiser.de>
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup boards_pyboard
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* @{
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*
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* @file
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* @brief Peripheral MCU configuration for the pyboard board
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*
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* @author Kaspar Schleiser <kaspar@schleiser.de>
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*/
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#ifndef PERIPH_CONF_H
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#define PERIPH_CONF_H
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#include "periph_cpu.h"
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#include "cfg_usb_otg_fs.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @name Clock settings
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*
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* @note This is auto-generated from
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* `cpu/stm32_common/dist/clk_conf/clk_conf.c`
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* @{
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*/
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/* give the target core clock (HCLK) frequency [in Hz],
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* maximum: 168MHz */
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#define CLOCK_CORECLOCK (168000000U)
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/* 0: no external high speed crystal available
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* else: actual crystal frequency [in Hz] */
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#define CLOCK_HSE (12000000U)
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/* 0: no external low speed crystal available,
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* 1: external crystal available (always 32.768kHz) */
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#define CLOCK_LSE (1U)
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/* peripheral clock setup */
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#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
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#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
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#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4 /* max 42MHz */
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#define CLOCK_APB1 (CLOCK_CORECLOCK / 4)
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#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2 /* max 84MHz */
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#define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
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/* Main PLL factors */
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#define CLOCK_PLL_M (6)
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#define CLOCK_PLL_N (168)
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#define CLOCK_PLL_P (2)
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#define CLOCK_PLL_Q (7)
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/** @} */
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/**
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* @name Timer configuration
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* @{
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*/
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static const timer_conf_t timer_config[] = {
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{
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.dev = TIM5,
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.max = 0xffffffff,
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.rcc_mask = RCC_APB1ENR_TIM5EN,
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.bus = APB1,
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.irqn = TIM5_IRQn
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}
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};
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#define TIMER_0_ISR isr_tim5
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#define TIMER_NUMOF ARRAY_SIZE(timer_config)
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/** @} */
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/**
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* @name UART configuration
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* @{
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*/
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static const uart_conf_t uart_config[] = {
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{
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.dev = USART1,
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.rcc_mask = RCC_APB2ENR_USART1EN,
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.rx_pin = GPIO_PIN(PORT_B, 7),
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.tx_pin = GPIO_PIN(PORT_B, 6),
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.rx_af = GPIO_AF7,
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.tx_af = GPIO_AF7,
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.bus = APB2,
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.irqn = USART1_IRQn,
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#ifdef MODULE_PERIPH_DMA
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.dma = DMA_STREAM_UNDEF,
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.dma_chan = UINT8_MAX,
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#endif
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},
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};
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#define UART_0_ISR (isr_usart1)
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#define UART_NUMOF ARRAY_SIZE(uart_config)
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/** @} */
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/**
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* @name SPI configuration
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*
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* @note The spi_divtable is auto-generated from
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* `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
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* @{
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*/
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static const uint8_t spi_divtable[2][5] = {
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{ /* for APB1 @ 42000000Hz */
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7, /* -> 164062Hz */
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6, /* -> 328125Hz */
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4, /* -> 1312500Hz */
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2, /* -> 5250000Hz */
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1 /* -> 10500000Hz */
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},
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{ /* for APB2 @ 84000000Hz */
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7, /* -> 328125Hz */
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7, /* -> 328125Hz */
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5, /* -> 1312500Hz */
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3, /* -> 5250000Hz */
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2 /* -> 10500000Hz */
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}
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};
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static const spi_conf_t spi_config[] = {
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{
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.dev = SPI1,
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.mosi_pin = GPIO_PIN(PORT_A, 7),
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.miso_pin = GPIO_PIN(PORT_A, 6),
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.sclk_pin = GPIO_PIN(PORT_A, 5),
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.cs_pin = GPIO_UNDEF,
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.mosi_af = GPIO_AF5,
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.miso_af = GPIO_AF5,
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.sclk_af = GPIO_AF5,
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.cs_af = GPIO_AF5,
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.rccmask = RCC_APB2ENR_SPI1EN,
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.apbbus = APB2,
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#ifdef MODULE_PERIPH_DMA
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.tx_dma = 1,
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.tx_dma_chan = 1,
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.rx_dma = 0,
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.rx_dma_chan = 1,
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#endif
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}
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};
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#define SPI_NUMOF ARRAY_SIZE(spi_config)
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/** @} */
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/**
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* @name I2C configuration
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* @{
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*/
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static const i2c_conf_t i2c_config[] = {
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{
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.dev = I2C2,
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.speed = I2C_SPEED_NORMAL,
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.scl_pin = GPIO_PIN(PORT_B, 10),
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.sda_pin = GPIO_PIN(PORT_B, 11),
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.scl_af = GPIO_AF4,
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.sda_af = GPIO_AF4,
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.bus = APB1,
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.rcc_mask = RCC_APB1ENR_I2C2EN,
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.clk = CLOCK_APB1,
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.irqn = I2C2_ER_IRQn,
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},
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};
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#define I2C_0_ISR isr_i2c2_er
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#define I2C_NUMOF ARRAY_SIZE(i2c_config)
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#endif /* PERIPH_CONF_H */
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/** @} */
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