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60 lines
1.1 KiB
C
60 lines
1.1 KiB
C
/*
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* Copyright 2016, Imagination Technologies Limited and/or its
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* affiliated group companies.
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*
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*/
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/**
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* @defgroup boards_mips-malta MIPS MALTA
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* @ingroup boards
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* @brief peripheral configuration for the MIPS Malta FPGA system
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* @{
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*
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* @file
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* @brief peripheral configuration for the MIPS Malta FPGA system
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*
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* @author Neil Jones <neil.jones@imgtec.com>
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*/
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#ifndef _PERIPH_CONF_H_
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#define _PERIPH_CONF_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief Timer definitions
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* @{
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*/
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#define TIMER_NUMOF (1)
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#define TIMER_0_CHANNELS (3)
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/** @} */
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/**
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* @brief No UART driver for this board currently
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* Note this value must be set though (to 0)
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*/
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#define UART_NUMOF (0)
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/**
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* @brief Enable DSP context save + restore.
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*/
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#define MIPS_DSP (1)
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/**
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* @brief Enable FPU context save + restore.
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*/
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#define MIPS_HARD_FLOAT (1)
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#ifdef __cplusplus
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}
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#endif
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#endif /*_PERIPH_CONF_H_*/
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/** @} */
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