mirror of
https://github.com/RIOT-OS/RIOT.git
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5a3326350b
- nucleo-f334r8: - Added USART1 and USART3 config - nucleo-f401re: - Changed order of UARTs to match the other boards - nucleo-f410rb: - Added USART6 configuration - Fixed incorrect DMA settings (according to reference manual of the MCU) - nucleo-f446re: - Changed order of UARTs to match the other boards - nucleo-l152re: - Changed order of UARTs to match the other boards The result of this harmonization is, that the first UART is always USART2, the other USARTs are added in ascending order.
277 lines
7.4 KiB
C
277 lines
7.4 KiB
C
/*
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* Copyright (C) 2014-2016 Freie Universität Berlin
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @defgroup boards_nucleo-l152re STM32 Nucleo-L152RE
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* @ingroup boards_common_nucleo64
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* @brief Support for the STM32 Nucleo-L152RE
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* @{
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*
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* @file
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* @brief Peripheral MCU configuration for the nucleo-l152re board
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*
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* @author Thomas Eichinger <thomas.eichinger@fu-berlin.de>
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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*/
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#ifndef PERIPH_CONF_H
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#define PERIPH_CONF_H
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#include "periph_cpu.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @name Clock system configuration
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* @{
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**/
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#define CLOCK_HSI (16000000U) /* frequency of internal oscillator */
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#define CLOCK_CORECLOCK (32000000U) /* targeted core clock frequency */
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/*
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* 0: no external low speed crystal available,
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* 1: external crystal available (always 32.768kHz)
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*
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* LSE might not be available by default in early (C-01) Nucleo boards.
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* For newer revisions, an LSE crystal is present and CLOCK_LSE can be set to 1
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* if one wants to use it.
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*/
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#ifndef CLOCK_LSE
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#define CLOCK_LSE (0)
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#endif
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/* configuration of PLL prescaler and multiply values */
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/* CORECLOCK := HSI / CLOCK_PLL_DIV * CLOCK_PLL_MUL */
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#define CLOCK_PLL_DIV RCC_CFGR_PLLDIV2
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#define CLOCK_PLL_MUL RCC_CFGR_PLLMUL4
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/* configuration of peripheral bus clock prescalers */
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#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 /* AHB clock -> 32MHz */
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#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* APB2 clock -> 32MHz */
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#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV1 /* APB1 clock -> 32MHz */
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/* configuration of flash access cycles */
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#define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY
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/* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */
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#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
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#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
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#define CLOCK_APB1 (CLOCK_CORECLOCK / 1)
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/** @} */
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/**
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* @name Timer configuration
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* @{
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*/
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static const timer_conf_t timer_config[] = {
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{
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.dev = TIM5,
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.max = 0xffffffff,
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.rcc_mask = RCC_APB1ENR_TIM5EN,
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.bus = APB1,
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.irqn = TIM5_IRQn
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}
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};
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#define TIMER_0_ISR (isr_tim5)
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#define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
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/** @} */
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/**
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* @name Real time counter configuration
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* @{
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*/
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#define RTC_NUMOF (1U)
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/** @} */
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/**
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* @name UART configuration
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* @{
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*/
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static const uart_conf_t uart_config[] = {
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{
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.dev = USART2,
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.rcc_mask = RCC_APB1ENR_USART2EN,
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.rx_pin = GPIO_PIN(PORT_A, 3),
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.tx_pin = GPIO_PIN(PORT_A, 2),
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.rx_af = GPIO_AF7,
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.tx_af = GPIO_AF7,
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.bus = APB1,
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.irqn = USART2_IRQn
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},
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{
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.dev = USART1,
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.rcc_mask = RCC_APB2ENR_USART1EN,
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.rx_pin = GPIO_PIN(PORT_A, 9),
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.tx_pin = GPIO_PIN(PORT_A, 10),
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.rx_af = GPIO_AF7,
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.tx_af = GPIO_AF7,
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.bus = APB2,
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.irqn = USART1_IRQn
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},
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{
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.dev = USART3,
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.rcc_mask = RCC_APB1ENR_USART3EN,
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.rx_pin = GPIO_PIN(PORT_C, 11),
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.tx_pin = GPIO_PIN(PORT_C, 10),
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.rx_af = GPIO_AF7,
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.tx_af = GPIO_AF7,
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.bus = APB1,
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.irqn = USART3_IRQn
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},
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};
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#define UART_0_ISR (isr_usart2)
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#define UART_1_ISR (isr_usart1)
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#define UART_2_ISR (isr_usart3)
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#define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
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/** @} */
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/**
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* @name PWM configuration
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* @{
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*/
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static const pwm_conf_t pwm_config[] = {
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{
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.dev = TIM2,
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.rcc_mask = RCC_APB1ENR_TIM2EN,
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.chan = { { .pin = GPIO_PIN(PORT_B, 3) /* D3 */, .cc_chan = 1 },
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{ .pin = GPIO_PIN(PORT_B, 10) /* D6 */, .cc_chan = 2 },
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{ .pin = GPIO_UNDEF, .cc_chan = 0 },
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{ .pin = GPIO_UNDEF, .cc_chan = 0 } },
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.af = GPIO_AF1,
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.bus = APB1
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},
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{
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.dev = TIM3,
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.rcc_mask = RCC_APB1ENR_TIM3EN,
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.chan = { { .pin = GPIO_PIN(PORT_B, 4) /* D5 */, .cc_chan = 0 },
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{ .pin = GPIO_PIN(PORT_C, 7) /* D9 */, .cc_chan = 1 },
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{ .pin = GPIO_PIN(PORT_C, 8), .cc_chan = 2 },
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{ .pin = GPIO_PIN(PORT_C, 9), .cc_chan = 3 } },
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.af = GPIO_AF2,
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.bus = APB1
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}
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};
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#define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0]))
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/** @} */
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/**
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* @name SPI configuration
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*
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* @note The spi_divtable is auto-generated from
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* `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
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* @{
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*/
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static const uint8_t spi_divtable[2][5] = {
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{ /* for APB1 @ 32000000Hz */
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7, /* -> 125000Hz */
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5, /* -> 500000Hz */
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4, /* -> 1000000Hz */
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2, /* -> 4000000Hz */
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1 /* -> 8000000Hz */
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},
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{ /* for APB2 @ 32000000Hz */
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7, /* -> 125000Hz */
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5, /* -> 500000Hz */
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4, /* -> 1000000Hz */
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2, /* -> 4000000Hz */
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1 /* -> 8000000Hz */
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}
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};
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static const spi_conf_t spi_config[] = {
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{
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.dev = SPI1,
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.mosi_pin = GPIO_PIN(PORT_A, 7),
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.miso_pin = GPIO_PIN(PORT_A, 6),
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.sclk_pin = GPIO_PIN(PORT_A, 5),
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.cs_pin = GPIO_UNDEF,
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.af = GPIO_AF5,
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.rccmask = RCC_APB2ENR_SPI1EN,
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.apbbus = APB2
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}
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};
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#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
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/** @} */
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/**
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* @name I2C configuration
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* @{
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*/
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static const i2c_conf_t i2c_config[] = {
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{
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.dev = I2C1,
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.speed = I2C_SPEED_NORMAL,
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.scl_pin = GPIO_PIN(PORT_B, 8),
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.sda_pin = GPIO_PIN(PORT_B, 9),
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.scl_af = GPIO_AF4,
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.sda_af = GPIO_AF4,
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.bus = APB1,
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.rcc_mask = RCC_APB1ENR_I2C1EN,
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.clk = CLOCK_APB1,
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.irqn = I2C1_EV_IRQn
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},
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{
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.dev = I2C2,
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.speed = I2C_SPEED_NORMAL,
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.scl_pin = GPIO_PIN(PORT_B, 10),
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.sda_pin = GPIO_PIN(PORT_B, 11),
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.scl_af = GPIO_AF4,
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.sda_af = GPIO_AF4,
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.bus = APB1,
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.rcc_mask = RCC_APB1ENR_I2C2EN,
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.clk = CLOCK_APB1,
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.irqn = I2C2_EV_IRQn
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}
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};
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#define I2C_0_ISR isr_i2c1_ev
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#define I2C_1_ISR isr_i2c2_ev
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#define I2C_NUMOF (sizeof(i2c_config) / sizeof(i2c_config[0]))
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/** @} */
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/**
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* @name ADC configuration
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* @{
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*/
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#define ADC_CONFIG { \
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{ GPIO_PIN(PORT_A, 0), 0 }, \
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{ GPIO_PIN(PORT_A, 1), 1 }, \
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{ GPIO_PIN(PORT_A, 4), 4 }, \
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{ GPIO_PIN(PORT_B, 0), 8 }, \
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{ GPIO_PIN(PORT_C, 1), 11 }, \
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{ GPIO_PIN(PORT_C, 0), 10 }, \
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}
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#define ADC_NUMOF (6U)
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/** @} */
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/**
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* @name DAC configuration
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* @{
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*/
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static const dac_conf_t dac_config[] = {
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{ .pin = GPIO_PIN(PORT_A, 4), .chan = 0 },
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{ .pin = GPIO_PIN(PORT_A, 5), .chan = 1 }
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};
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#define DAC_NUMOF (sizeof(dac_config) / sizeof(dac_config[0]))
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#endif /* PERIPH_CONF_H */
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/** @} */
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