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52 lines
1.1 KiB
C
52 lines
1.1 KiB
C
/*
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* Copyright (C) 2015 Eistec AB
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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*/
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/**
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* @defgroup cpu_k60 NXP Kinetis K60
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* @ingroup cpu
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* @brief CPU specific implementations for the NXP Kinetis K60
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* Cortex-M4 MCU
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* @{
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*
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* @file
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* @brief Implementation specific CPU configuration options
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*
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* @author Joakim Nohlgård <joakim.nohlgard@eistec.se>
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*/
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#ifndef CPU_CONF_H
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#define CPU_CONF_H
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#if defined(CPU_MODEL_MK60DN512VLL10) || defined(CPU_MODEL_MK60DN256VLL10)
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#include "vendor/MK60D10.h"
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/* K60 rev 2.x replaced the RNG module in 1.x by the RNGA PRNG module */
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#define KINETIS_RNGA (RNG)
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#else
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#error Unknown CPU model. Update Makefile.include in the board directory.
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#endif
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#include "cpu_conf_kinetis.h"
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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/**
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* @brief This CPU provides an additional ADC clock divider as CFG1[ADICLK]=1
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*/
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#define KINETIS_HAVE_ADICLK_BUS_DIV_2 1
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#ifdef __cplusplus
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}
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#endif
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#endif /* CPU_CONF_H */
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/** @} */
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