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89 lines
2.1 KiB
C
89 lines
2.1 KiB
C
/*
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* bl_board_init.c
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*
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* Created on: 19.08.2008
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* Author: heiko, kaspar
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*/
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#include "cpu.h"
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#include "bits.h"
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#include "VIC.h"
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#define PLOCK 0x400
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static void feed(void)
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{
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PLL0FEED = 0xAA;
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PLL0FEED = 0x55;
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}
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void bl_init_clks(void)
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{
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// Setting the Phased Lock Loop (PLL)
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// ----------------------------------
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//
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// Olimex LPC-P2148 has a 12.0000 mhz crystal
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//
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// We'd like the LPC2148 to run at 60 mhz (has to be an even multiple of crystal)
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//
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// According to the Philips LPC2148 manual: M = cclk / Fosc where: M = PLL multiplier (bits 0-4 of PLLCFG)
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// cclk = 60000000 hz
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// Fosc = 12000000 hz
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//
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// Solving: M = 60000000 / 12000000 = 5
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//
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// Note: M - 1 must be entered into bits 0-4 of PLLCFG (assign 4 to these bits)
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//
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//
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// The Current Controlled Oscilator (CCO) must operate in the range 156 mhz to 320 mhz
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//
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// According to the Philips LPC2148 manual: Fcco = cclk * 2 * P where: Fcco = CCO frequency
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// cclk = 60000000 hz
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// P = PLL divisor (bits 5-6 of PLLCFG)
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//
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// Solving: Fcco = 60000000 * 2 * P
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// P = 2 (trial value)
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// Fcco = 60000000 * 2 * 2
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// Fcc0 = 240000000 hz (good choice for P since it's within the 156 mhz to 320 mhz range)
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//
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// From Table 22 (page 34) of Philips LPC2148 manual P = 2, PLLCFG bits 5-6 = 1 (assign 1 to these bits)
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//
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// Finally: PLLCFG = 0 01 00100 = 0x24
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//
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// Final note: to load PLLCFG register, we must use the 0xAA followed 0x55 write sequence to the PLLFEED register
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// this is done in the short function feed() below
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//
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// Setting Multiplier and Divider values
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PLL0CFG = 0x24;
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feed();
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// Enabling the PLL */
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PLL0CON = 0x1;
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feed();
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// Wait for the PLL to lock to set frequency
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while(!(PLL0STAT & PLOCK)) ;
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// Connect the PLL as the clock source
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PLL0CON = 0x3;
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feed();
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// Enabling MAM and setting number of clocks used for Flash memory fetch
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MAMTIM = 0x3;
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MAMCR = 0x2;
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// Setting peripheral Clock (pclk) to 1/2 System Clock (cclk)
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VPBDIV = PCLK_DIV;
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}
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void bl_init_ports(void)
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{
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}
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