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d37adee32d
There is no hardware limitation for custom boards based on STM32 to uses SPI bus with signals coming from different PORT and alternate functions. This patch allow alternate's function definition per pin basis, thus enable the support of SPI bus signals routed on differents PORT. Signed-off-by: Yannick Gicquel <ygicquel@gmail.com>
189 lines
4.3 KiB
C
189 lines
4.3 KiB
C
/*
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* Copyright (C) 2017 Inria
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup boards_nucleo-f767zi
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* @{
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*
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* @file
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* @brief Peripheral MCU configuration for the nucleo-f767zi board
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*
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* @author Alexandre Abadie <alexandre.abadie@inria.fr>
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*/
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#ifndef PERIPH_CONF_H
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#define PERIPH_CONF_H
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#include "periph_cpu.h"
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#include "f7/cfg_clock_216_8_1.h"
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#include "cfg_i2c1_pb8_pb9.h"
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#include "cfg_spi_divtable.h"
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#include "cfg_rtt_default.h"
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#include "cfg_timer_tim2.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @name DMA streams configuration
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* @{
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*/
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#ifdef MODULE_PERIPH_DMA
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static const dma_conf_t dma_config[] = {
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{ .stream = 4 }, /* DMA1 Stream 4 - USART3_TX */
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{ .stream = 14 }, /* DMA2 Stream 6 - USART6_TX */
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{ .stream = 6 }, /* DMA1 Stream 6 - USART2_TX */
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{ .stream = 8 }, /* DMA2 Stream 0 - ETH_TX */
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};
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#define DMA_0_ISR isr_dma1_stream4
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#define DMA_1_ISR isr_dma2_stream6
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#define DMA_2_ISR isr_dma1_stream6
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#define DMA_3_ISR isr_dma2_stream0
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#define DMA_NUMOF ARRAY_SIZE(dma_config)
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#endif
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/** @} */
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/**
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* @name UART configuration
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* @{
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*/
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static const uart_conf_t uart_config[] = {
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{
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.dev = USART3,
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.rcc_mask = RCC_APB1ENR_USART3EN,
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.rx_pin = GPIO_PIN(PORT_D, 9),
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.tx_pin = GPIO_PIN(PORT_D, 8),
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.rx_af = GPIO_AF7,
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.tx_af = GPIO_AF7,
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.bus = APB1,
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.irqn = USART3_IRQn,
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#ifdef MODULE_PERIPH_DMA
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.dma = 0,
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.dma_chan = 7
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#endif
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},
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{
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.dev = USART6,
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.rcc_mask = RCC_APB2ENR_USART6EN,
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.rx_pin = GPIO_PIN(PORT_G, 9),
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.tx_pin = GPIO_PIN(PORT_G, 14),
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.rx_af = GPIO_AF8,
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.tx_af = GPIO_AF8,
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.bus = APB2,
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.irqn = USART6_IRQn,
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#ifdef MODULE_PERIPH_DMA
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.dma = 1,
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.dma_chan = 5
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#endif
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},
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{
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.dev = USART2,
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.rcc_mask = RCC_APB1ENR_USART2EN,
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.rx_pin = GPIO_PIN(PORT_D, 6),
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.tx_pin = GPIO_PIN(PORT_D, 5),
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.rx_af = GPIO_AF7,
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.tx_af = GPIO_AF7,
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.bus = APB1,
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.irqn = USART2_IRQn,
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#ifdef MODULE_PERIPH_DMA
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.dma = 2,
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.dma_chan = 4
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#endif
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}
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};
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#define UART_0_ISR (isr_usart3)
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#define UART_1_ISR (isr_usart6)
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#define UART_2_ISR (isr_usart2)
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#define UART_NUMOF ARRAY_SIZE(uart_config)
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/** @} */
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/**
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* @name SPI configuration
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*
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* @note The spi_divtable is auto-generated from
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* `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
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* @{
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*/
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static const spi_conf_t spi_config[] = {
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{
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.dev = SPI1,
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.mosi_pin = GPIO_PIN(PORT_A, 7),
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.miso_pin = GPIO_PIN(PORT_A, 6),
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.sclk_pin = GPIO_PIN(PORT_A, 5),
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.cs_pin = GPIO_UNDEF,
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.mosi_af = GPIO_AF5,
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.miso_af = GPIO_AF5,
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.sclk_af = GPIO_AF5,
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.cs_af = GPIO_AF5,
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.rccmask = RCC_APB2ENR_SPI1EN,
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.apbbus = APB2
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},
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{
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.dev = SPI4,
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.mosi_pin = GPIO_PIN(PORT_E, 6),
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.miso_pin = GPIO_PIN(PORT_E, 5),
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.sclk_pin = GPIO_PIN(PORT_E, 2),
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.cs_pin = GPIO_UNDEF,
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.mosi_af = GPIO_AF5,
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.miso_af = GPIO_AF5,
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.sclk_af = GPIO_AF5,
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.cs_af = GPIO_AF5,
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.rccmask = RCC_APB2ENR_SPI4EN,
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.apbbus = APB2
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}
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};
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#define SPI_NUMOF ARRAY_SIZE(spi_config)
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/** @} */
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/**
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* @name ETH configuration
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* @{
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*/
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static const eth_conf_t eth_config = {
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.mode = RMII,
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.mac = { 0 },
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.speed = ETH_SPEED_100TX_FD,
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.dma = 3,
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.dma_chan = 8,
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.phy_addr = 0x01,
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.pins = {
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GPIO_PIN(PORT_G, 13),
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GPIO_PIN(PORT_B, 13),
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GPIO_PIN(PORT_G, 11),
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GPIO_PIN(PORT_C, 4),
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GPIO_PIN(PORT_C, 5),
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GPIO_PIN(PORT_A, 7),
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GPIO_PIN(PORT_C, 1),
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GPIO_PIN(PORT_A, 2),
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GPIO_PIN(PORT_A, 1),
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}
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};
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#define ETH_RX_BUFFER_COUNT (4)
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#define ETH_TX_BUFFER_COUNT (4)
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#define ETH_RX_BUFFER_SIZE (1524)
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#define ETH_TX_BUFFER_SIZE (1524)
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#define ETH_DMA_ISR isr_dma2_stream0
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#endif /* PERIPH_CONF_H */
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/** @} */
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