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https://github.com/RIOT-OS/RIOT.git
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5422f0da72
- unified dbp, hsi, and lfclk functions - all of them now work for all STM32 CPUs - renamed from bdp to dbp as this is the expression used in the reference manuals (old naming was a typo...)
157 lines
4.8 KiB
C
157 lines
4.8 KiB
C
/*
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* Copyright (C) 2017 Freie Universität Berlin
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_stm32f1
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* @{
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*
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* @file
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* @brief Implementation of STM32F1 clock configuration
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*
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* @author Stefan Pfeiffer <stefan.pfeiffer@fu-berlin.de>
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* @author Alaeddine Weslati <alaeddine.weslati@inria.fr>
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* @author Thomas Eichinger <thomas.eichinger@fu-berlin.de>
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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* @author Nick van IJzendoorn <nijzendoorn@engineering-spirit.nl>
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* @author Víctor Ariño <victor.arino@zii.aero>
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*
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* @}
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*/
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#include "irq.h"
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#include "cpu.h"
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#include "stmclk.h"
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#include "periph_conf.h"
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/* make sure we have all needed information about the clock configuration */
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#ifndef CLOCK_HSE
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#error "Please provide CLOCK_HSE in your board's perhip_conf.h"
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#endif
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#ifndef CLOCK_LSE
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#error "Please provide CLOCK_LSE in your board's periph_conf.h"
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#endif
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#ifndef CLOCK_CORECLOCK
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#error "Please provide CLOCK_CORECLOCK in your board's periph_conf.h"
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#endif
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#if !defined(CLOCK_PLL_MUL) || !defined(CLOCK_PLL_DIV)
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#error "Please provide a valid PLL configuration in your board's periph_conf.h"
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#endif
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#if !defined(CLOCK_AHB_DIV) || !defined(CLOCK_AHB) || \
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!defined(CLOCK_APB1_DIV) || !defined(CLOCK_APB1) || \
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!defined(CLOCK_APB2_DIV) || !defined(CLOCK_APB2)
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#error "Please provide a AHB and APBx configuration in your board configuration"
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#endif
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/* make sure the selected system clock is valid */
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#if (CLOCK_CORECLOCK > 72000000)
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#error "clock config: the selected system clock exceeds 72MHz"
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#endif
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/* figure out which base block to use */
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#if CLOCK_HSE
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#if (CLOCK_HSE < 4000000) || (CLOCK_HSE > 16000000)
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#error "clock config: HSE value is out of valid range"
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#endif
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#define BASECLK (CLOCK_HSE)
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#else
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#define BASECLK (8000000) /* HSI is alway 8MHz */
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#endif
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/* if PLL is configured, verify its parameters */
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#if (CLOCK_PLL_DIV && CLOCK_PLL_MUL)
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#define USEPLL
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/* check clock config */
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#if (CLOCK_CORECLOCK != ((BASECLK / CLOCK_PLL_DIV) * CLOCK_PLL_MUL))
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#error "clock config: PLL configuration does not yield expected system clock"
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#endif
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/* make sure PLL_MUL is in range */
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#if (CLOCK_PLL_MUL < 2) || (CLOCK_PLL_MUL > 17)
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#error "clock config: CLOCK_PLL_MUL is out of range"
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#endif
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/* make sure PLL_DIV is 2 when using HSI as input */
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#if (!CLOCK_HSE) && (CLOCK_PLL_DIV != 2)
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#error "clock config: CLOCK_PLL_DIV must be 2 when using HSI oscillator"
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#endif
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/* and produce the actual PLL configuration */
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#if CLOCK_HSE
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#define PLLSRC (RCC_CFGR_PLLSRC)
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#if (CLOCK_PLL_DIV == 2)
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#define PLLDIV (RCC_CFGR_PLLXTPRE)
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#else
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#define PLLDIV (0)
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#endif
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#else
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#define PLLSRC (0)
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#define PLLDIV (0)
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#endif
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#define PLLMUL ((CLOCK_PLL_MUL - 2) << 18)
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/* and join it for writing the the CFGR register */
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#define PLLCFG (PLLMUL | PLLDIV | PLLSRC)
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#else
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#define PLLCFG (0)
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#endif
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/* now we need to select the system clock source configuration */
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#ifdef USEPLL
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#define SYSCLK_SRC RCC_CFGR_SW_PLL
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#define SYSCLK_BSY RCC_CFGR_SWS_PLL
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#elif CLK_HSE
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#define SYSCLK_SRC RCC_CFGR_SW_HSE
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#define SYSCLK_BSY RCC_CFGR_SWS_HSE
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#else
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#define SYSCLK_SRC RCC_CFGR_SW_HSI
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#define SYSCLK_BSY RCC_CFGR_SWS_HSI
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#endif
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/* Configuration of flash access cycles */
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#define FLASH_WAITSTATES ((CLOCK_CORECLOCK - 1) / 24000000U)
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/* define some bitfields */
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#define HSITRIM (1 << 7)
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#define SWSHSI (0)
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void stmclk_init_sysclk(void)
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{
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/* disable any IRQs */
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unsigned is = irq_disable();
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RCC->CIR = 0;
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/* enable HSI and use it as system clock */
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stmclk_enable_hsi();
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RCC->CFGR &= ~(RCC_CFGR_SW);
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while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI) {}
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/* its safe now to program the flash wait states */
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FLASH->ACR = (FLASH_ACR_PRFTBE | FLASH_WAITSTATES);
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/* now we are in a defined state and can stop all other clocks */
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RCC->CR = (HSITRIM | RCC_CR_HSION);
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/* next we put in the desired PLL and peripheral bus configuration */
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RCC->CFGR = (CLOCK_AHB_DIV | CLOCK_APB1_DIV | CLOCK_APB2_DIV | PLLCFG);
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/* now we need to (re-)enable the used clocks */
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#if CLOCK_HSE
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RCC->CR |= RCC_CR_HSEON;
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while (!(RCC->CR & RCC_CR_HSERDY)) {}
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#endif
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#ifdef USEPLL
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RCC->CR |= RCC_CR_PLLON;
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while (!(RCC->CR & RCC_CR_PLLRDY)) {}
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#endif
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/* leaves switching the system clock */
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RCC->CFGR |= SYSCLK_SRC;
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while ((RCC->CFGR & RCC_CFGR_SWS) != SYSCLK_BSY) {}
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/* disable HSI (if not used) */
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stmclk_disable_hsi();
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/* re-enable IRQs */
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irq_restore(is);
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}
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