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156 lines
3.1 KiB
C
156 lines
3.1 KiB
C
/*
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* Copyright (C) 2014-2016 Freie Universität Berlin
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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*/
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/**
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* @ingroup cpu_stm32
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* @ingroup drivers_periph_timer
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* @{
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*
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* @file
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* @brief Low-level timer driver implementation
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*
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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* @author Thomas Eichinger <thomas.eichinger@fu-berlin.de>
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*
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* @}
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*/
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#include "cpu.h"
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#include "periph/timer.h"
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/**
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* @brief Interrupt context for each configured timer
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*/
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static timer_isr_ctx_t isr_ctx[TIMER_NUMOF];
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/**
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* @brief Get the timer device
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*/
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static inline TIM_TypeDef *dev(tim_t tim)
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{
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return timer_config[tim].dev;
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}
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int timer_init(tim_t tim, unsigned long freq, timer_cb_t cb, void *arg)
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{
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/* check if device is valid */
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if (tim >= TIMER_NUMOF) {
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return -1;
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}
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/* remember the interrupt context */
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isr_ctx[tim].cb = cb;
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isr_ctx[tim].arg = arg;
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/* enable the peripheral clock */
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periph_clk_en(timer_config[tim].bus, timer_config[tim].rcc_mask);
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/* configure the timer as upcounter in continuous mode */
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dev(tim)->CR1 = 0;
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dev(tim)->CR2 = 0;
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dev(tim)->ARR = timer_config[tim].max;
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/* set prescaler */
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dev(tim)->PSC = ((periph_timer_clk(timer_config[tim].bus) / freq) - 1);
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/* generate an update event to apply our configuration */
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dev(tim)->EGR = TIM_EGR_UG;
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/* enable the timer's interrupt */
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NVIC_EnableIRQ(timer_config[tim].irqn);
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/* reset the counter and start the timer */
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timer_start(tim);
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return 0;
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}
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int timer_set_absolute(tim_t tim, int channel, unsigned int value)
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{
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if (channel >= (int)TIMER_CHANNEL_NUMOF) {
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return -1;
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}
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TIM_CHAN(tim, channel) = (value & timer_config[tim].max);
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dev(tim)->SR &= ~(TIM_SR_CC1IF << channel);
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dev(tim)->DIER |= (TIM_DIER_CC1IE << channel);
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return 0;
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}
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int timer_clear(tim_t tim, int channel)
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{
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if (channel >= (int)TIMER_CHANNEL_NUMOF) {
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return -1;
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}
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dev(tim)->DIER &= ~(TIM_DIER_CC1IE << channel);
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return 0;
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}
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unsigned int timer_read(tim_t tim)
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{
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return (unsigned int)dev(tim)->CNT;
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}
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void timer_start(tim_t tim)
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{
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dev(tim)->CR1 |= TIM_CR1_CEN;
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}
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void timer_stop(tim_t tim)
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{
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dev(tim)->CR1 &= ~(TIM_CR1_CEN);
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}
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static inline void irq_handler(tim_t tim)
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{
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uint32_t status = (dev(tim)->SR & dev(tim)->DIER);
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for (unsigned int i = 0; i < TIMER_CHANNEL_NUMOF; i++) {
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if (status & (TIM_SR_CC1IF << i)) {
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dev(tim)->DIER &= ~(TIM_DIER_CC1IE << i);
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isr_ctx[tim].cb(isr_ctx[tim].arg, i);
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}
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}
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cortexm_isr_end();
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}
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#ifdef TIMER_0_ISR
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void TIMER_0_ISR(void)
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{
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irq_handler(0);
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}
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#endif
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#ifdef TIMER_1_ISR
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void TIMER_1_ISR(void)
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{
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irq_handler(1);
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}
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#endif
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#ifdef TIMER_2_ISR
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void TIMER_2_ISR(void)
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{
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irq_handler(2);
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}
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#endif
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#ifdef TIMER_3_ISR
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void TIMER_3_ISR(void)
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{
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irq_handler(3);
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}
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#endif
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#ifdef TIMER_4_ISR
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void TIMER_4_ISR(void)
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{
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irq_handler(4);
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}
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#endif
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