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https://github.com/RIOT-OS/RIOT.git
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d1261a7ef0
This PR sets the tranceiver in PLL_ON state to avoid corruption of the data in the frame buffer and sets it back to the last state which the transceiver had before changing into transmit mode after the data is read out. This is done to avoid data corruption when `_recv(...)` is called to retrieve the buffer size and frame buffer protection is released.
211 lines
7.2 KiB
C
211 lines
7.2 KiB
C
/*
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* Copyright (C) 2013 Alaeddine Weslati <alaeddine.weslati@inria.fr>
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* Copyright (C) 2015 Freie Universität Berlin
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* 2017 HAW Hamburg
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup drivers_at86rf2xx
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* @{
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*
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* @file
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* @brief Implementation of public functions for AT86RF2xx drivers
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*
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* @author Alaeddine Weslati <alaeddine.weslati@inria.fr>
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* @author Thomas Eichinger <thomas.eichinger@fu-berlin.de>
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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* @author Kaspar Schleiser <kaspar@schleiser.de>
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* @author Oliver Hahm <oliver.hahm@inria.fr>
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* @author Sebastian Meiling <s@mlng.net>
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* @}
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*/
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#include "luid.h"
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#include "byteorder.h"
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#include "net/ieee802154.h"
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#include "net/gnrc.h"
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#include "at86rf2xx_registers.h"
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#include "at86rf2xx_internal.h"
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#include "at86rf2xx_netdev.h"
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#define ENABLE_DEBUG (0)
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#include "debug.h"
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void at86rf2xx_setup(at86rf2xx_t *dev, const at86rf2xx_params_t *params)
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{
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netdev_t *netdev = (netdev_t *)dev;
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netdev->driver = &at86rf2xx_driver;
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/* initialize device descriptor */
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memcpy(&dev->params, params, sizeof(at86rf2xx_params_t));
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/* State to return after receiving or transmitting */
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dev->idle_state = AT86RF2XX_STATE_TRX_OFF;
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/* radio state is P_ON when first powered-on */
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dev->state = AT86RF2XX_STATE_P_ON;
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dev->pending_tx = 0;
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}
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void at86rf2xx_reset(at86rf2xx_t *dev)
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{
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eui64_t addr_long;
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at86rf2xx_hardware_reset(dev);
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netdev_ieee802154_reset(&dev->netdev);
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/* Reset state machine to ensure a known state */
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if (dev->state == AT86RF2XX_STATE_P_ON) {
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at86rf2xx_set_state(dev, AT86RF2XX_STATE_FORCE_TRX_OFF);
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}
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/* get an 8-byte unique ID to use as hardware address */
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luid_get(addr_long.uint8, IEEE802154_LONG_ADDRESS_LEN);
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/* make sure we mark the address as non-multicast and not globally unique */
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addr_long.uint8[0] &= ~(0x01);
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addr_long.uint8[0] |= (0x02);
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/* set short and long address */
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at86rf2xx_set_addr_long(dev, ntohll(addr_long.uint64.u64));
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at86rf2xx_set_addr_short(dev, ntohs(addr_long.uint16[0].u16));
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/* set default PAN id */
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at86rf2xx_set_pan(dev, AT86RF2XX_DEFAULT_PANID);
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/* set default channel */
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at86rf2xx_set_chan(dev, AT86RF2XX_DEFAULT_CHANNEL);
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/* set default TX power */
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at86rf2xx_set_txpower(dev, AT86RF2XX_DEFAULT_TXPOWER);
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/* set default options */
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at86rf2xx_set_option(dev, AT86RF2XX_OPT_AUTOACK, true);
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at86rf2xx_set_option(dev, AT86RF2XX_OPT_CSMA, true);
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static const netopt_enable_t enable = NETOPT_ENABLE;
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netdev_ieee802154_set(&dev->netdev, NETOPT_ACK_REQ,
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&enable, sizeof(enable));
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/* enable safe mode (protect RX FIFO until reading data starts) */
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at86rf2xx_reg_write(dev, AT86RF2XX_REG__TRX_CTRL_2,
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AT86RF2XX_TRX_CTRL_2_MASK__RX_SAFE_MODE);
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#ifdef MODULE_AT86RF212B
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at86rf2xx_set_page(dev, AT86RF2XX_DEFAULT_PAGE);
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#endif
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/* don't populate masked interrupt flags to IRQ_STATUS register */
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uint8_t tmp = at86rf2xx_reg_read(dev, AT86RF2XX_REG__TRX_CTRL_1);
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tmp &= ~(AT86RF2XX_TRX_CTRL_1_MASK__IRQ_MASK_MODE);
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at86rf2xx_reg_write(dev, AT86RF2XX_REG__TRX_CTRL_1, tmp);
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/* configure smart idle listening feature */
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#if AT86RF2XX_SMART_IDLE_LISTENING
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tmp = at86rf2xx_reg_read(dev, AT86RF2XX_REG__TRX_RPC);
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tmp |= (AT86RF2XX_TRX_RPC_MASK__RX_RPC_EN |
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AT86RF2XX_TRX_RPC_MASK__PDT_RPC_EN |
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AT86RF2XX_TRX_RPC_MASK__PLL_RPC_EN |
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AT86RF2XX_TRX_RPC_MASK__XAH_TX_RPC_EN |
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AT86RF2XX_TRX_RPC_MASK__IPAN_RPC_EN);
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at86rf2xx_reg_write(dev, AT86RF2XX_REG__TRX_RPC, tmp);
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at86rf2xx_set_rxsensitivity(dev, RSSI_BASE_VAL);
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#endif
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/* disable clock output to save power */
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tmp = at86rf2xx_reg_read(dev, AT86RF2XX_REG__TRX_CTRL_0);
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tmp &= ~(AT86RF2XX_TRX_CTRL_0_MASK__CLKM_CTRL);
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tmp &= ~(AT86RF2XX_TRX_CTRL_0_MASK__CLKM_SHA_SEL);
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tmp |= (AT86RF2XX_TRX_CTRL_0_CLKM_CTRL__OFF);
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at86rf2xx_reg_write(dev, AT86RF2XX_REG__TRX_CTRL_0, tmp);
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/* enable interrupts */
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at86rf2xx_reg_write(dev, AT86RF2XX_REG__IRQ_MASK,
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AT86RF2XX_IRQ_STATUS_MASK__TRX_END);
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/* clear interrupt flags */
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at86rf2xx_reg_read(dev, AT86RF2XX_REG__IRQ_STATUS);
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/* State to return after receiving or transmitting */
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dev->idle_state = AT86RF2XX_STATE_RX_AACK_ON;
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/* go into RX state */
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at86rf2xx_set_state(dev, AT86RF2XX_STATE_RX_AACK_ON);
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DEBUG("at86rf2xx_reset(): reset complete.\n");
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}
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size_t at86rf2xx_send(at86rf2xx_t *dev, const uint8_t *data, size_t len)
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{
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/* check data length */
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if (len > AT86RF2XX_MAX_PKT_LENGTH) {
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DEBUG("[at86rf2xx] Error: data to send exceeds max packet size\n");
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return 0;
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}
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at86rf2xx_tx_prepare(dev);
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at86rf2xx_tx_load(dev, data, len, 0);
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at86rf2xx_tx_exec(dev);
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return len;
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}
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void at86rf2xx_tx_prepare(at86rf2xx_t *dev)
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{
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uint8_t state;
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dev->pending_tx++;
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state = at86rf2xx_set_state(dev, AT86RF2XX_STATE_TX_ARET_ON);
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if (state != AT86RF2XX_STATE_TX_ARET_ON) {
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dev->idle_state = state;
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}
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dev->tx_frame_len = IEEE802154_FCS_LEN;
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}
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size_t at86rf2xx_tx_load(at86rf2xx_t *dev, const uint8_t *data,
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size_t len, size_t offset)
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{
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dev->tx_frame_len += (uint8_t)len;
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at86rf2xx_sram_write(dev, offset + 1, data, len);
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return offset + len;
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}
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void at86rf2xx_tx_exec(const at86rf2xx_t *dev)
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{
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netdev_t *netdev = (netdev_t *)dev;
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/* write frame length field in FIFO */
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at86rf2xx_sram_write(dev, 0, &(dev->tx_frame_len), 1);
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/* trigger sending of pre-loaded frame */
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at86rf2xx_reg_write(dev, AT86RF2XX_REG__TRX_STATE,
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AT86RF2XX_TRX_STATE__TX_START);
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if (netdev->event_callback &&
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(dev->flags & AT86RF2XX_OPT_TELL_TX_START)) {
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netdev->event_callback(netdev, NETDEV_EVENT_TX_STARTED);
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}
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}
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bool at86rf2xx_cca(at86rf2xx_t *dev)
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{
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uint8_t reg;
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uint8_t old_state = at86rf2xx_set_state(dev, AT86RF2XX_STATE_TRX_OFF);
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/* Disable RX path */
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uint8_t rx_syn = at86rf2xx_reg_read(dev, AT86RF2XX_REG__RX_SYN);
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reg = rx_syn | AT86RF2XX_RX_SYN__RX_PDT_DIS;
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at86rf2xx_reg_write(dev, AT86RF2XX_REG__RX_SYN, reg);
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/* Manually triggered CCA is only possible in RX_ON (basic operating mode) */
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at86rf2xx_set_state(dev, AT86RF2XX_STATE_RX_ON);
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/* Perform CCA */
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reg = at86rf2xx_reg_read(dev, AT86RF2XX_REG__PHY_CC_CCA);
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reg |= AT86RF2XX_PHY_CC_CCA_MASK__CCA_REQUEST;
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at86rf2xx_reg_write(dev, AT86RF2XX_REG__PHY_CC_CCA, reg);
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/* Spin until done (8 symbols + 12 µs = 128 µs + 12 µs for O-QPSK)*/
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do {
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reg = at86rf2xx_reg_read(dev, AT86RF2XX_REG__TRX_STATUS);
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} while ((reg & AT86RF2XX_TRX_STATUS_MASK__CCA_DONE) == 0);
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/* return true if channel is clear */
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bool ret = !!(reg & AT86RF2XX_TRX_STATUS_MASK__CCA_STATUS);
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/* re-enable RX */
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at86rf2xx_reg_write(dev, AT86RF2XX_REG__RX_SYN, rx_syn);
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/* Step back to the old state */
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at86rf2xx_set_state(dev, AT86RF2XX_STATE_TRX_OFF);
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at86rf2xx_set_state(dev, old_state);
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return ret;
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}
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