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166 lines
7.5 KiB
C
166 lines
7.5 KiB
C
/***************************************************************************//**
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* @file
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* @brief CMSIS Cortex-M3/M4 System Layer for EFR32 devices.
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* @version 5.7.0
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*******************************************************************************
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* # License
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* <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b>
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*******************************************************************************
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*
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* SPDX-License-Identifier: Zlib
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*
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* The licensor of this software is Silicon Laboratories Inc.
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*
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* This software is provided 'as-is', without any express or implied
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* warranty. In no event will the authors be held liable for any damages
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* arising from the use of this software.
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*
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* Permission is granted to anyone to use this software for any purpose,
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* including commercial applications, and to alter it and redistribute it
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* freely, subject to the following restrictions:
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*
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* 1. The origin of this software must not be misrepresented; you must not
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* claim that you wrote the original software. If you use this software
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* in a product, an acknowledgment in the product documentation would be
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* appreciated but is not required.
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* 2. Altered source versions must be plainly marked as such, and must not be
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* misrepresented as being the original software.
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* 3. This notice may not be removed or altered from any source distribution.
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*
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******************************************************************************/
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#ifndef SYSTEM_EFR32_H
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#define SYSTEM_EFR32_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <stdint.h>
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/***************************************************************************//**
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* @addtogroup Parts
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* @{
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******************************************************************************/
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/***************************************************************************//**
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* @addtogroup EFR32 EFR32
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* @{
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******************************************************************************/
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/*******************************************************************************
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************************** GLOBAL VARIABLES *******************************
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******************************************************************************/
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extern uint32_t SystemCoreClock; /**< System Clock Frequency (Core Clock) */
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extern uint32_t SystemHfrcoFreq; /**< System HFRCO frequency */
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/*******************************************************************************
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***************************** PROTOTYPES **********************************
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******************************************************************************/
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void Reset_Handler(void); /**< Reset Handler */
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void NMI_Handler(void); /**< NMI Handler */
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void HardFault_Handler(void); /**< Hard Fault Handler */
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void MemManage_Handler(void); /**< MPU Fault Handler */
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void BusFault_Handler(void); /**< Bus Fault Handler */
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void UsageFault_Handler(void); /**< Usage Fault Handler */
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void SVC_Handler(void); /**< SVCall Handler */
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void DebugMon_Handler(void); /**< Debug Monitor Handler */
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void PendSV_Handler(void); /**< PendSV Handler */
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void SysTick_Handler(void); /**< SysTick Handler */
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void EMU_IRQHandler(void); /**< EMU IRQ Handler */
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void FRC_PRI_IRQHandler(void); /**< FRC_PRI IRQ Handler */
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void WDOG0_IRQHandler(void); /**< WDOG0 IRQ Handler */
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void WDOG1_IRQHandler(void); /**< WDOG1 IRQ Handler */
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void FRC_IRQHandler(void); /**< FRC IRQ Handler */
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void MODEM_IRQHandler(void); /**< MODEM IRQ Handler */
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void RAC_SEQ_IRQHandler(void); /**< RAC_SEQ IRQ Handler */
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void RAC_RSM_IRQHandler(void); /**< RAC_RSM IRQ Handler */
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void BUFC_IRQHandler(void); /**< BUFC IRQ Handler */
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void LDMA_IRQHandler(void); /**< LDMA IRQ Handler */
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void GPIO_EVEN_IRQHandler(void); /**< GPIO_EVEN IRQ Handler */
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void TIMER0_IRQHandler(void); /**< TIMER0 IRQ Handler */
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void USART0_RX_IRQHandler(void); /**< USART0_RX IRQ Handler */
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void USART0_TX_IRQHandler(void); /**< USART0_TX IRQ Handler */
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void ACMP0_IRQHandler(void); /**< ACMP0 IRQ Handler */
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void ADC0_IRQHandler(void); /**< ADC0 IRQ Handler */
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void IDAC0_IRQHandler(void); /**< IDAC0 IRQ Handler */
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void I2C0_IRQHandler(void); /**< I2C0 IRQ Handler */
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void GPIO_ODD_IRQHandler(void); /**< GPIO_ODD IRQ Handler */
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void TIMER1_IRQHandler(void); /**< TIMER1 IRQ Handler */
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void USART1_RX_IRQHandler(void); /**< USART1_RX IRQ Handler */
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void USART1_TX_IRQHandler(void); /**< USART1_TX IRQ Handler */
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void LEUART0_IRQHandler(void); /**< LEUART0 IRQ Handler */
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void PCNT0_IRQHandler(void); /**< PCNT0 IRQ Handler */
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void CMU_IRQHandler(void); /**< CMU IRQ Handler */
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void MSC_IRQHandler(void); /**< MSC IRQ Handler */
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void CRYPTO0_IRQHandler(void); /**< CRYPTO IRQ Handler */
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void LETIMER0_IRQHandler(void); /**< LETIMER0 IRQ Handler */
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void AGC_IRQHandler(void); /**< AGC IRQ Handler */
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void PROTIMER_IRQHandler(void); /**< PROTIMER IRQ Handler */
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void RTCC_IRQHandler(void); /**< RTCC IRQ Handler */
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void SYNTH_IRQHandler(void); /**< SYNTH IRQ Handler */
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void CRYOTIMER_IRQHandler(void); /**< CRYOTIMER IRQ Handler */
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void RFSENSE_IRQHandler(void); /**< RFSENSE IRQ Handler */
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void FPUEH_IRQHandler(void); /**< FPUEH IRQ Handler */
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void SMU_IRQHandler(void); /**< SMU IRQ Handler */
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void WTIMER0_IRQHandler(void); /**< WTIMER0 IRQ Handler */
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void WTIMER1_IRQHandler(void); /**< WTIMER1 IRQ Handler */
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void PCNT1_IRQHandler(void); /**< PCNT1 IRQ Handler */
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void PCNT2_IRQHandler(void); /**< PCNT2 IRQ Handler */
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void USART2_RX_IRQHandler(void); /**< USART2_RX IRQ Handler */
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void USART2_TX_IRQHandler(void); /**< USART2_TX IRQ Handler */
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void I2C1_IRQHandler(void); /**< I2C1 IRQ Handler */
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void USART3_RX_IRQHandler(void); /**< USART3_RX IRQ Handler */
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void USART3_TX_IRQHandler(void); /**< USART3_TX IRQ Handler */
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void VDAC0_IRQHandler(void); /**< VDAC0 IRQ Handler */
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void CSEN_IRQHandler(void); /**< CSEN IRQ Handler */
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void LESENSE_IRQHandler(void); /**< LESENSE IRQ Handler */
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void CRYPTO1_IRQHandler(void); /**< CRYPTO1 IRQ Handler */
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void TRNG0_IRQHandler(void); /**< TRNG0 IRQ Handler */
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void SYSCFG_IRQHandler(void); /**< SYSCFG IRQ Handler */
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uint32_t SystemCoreClockGet(void);
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/***************************************************************************//**
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* @brief
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* Update CMSIS SystemCoreClock variable.
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*
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* @details
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* CMSIS defines a global variable SystemCoreClock that shall hold the
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* core frequency in Hz. If the core frequency is dynamically changed, the
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* variable must be kept updated in order to be CMSIS compliant.
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*
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* Notice that only if changing the core clock frequency through the EFR CMU
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* API, this variable will be kept updated. This function is only provided
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* for CMSIS compliance and if a user modifies the the core clock outside
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* the CMU API.
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******************************************************************************/
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static __INLINE void SystemCoreClockUpdate(void)
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{
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(void)SystemCoreClockGet();
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}
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uint32_t SystemMaxCoreClockGet(void);
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void SystemInit(void);
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uint32_t SystemHFClockGet(void);
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uint32_t SystemHFXOClockGet(void);
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void SystemHFXOClockSet(uint32_t freq);
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uint32_t SystemLFRCOClockGet(void);
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uint32_t SystemULFRCOClockGet(void);
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uint32_t SystemLFXOClockGet(void);
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void SystemLFXOClockSet(uint32_t freq);
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/** @} End of group */
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/** @} End of group Parts */
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#ifdef __cplusplus
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}
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#endif
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#endif /* SYSTEM_EFR32_H */
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