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8ed8daa493
The interval load value was only set to 0xffff regardless of the counter mode used which mad the 32bit timer apparently stop after 0xffff (it would never reach values >0xffff). When a GPTM is configured to one of the 32-bit modes, TAILR appears as a 32-bit register (the upper 16-bits correspond to the contents of the GPTM Timer B Interval Load (TBILR) register). In a 16-bit mode, the upper 16 bits of this register read as 0s and have no effect on the state of TBILR. Thsi commit set the correct value for TAILR depending on the configured timer mode. |
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.. | ||
include | ||
ldscripts | ||
periph | ||
radio | ||
cpu.c | ||
doc.txt | ||
Kconfig | ||
Makefile | ||
Makefile.dep | ||
Makefile.features | ||
Makefile.include | ||
vectors.c |