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https://github.com/RIOT-OS/RIOT.git
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100bd51a64
This CPU is used in the WeIO (www.we-io.net) board. Peripheral included : - timer - uart - gpio
219 lines
4.8 KiB
C
219 lines
4.8 KiB
C
/*
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* Copyright (C) 2015 Freie Universität Berlin
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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*/
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/**
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* @ingroup cpu_lpc11u34
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* @{
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*
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* @file
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* @brief Implementation of the low-level UART driver for the LPC11U34
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*
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* @author Paul RATHGEB <paul.rathgeb@skynet.be>
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* @}
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*/
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#include <stdint.h>
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#include "cpu.h"
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#include "sched.h"
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#include "thread.h"
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#include "periph/uart.h"
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#include "periph_conf.h"
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/* guard the file in case no UART is defined */
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#if (UART_0_EN)
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/**
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* @brief Struct holding the configuration data for a UART device
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*/
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typedef struct {
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uart_rx_cb_t rx_cb; /**< receive callback */
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uart_tx_cb_t tx_cb; /**< transmit callback */
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void *arg; /**< callback argument */
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} uart_conf_t;
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/**
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* @brief UART device configurations
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*/
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static uart_conf_t config[UART_NUMOF];
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int uart_init(uart_t uart, uint32_t baudrate, uart_rx_cb_t rx_cb, uart_tx_cb_t tx_cb, void *arg)
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{
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int res = uart_init_blocking(uart, baudrate);
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if (res < 0) {
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return res;
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}
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/* save callbacks */
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config[uart].rx_cb = rx_cb;
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config[uart].tx_cb = tx_cb;
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config[uart].arg = arg;
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switch (uart) {
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#if UART_0_EN
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case UART_0:
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/* configure and enable global device interrupts */
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NVIC_SetPriority(UART_0_IRQ, UART_IRQ_PRIO);
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NVIC_EnableIRQ(UART_0_IRQ);
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/* enable RX interrupt */
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UART_0_DEV->IER |= (1 << 0);
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break;
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#endif
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}
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return 0;
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}
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int uart_init_blocking(uart_t uart, uint32_t baudrate)
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{
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switch (uart) {
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#if UART_0_EN
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case UART_0:
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/* this implementation only supports 115200 baud */
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if (baudrate != 115200) {
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return -2;
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}
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/* select and configure the pin for RX */
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UART_0_RX_PINSEL &= ~0x07;
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UART_0_RX_PINSEL |= (UART_0_AF);
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/* select and configure the pin for TX */
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UART_0_TX_PINSEL &= ~0x07;
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UART_0_TX_PINSEL |= (UART_0_AF);
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/* power on UART device and select peripheral clock */
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UART_0_CLKEN();
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UART_0_CLKSEL();
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/* set mode to 8N1 and enable access to divisor latch */
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UART_0_DEV->LCR = ((0x3 << 0) | (1 << 7)) | (3 << 4);
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/* set baud rate registers (fixed for now) */
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UART_0_DEV->DLM = 0;
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UART_0_DEV->DLL = 17;
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UART_0_DEV->FDR |= (8) | (15 << 4);
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/* disable access to divisor latch */
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UART_0_DEV->LCR &= ~0x80;
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/* enable FIFOs */
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UART_0_DEV->FCR = (1 << 0) | (1 << 1) | (1 << 2) | (2 << 6);
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break;
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#endif
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default:
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return -1;
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}
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return 0;
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}
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void uart_tx_begin(uart_t uart)
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{
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switch (uart) {
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#if UART_0_EN
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case UART_0:
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/* enable TX interrupt */
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UART_0_DEV->IER |= (1 << 1);
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break;
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#endif
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}
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}
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int uart_write(uart_t uart, char data)
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{
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switch (uart) {
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#if UART_0_EN
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case UART_0:
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UART_0_DEV->THR = (uint8_t)data;;
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break;
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#endif
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default:
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return -1;
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}
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return 1;
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}
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int uart_read_blocking(uart_t uart, char *data)
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{
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switch (uart) {
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#if UART_0_EN
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case UART_0:
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while (!(UART_0_DEV->LSR & (1 << 0))); /* wait for RDR bit to be set */
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*data = (char)UART_0_DEV->RBR;
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break;
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#endif
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default:
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return -1;
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}
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return 1;
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}
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int uart_write_blocking(uart_t uart, char data)
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{
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switch (uart) {
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#if UART_0_EN
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case UART_0:
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while (!(UART_0_DEV->LSR & (1 << 5))); /* wait for THRE bit to be set */
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UART_0_DEV->THR = (uint8_t)data;
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break;
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#endif
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default:
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return -1;
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}
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return 1;
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}
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void uart_poweron(uart_t uart)
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{
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switch (uart) {
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#if UART_0_EN
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case UART_0:
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UART_0_CLKEN();
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break;
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#endif
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}
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}
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void uart_poweroff(uart_t uart)
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{
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switch (uart) {
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#if UART_0_EN
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case UART_0:
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UART_0_CLKDIS();
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break;
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#endif
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}
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}
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#if UART_0_EN
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void UART_0_ISR(void)
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{
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if (UART_0_DEV->LSR & (1 << 0)) { /* is RDR flag set? */
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char data = (char)UART_0_DEV->RBR;
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config[UART_0].rx_cb(config[UART_0].arg, data);
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}
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if (UART_0_DEV->LSR & (1 << 5)) { /* THRE flag set? */
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if (UART_0_DEV->IER & (1 << 1)) {
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if (config[UART_0].tx_cb(config[UART_0].arg) == 0) {
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/* disable TX interrupt */
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UART_0_DEV->IER &= ~(1 << 1);
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}
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}
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}
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if (sched_context_switch_request) {
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thread_yield();
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}
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}
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#endif
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#endif /* (UART_0_EN) */
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