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0368239a63
Now, MCU is able to go in stop mode if necessary when periph_pm feature is activated. Regarding LPSDSR bit that deactivates or not regulator in stop mode, it is up to the user to set/clear this bit. In order to save power, voltage regulator can be set in low power state during stop mode but it increases wakeup time. Signed-off-by: Aurelien Fillau <aurelien.fillau@gmail.com>
113 lines
3.2 KiB
C
113 lines
3.2 KiB
C
/*
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* Copyright (C) 2016 Kaspar Schleiser <kaspar@schleiser.de>
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* 2015 Freie Universität Berlin
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* 2015 Engineering-Spirit
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_stm32_common
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* @ingroup drivers_periph_pm
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* @{
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*
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* @file
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* @brief Implementation of the kernels power management interface
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*
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* @author Nick v. IJzendoorn <nijzndoorn@engineering-spirit.nl>
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* @author Kaspar Schleiser <kaspar@schleiser.de>
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* @author Fabian Nack <nack@inf.fu-berlin.de>
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*
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* @}
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*/
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#include "irq.h"
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#include "periph/pm.h"
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#if defined(CPU_FAM_STM32F1) || defined(CPU_FAM_STM32F2) || \
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defined(CPU_FAM_STM32F4) || defined(CPU_FAM_STM32L0)
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#include "stmclk.h"
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#endif
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#define ENABLE_DEBUG (0)
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#include "debug.h"
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#ifndef PM_STOP_CONFIG
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/**
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* @brief Define config flags for stop mode
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*
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* Available values can be found in reference manual, PWR section, register CR.
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*/
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#define PM_STOP_CONFIG (PWR_CR_LPDS | PWR_CR_FPDS)
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#endif
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void pm_set(unsigned mode)
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{
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int deep = 0;
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/* I just copied it from stm32f1/2/4, but I suppose it would work for the
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* others... /KS */
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#if defined(CPU_FAM_STM32F1) || defined(CPU_FAM_STM32F2) || \
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defined(CPU_FAM_STM32F4) || defined(CPU_FAM_STM32L0)
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switch (mode) {
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case STM32_PM_STANDBY:
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/* Set PDDS to enter standby mode on deepsleep and clear flags */
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PWR->CR |= (PWR_CR_PDDS | PWR_CR_CWUF | PWR_CR_CSBF);
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/* Enable WKUP pin to use for wakeup from standby mode */
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#if defined(CPU_FAM_STM32L0)
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PWR->CSR |= (PWR_CSR_EWUP1 | PWR_CSR_EWUP2);
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#if !defined(CPU_MODEL_STM32L053R8)
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/* STM32L053 only have 2 wake pins */
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PWR->CSR |= PWR_CSR_EWUP3;
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#endif
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#else
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PWR->CSR |= PWR_CSR_EWUP;
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#endif
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/* Set SLEEPDEEP bit of system control block */
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deep = 1;
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break;
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case STM32_PM_STOP:
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#if defined(CPU_FAM_STM32L0)
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/* Clear PDDS to enter stop mode on */
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/*
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* Regarding LPSDSR, it's up to the user to configure it :
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* 0: Voltage regulator on during Deepsleep/Sleep/Low-power run mode
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* 1: Voltage regulator in low-power mode during
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* Deepsleep/Sleep/Low-power run mode
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*/
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PWR->CR &= ~(PWR_CR_PDDS);
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#else
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/* Clear PDDS and LPDS bits to enter stop mode on */
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/* deepsleep with voltage regulator on */
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PWR->CR &= ~(PWR_CR_PDDS | PWR_CR_LPDS);
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PWR->CR |= PM_STOP_CONFIG;
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#endif
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/* Set SLEEPDEEP bit of system control block */
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deep = 1;
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break;
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}
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#else
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(void) mode;
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#endif
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cortexm_sleep(deep);
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#if defined(CPU_FAM_STM32F1) || defined(CPU_FAM_STM32F2) || \
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defined(CPU_FAM_STM32F4) || defined(CPU_FAM_STM32L0)
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if (deep) {
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/* Re-init clock after STOP */
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stmclk_init_sysclk();
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}
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#endif
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}
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#if defined(CPU_FAM_STM32F1) || defined(CPU_FAM_STM32F2) || \
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defined(CPU_FAM_STM32F4) || defined(CPU_FAM_STM32L0)
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void pm_off(void)
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{
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irq_disable();
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pm_set(0);
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}
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#endif
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