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c5c83cfe3c
- Updated to inline-able IRQ API
- Improved robustness of functions
- Added memory barrier to prevent the compiler from moving code outside of
a critical section guarded by irq_disable() ... irq_restore()
- Reduced overhead of `irq_disable()`
- After clearing the global interrupt enable (GIE) bit, IRQs remain enabled
for up to one CPU cycle
- The previous implementation just added a nop to fill that cycle
- This implementation uses the cycle for masking the return value
- Reduced overhead of `irq_restore()`
- Now only one CPU cycle is needed
- `irq_disable()`, `irq_restore()`, and `irq_enable()` work now in constant time
102 lines
2.7 KiB
C
102 lines
2.7 KiB
C
/*
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* Copyright (C) 2014 Freie Universität Berlin
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* 2020 Otto-von-Guericke-Universität Magdeburg
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_msp430_common
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* @{
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*
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* @file
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* @brief ISR related functions
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*
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* @author Kaspar Schleiser <kaspar@schleiser.de>
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* @author Oliver Hahm <oliver.hahm@inria.fr>
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* @author Marian Buschsieweke <marian.buschsieweke@ovgu.de>
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*
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*/
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#ifndef IRQ_ARCH_H
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#define IRQ_ARCH_H
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#include "irq.h"
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#include "cpu.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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extern volatile int __irq_is_in;
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__attribute__((always_inline)) static inline unsigned int irq_disable(void)
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{
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unsigned int state;
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__asm__ volatile(
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"mov.w r2, %[state]" "\n\t"
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"bic %[gie], r2" "\n\t"
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/*
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* BEWARE: IRQs remain enabled for one instruction after clearing the
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* GIE bit in the status register (r2). Thus, the next instruction is
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* not only used to sanitize the IRQ state, but also delays the actual
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* critical section by one CPU cycle, so that IRQs are indeed disabled
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* by then.
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*/
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"and %[gie], %[state]" "\n\t"
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: [state] "=r"(state)
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: [gie] "i"(GIE)
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: "memory"
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);
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return state;
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}
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__attribute__((always_inline)) static inline unsigned int irq_enable(void)
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{
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unsigned int state;
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__asm__ volatile(
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"mov.w r2, %[state]" "\n\t"
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"bis %[gie], r2" "\n\t"
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/*
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* BEWARE: IRQs remain disabled for one instruction after setting the
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* GIE bit in the status register (r2). Thus, the next instruction is
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* not only used to sanitize the IRQ state, but also ensures that the
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* first instruction after this function is run with IRQs enabled.
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*/
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"and %[gie], %[state]" "\n\t"
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: [state] "=r"(state)
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: [gie] "i"(GIE)
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: "memory"
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);
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return state;
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}
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__attribute__((always_inline)) static inline void irq_restore(unsigned int state)
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{
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__asm__ volatile(
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"bis %[state], r2" "\n\t"
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: /* no outputs */
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: [state] "r"(state)
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: "memory"
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);
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/* BEWARE: IRQs remain disabled for up to one CPU cycle after this function
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* call. But that doesn't seem to be harmful.
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*/
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}
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__attribute__((always_inline)) static inline int irq_is_in(void)
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{
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return __irq_is_in;
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}
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#ifdef __cplusplus
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}
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#endif
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/** @} */
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#endif /* IRQ_ARCH_H */
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