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https://github.com/RIOT-OS/RIOT.git
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c2c2cc8592
Since https://github.com/RIOT-OS/RIOT/pull/20935 gpio_write() uses a `bool` instead of an `int`. This does the same treatment for `gpio_read()`. This does indeed add an instruction to `gpio_read()` implementations. However, users caring about an instruction more are better served with `gpio_ll_read()` anyway. And `gpio_read() == 1` is often seen in newcomer's code, which would now work as expected.
389 lines
11 KiB
C
389 lines
11 KiB
C
/*
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* Copyright (C) 2014-2015 Freie Universität Berlin
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* 2015 Hamburg University of Applied Sciences
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* 2017-2020 Inria
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* 2017 OTA keys S.A.
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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*/
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/**
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* @ingroup cpu_stm32
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* @ingroup drivers_periph_gpio
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* @{
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*
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* @file
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* @brief Low-level GPIO driver implementation
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*
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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* @author Fabian Nack <nack@inf.fu-berlin.de>
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* @author Alexandre Abadie <alexandre.abadie@inria.fr>
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* @author Katja Kirstein <katja.kirstein@haw-hamburg.de>
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* @author Vincent Dupont <vincent@otakeys.com>
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* @author Joshua DeWeese <jdeweese@primecontrols.com>
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*
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* @}
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*/
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#include "cpu.h"
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#include "bitarithm.h"
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#include "periph/gpio.h"
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#include "periph_conf.h"
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#ifdef MODULE_PERIPH_GPIO_IRQ
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/**
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* @brief The STM32F0 family has 16 external interrupt lines
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*/
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#define EXTI_NUMOF (16U)
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#define EXTI_MASK (0xFFFF)
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/**
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* @brief Allocate memory for one callback and argument per EXTI channel
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*/
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static gpio_isr_ctx_t isr_ctx[EXTI_NUMOF];
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#endif /* MODULE_PERIPH_GPIO_IRQ */
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#if defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \
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defined(CPU_FAM_STM32G4) || defined(CPU_FAM_STM32G0) || \
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defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32U5) || \
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defined(CPU_FAM_STM32WL) || defined(CPU_FAM_STM32C0)
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#define EXTI_REG_RTSR (EXTI->RTSR1)
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#define EXTI_REG_FTSR (EXTI->FTSR1)
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#define EXTI_REG_PR (EXTI->PR1)
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#define EXTI_REG_IMR (EXTI->IMR1)
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#elif defined(CPU_FAM_STM32MP1)
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#define EXTI_REG_RTSR (EXTI->RTSR1)
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#define EXTI_REG_FTSR (EXTI->FTSR1)
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#define EXTI_REG_PR (EXTI->PR1)
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#define EXTI_REG_IMR (EXTI_C2->IMR1)
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#else
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#define EXTI_REG_RTSR (EXTI->RTSR)
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#define EXTI_REG_FTSR (EXTI->FTSR)
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#define EXTI_REG_PR (EXTI->PR)
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#define EXTI_REG_IMR (EXTI->IMR)
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#endif
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/**
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* @brief Extract the port base address from the given pin identifier
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*/
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static inline GPIO_TypeDef *_port(gpio_t pin)
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{
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return (GPIO_TypeDef *)(pin & ~(0x0f));
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}
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/**
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* @brief Extract the port number form the given identifier
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*
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* The port number is extracted by looking at bits 10, 11, 12, 13 of the base
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* register addresses.
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*/
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static inline int _port_num(gpio_t pin)
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{
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#if defined(CPU_FAM_STM32MP1)
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return (((pin - GPIOA_BASE) >> 12) & 0x0f);
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#else
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return ((pin >> 10) & 0x0f);
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#endif
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}
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/**
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* @brief Extract the pin number from the last 4 bit of the pin identifier
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*/
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static inline int _pin_num(gpio_t pin)
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{
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return (pin & 0x0f);
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}
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static inline void port_init_clock(GPIO_TypeDef *port, gpio_t pin)
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{
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(void)port; /* <-- Only used for when port G requires special handling */
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#if defined(RCC_AHBENR_GPIOAEN)
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periph_clk_en(AHB, (RCC_AHBENR_GPIOAEN << _port_num(pin)));
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#elif defined(RCC_AHB1ENR_GPIOAEN)
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periph_clk_en(AHB1, (RCC_AHB1ENR_GPIOAEN << _port_num(pin)));
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#elif defined(RCC_AHB2ENR_GPIOAEN)
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periph_clk_en(AHB2, (RCC_AHB2ENR_GPIOAEN << _port_num(pin)));
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#elif defined(RCC_AHB2ENR1_GPIOAEN)
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periph_clk_en(AHB2, (RCC_AHB2ENR1_GPIOAEN << _port_num(pin)));
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#elif defined(RCC_MC_AHB4ENSETR_GPIOAEN)
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periph_clk_en(AHB4, (RCC_MC_AHB4ENSETR_GPIOAEN << _port_num(pin)));
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#elif defined (RCC_IOPENR_GPIOAEN)
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periph_clk_en(IOP, (RCC_IOPENR_GPIOAEN << _port_num(pin)));
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#else
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#error "GPIO periph clock undefined"
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#endif
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#ifdef PWR_CR2_IOSV
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if (port == GPIOG) {
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/* Port G requires external power supply */
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periph_clk_en(APB1, RCC_APB1ENR1_PWREN);
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PWR->CR2 |= PWR_CR2_IOSV;
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}
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#endif /* PWR_CR2_IOSV */
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}
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static inline void set_mode(GPIO_TypeDef *port, int pin_num, unsigned mode)
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{
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uint32_t tmp = port->MODER;
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tmp &= ~(0x3 << (2 * pin_num));
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tmp |= ((mode & 0x3) << (2 * pin_num));
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port->MODER = tmp;
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}
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int gpio_init(gpio_t pin, gpio_mode_t mode)
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{
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GPIO_TypeDef *port = _port(pin);
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int pin_num = _pin_num(pin);
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/* enable clock */
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port_init_clock(port, pin);
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/* set mode */
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set_mode(port, pin_num, mode);
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/* set pull resistor configuration */
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port->PUPDR &= ~(0x3 << (2 * pin_num));
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port->PUPDR |= (((mode >> 2) & 0x3) << (2 * pin_num));
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/* set output mode */
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port->OTYPER &= ~(1 << pin_num);
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port->OTYPER |= (((mode >> 4) & 0x1) << pin_num);
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/* set pin speed to maximum */
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port->OSPEEDR |= (3 << (2 * pin_num));
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return 0;
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}
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void gpio_init_af(gpio_t pin, gpio_af_t af)
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{
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GPIO_TypeDef *port = _port(pin);
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uint32_t pin_num = _pin_num(pin);
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/* enable clock */
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port_init_clock(port, pin);
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/* set selected function */
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port->AFR[(pin_num > 7) ? 1 : 0] &= ~(0xf << ((pin_num & 0x07) * 4));
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port->AFR[(pin_num > 7) ? 1 : 0] |= (af << ((pin_num & 0x07) * 4));
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/* set pin to AF mode */
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set_mode(port, pin_num, 2);
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}
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void gpio_init_analog(gpio_t pin)
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{
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/* enable clock, needed as this function can be used without calling
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* gpio_init first */
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#if defined(RCC_AHBENR_GPIOAEN)
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periph_clk_en(AHB, (RCC_AHBENR_GPIOAEN << _port_num(pin)));
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#elif defined(RCC_AHB1ENR_GPIOAEN)
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periph_clk_en(AHB1, (RCC_AHB1ENR_GPIOAEN << _port_num(pin)));
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#elif defined(RCC_AHB2ENR_GPIOAEN)
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periph_clk_en(AHB2, (RCC_AHB2ENR_GPIOAEN << _port_num(pin)));
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#elif defined(RCC_AHB2ENR1_GPIOAEN)
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periph_clk_en(AHB2, (RCC_AHB2ENR1_GPIOAEN << _port_num(pin)));
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#elif defined(RCC_MC_AHB4ENSETR_GPIOAEN)
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periph_clk_en(AHB4, (RCC_MC_AHB4ENSETR_GPIOAEN << _port_num(pin)));
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#elif defined (RCC_IOPENR_GPIOAEN)
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periph_clk_en(IOP, (RCC_IOPENR_GPIOAEN << _port_num(pin)));
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#else
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#error "GPIO periph clock undefined"
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#endif
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/* set to analog mode, PUPD has to be 0b00 */
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_port(pin)->MODER |= (0x3 << (2 * _pin_num(pin)));
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_port(pin)->PUPDR &= ~(0x3 << (2 * _pin_num(pin)));
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}
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void gpio_irq_enable(gpio_t pin)
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{
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EXTI_REG_IMR |= (1 << _pin_num(pin));
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}
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void gpio_irq_disable(gpio_t pin)
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{
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EXTI_REG_IMR &= ~(1 << _pin_num(pin));
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}
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bool gpio_read(gpio_t pin)
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{
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return (_port(pin)->IDR & (1 << _pin_num(pin)));
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}
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void gpio_set(gpio_t pin)
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{
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_port(pin)->BSRR = (1 << _pin_num(pin));
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}
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void gpio_clear(gpio_t pin)
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{
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_port(pin)->BSRR = (1 << (_pin_num(pin) + 16));
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}
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void gpio_toggle(gpio_t pin)
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{
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if (gpio_read(pin)) {
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gpio_clear(pin);
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} else {
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gpio_set(pin);
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}
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}
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void gpio_write(gpio_t pin, bool value)
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{
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if (value) {
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gpio_set(pin);
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} else {
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gpio_clear(pin);
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}
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}
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#ifdef MODULE_PERIPH_GPIO_IRQ
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int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank,
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gpio_cb_t cb, void *arg)
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{
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int pin_num = _pin_num(pin);
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int port_num = _port_num(pin);
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/* set callback */
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isr_ctx[pin_num].cb = cb;
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isr_ctx[pin_num].arg = arg;
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/* enable clock of the SYSCFG module for EXTI configuration */
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#if !defined(CPU_FAM_STM32WB) && !defined(CPU_FAM_STM32MP1) && \
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!defined(CPU_FAM_STM32WL)
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#ifdef CPU_FAM_STM32F0
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periph_clk_en(APB2, RCC_APB2ENR_SYSCFGCOMPEN);
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#elif defined(CPU_FAM_STM32G0) || defined(CPU_FAM_STM32C0)
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periph_clk_en(APB12, RCC_APBENR2_SYSCFGEN);
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#elif defined(CPU_FAM_STM32U5)
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periph_clk_en(APB3, RCC_APB3ENR_SYSCFGEN);
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#else
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periph_clk_en(APB2, RCC_APB2ENR_SYSCFGEN);
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#endif
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#endif
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/* initialize pin as input */
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gpio_init(pin, mode);
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/* enable global pin interrupt */
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#if defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32U5)
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NVIC_EnableIRQ(EXTI0_IRQn + pin_num);
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#elif defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32L0) || \
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defined(CPU_FAM_STM32G0) || defined(CPU_FAM_STM32C0)
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if (pin_num < 2) {
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NVIC_EnableIRQ(EXTI0_1_IRQn);
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}
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else if (pin_num < 4) {
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NVIC_EnableIRQ(EXTI2_3_IRQn);
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}
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else {
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NVIC_EnableIRQ(EXTI4_15_IRQn);
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}
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#elif defined(CPU_FAM_STM32MP1)
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if (pin_num < 5) {
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NVIC_EnableIRQ(EXTI0_IRQn + pin_num);
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}
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else if (pin_num < 6) {
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NVIC_EnableIRQ(EXTI5_IRQn);
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}
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else if (pin_num < 10) {
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NVIC_EnableIRQ(EXTI6_IRQn + pin_num - 6);
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}
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else if (pin_num < 11) {
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NVIC_EnableIRQ(EXTI10_IRQn);
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}
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else if (pin_num < 12) {
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NVIC_EnableIRQ(EXTI11_IRQn);
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}
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else if (pin_num < 14) {
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NVIC_EnableIRQ(EXTI12_IRQn + pin_num - 12);
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}
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else if (pin_num < 15) {
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NVIC_EnableIRQ(EXTI14_IRQn);
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}
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else {
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NVIC_EnableIRQ(EXTI15_IRQn);
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}
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#else
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if (pin_num < 5) {
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NVIC_EnableIRQ(EXTI0_IRQn + pin_num);
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}
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else if (pin_num < 10) {
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NVIC_EnableIRQ(EXTI9_5_IRQn);
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}
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else {
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NVIC_EnableIRQ(EXTI15_10_IRQn);
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}
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#endif
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/* configure the active flank */
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EXTI_REG_RTSR &= ~(1 << pin_num);
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EXTI_REG_RTSR |= ((flank & 0x1) << pin_num);
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EXTI_REG_FTSR &= ~(1 << pin_num);
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EXTI_REG_FTSR |= ((flank >> 1) << pin_num);
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#if defined(CPU_FAM_STM32G0) || defined(CPU_FAM_STM32L5) || \
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defined(CPU_FAM_STM32U5) || defined(CPU_FAM_STM32C0)
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/* enable specific pin as exti sources */
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EXTI->EXTICR[pin_num >> 2] &= ~(0xf << ((pin_num & 0x03) * 8));
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EXTI->EXTICR[pin_num >> 2] |= (port_num << ((pin_num & 0x03) * 8));
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#elif defined(CPU_FAM_STM32MP1)
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/* enable specific pin as exti sources */
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EXTI->EXTICR[pin_num >> 2] &= ~(0xf << ((pin_num & 0x03) * 4));
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EXTI->EXTICR[pin_num >> 2] |= (port_num << ((pin_num & 0x03) * 4));
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#else
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/* enable specific pin as exti sources */
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SYSCFG->EXTICR[pin_num >> 2] &= ~(0xf << ((pin_num & 0x03) * 4));
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SYSCFG->EXTICR[pin_num >> 2] |= (port_num << ((pin_num & 0x03) * 4));
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#endif
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#if defined(CPU_FAM_STM32G0) || defined(CPU_FAM_STM32L5) || \
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defined(CPU_FAM_STM32U5) || defined(CPU_FAM_STM32MP1) || \
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defined(CPU_FAM_STM32C0)
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/* clear any pending requests */
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EXTI->RPR1 = (1 << pin_num);
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EXTI->FPR1 = (1 << pin_num);
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#else
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/* clear any pending requests */
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EXTI_REG_PR = (1 << pin_num);
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#endif
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/* unmask the pins interrupt channel */
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EXTI_REG_IMR |= (1 << pin_num);
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return 0;
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}
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void isr_exti(void)
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{
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#if defined(CPU_FAM_STM32G0) || defined(CPU_FAM_STM32L5) || \
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defined(CPU_FAM_STM32U5) || defined(CPU_FAM_STM32MP1) || \
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defined(CPU_FAM_STM32C0)
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/* get all interrupts handled by this ISR */
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uint32_t pending_rising_isr = (EXTI->RPR1 & EXTI_MASK);
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uint32_t pending_falling_isr = (EXTI->FPR1 & EXTI_MASK);
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/* clear by writing a 1 */
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EXTI->RPR1 = pending_rising_isr;
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EXTI->FPR1 = pending_falling_isr;
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/* only generate interrupts against lines which have their IMR set */
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uint32_t pending_isr = (pending_rising_isr | pending_falling_isr) & EXTI_REG_IMR;
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#else
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/* read all pending interrupts wired to isr_exti */
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uint32_t pending_isr = (EXTI_REG_PR & EXTI_MASK);
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/* clear by writing a 1 */
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EXTI_REG_PR = pending_isr;
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/* only generate soft interrupts against lines which have their IMR set */
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pending_isr &= EXTI_REG_IMR;
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#endif
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/* iterate over all set bits */
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uint8_t pin = 0;
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while (pending_isr) {
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pending_isr = bitarithm_test_and_clear(pending_isr, &pin);
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isr_ctx[pin].cb(isr_ctx[pin].arg);
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}
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cortexm_isr_end();
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}
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#endif /* MODULE_PERIPH_GPIO_IRQ */
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