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7c0a4b8390
The assumption that all STM32 timers have exactly four channels no longer holds. E.g. the STM32L4 has the following general purpose timers: - TIM2: 32 bit, 4 channels - TIM15: 16 bit, 2 channels - TIM16: 16 bit, 1 channel Hence, a new field is added to the timer configuration to also contain the number of timer channels. Due to alignment the `struct` previously was padded by 16 bit, so adding another 8 bit field doesn't increase its size. For backward compatibility, a value of `0` is considered as alias for `TIMER_CHANNEL_NUMOF` (or 4), so that the number of timer channels only needs to be set when the timer is different from the typical 4 channel timer. This helps backward compatibility.
66 lines
1.5 KiB
C
66 lines
1.5 KiB
C
/*
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* Copyright (C) 2016 Freie Universität Berlin
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* 2017 OTA keys S.A.
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_stm32
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* @{
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*
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* @file
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* @brief Timer CPU specific definitions for the STM32 family
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*
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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* @author Vincent Dupont <vincent@otakeys.com>
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*/
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#ifndef PERIPH_CPU_TIMER_H
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#define PERIPH_CPU_TIMER_H
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#include <stdint.h>
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#include "cpu.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief All STM timers have at most 4 capture-compare channels
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*/
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#define TIMER_CHANNEL_NUMOF (4U)
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/**
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* @brief The driver provides a relative set function
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*/
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#define PERIPH_TIMER_PROVIDES_SET
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/**
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* @brief Define a macro for accessing a timer channel
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*/
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#define TIM_CHAN(tim, chan) *(&dev(tim)->CCR1 + chan)
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/**
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* @brief Timer configuration
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*/
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typedef struct {
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TIM_TypeDef *dev; /**< timer device */
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uint32_t max; /**< maximum value to count to (16/32 bit) */
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uint32_t rcc_mask; /**< corresponding bit in the RCC register */
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uint8_t bus; /**< APBx bus the timer is clock from */
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uint8_t irqn; /**< global IRQ channel */
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uint8_t channel_numof; /**< number of channels, 0 is alias for
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@ref TIMER_CHANNEL_NUMOF */
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} timer_conf_t;
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#ifdef __cplusplus
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}
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#endif
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#endif /* PERIPH_CPU_TIMER_H */
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/** @} */
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