mirror of
https://github.com/RIOT-OS/RIOT.git
synced 2024-12-29 04:50:03 +01:00
bf96c28889
Generated new vendor header files from upstream SVD files using:
./SVDConv "$PICO_SDK_DIR"/src/rp2040/hardware_regs/rp2040.svd \
--generate=header --fields=macro --fields=enum
Note: The missing `--fields=struct` flag resulted in the header no
longer containing bit-fields to represent different fields
within registers. While this would generally ease writing code,
the RP2040 has the unpleasant feature of corrupting the
remaining bits of the register when a write access that is not
word-sized occurs in the memory mapped I/O area. This could
happen e.g. when a bit field is byte-sized and byte-aligned.
58 lines
1.9 KiB
C
58 lines
1.9 KiB
C
/*
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* Copyright (C) 2021 Otto-von-Guericke Universität Magdeburg
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_rpx0xx
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* @{
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*
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* @file
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* @brief Implementation of the ring oscillator (ROSC)
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*
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* @author Marian Buschsieweke <marian.buschsieweke@ovgu.de>
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* @author Fabian Hüßler <fabian.huessler@ovgu.de>
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*
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* @}
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*/
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#include "vendor/RP2040.h"
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#include "io_reg.h"
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/**
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* @brief Start the ring oscillator in default mode.
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* The ROSC is running at boot time but may be turned off
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* to save power when switching to the accurate XOSC.
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* The default ROSC provides an instable frequency of 1.8 MHz to 12 MHz.
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*/
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void rosc_start(void)
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{
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/* set drive strengths to default 0 */
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io_reg_atomic_clear(&ROSC->FREQA, ROSC_FREQA_PASSWD_Msk);
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io_reg_atomic_clear(&ROSC->FREQB, ROSC_FREQB_PASSWD_Msk);
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/* apply settings with magic value 0x9696 */
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const uint32_t magic = 0x9696U;
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io_reg_write_dont_corrupt(&ROSC->FREQA, magic << ROSC_FREQA_PASSWD_Pos,
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ROSC_FREQA_PASSWD_Msk);
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io_reg_write_dont_corrupt(&ROSC->FREQB, magic << ROSC_FREQB_PASSWD_Pos,
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ROSC_FREQB_PASSWD_Msk);
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/* default divider is 16 */
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io_reg_write_dont_corrupt(&ROSC->DIV, 16 << ROSC_DIV_DIV_Pos, ROSC_DIV_DIV_Msk);
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io_reg_atomic_set(&ROSC->CTRL, ROSC_CTRL_ENABLE_ENABLE << ROSC_CTRL_ENABLE_Pos);
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while (!(ROSC->STATUS & ROSC_STATUS_STABLE_Msk)) { }
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}
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/**
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* @brief Turn off the ROSC to save power.
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* The system clock must be switched to to another lock source
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* before the ROSC is stopped, other wise the chip will be lock up.
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*/
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void rosc_stop(void)
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{
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io_reg_atomic_set(&ROSC->CTRL, ROSC_CTRL_ENABLE_DISABLE << ROSC_CTRL_ENABLE_Pos);
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}
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