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RIOT/cpu/qn908x/ldscripts/qn908x.ld
iosabi cde8ac6093 cpu/qn908x: Initial minimal support for NXP QN908x CPUs.
The NXP QN908x CPU family is a Cortex-M4F CPU with integrated USB,
Bluetooth Low Energy and in some variants NFC. This patch implements the
first steps for having support for this CPU.

While the QN908x can be considered the successor of similar chips from
NXP like the KW41Z when looking at the feature set, the internal
architecture, boot image format and CPU peripherals don't match those
in the Kinetis line. Therefore, this patch creates a new directory for
just the QN908x chip under cpu/qn908x.

The minimal set of peripherals are implemented in this patch to allow
the device to boot and enable a GPIO: the gpio and wdt peripheral
modules only.

The wdt driver is required to boot and disable the wdt. On reset, the
wdt is disabled by the chip, however the QN908x bootloader stored in
the internal ROM enables the wdt and sets a timer to reboot after 10
seconds, therefore it is needed to disable the wdt in RIOT OS soon
after booting. This patch sets it up such that when no periph_wdt module
is used the Watchdog is disabled, but if the periph_wdt is used it must
be configured (initialized) within the first 10 seconds.

Tests performed:
Defined a custom board for this CPU and compiled a simple application
that blinks some LEDs. Manually tested with periph_wdt and with
periph_wdt_cb as well.
2020-12-02 02:47:07 +00:00

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/*
* Copyright (C) 2020 iosabi
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @addtogroup cpu_qn908x
* @{
*
* @file
* @brief Sections definitions for the NXP QN908x MCUs
*
* @author iosabi <iosabi@protonmail.com>
*
* This linker script organizes the flash headers to generate a "Legacy" image
* as described in the "Boot Process" section of the QN908x user manual. A
* legacy image contains an "Image vector table" which is the standard ARM
* vector table with some special values in the reserved fields. In particular,
* this needs a to have a valid checksum at address 0x1c to be considered a
* valid image by the bootloader, which is not set by the build process.
*
* @}
*/
OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
OUTPUT_ARCH(arm)
_vectors_length = 0x114;
/* The Flash lock and protect descriptor occupies the last flash page of 0x800
* bytes. See "Flash lock and protection" protection section. */
_flash_lock_length = 0x800;
INCLUDE cortexm_rom_offset.ld
MEMORY
{
/* Note: What we call "rom" here is the flash region for consistency with
* the rest of the RIOT build system naming. There is a 256 kB ROM memory in
* the QN908x holding the bootloader and Bluetooth stack that can't be
* modified by the user.
*/
vectors : ORIGIN = _rom_start_addr + _rom_offset, LENGTH = _vectors_length
rom (rx) : ORIGIN = _rom_start_addr + _rom_offset + _vectors_length, LENGTH = _fw_rom_length - _vectors_length - _flash_lock_length
ram (!rx) : ORIGIN = _ram_start_addr, LENGTH = _ram_length
}
SECTIONS
{
/* "Image vector table" 0x000-0x114, defined in the "Boot process" section,
* must have exactly this size, otherwise we configured something wrong.
*/
.vectors :
{
PROVIDE(_isr_vectors = .);
KEEP(*(SORT(.vector*)))
} > vectors
ASSERT (SIZEOF(.vectors) == _vectors_length,
"Image vector table size mismatch.")
ASSERT (ADDR(.vectors) == _rom_start_addr + _rom_offset,
"Image vector table must start at the beginning of the flash")
ASSERT (LOADADDR(.vectors) == _rom_start_addr + _rom_offset,
"Image vector table must start at the beginning of the flash")
}
INCLUDE cortexm_base.ld